Binary translation method and device, electronic equipment and readable storage medium

Abstract

The invention discloses a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the steps of obtaining a translation result of each basic block from a cache of a translator; when an instruction in the translation result is executed, if it is determined that the currently executed instruction is a target instruction with memory access alignment abnormity, remapping is performed according to a first memory access address included in the target instruction, a second memory access address is generated, and a memory area corresponding to the first memory access address is configured to be inaccessible; and executing memory access operation aiming at the second memory access address to access data of the second memory access address. The problem that in the prior art, execution of all other threads is stopped unconditionally, and consequently the execution efficiency of source program instruction translation is affected can be solved.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and specifically relates to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation can convert instructions of one instruction set architecture (ISA) into instructions of another ISA. When the host platform translates instructions of the client platform, if the memory access address corresponding to the processing instruction does not meet the access alignment requirements supported by the host platform, it will usually split an unaligned memory access operation into multiple aligned memory access operations for execution. However, if this method is used to simulate atomic instructions in the client, the multiple memory access operations after splitting cannot meet the atomicity of the instruction, and will often be interrupted by other threads or processes during the operation.

[0003] In the related art, in the above situation, in order to avoid being interrupted by other threads or processes during the operation, it is usually adopted to stop other threads when executing this instruction to ensure the atomicity of the atomic instruction in the client when it is executed after translation. However, using this method, unconditionally stopping the execution of all other threads will affect the efficiency of the translation and execution of the source program instructions. Summary of the invention

[0004] The present application aims to provide a binary translation method, device, electronic device and readable storage medium, which at least solves the problem of unconditionally stopping the execution of all other threads in the prior art, which affects the efficiency of the translation and execution of source program instructions.

[0005] In order to solve the above technical problems, this application is implemented as follows: In a first aspect, an embodiment of the present application provides a binary translation method, comprising: Get the translation result of each basic block from the translator's cache; When executing the instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remapping is performed according to a first memory access address included in the target instruction to generate a second memory access address, and a memory slice area corresponding to the first memory access address is configured as inaccessible; A memory access operation is performed on the second memory access address to access data at the second memory access address.

[0006] In a second aspect, the embodiment of the present application further provides a binary translation device, including: A first acquisition module, used for acquiring the translation result of each basic block from the cache of the translator; A generating module, configured to, when executing an instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remap the instruction according to a first memory access address included in the target instruction to generate a second memory access address, and configure a memory slice area corresponding to the first memory access address as inaccessible; An execution module is used to perform a memory access operation on the second memory access address to access data at the second memory access address.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the method described in the first aspect.

[0008] In a fourth aspect, an embodiment of the present application further provides a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method described in the first aspect.

[0009] In summary, in the binary translation method of the present application, the memory access address of the memory slice can be remapped according to the first memory access address with a memory access alignment exception, and the non-aligned memory access can be converted into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation to avoid interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. Other threads that are not involved in data operations in the first memory slice can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, the concurrency performance of the entire system and the efficiency of source program instruction translation and execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flowchart of a binary translation method provided in an embodiment of the present application; Figure 2 is a schematic diagram of a binary translation method provided in an embodiment of the present application; Figure 3 is a schematic diagram of another binary translation method provided in an embodiment of the present application; Figure 4 is a block diagram of a binary translation device provided in an embodiment of the present application; Figure 5 is a block diagram of an electronic device according to an exemplary embodiment; Figure 6 It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0011] The binary memory access provided by the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0012] Before introducing the binary translation method, device, electronic device and readable storage medium provided by the present application, the application scenarios involved in each embodiment of the present application are first introduced. The present application can be applied to the scenario of running the translation result on the target architecture platform, wherein the translation result is the target program after the source program corresponding to the source architecture platform is translated by the translator.

[0013] At present, there are many differences in the instructions that can be supported by hardware designs of different instruction set architectures (ISA), which leads to incompatibility between executable files compiled based on one ISA and other platforms. Binary translation technology can translate the source program of the source architecture platform according to the different instruction set architecture platforms, so that the source program corresponding to the source architecture platform can run on another target architecture platform.

[0014] The source program is an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture, and therefore, the source program can run normally on the client architecture platform. The target architecture platform (host architecture platform) is a machine platform to which the source program is desired to be transplanted. The source program can be run on the client architecture platform using source binary code. If it is desired to run the source program on the target architecture platform, the source binary code corresponding to the source program needs to be translated into target binary code. The target binary code is an executable code (or host code) based on a second instruction set architecture, so that the target binary code can be run on the target architecture platform. That is, the source program can be run in a binary translation environment in the target architecture platform through binary translation technology.

[0015] Among them, the atomic instructions in the source program are a special type of instructions whose execution process is indivisible (atomic). In a multi-threaded or multi-processor system, atomic instructions can ensure that their operations will not be interrupted during execution, thereby avoiding race conditions and data consistency issues. The number of operation bits supported by atomic instructions depends on the type of instruction and the characteristics of the processor architecture. Some architectures only support atomic instructions of up to 64 bits (8 bytes), while some architectures support atomic instructions of up to 128 bits (16 bytes), such as the cmpxchg16b instruction in x86-64, which can support atomic instructions of up to 128 bits (16 bytes).

[0016] Due to the differences in architectural characteristics between the host platform and the client platform, when the host platform translates the instructions of the client platform, if the memory access address corresponding to the instruction does not meet the access alignment status requirements supported by the host platform, there will be a memory access alignment exception in the host platform. In this way, it is impossible to guarantee the consistency of the running results after translating the instructions of the client platform to the host platform, which in turn affects the accuracy of the source program instruction translation.

[0017] In order to ensure the consistency of the running results after translating the instructions of the client platform to the host platform, an unaligned memory access operation is usually split into multiple aligned memory access operations for execution. However, if this method is used to simulate the atomic instructions in the client, in a multi-threaded or multi-process concurrent environment, the multiple memory access operations after the split cannot meet the atomicity of the instructions and will be interrupted by other threads or processes during the operation, resulting in incorrect execution results of the final operation combination.

[0018] In the related art, in the above situation, in order to avoid being interrupted by other threads or processes during the operation, and to avoid being observed by other threads or processes in the intermediate state or out-of-order results, it is usually adopted to stop other threads when executing this instruction to ensure the atomicity of the atomic instruction in the client after translation and execution. However, using this method to unconditionally stop the execution of all other threads will affect the efficiency of the translation and execution of the source program instructions.

[0019] In order to solve the above problems, the present application provides a binary translation method, device, electronic device and readable storage medium. The memory access address of the memory slice can be remapped according to the first memory access address with memory access alignment exception, and the non-aligned memory access can be converted into a memory access operation based on the new address (second memory access address). In this way, the entire memory access process can be executed as an atomic operation to avoid interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. For other threads that are not involved in data operations in the first memory slice, they can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

[0020] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0021] Figure 1 : is a flowchart of a binary translation method provided in this embodiment, comprising the following steps: Step 101, obtaining the translation result of each basic block from the cache of the translator.

[0022] In this step, during the execution of multiple basic blocks included in the source program, the translation result of each basic block can be obtained from the cache of the translator.

[0023] The source program may represent an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture and includes a plurality of basic blocks, where a basic block refers to a sequence of instructions executed sequentially in the source program. After the translator reads the binary file, it translates and executes the source program based on the basic block as the granularity.

[0024] First, when it is necessary to run the source program developed based on the source architecture platform on the target architecture platform, for each basic block included in the source program, the source architecture instructions in the basic block can be translated into target architecture instructions in real time according to the instructions actually executed on the basic block.

[0025] For example, the source architecture platform can be represented as an x86 architecture platform, the target architecture platform can be represented as another architecture platform, and the binary program can be represented as an x86 program. When an x86 program developed based on the x86 architecture platform is run on another architecture platform, instructions in a basic block in the x86 program can be translated.

[0026] For example, a basic block instruction included in an x86 program can be represented as follows: MOV EAX,5; assign the immediate value 5 to the EAX register; MOV EBX,3; assign the immediate value 3 to the EBX register; ADD EAX,EBX; Add the values ​​of EAX and EBX and store the result in EAX; MOV DWORD PTR [0x1000],EAX; stores the value of EAX to the memory address [0x1000].

[0027] Since the register naming and instruction format in the instruction set of another architecture platform are different from those of x86, the general registers of another architecture platform can be set to a0, a1, etc. When translating the basic block instruction into an instruction that can be executed on another architecture platform, the translation result corresponding to the basic block can be expressed as follows: li a0,5; load the immediate value 5 into the a0 register; li a1,3; load the immediate value 3 into the a1 register; add a0,a0,a1; add the values ​​of a0 and a1 and store the result in a0; sd a0,0x1000; stores the value of a0 to memory address 0x1000.

[0028] The translated instruction sequence may be used as the translation result of the basic block instruction included in the x86 program, and the translated instruction sequence may be stored in a cache. When the basic block is executed, the translation result of the basic block may be obtained from the cache.

[0029] Step 102, when executing the instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remap it according to the first memory access address included in the target instruction to generate a second memory access address, and configure the memory slice corresponding to the first memory access address as inaccessible.

[0030] The second memory access address is an address obtained by remapping the memory area determined according to the first memory access address.

[0031] Considering that different architectures have different regulations on the memory access address alignment of the instructions they support, the address alignment requirements for memory access by instructions in the x86 architecture are relatively loose. For example, the x86 architecture allows unaligned memory access. Although unaligned access will lead to performance degradation, especially when it involves crossing cache lines or memory page boundaries, for atomic instructions using the LOCK prefix, such as LOCK XADD (used to atomically complete the exchange and addition operation in a multi-processor environment) or LOCK CMPXCHG (equivalent to the atomic comparison and exchange operation in a multi-processor environment), the atomicity of the operation can be guaranteed under the x86 architecture even if the target address is not aligned. In another architecture after binary translation, atomic instructions have requirements for the alignment of memory access addresses. The memory address of atomic operations is required to be aligned to the natural boundary of the data, which means that 32-bit data needs to be 4-byte aligned and 64-bit data needs to be 8-byte aligned. If the target address of the atomic instruction is not aligned, an unaligned access exception will be triggered, causing the program to crash or undefined behavior.

[0032] In addition, the number of bits supported by atomic instructions depends on the type of instruction and the characteristics of the processor architecture. Some architectures only support up to 64-bit (8-byte) atomic instructions, such as the RISC-V architecture (reduced instruction set architecture), while some architectures support up to 128-bit (16-byte) atomic instructions, such as the cmpxchg16b instruction in x86-64 (an instruction used to perform 16-byte (128-bit) comparison and exchange operations in the x86-64 architecture), which can support up to 128-bit (16-byte) atomic instructions. When translating x86-64-based instructions to the RISC-V architecture for operation, although the memory address alignment can be guaranteed in some cases, there are still cases where the instructions under the RISC-V architecture after translation cannot guarantee the atomicity of the instructions.

[0033] For example, when translating x86-64-based instructions to run on the RISC-V architecture, you can define the structure so that the starting address of each data member is an integer multiple of its own size. For example, if a structure contains a 4-byte integer and an 8-byte double-precision floating-point number, put the 4-byte integer in front and ensure that its address is a multiple of 4, and put the 8-byte double-precision floating-point number in the back and ensure that its address is a multiple of 8. In this way, when performing memory access operations, the alignment requirements of RISC-V can be naturally met.

[0034] In summary, when executing the instruction sequence of the basic block in the source program, when the maximum bit width of the atomic instruction supported by the host machine is smaller than the instruction bit width included in the instructions of the source program in the client to be executed, it can be considered that there is a memory access alignment exception in the target instruction to be executed; or when the memory access address alignment regulations of the atomic instructions under the host machine architecture are stricter than the memory access address alignment regulations of the atomic instructions under the client architecture, it can also be considered that there is a memory access alignment exception in the target instruction to be executed.

[0035] For example, in a possible implementation, in order to ensure the atomicity of atomic instructions during execution, the unaligned memory access operation can be split into multiple aligned memory access operations for execution. For example, in a 32-bit system, a 32-bit (4-byte) integer is to be read starting from the memory address 0x1001. Since the starting address is not a multiple of 4, this is an unaligned memory access operation. In this case, the offset of the unaligned address relative to the 4-byte alignment boundary can be calculated. If the offset is greater than 0, the data can be split into two parts for reading. One part is the bytes from the unaligned address to the next alignment boundary, and the other part is the bytes required in the next alignment block. If the address is already aligned, 4 bytes of data are read directly.

[0036] Alternatively, in another possible implementation, in order to ensure the atomicity of atomic instructions during execution, when the maximum bit width of atomic instructions supported by the host machine is smaller than the instruction bit width included in the instructions of the source program in the client machine to be executed, the instructions are executed by combining a spin lock with multiple atomic operations. In the case of RISC-V simulating the 128-bit atomic exchange or accumulation operation of x86-64, for example, the atomic instructions supported by the host machine (such as RISC-V's 64-bit atomic instructions) are used to perform atomic operations on different parts of the target data in each attempt through a loop attempt. During the operation, a spin lock is used to ensure that only one thread can operate on the target data at the same time. For example, when implementing the atomic exchange of 128-bit data, the upper 64 bits and lower 64 bits of the data are read first, and then the atomic comparison and exchange instructions are tried to exchange the upper 64 bits and lower 64 bits respectively. If any of the operations fails, the whole process is restarted, thereby ensuring the atomicity of the final operation through multiple attempts and synchronization mechanisms.

[0037] However, in a multi-threaded or multi-process concurrent environment, since the multiple memory access operations after the split are not atomic operations, they will be interrupted by other running threads or processes during the memory access operation, resulting in incorrect execution results of the final operation combination. For example, suppose in a 32-bit system, a 32-bit integer is read from address 0x1001, and we split it into two parts: the part from 0x1001 to 0x1003 and the part starting from 0x1004. If other threads or processes modify the data in the relevant memory area in the form of data storage during the access and reading of these two parts, the data finally read will not be a coherent and correct 32-bit integer. If thread A is performing an unaligned memory access split operation, it first reads the data at 0x1001-0x1003, and thread B modifies the data at 0x1004, and then thread A reads the data starting at 0x1004, so the 32-bit integer obtained by thread A is wrong, resulting in a memory access alignment exception.

[0038] In the present application, when it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, it can be remapped according to the first memory access address included in the target instruction to generate a corresponding second memory access address, and the memory slice corresponding to the first memory access address can be configured as inaccessible.

[0039] In this embodiment, it may first be determined that the currently executed instruction is a target instruction with a memory access alignment exception.

[0040] Optionally, during the execution of instructions, the system will check each instruction involving memory access. The checking method is usually to calculate the memory access address of the instruction modulo the number of alignment bytes of the corresponding data type, and to determine whether the alignment requirements are met by comparing the memory access address of the instruction with the data type involved in the instruction. If the result is not zero, it means that the memory access address does not meet the alignment requirements. At this time, this instruction is the target instruction with a memory access alignment exception. For example, for a 32-bit integer access instruction, if its memory access address modulo 4 is not 0, it means that the address is not an integer multiple of 4, that is, the address is not accessed in a 4-byte aligned manner, and it can be determined that the instruction has a memory access alignment exception.

[0041] Optionally, the initial memory access address included in the target instruction can be obtained according to the address type of the first memory access address included in the target instruction; then the memory slice corresponding to the initial memory access address is remapped to obtain the mapped second memory access address.

[0042] In one possible implementation, the first memory access address included in the target instruction is the initial memory access address included in the corresponding instruction in the basic block of the target instruction before translation, wherein the initial memory access address is a memory access address of a non-aligned memory access address type; then the initial memory access address can be directly translated in an aligned manner to obtain a target instruction including the initial memory access address, in which case the first memory access address in the target instruction is consistent with the initial memory access address.

[0043] For example, when an x86 program developed based on the x86 architecture platform is run on the RISC-V architecture platform, the instruction sequence based on x86-64 can be expressed as follows: mov eax,0x1003; Assume that the data address is stored in register eax; mov ebx,[eax]; Read 32-bit data from the unaligned address to register ebx; inc ebx; add 1 to the data; mov [eax],ebx; write the modified data back to the unaligned address; Among them, 0x1003 is the initial memory access address. Since the ideal alignment address of 32-bit data is a multiple of 4, 0x1003 is non-aligned. Then the initial memory access address 0x1003 can be directly translated in an aligned manner to obtain the target instruction sequence under the RISC-V architecture, which is expressed as follows: li a0,0x1003; store address 0x1003 into register a0; lw t0,0(a0); read 32-bit data from aligned address 0x1000 to register t0; ;Extract the data corresponding to 0x1003 through logical operation; andi t1,t0,0x000000FF; Assume that t1 is used to store the data that is ultimately needed; addi t1,t1,1; add 1 to the data; ; Build the complete 32-bit data for writing back; slli t2,t1,24; or t0,t0,t2; Assume t2 is a temporary register; sw t0,0(a0); write the modified data back to address 0x1003; From the above instruction sequence, it can be seen that the first memory access address (i.e., 0x1003) is consistent with the initial memory access address. The operation on the non-aligned address 0x1003 can be simulated by performing logical operations on the data read from the aligned address 0x1000.

[0044] In another possible implementation, the first memory access address included in the target instruction is a pre-set preset unaligned memory access address. This is because the instruction corresponding to the target instruction in the basic block before translation includes an initial memory access address whose instruction bit width is greater than the maximum bit width supported by the host architecture. Although the memory access address alignment can be guaranteed in some cases, there are cases where the atomicity of the host instruction cannot be guaranteed after translation. Therefore, in this case, the preset unaligned memory access address can be stored in a preset register, and the instruction including the preset unaligned memory access address can be written to the corresponding instruction position obtained after the translation of the currently translated instruction. In this way, the characteristic that the preset unaligned memory access address can trigger the execution stop signal can be utilized to enable the subsequent steps of the present application to ensure the atomicity of the translated instruction.

[0045] For example, when translating x86-64-based instructions to run on the RISC-V architecture, you can define the structure so that the starting address of each data member is an integer multiple of its own size. For example, if a structure contains a 4-byte integer and an 8-byte double-precision floating-point number, put the 4-byte integer in front and ensure that its address is a multiple of 4, and put the 8-byte double-precision floating-point number in the back and ensure that its address is a multiple of 8. In this way, when performing memory access operations, the alignment requirements of RISC-V can be naturally met.

[0046] In summary, in the case of the above method, the first memory access address included in the target instruction can correspond to different address types. Specifically, the address type of the first memory access address included in the target instruction can be determined by determining whether the first memory access address satisfies a preset instruction template. The preset instruction template includes different instruction address types. When the first memory access address satisfies the first type in the preset instruction template, the address type of the first memory access address can be a preset unaligned memory access address. The preset unaligned memory access address is first an unaligned instruction. On this basis, the preset unaligned memory access address is also a fixed string of codes pre-set by the R&D personnel. For example, the unaligned memory access address can be pre-set to 0x1003. That is to say, when the specific value of the memory access address included in the instruction is determined to be 0x1003, it can be determined that the first memory access address is the preset unaligned memory access address.

[0047] Correspondingly, in the case where the first memory access address satisfies the second type in the preset instruction template, the address type of the first memory access address can be a non-aligned memory access address, which means that when performing a memory access operation, the access start address is not an integer multiple of the size of the accessed data type. For example, in a system that requires 4-byte alignment, if a 4-byte integer is to be accessed, its start address should normally be a multiple of 4 (such as 0, 4, 8, etc.). If the start address is an address that is not a multiple of 4, such as 1, 2 or 3, it is a non-aligned memory access address.

[0048] In the case where the address type of the first memory access address included in the target instruction is a preset non-aligned memory access address, the memory access address stored in the register can be first obtained, and then the memory access address stored in the register is used as the initial memory access address included in the target instruction. The target instruction is a stop instruction including a preset non-aligned memory access address written at the corresponding instruction position obtained after the currently translated instruction is translated, and the memory access address is the memory access address included in the currently translated instruction.

[0049] And when it is determined that the address type of the first memory access address included in the target instruction is a non-aligned memory access address, the first memory access address is directly used as the initial memory access address included in the target instruction.

[0050] Then, for the two address types of the first memory access address, namely, the preset non-aligned memory access address and the non-aligned memory access address, the memory slice corresponding to the initial memory access address may be remapped to obtain the mapped second memory access address.

[0051] Optionally, the memory capacity of the memory slice corresponding to the initial memory access address may be obtained first.

[0052] For example, the size of the free memory area to be allocated may be determined according to the size of data to be accessed by the memory area corresponding to the initial memory access address.

[0053] For example, in a system, the page size is 4KB (i.e. 2^12 bytes), and the process's current initial memory access address is 0x00001200, and it needs to access 3KB of continuous data starting from this address. Since the page size is 4KB, the 3KB data does not cross the page boundary and is still within the page with the virtual page number 1, so the size of the free memory area to be allocated is determined to be one page.

[0054] The cache can then be searched for a free memory slice that includes the memory capacity.

[0055] Optionally, a system call function provided by the operating system (such as the mremap function of the system call for remapping a memory area in a Linux system) may be used to search for a free memory segment including the memory capacity.

[0056] For example, first, the first starting address of the memory slice corresponding to the initial memory access address and the memory size of the memory slice corresponding to the initial memory access address can be obtained, and then the flag of the remapping behavior can be determined, wherein the flag is used to control the behavior of the remapping function mremap, and common flags include the MREMAP_MAYMOVE flag and the MREMAP_FIXED flag, wherein the MREMAP_MAYMOVE flag is used to allow the operating system to move the mapping area to a new address. If this flag is not specified, the operating system cannot expand the mapping area at the original address, and the mremap remapping will fail; and the MREMAP_FIXED flag is used to indicate that the new mapping address will be specified by the additional parameter new_address (address parameter).

[0057] Specifically, if the MREMAP_MAYMOVE flag is set when using the mremap function, the mapping area (i.e., the memory area corresponding to the initial memory access address) can be moved to the free memory area, and if the MREMAP_FIXED flag is set when using the mremap function, the new mapping address (i.e., the second starting address of the free memory area) can be specified by an additional parameter (new_address). When specifying a new mapping address, the mremap function can be called to move the memory area corresponding to the initial memory access address to the free memory area according to the memory size of the memory area corresponding to the initial memory access address and the first starting address of the memory area corresponding to the initial memory access address.

[0058] In a possible implementation, when the MREMAP_FIXED flag is specified, an additional parameter (new_address) may be used to specify a new mapping address (ie, the second starting address of the free memory area).

[0059] In another possible implementation, when the MREMAP_MAYMOVE flag is specified, the operating system will try to find a sufficiently large continuous free memory block at another location and copy the data of the original mapping area to the new location. At this time, the new starting address will be the second starting address of the free memory area found by the operating system.

[0060] In some embodiments, the memory access address of the free memory slice refers to an address generated after the memory slice corresponding to the initial memory access address is remapped to the corresponding memory slice in order to correctly access data in the remapped memory slice.

[0061] In this step, before generating the memory access address of the free memory area, it is necessary to determine that the free memory area has been successfully mapped. Specifically, it can be determined that the free memory area has been successfully mapped by determining that the mremap operation has been successfully completed and a valid second starting address of the free memory area has been obtained.

[0062] For example, you can check the return value of the mremap function to determine whether the mapping operation has been successfully completed. When the mremap function is successfully called, it will return the starting address of the remapped memory area (that is, the second starting address of the free memory area). When it fails, it will return MAP_FAILED (usually defined as (void *)-1). Therefore, you can check the return value to determine whether the operation is successful. If the second starting address of the returned free memory area is not equal to MAP_FAILED, it means that the mremap mapping operation is successful, and the memory area corresponding to the initial memory access address is remapped and successfully mapped to the free memory area. At this time, you can continue to use the new mapping area free memory area. Otherwise, if the second starting address of the returned free memory area is equal to MAP_FAILED, it means that the mremap mapping operation has failed, indicating that the remapping operation of the memory area corresponding to the initial memory access address has failed.

[0063] When it is determined that the free memory area has been successfully mapped, a memory access address of the free memory area may be generated.

[0064] For example, first, the offset of the memory address to be accessed relative to the first starting address can be determined, wherein the first starting address is the starting address of the memory slice corresponding to the initial memory access address; then the second starting address of the free memory slice can be added to the offset to obtain the memory address of the free memory slice, and the memory address of the free memory slice is the second memory access address.

[0065] In some embodiments, when the memory slice corresponding to the initial memory access address is remapped, the first starting address of the memory slice corresponding to the initial memory access address can be mapped to the second starting address of the free memory slice.

[0066] For example, on a system with a page size of 4KB (2^12 bytes), a process has the following initial virtual address to physical address mapping:

[0067] Assume that the current initial memory access address of the process is 0x00001200, and it needs to access 3KB of continuous data starting from this address. Since the page size is 4KB, the 3KB data does not cross the page boundary and is still within the page with virtual page number 1; now, assume that the system needs to adjust the virtual address range of this part of the data, such as mapping it to a new virtual address range of 0x00008000-0x00008FFF.

[0068] First, by looking up the mapping relationship, we can know that the physical page frame number corresponding to the current virtual page number 1 is 5. Then, a new mapping entry is added to the page table, the virtual page number corresponds to the new virtual address range (here the new virtual page number can be set to 8, corresponding to the virtual address 0x00008000-0x00008FFF), and it is mapped to the original physical page frame number 5; at the same time, since the original virtual address range 0x00001000-0x00001FFF is no longer needed to map the physical page frame number 5, the mapping entry can be deleted from the page table (or marked as invalid).

[0069] In this way, when the process subsequently accesses the address in the new virtual address range 0x00008000-0x00008FFF, the memory management unit (MMU) will correctly map it to the physical address 0x00005000-0x00005FFF according to the updated page table, thus realizing the remapping of the virtual address based on the data size corresponding to the initial memory access address (without crossing pages) without changing the physical page.

[0070] Through the above operations, the system can complete the remapping of the virtual address according to the data size corresponding to the initial memory access address without changing the physical page, so that the process can access the data on the original physical page through the new virtual address range.

[0071] It should be noted that after generating the corresponding second memory access address according to the first memory access address included in the target instruction, the memory area corresponding to the first memory access address can be configured as inaccessible, so that when the program logic is transferred to use the newly generated second memory access address for data access, other threads of the program can be prevented from accessing the first memory access address, thereby avoiding reading or writing wrong data, causing program crashes, data corruption, etc. For example, in a complex multi-threaded program, different threads will share memory resources. If the old memory access address area is not set to inaccessible, a thread may mistakenly operate the area, resulting in inconsistent data.

[0072] Specifically, when other threads of the program access the first memory access address, if the operating system recognizes that the first memory access address is inaccessible due to the execution of the scheme included in the present application, an access error signal will be provided for the first memory access address, so that other threads of the program can trigger the access error signal when accessing the first memory access address. When the operating system detects the access error signal, the other threads of the program can be controlled to be in a stop waiting state, and continue to access the first memory access address periodically until the access error signal is no longer triggered and the first memory access address is accessed normally.

[0073] In this way, the present application can generate a corresponding second memory access address based on the first memory access address included in the target instruction, and configure the memory slice corresponding to the first memory access address as inaccessible. In this way, during the execution process, only the current instruction execution logic can operate on the memory data corresponding to the first memory access address included in the target instruction, while other instruction execution logics involving the corresponding memory data in the target instruction cannot operate. In this way, data competition problems caused by different instruction execution logics operating on the same data at the same time can be avoided.

[0074] For example, each thread has its own address space or has a clear access range division in the shared address space. When a thread is remapped to the second memory access address for memory access due to a memory access alignment exception, its operation is performed within its own memory access permission and range, and will not interfere with other threads' normal access to other memory access addresses. For example, in a multi-threaded database management system, a thread encounters a memory access alignment exception when processing a data query and remaps the address to access the data, while other threads may be inserting, updating, and other operations on other memory access addresses. The memory access between them is independent of each other and does not affect each other, so there is no need to stop other threads.

[0075] Since only the current instruction execution logic can operate the data corresponding to the second memory access address, the consistency of the data can be ensured when it is accessed and modified, so that the program will not produce erroneous results due to the interference of multiple execution logics when processing these data, and there is no need to stop the continued execution of other instruction execution logics. Other threads that do not involve the first memory access address data operation can continue to execute unaffected tasks, thereby avoiding unnecessary thread blocking and improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

[0076] By adopting the above technical solution, the multi-threaded program can process in an orderly manner when facing changes in the memory access address state, which not only ensures that there will be no blind operation when the address is inaccessible, but also ensures that normal access can be restored in time when the address becomes available again.

[0077] Step 103: Perform a memory access operation on the second memory access address to access data at the second memory access address.

[0078] By adopting the above technical solution, the memory access address of the memory slice can be remapped according to the first memory access address with the memory access alignment exception, and the non-aligned memory access can be converted into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation to avoid interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory access alignment problem by remapping the memory. For other threads that are not involved in data operations in the first memory slice, they can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

[0079] Figure 2 : is a flowchart of a binary translation method provided in an embodiment of the present application, comprising the following steps: Step 201, translate each basic block included in the source program in the client, and translate the instructions included in each basic block into instructions corresponding to the host architecture.

[0080] The source program may represent an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture and includes a plurality of basic blocks, where the basic block refers to a sequence of instructions executed sequentially in the source program.

[0081] First, when it is necessary to run the source program developed based on the source architecture platform on the target architecture platform, for each basic block included in the source program, the source architecture instructions in the basic block can be translated into target architecture instructions in real time according to the instructions actually executed on the basic block.

[0082] For example, for instructions in each basic block, the client instructions may be mapped to host instructions according to instruction set manuals of the client and host.

[0083] Specifically, the operation code of the client instruction may be first converted into the operation code of the host instruction. For example, the ADD instruction of the client corresponds to the ADD instruction of the host.

[0084] Then, the operands of the client instructions may be converted, where the operands are operands used to process the instructions, and may include registers, memory addresses, and immediate numbers, etc. The conversion may be performed according to the register naming rules and memory access methods of the host machine.

[0085] For example, for register operands, different instruction set architectures usually have different register names and numbers. For example, the ARM architecture has general registers such as R0-R15, while the x86 architecture has general registers such as EAX, EBX, ECX, and EDX. Therefore, a register mapping table can be established to map the client's register name to the host's register name to obtain the register operand in the host instruction; for memory operands, due to the different memory access methods (such as byte order, alignment requirements), memory address representation and calculation methods of different architectures. For example, some architectures use big-endian byte order, while others use little-endian byte order; some architectures have strict requirements for address alignment of memory access. Therefore, if the byte order of the client and host is different, byte order conversion may be required when performing memory read and write operations, and if the representation and calculation methods of the memory addresses of the client and host are different, the memory address in the client instruction can be adjusted according to the host's memory address calculation rules. For example, the memory address of some architectures needs to add the value of the base register or perform offset calculation.

[0086] After the opcode and operand of the client instruction are converted, the control flow processing of the instruction sequence can continue. For jump instructions and branch instructions, it is necessary to ensure that the translated instructions can correctly implement the same control flow logic. For example, the JMP instruction (jump instruction) of the client needs to be converted to the corresponding jump instruction of the host, and the target address needs to be correctly converted.

[0087] When the above operation flow is adopted, the instructions included in each basic block can be translated into instructions corresponding to the host machine architecture.

[0088] Step 202, obtaining the encoding length of the memory access address in the instruction currently translated by the translator.

[0089] In this step, since different instruction set architectures have different instruction encoding formats, the currently translated instruction can be parsed according to the specification of the instruction set corresponding to the current client architecture, so as to determine the location and encoding method of the memory access address in the instruction, and after parsing the instruction, find the field representing the memory access address. Among them, the location and length of this field vary depending on the architecture, so when the memory access address field is determined, the encoding length of the memory access address can be directly identified.

[0090] For example, take an x86 memory access instruction 0x8B 0x0D 0x12 0x34 0x56 0x78, which is a MOV instruction used to move data from memory to a register.

[0091] For 0x8B, this opcode usually corresponds to the MOV instruction, which moves the value of one operand to another operand.

[0092] For 0x0D, the binary representation is 00001101, where Mod = 00, Reg = 001, and R / M = 101. According to the combination of Mod and R / M, this indicates that a 32-bit offset is used to calculate the memory address. Reg = 001 usually corresponds to register ECX, which means that the target register is ECX.

[0093] For 0x12 0x34 0x56 0x78, it means the offset is 0x78563412. Then, when the encoding length of "0x8B 0x0D0x12 0x34 0x56 0x78" is obtained, it can be determined that the encoding length of the initial memory access address in this instruction is 32 bits (4 bytes).

[0094] Step 203: When the encoding length is greater than or equal to the encoding length corresponding to the host architecture, it is determined that a memory access alignment exception exists in the currently translated instruction.

[0095] The encoding length corresponding to the host architecture refers to the memory address encoding length specified by the architecture of the target computer system running the translated instructions, which is determined by the hardware design and memory management mechanism of the architecture. For example, in the 32-bit x86 architecture, 32-bit encoding is usually used to represent the memory address; while in the 64-bit x86-64 architecture, 64-bit encoding is used.

[0096] When the encoding length of the memory access address included in the currently translated instruction is greater than or equal to the encoding length corresponding to the host architecture, such as the cmpxchg16b instruction in x86-64 (an instruction used to perform 16-byte (128-bit) comparison and exchange operations in the x86-64 architecture), up to 128-bit (16-byte) atomic instructions can be supported. When translating x86-64-based instructions to the RISC-V architecture for operation, there is a situation where the instructions under the RISC-V architecture after translation cannot guarantee the atomicity of the instructions.

[0097] Step 204: store the initial memory access address included in the currently translated instruction in a predetermined preset register.

[0098] In this step, if it is determined that the currently translated instruction has a memory access alignment exception, the memory access address included in the currently translated instruction may be stored in a predetermined preset register.

[0099] Among them, the register is a high-speed storage unit inside the CPU (processor) that can be quickly accessed by the CPU. Storing the memory access address in the register allows the CPU to quickly obtain the address, facilitating the subsequent generation of stop instructions and the execution of related operations.

[0100] Step 205: In the translation result, a stop instruction including a preset non-aligned memory access address is written at a corresponding instruction position obtained after the current translated instruction is translated.

[0101] The purpose of the stop instruction is to interrupt the normal execution flow of the program at a specific moment. By setting its memory access address to a preset non-aligned memory access address, the system's processing mechanism for non-aligned memory access can be used to trigger an exception.

[0102] In this step, after the memory access address included in the currently translated instruction is stored in the register, a stop instruction can be generated, the memory access address corresponding to the stop instruction is a preset non-aligned memory access address, and when the translation result is executed, the stop instruction is executed, and an execution stop signal is triggered when the preset non-aligned memory access address is accessed, wherein the execution stop signal is a SIGBUS signal (bus error signal). When the SIGBUS signal is triggered, the execution of the translation result can be stopped.

[0103] Considering that in some host architectures, there are requirements for memory access address alignment. If the memory access address included in the currently translated instruction has a memory access alignment exception, but when these host architectures execute the translated instruction sequence, if the instruction corresponding to the current instruction after translation is directly executed, the system of the host architecture will not force the program to terminate, but continue to execute subsequent instructions. However, in this case, the program will perform calculations based on incorrect memory data, resulting in incorrect results.

[0104] Therefore, when there is a memory access alignment exception in the memory access address included in the currently translated instruction, a stop instruction including the preset non-aligned memory access address can be written at the corresponding instruction position obtained after the translation of the currently translated instruction. In this way, when these host architectures execute the translated instruction sequence, the stop instruction is synchronously executed at the translated instruction position, and the normal execution flow of the program is terminated to avoid the program from performing calculations based on erroneous memory data, thereby preventing erroneous results from being generated.

[0105] Step 206: Use the stop instruction as the target instruction.

[0106] Step 207: When the address type of the memory access address in the currently translated instruction is a non-aligned memory access address, it is determined that the currently translated instruction has a memory access alignment exception.

[0107] In this step, it may first be detected whether the memory access address included in the currently translated instruction is a non-aligned memory access address.

[0108] For example, during the instruction translation process, the system will check each instruction involving memory access. The checking method is usually to calculate the memory access address of the instruction modulo the number of aligned bytes of the corresponding data type. If the result is not zero, it means that the memory access address is a non-aligned memory access address. At this time, this instruction is the target instruction with a memory access alignment exception.

[0109] For example, for an instruction to access a 32-bit integer, if the memory access address modulo 4 is not 0, it means that the address is not an integer multiple of 4, that is, the address is not accessed in a 4-byte aligned manner, and it can be determined that the instruction has a memory access alignment exception.

[0110] Then, when it is detected that the memory access address included in the currently translated instruction is a non-aligned memory access address, it is determined that the currently translated instruction has a memory access alignment exception.

[0111] Step 208: Translate the currently translated instruction to obtain the target instruction.

[0112] In this step, the currently translated instruction may be translated according to a translation method for memory access address alignment to obtain the target instruction including a non-aligned memory access address.

[0113] Considering that in some host architectures, although there are requirements for memory access address alignment, there is still a certain degree of support for unaligned memory access. When encountering instructions with memory access alignment exceptions, the hardware can automatically handle unaligned access. For example, it can split an unaligned memory access into multiple aligned memory access operations, read or write data from different memory blocks, and then combine them.

[0114] Therefore, the currently translated instruction may continue to be translated according to the translation method of memory access address alignment to obtain the target instruction including the non-aligned memory access address.

[0115] Although the target instruction obtained here still includes non-aligned memory access addresses, when these host architectures execute the translated instruction sequence, they can directly execute the instructions corresponding to the current instruction after translation, and the program will not stop immediately due to memory access alignment exceptions during execution. However, due to the process of multiple accesses and data combination, the results of data reading or writing may be erroneous, affecting the correctness of the program.

[0116] However, in combination with the implementation method of step 102 in the present application, the problem here can be eliminated. This is because the present application can generate a corresponding second memory access address based on the first memory access address included in the target instruction, and configure the memory slice corresponding to the first memory access address as inaccessible. In this way, during the execution process, only the current instruction execution logic can operate on the memory data corresponding to the first memory access address included in the target instruction, while other instruction execution logics involving the corresponding memory data in the target instruction cannot operate. In this way, data competition problems caused by different instruction execution logics operating on the same data at the same time can be avoided.

[0117] For example, each thread has its own address space or has a clear access range division within the shared address space. When a thread is remapped to the second memory access address for memory access due to a memory access alignment exception, its operation is performed within its own memory access permission and range, and will not interfere with other threads' normal access to other memory access addresses. For example, in a multi-threaded database management system, a thread encounters a memory access alignment exception when processing a data query and remaps the address to access the data, while other threads may be inserting or updating data at other memory access addresses. The memory accesses between them are independent of each other and do not affect each other, so there is no need to stop these threads that insert or update data at other memory access addresses.

[0118] Since only the current instruction execution logic can operate the data corresponding to the second memory access address, the consistency of the data can be ensured when it is accessed and modified, so that the program will not produce erroneous results due to the interference of multiple execution logics when processing these data, and there is no need to stop the continued execution of other instruction execution logics. Other threads that do not involve the first memory access address data operation can continue to execute unaffected tasks, thereby avoiding unnecessary thread blocking and improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

[0119] Figure 3 Another binary translation method provided in the embodiment of the present application includes the following steps: Step 301, obtaining the translation result of each basic block from the cache of the translator.

[0120] In this step, the implementation method may be the same as that of the above step 101, and the specific implementation steps will not be repeated here.

[0121] Step 302: During the execution of the instructions in the translation result, synchronously detect an execution stop signal.

[0122] In this step, the current instruction in the translation result may be executed, and then an execution stop signal may be detected during the execution process.

[0123] During the execution of instructions, various exceptions may occur, such as memory access errors, division by zero errors, etc. These exceptions often trigger corresponding execution stop signals. By detecting these signals, the program can detect and respond to errors in a timely manner, making it easier for developers to debug and locate the problem. For example, when a memory alignment exception triggers a SIGBUS signal (bus error signal), the program can capture the signal and process it accordingly to avoid program crashes.

[0124] For example, during the execution of the current instruction in the translation result, if an execution stop signal is triggered due to various abnormal situations, a tool and mechanism for monitoring the execution status of the program can be used to detect the execution stop signal.

[0125] For example, during debugging, a debugger (such as GDB) may be used to monitor the execution of a program to receive an execution stop signal.

[0126] In some embodiments, during the execution of instructions, the system checks each instruction involving memory access. The checking method is usually to calculate the memory access address of the instruction modulo the number of alignment bytes of the corresponding data type. If the result is not zero, it means that the memory access address does not meet the alignment requirements. At this time, this instruction is the target instruction with a memory access alignment exception. Or when checking each instruction involving memory access, if the bit width of the memory access address in the instruction is greater than the maximum bit width supported by the host architecture, it means that the memory access address cannot be addressed and accessed in a normal and effective manner under the host architecture, which means that under the memory management and access rules of the host architecture, the address that the instruction attempts to access exceeds the range allowed by the architecture, which means that the instruction is a target instruction with a memory access alignment exception.

[0127] For example, for an instruction to access a 32-bit integer, if the modulo 4 of the memory access address is not 0, it is determined that the instruction has a memory access alignment exception.

[0128] For example, the client architecture uses 64-bit encoding to represent memory access addresses, while the host machine is a 32-bit architecture and can only process 32-bit memory access addresses. When the memory access address in the client instruction exceeds the range that can be represented by 32 bits, the host machine cannot correctly process the address, which will cause alignment problems. In this case, it can also be determined that the instruction has a memory access alignment exception.

[0129] Then, when the execution stop signal is detected, if it is determined that the stop instruction that triggers the execution stop signal is an instruction with a memory access alignment exception, steps 303 - 312 are executed.

[0130] In some embodiments, when the execution stop signal is detected, the stop instruction that generates the execution stop signal can be first obtained; if it is determined that the stop instruction that triggers the execution stop signal is an instruction without a memory access alignment exception, the associated function corresponding to the stop instruction can be obtained, and the associated function corresponding to the stop instruction can be executed, thereby also achieving the effect of stopping the execution of the translation result.

[0131] Therefore, when the execution stop signal is detected, if it is determined that the stop instruction that triggers the execution stop signal is an instruction without a memory access alignment exception, step 313 is executed.

[0132] In the case where it is determined that the address type of the first memory access address included in the target instruction is a preset non-aligned memory access address, executing steps 303, 304, 306-312; In the case where it is determined that the address type of the first memory access address included in the target instruction is a non-aligned memory access address, executing steps 305-312; Step 303, obtaining a memory access address in a preset register.

[0133] In this step, when it is determined that the address type of the first memory access address included in the target instruction is a preset non-aligned memory access address, the memory access address stored in the register can be obtained.

[0134] The preset non-aligned memory access address is a pre-set address that does not comply with the system memory alignment rule. The purpose of the execution stop signal is to interrupt the normal execution flow of the program at a specific moment. And the memory access address stored in the register is the memory access address included in the corresponding instruction in the source program before the instruction translation at the target instruction position.

[0135] Considering that the first memory access address included in the target instruction is a pre-set preset unaligned memory access address, this is because the instruction bit width of the initial memory access address included in the corresponding instruction in the basic block of the target instruction before translation is greater than the maximum bit width supported by the host architecture. Although the memory access address alignment can be guaranteed in some cases, there are situations where the atomicity of the host instruction cannot be guaranteed after translation. Therefore, in this case, the preset unaligned memory access address can be stored in a register, and the instruction including the preset unaligned memory access address can be written at the corresponding instruction position obtained after the translation of the currently translated instruction. In this way, the characteristic that the preset unaligned memory access address can trigger the execution stop signal can be utilized to enable the subsequent steps of the present application to ensure the atomicity of the translated instruction.

[0136] In program design, if an instruction including the preset non-aligned memory access address is executed, an execution stop signal can be actively triggered. When the execution stop signal is detected and it is found that the memory access address of the target instruction is the preset non-aligned memory access address, it indicates that the program has encountered an expected abnormal situation, and the memory access address stored in the register can be obtained from the register according to the expected set steps.

[0137] Step 304: Use the memory access address as the initial memory access address in the target instruction.

[0138] Optionally, the memory access address stored in the register is used as the initial memory access address included in the target instruction.

[0139] In this step, during the instruction execution process, when an execution stop signal is detected and it is determined that the target instruction that triggers the signal contains a preset non-aligned memory access address, the memory access address in the target instruction is replaced with the memory access address stored in the register, wherein the target instruction is a stop instruction including the preset non-aligned memory access address written at the corresponding instruction position obtained after the current instruction is translated. The stop instruction of the preset non-aligned memory access address adopts Figure 2The stop instruction used in the illustrated embodiment can ensure that the memory address that the corresponding instruction in the source program needs to access is used in the subsequent execution steps. By obtaining and using the correct memory address, the continuity of the program logic can be guaranteed, so that the program can complete various tasks as expected by the developer.

[0140] Step 305: Use the first memory access address as the initial memory access address in the target instruction.

[0141] In this step, when it is determined that the address type of the first memory access address included in the target instruction is a non-aligned memory access address, the first memory access address can be directly used as the initial memory access address included in the target instruction.

[0142] Step 306, obtaining the memory capacity of the memory area corresponding to the initial memory access address.

[0143] For example, the size of the free memory area to be allocated may be determined according to the size of data to be accessed by the memory area corresponding to the initial memory access address.

[0144] For example, in a system, the page size is 4KB (i.e. 2^12 bytes), and the process's current initial memory access address is 0x00001200, and it needs to access 3KB of continuous data starting from this address. Since the page size is 4KB, the 3KB data does not cross the page boundary and is still within the page with the virtual page number 1, so the size of the free memory area to be allocated is determined to be one page.

[0145] In this embodiment, the memory capacity corresponding to the memory data is obtained in the following manner: Method 1: Analyze instruction opcodes; The opcode of an instruction defines the specific operation to be performed by the instruction. Different opcodes have different requirements for data access methods and data capacity.

[0146] If the opcode is a load instruction, you need to further check the operand of the instruction to determine whether to load a byte, a word (usually 2 bytes), a double word (usually 4 bytes), or a larger data type. For example, in some architectures, the LOADB instruction means loading a byte of data, and LOADW means loading a word of data. For another example, if the opcode is a storage instruction, the size of the data to be stored can be known based on the opcode. For example, STOREQ means storing an 8-byte quadword of data.

[0147] Method 2: Consider operands and addressing modes; The operands and addressing modes of the instruction can provide more information about the memory address and data capacity.

[0148] If there is an immediate operand in the instruction, it indicates the offset or length of the data to be accessed. For example, the instruction LOAD R1, [R2 + #4] means to load data from the address of register R2 plus 4. Here 4 is the offset, and the data type needs to be combined to determine the capacity of the data to be loaded.

[0149] In register indirect addressing mode, the value in the register is the memory address. At this time, the data range to be accessed needs to be determined based on the instruction context and other related information. For example, if register R3 points to the first address of an array, the instruction LOAD R4, [R3] loads the first element of the array. The data type of the array element needs to be known to determine the data capacity to be loaded.

[0150] Step 307, searching the cache for a free memory area including the memory capacity.

[0151] Optionally, a system call function provided by the operating system (such as the mremap function of the system call for remapping a memory area in a Linux system) may be used to search for a free memory segment including the memory capacity.

[0152] For example, first, the first starting address of the memory slice corresponding to the initial memory access address and the memory size of the memory slice corresponding to the initial memory access address can be obtained, and then the flag of the remapping behavior can be determined, wherein the flag is used to control the behavior of the remapping function mremap. Common flags include the MREMAP_MAYMOVE flag and the MREMAP_FIXED flag, wherein the MREMAP_MAYMOVE flag is used to allow the operating system to move the mapping area to a new address. If this flag is not specified, the operating system cannot expand the mapping area at the original address, and the mremap remapping will fail; and the MREMAP_FIXED flag is used to indicate that the new mapping address will be specified by an additional parameter new_address (address parameter).

[0153] Specifically, if the MREMAP_MAYMOVE flag is set when using the mremap function, the mapping area (i.e., the memory area corresponding to the initial memory access address) can be moved to the free memory area, and if the MREMAP_FIXED flag is set when using the mremap function, the new mapping address (i.e., the second starting address of the free memory area) can be specified by an additional parameter (new_address). When specifying a new mapping address, the mremap function can be called to move the memory area corresponding to the initial memory access address to the free memory area according to the memory size of the memory area corresponding to the initial memory access address and the first starting address of the memory area corresponding to the initial memory access address.

[0154] In a possible implementation, when the MREMAP_FIXED flag is specified, an additional parameter (new_address) may be used to specify a new mapping address (ie, the second starting address of the free memory area).

[0155] In another possible implementation, when the MREMAP_MAYMOVE flag is specified, the operating system will try to find a sufficiently large continuous free memory block at another location and copy the data of the original mapping area to the new location. At this time, the new starting address will be the second starting address of the free memory area found by the operating system.

[0156] Step 308, obtaining a first starting address of the memory area corresponding to the initial memory access address, and obtaining a second starting address of the free memory area.

[0157] For example, the memory area corresponding to the initial memory access address is in pages, and the page size is 4KB (i.e. 2 12 Bytes). Assuming that the initial memory access address is 0x10023, when obtaining the first starting address of the memory area corresponding to the initial memory access address, it can be calculated by dividing the address by the page size. For example, the page number = 0x10023÷4KB=4 (the division here is an integer division operation). The first starting address = 4×4KB=0x10000. In other words, the starting address of the memory area (page) containing the address 0x10000 is 0x10000.

[0158] When obtaining the second starting address of the free memory area, a free memory linked list can be first determined. The linked list nodes store the starting address and size of each free memory area. When a free memory area needs to be allocated, the linked list is traversed to find a free memory area of ​​a suitable size. For example, there is a node in the linked list that represents a free memory area with a size of 8KB and a starting address of 0x20000. Then 0x20000 is the second starting address of the free memory area we obtained.

[0159] Step 309, calculating the offset of the initial memory access address relative to the first start address.

[0160] The offset represents the distance of the initial memory access address from the start address in the memory slice to which it belongs. The offset can be obtained by subtracting the first start address from the initial memory access address.

[0161] For example, assuming that the first starting address is 0x10000 and the initial memory access address is 0x10023, the offset = initial memory access address - first starting address = 0x10023 - 0x10000 = 0x23.

[0162] Step 310, adding the offset to the second starting address to obtain a memory access address for the free memory slice.

[0163] The memory access address of the free memory slice refers to an address generated after the memory slice corresponding to the initial memory access address is remapped to the corresponding memory slice in order to correctly access the data in the remapped memory slice.

[0164] In this step, before generating the memory access address of the free memory area, it is necessary to determine that the free memory area has been successfully mapped. Specifically, it can be determined that the free memory area has been successfully mapped by determining that the mremap operation has been successfully completed and a valid second starting address of the free memory area has been obtained.

[0165] For example, you can check the return value of the mremap function to determine whether the mapping operation has been successfully completed. When the mremap function is successfully called, it will return the starting address of the remapped memory area (that is, the second starting address of the free memory area). When it fails, it will return MAP_FAILED (usually defined as (void *)-1). Therefore, you can check the return value to determine whether the operation is successful. If the second starting address of the returned free memory area is not equal to MAP_FAILED, it means that the mremap mapping operation is successful, indicating that the memory area corresponding to the initial memory access address is remapped and successfully mapped to the free memory area. At this time, you can continue to use the new mapping area free memory area. Otherwise, if the second starting address of the returned free memory area is equal to MAP_FAILED, it means that the mremap mapping operation failed, indicating that the remapping operation of the memory area corresponding to the initial memory access address failed.

[0166] When it is determined that the free memory area has been successfully mapped, a memory access address of the free memory area may be generated.

[0167] For example, first, the offset of the memory access address to be accessed relative to the first starting address can be determined, where the first starting address is the starting address of the memory slice corresponding to the initial memory access address; then the second starting address of the free memory slice can be added to the offset to obtain the memory access address of the free memory slice.

[0168] For example, assuming that the first starting address is 0x10000 and the initial memory access address is 0x10023, the offset is calculated to be 0x10023 - 0x10000 = 0x23. It is also known that the second starting address of the free memory area is 0x20000. Then the memory access address of the free memory area = the second starting address + offset = 0x20000 + 0x23 = 0x20023.

[0169] Step 311: Use the memory access address of the free memory area as the remapped second memory access address.

[0170] Step 312: Perform a memory access operation on the second memory access address to access data at the second memory access address.

[0171] In this step, if the target instruction that triggers the execution stop signal, the corresponding pre-translation instruction in the pre-translation basic block is an atomic read operation, and data can be re-read from the second memory access address and then stored in the destination register of the pre-translation instruction.

[0172] For example, each thread has its own address space or has a clear access range division in the shared address space. When a thread is remapped to the second memory access address for memory access due to a memory access alignment exception, its operation is performed within its own memory access permission and range, and will not interfere with other threads' normal access to other memory access addresses. For example, in a multi-threaded database management system, a thread encounters a memory access alignment exception when processing a data query and remaps the address to access the data, while other threads may be inserting, updating, and other operations on other memory access addresses. The memory access between them is independent of each other and does not affect each other, so there is no need to stop other threads.

[0173] If the target instruction that triggers the execution stop signal has a corresponding pre-translation instruction in the pre-translation basic block that is an atomic write operation, data can be obtained from the source register of the pre-translation instruction and then written using the second memory access address.

[0174] Specifically, when writing data into the destination register of the pre-translation instruction, or when writing data using the second memory access address, the characteristics of the signal processing flow of the operating system are utilized.

[0175] When the execution stop signal is triggered, the operating system kernel will place the register scene of the target instruction that triggered the signal in a piece of memory accessible to the user state. The user program can access this piece of memory storing the register scene from the parameters of the signal processing function. For example, the ucontext_t structure of the signal processing function parameters in the Linux system can be used to obtain the register scene information. When the signal processing function is completed, the kernel will restore the register value in this piece of memory to the hardware register.

[0176] Therefore, the present application can utilize the characteristics of the signal processing function and use ucontext_t to replace the host machine instruction that triggers the exception to complete the read and write operations. After completing the read and write operations, the original memory address is restored to end the signal processing process and the next instruction that triggers the exception is continued to be executed.

[0177] Step 313, obtaining the associated function corresponding to the stop instruction, and executing the associated function respectively.

[0178] For example, when a binary program based on the x86 architecture is translated to run on the host architecture, the memory access address included in the target instruction can be set to 0xFFFF0000, which is a 4-byte aligned address that meets the alignment requirements of the int type, and this address corresponds to a physical memory page that is not allocated to the current process. Under the x86 architecture, virtual addresses need to be mapped to actual physical memory pages before they can be accessed. When trying to access an address that does not have a valid physical memory mapping, the hardware will detect this error and trigger a SIGBUS signal. When translating an x86 binary program to the host architecture, the host's memory management mechanism cannot correctly handle the mapping of this virtual address, resulting in an error.

[0179] In this implementation, during the process of program execution of the translation result, if an execution stop signal is detected and the memory access address included in the target instruction is obtained and set to 0xFFFF0000, the memory access address is a 4-byte aligned address, which meets the alignment requirement of the int type, but corresponds to a physical memory page that is not allocated to the current process. This situation will trigger the execution stop signal, so the associated function corresponding to the memory access address 0xFFFF0000 can be found and executed in the program, that is, jump to the error handler to respond to the current stop signal.

[0180] Specifically, the stop instruction can trigger a stop execution signal, and the processing function corresponding to the stop execution signal includes specific processing steps. Therefore, when the stop instruction is an instruction that does not include a memory access address with a memory access alignment exception, the execution steps corresponding to the processing function corresponding to the stop instruction can be obtained, and the execution steps included in the processing function can be executed.

[0181] In this embodiment, since each signal usually has a corresponding processing function in the program, the stop execution signal is also associated with a specific processing function, which includes a series of specific operation steps. These steps define the subsequent execution operations of the program after receiving the stop execution signal. For example, it may include saving the current program running status, cleaning up resources, closing related connections, and other operations.

[0182] For example, a processing function named handle_stop_signal can be defined, which can include a series of operation steps for performing corresponding processing on the program after receiving the stop execution signal. The specific operation steps are as follows: S1, save the current program running status; The data packet number, processing progress and other information currently being processed can be saved to a log file for subsequent recovery.

[0183] S2, clean up resources; The memory space, buffer and other resources occupied by the thread can be released.

[0184] S3. Close the relevant connection; The connection with the network server can be closed to avoid resource waste and data leakage.

[0185] Optionally, in a data processing program, the stop instruction can be used to end the execution of a thread under specific conditions. When it is detected that the stop instruction is an instruction that does not include a memory access address with a memory access alignment exception, the processing function corresponding to the stop instruction can be executed. The function includes execution steps such as saving unprocessed data and closing thread resources.

[0186] For example, when the program detects a stop instruction, it can determine whether the memory access address of the instruction has an alignment exception. Assume that there is a thread dedicated to processing TCP data packets. When a stop instruction is received and the memory access address of the instruction does not have an alignment exception, the processing function corresponding to the stop instruction is executed. The specific steps are as follows: T1. Save the unprocessed data; The remainder of the TCP packet currently being processed can be saved to a temporary file for later reprocessing.

[0187] T2. Close thread resources; The thread can be terminated to release the CPU and memory resources occupied by the thread.

[0188] Furthermore, a mapping table (such as a dictionary, an array, etc.) may be used to store the association between the memory access address without the memory access alignment exception and the corresponding error handling function. When a stop signal is detected and the memory access address without the memory access alignment exception of the stop instruction is obtained, the corresponding error handling function is found and executed by querying the mapping table.

[0189] For example, in the case of using Python programming code as an example, the dictionary error_handler_mapping can be used to store the mapping relationship between the memory access address of the non-existent memory access alignment exception and the error handling function. After obtaining the memory access address of the non-existent memory access alignment exception of the stop instruction, the in operator is used to check whether the memory access address of the non-existent memory access alignment exception exists in the dictionary, and if so, the corresponding function is called.

[0190] And in the case of using C language programming code as an example, a structure ErrorHandlerMapping can be defined to store the memory access address and the corresponding function pointer for the memory access alignment exception, and an array error_handler_mappings can be used to store all mapping relationships. In this way, the array can be traversed to find the item matching the stop instruction and call the corresponding function.

[0191] In this way, execution stop signals from different sources can be handled flexibly, ensuring that the program can respond and handle correctly in various situations.

[0192] In summary, in the binary translation method of the present application, the memory access address of the memory slice can be remapped according to the first memory access address with the memory access alignment exception, and the non-aligned memory access can be converted into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation to avoid interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. Other threads that are not involved in data operations in the first memory slice can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

[0193] Figure 4 is a block diagram of a binary translation device provided in an embodiment of the present application, such as Figure 4 As shown, the device 400 includes: A first acquisition module 401 is used to acquire the translation result of each basic block from the cache of the translator; A generating module 402 is used for, when executing the instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remapping is performed according to the first memory access address included in the target instruction to generate a second memory access address, and configuring the memory slice corresponding to the first memory access address as inaccessible; The execution module 403 is used to perform a memory access operation on the second memory access address to access data at the second memory access address.

[0194] Optionally, the generation module 402 is used to synchronously detect an execution stop signal during the execution of the instructions in the translation result; when the execution stop signal is detected, if it is determined that the stop instruction that triggers the execution stop signal is an instruction with a memory access alignment exception, then the currently executed instruction is the target instruction, so that the execution of the translation result is stopped.

[0195] Optionally, the generation module 402 is used to obtain an initial memory access address in the target instruction according to the address type of the first memory access address; and remap the memory slice corresponding to the initial memory access address to obtain the second memory access address.

[0196] Optionally, the generation module 402 is used to obtain a memory access address in a preset register when the address type is a preset non-aligned memory access address; the target instruction is a stop instruction including a preset non-aligned memory access address written at a corresponding instruction position obtained after translating the currently translated instruction, and the memory access address is the memory access address included in the currently translated instruction; and the memory access address is used as the initial memory access address in the target instruction.

[0197] Optionally, the generating module 402 is configured to use the first memory access address as the initial memory access address in the target instruction when the address type is a non-aligned memory access address.

[0198] Optionally, the generation module 402 is used to obtain the memory capacity of the memory slice corresponding to the initial memory access address; search for a free memory slice including the memory capacity in the cache, and generate a memory access address of the free memory slice; and use the memory access address of the free memory slice as the remapped second memory access address.

[0199] Optionally, the generation module 402 is used to obtain a first starting address of the memory slice corresponding to the initial memory access address, and to obtain a second starting address of the free memory slice; and to obtain the memory access address of the free memory slice according to the first starting address and the second starting address.

[0200] Optionally, the device further comprises: A second acquisition module is used to acquire the encoding length of the memory access address in the instruction currently translated by the translator; A first determination module is used to determine that a memory access alignment exception exists in the currently translated instruction when the encoding length is greater than or equal to the encoding length corresponding to the host architecture; The second determining module is used to determine the translated target instruction according to the currently translated instruction.

[0201] Optionally, the second determination module is used to write a stop instruction including a preset non-aligned memory access address at a corresponding instruction position obtained after translating the currently translated instruction; and store the initial memory access address included in the currently translated instruction in a predetermined preset register; and use the stop instruction as the target instruction.

[0202] Optionally, the device further comprises: A third acquisition module is used to acquire the instruction currently translated by the translator; The third determination module is used to determine that the currently translated instruction has a memory access alignment exception when the address type of the memory access address in the currently translated instruction is a non-aligned memory access address, and translate the currently translated instruction to obtain the target instruction.

[0203] In summary, this embodiment can remap the memory access address of the memory slice according to the first memory access address with the memory access alignment exception, and convert the non-aligned memory access into a memory access operation based on the new address (the second memory access address). In this way, the entire memory access process can be executed as an atomic operation to avoid interference from other threads or processes; and the memory slice corresponding to the first memory access address is configured as inaccessible. This solution does not need to stop other threads, but solves the memory alignment problem by remapping the memory. Other threads that are not involved in data operations in the first memory slice can continue to execute unaffected tasks, reducing unnecessary thread blocking and scheduling overhead, thereby improving the overall execution efficiency, and improving the concurrency performance of the entire system and the efficiency of source program instruction translation and execution.

[0204] Figure 5 1 is a block diagram of an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0205] Reference Figure 5 , the electronic device 500 may include one or more of the following components: a processing component 502 , a memory 504 , a power component 506 , a multimedia component 508 , an audio component 510 , an input / output interface 512 , a sensor component 514 , and a communication component 516 .

[0206] The processing component 502 generally controls the overall operation of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 502 may include one or more processors 520 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 502 may include one or more modules to facilitate the interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate the interaction between the multimedia component 508 and the processing component 502.

[0207] The memory 504 is used to store various types of data to support the operation of the electronic device 500. Examples of such data include instructions for any application or method operating on the electronic device 500, contact data, phone book data, messages, pictures, multimedia, etc.

[0208] The power supply component 506 provides power to the various components of the electronic device 500. The power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 500.

[0209] The multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the demarcation of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 508 includes a front camera and / or a rear camera. When the electronic device 500 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0210] The audio component 510 is used to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC), and when the electronic device 500 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 504 or sent via the communication component 516. In some embodiments, the audio component 510 also includes a speaker for outputting audio signals.

[0211] The input / output interface 512 provides an interface between the processing component 502 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0212] The sensor assembly 514 includes one or more sensors for providing various aspects of status assessment for the electronic device 500. The sensor assembly 514 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 514 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 514 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0213] The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 516 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 516 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0214] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement a binary translation method provided in an embodiment of the present application.

[0215] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, and the instructions can be executed by a processor 520 of an electronic device 500 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0216] Figure 6 6 is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be provided as a server. Figure 6The electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632 for storing instructions that can be executed by the processing component 622, such as an application. The application stored in the memory 632 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute instructions to perform a binary translation method provided in an embodiment of the present application.

[0217] The electronic device 600 may further include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output interface 658. The electronic device 600 may operate based on an operating system stored in the memory 632.

[0218] An embodiment of the present application also provides a computer program product, including a computer program, and a binary translation method implemented when the computer program is executed by a processor.

[0219] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0220] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A binary translation method, characterized in that: The method comprises: Get the translation result of each basic block from the translator's cache; When executing the instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remapping is performed according to a first memory access address included in the target instruction to generate a second memory access address, and a memory slice area corresponding to the first memory access address is configured as inaccessible; A memory access operation is performed on the second memory access address to access data at the second memory access address.

2. The method according to claim 1, characterized in that Determining that the currently executed instruction is a target instruction with a memory access alignment exception includes: During the execution of the instructions in the translation result, synchronously detecting an execution stop signal; When the execution stop signal is detected, if it is determined that the stop instruction that triggers the execution stop signal is an instruction with a memory access alignment exception, the currently executed instruction is the target instruction, and the translation result is stopped from being executed.

3. The method according to claim 1, characterized in that Generating the second memory access address comprises: According to the address type of the first memory access address, an initial memory access address in the target instruction is obtained; the target instruction is a stop instruction including a preset non-aligned memory access address written at a corresponding instruction position obtained after the translation of the currently translated instruction; The memory slice area corresponding to the initial memory access address is remapped to obtain the second memory access address.

4. The method according to claim 3, characterized in that The obtaining the initial memory access address in the target instruction includes: In the case where the address type is a preset non-aligned memory access address, obtaining a memory access address in a preset register; the memory access address is included in the currently translated instruction; The memory access address is used as an initial memory access address in the target instruction.

5. The method according to claim 3, characterized in that: The obtaining the initial memory access address in the target instruction includes: In a case where the address type is a non-aligned memory access address, the first memory access address is used as an initial memory access address in the target instruction.

6. The method according to claim 3, characterized in that The remapping of the memory slice area corresponding to the initial memory access address includes: Obtaining the memory capacity of the memory area corresponding to the initial memory access address; Searching the cache for a free memory area including the memory capacity, and generating a memory access address of the free memory area; The memory access address of the free memory slice is used as the remapped second memory access address.

7. The method according to claim 6, characterized in that The generating of the memory access address of the free memory area comprises: Obtaining a first starting address of a memory slice area corresponding to the initial memory access address, and obtaining a second starting address of the free memory slice area; A memory access address of the free memory slice is obtained according to the first starting address and the second starting address.

8. The method according to claim 1, characterized in that The method further comprises: Obtaining the encoding length of the memory access address in the instruction currently translated by the translator; When the encoding length is greater than or equal to the encoding length corresponding to the host architecture, determining that a memory access alignment exception exists in the currently translated instruction; The translated target instruction is determined according to the currently translated instruction.

9. The method according to claim 8, characterized in that The determining the target instruction after translation according to the currently translated instruction comprises: Writing a stop instruction including a preset non-aligned memory access address at the corresponding instruction position obtained after the instruction is translated; and storing the memory access address included in the instruction is translated into a preset register; The stop instruction is used as the target instruction.

10. The method according to claim 1, characterized in that The method further comprises: Obtaining the instruction currently translated by the translator; When the address type of the memory access address in the currently translated instruction is a non-aligned memory access address, it is determined that the currently translated instruction has a memory access alignment exception, and the currently translated instruction is translated to obtain the target instruction.

11. A binary translation device, characterized in that: The device comprises: A first acquisition module, used for acquiring the translation result of each basic block from the cache of the translator; A generating module, configured to, when executing an instruction in the translation result, if it is determined that the currently executed instruction is a target instruction with a memory access alignment exception, remap the instruction according to a first memory access address included in the target instruction to generate a second memory access address, and configure a memory slice area corresponding to the first memory access address as inaccessible; An execution module is used to perform a memory access operation on the second memory access address to access data at the second memory access address.

12. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction implements the steps of the method according to any one of claims 1 to 10 when executed by the processor.

13. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method as claimed in any one of claims 1 to 10.

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