Instruction stream generation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an instruction stream generation method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that a register jump instruction is determined from a first instruction stream; based on the number of source registers corresponding to the register jump instruction, determining a preposed operation code set corresponding to the register jump instruction; generating a second instruction stream based on the source register code of the register jump instruction and the preamble set; wherein the second instruction stream is used for providing a jump address for the register jump instruction; and inserting the second instruction stream into the first instruction stream to obtain a target instruction stream. In the embodiment of the invention, the second instruction stream in the target instruction stream provides the jump address for the corresponding register jump instruction, so that the jump controllability of the register jump instruction in the target instruction stream can be improved, and the test stability when the CPU is tested through the target instruction stream is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to an instruction stream generation method, device, electronic device and storage medium. Background Art

[0002] At present, with the continuous development of computer technology, the design of the central processing unit (CPU) is becoming more and more complex. How to verify the CPU during the design and development process is becoming more and more important in the CPU development process.

[0003] Usually, an instruction generator is used to generate an instruction stream according to a certain generation rule or randomly, and the generated instruction stream is input into the simulated CPU core or CPU physical core, and the CPU is tested by observing the processing and response of the CPU to these instruction streams. In these instruction streams, instructions with various opcodes need to be included to test the instruction processing function of the simulated CPU core or CPU physical core. However, the generated instruction stream may contain register jump instructions, which often generate unpredictable instruction jumps when executed, resulting in errors in the execution of the instruction stream and affecting the stability of the instruction stream test on the CPU. Summary of the invention

[0004] The embodiments of the present invention provide an instruction stream generation method, device, electronic device and storage medium, which can improve the test stability when testing a CPU through an instruction stream.

[0005] In order to solve the above problem, an embodiment of the present invention discloses an instruction stream generation method, the method comprising: determining a register jump instruction from the first instruction stream; Determining a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction; Generate a second instruction stream based on the source register encoding of the register jump instruction and the preceding opcode set; wherein the second instruction stream is used to provide a jump address to the register jump instruction; Insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test a central processing unit.

[0006] Optionally, the prefix operation code set includes a first prefix operation code and a second prefix operation code corresponding to the first prefix operation code, and determining the prefix operation code set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction includes: Based on the number of source registers corresponding to the register jump instruction, randomly select a first preceding opcode from a preset opcode library; Based on the number of source registers corresponding to the first preceding operation code, a second preceding operation code corresponding to the first preceding operation code is randomly selected from a preset operation code library.

[0007] Optionally, the randomly selecting a second preceding opcode corresponding to the first preceding opcode from a preset opcode library based on the number of source registers corresponding to the first preceding opcode includes: Based on the input data type corresponding to the first preceding operation code, determining a candidate operation code having an output data type that is the same as the input data type from the preset operation code library; Based on the number of source registers corresponding to the first preceding operation code, a second preceding operation code corresponding to the first preceding operation code is randomly selected from the candidate operation codes.

[0008] Optionally, the prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and the generating a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set includes: Determining, based on the source register code of the register jump instruction, the destination register code corresponding to each first preceding operation code in the preceding operation code set; Determine a second instruction corresponding to each first preceding operation code based on a destination register code corresponding to each first preceding operation code and a source register code randomly generated for each first preceding operation code, and generate a second instruction corresponding to a second preceding operation code of each first preceding operation code based on a source register code corresponding to each first preceding operation code; The second instructions are arranged based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

[0009] Optionally, the generating, based on the source register code corresponding to each first preceding operation code, a second instruction corresponding to a second preceding operation code of each first preceding operation code includes: Determining a target execution result of each first preceding opcode in the preceding opcode set based on a jump address of the register jump instruction and an instruction jump rule corresponding to the register jump instruction; Determine an immediate value corresponding to a second preceding operation code of each first preceding operation code based on a target execution result of each first preceding operation code and an operation rule of each first preceding operation code; Based on the source register code corresponding to each first preceding operation code and the immediate value, a second instruction corresponding to the second preceding operation code of each first preceding operation code is generated.

[0010] Optionally, the method further includes: A jump address of the register jump instruction is selected from an instruction address set corresponding to the target instruction stream.

[0011] Optionally, inserting the second instruction stream into the first instruction stream to obtain a target instruction stream includes: Determining an execution order corresponding to each first instruction in the first instruction stream; Selecting a target instruction from the first instruction whose execution order is less than or equal to the register jump instruction; The second instruction stream is inserted before the target instruction in the first instruction stream to obtain a target instruction stream.

[0012] On the other hand, an embodiment of the present invention discloses an instruction stream generating device, the device comprising: An instruction determination module, used for determining a register jump instruction from a first instruction stream; An operation code determination module, configured to determine a set of preceding operation codes corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction; An instruction stream module, configured to generate a second instruction stream based on the source register encoding of the register jump instruction and the preceding opcode set; wherein the second instruction stream is configured to provide a jump address to the register jump instruction; The insertion module is used to insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test the central processing unit.

[0013] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0014] The embodiment of the present invention further discloses a computer-readable storage medium on which instructions are stored. When executed by one or more processors, the processors execute the method as described above.

[0015] The embodiment of the present invention includes the following advantages: in the instruction stream generation method provided in the embodiment of the present invention, a register jump instruction is determined from a first instruction stream; based on the number of source registers corresponding to the register jump instruction, a prefix opcode set corresponding to the register jump instruction is determined; based on the source register encoding and prefix opcode set of the register jump instruction, a second instruction stream is generated; wherein the second instruction stream is used to provide a jump address to the register jump instruction; the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream. A corresponding second instruction stream can be generated for the register jump instruction in the first instruction stream, and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream, so that when the CPU is tested through the target instruction stream, the jump address can be provided for the corresponding register jump instruction through the second instruction stream in the target instruction stream, so that the jump controllability of the register jump instruction in the target instruction stream can be improved, thereby improving the test stability when the CPU is tested through the target instruction stream. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0017] Figure 1 is a flowchart of a method for generating an instruction stream provided by an embodiment of the present invention; Figure 2 is a block diagram of an instruction stream generating device provided by an embodiment of the present invention; Figure 3 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] Reference Figure 1 , shows a flow chart of the steps of an instruction stream generation method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may specifically include the following steps: Step 101, determining a register jump instruction from a first instruction stream.

[0020] In an embodiment of the present invention, the first instruction stream may be an instruction stream for testing a CPU or CPU core to be tested. The above-mentioned test environment may include a hardware environment and a simulation environment, that is, the CPU core to be tested may be a physical core or a simulation core. Among them, the first instruction stream may represent an instruction stream generated by a certain rule, or may refer to a randomly generated instruction stream, and the instructions contained in the first instruction stream may belong to the instruction architecture of the CPU or CPU core to be tested.

[0021] In an embodiment of the present invention, a register jump instruction may represent an instruction to jump to a specified instruction to continue execution. Register jump instructions may include but are not limited to jump instructions that depend on a source register (SourceRegister), such as JUMP_REG, JMP, JR, JALR, and BX. Among them, the source register represents a register that provides input data when executing an instruction. Exemplarily, a register jump instruction may be "JR rs1", which may represent jumping to the instruction address specified by the r1 register to continue execution; a register jump instruction may be "JUMP_REG rd rs1 rs2", which may represent jumping to the instruction address specified by the sum of the rs1 register and the rs2 register to continue execution, and storing the jump address in the rd register.

[0022] In an embodiment of the present invention, all register jump instructions contained in the first instruction stream can be determined, and the first instruction stream can contain one or more register jump instructions. Specifically, the opcode of each first instruction in the first instruction stream can be identified, and the opcode of the identified first instruction can be matched with the opcode corresponding to the register jump instruction, so as to determine whether each instruction in the first instruction stream is a register jump instruction.

[0023] Step 102: Determine a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction.

[0024] In the embodiment of the present invention, for each register jump instruction in the first instruction stream, the corresponding source register number can be determined, and based on the source register number, the corresponding prefix opcode set of the register jump instruction can be determined. That is, for each register jump instruction in the first instruction stream, the corresponding prefix opcode set can be determined. The prefix opcode set represents a set consisting of all prefix opcodes used to write required data to the source register of the corresponding register jump instruction.

[0025] In an embodiment of the present invention, according to the number of source registers of the register jump instruction, an opcode of the source register number can be selected from a preset opcode library as a set of pre-opcodes corresponding to the register jump instruction. The preset opcode library may include but is not limited to opcodes such as ADD, SUB, MUL, DIV, INC, DEC, etc. that can be used to write data in a register. The above-mentioned method of selecting an opcode may include but is not limited to random selection, sequential selection, reverse selection, alternating selection, etc., which is not specifically limited in the embodiment of the present invention.

[0026] For example, if the first instruction stream includes a register jump instruction "JUMP_REG rd rs1 rs2", it can be determined that the number of source registers corresponding to it is 2, namely registers rs1 and rs2, and a prefix opcode set including two prefix opcodes can be generated, such as [ADD, SUB]. It should be noted that the prefix opcode set may include or not include a repeated opcode, which is not specifically limited in the embodiment of the present invention.

[0027] Step 103: Generate a second instruction stream based on the source register encoding of the register jump instruction and the preceding opcode set; wherein the second instruction stream is used to provide a jump address for the register jump instruction.

[0028] In an embodiment of the present invention, the source register code of the source register corresponding to the register jump instruction can also be obtained, and based on the source register code and the prefix operation code set corresponding to the register jump instruction, the second instruction corresponding to each prefix operation code in the prefix operation code set is generated to obtain a second instruction stream composed of the second instructions.

[0029] In an embodiment of the present invention, different types of prefix operation codes have different input methods. Some prefix operation codes only use source registers as data sources, some prefix operation codes only use immediate values ​​as operation sources, and other prefix operation codes may use both immediate values ​​and source registers as data sources.

[0030] Specifically, for the preceding opcode in the preceding opcode set, a source register code of the corresponding register jump instruction can be used as its destination register code. When it relies on the source register as the data source, the source register code corresponding to the preceding opcode is randomly generated, and based on the jump address of the register jump instruction, the register data is written into the source register corresponding to the preceding opcode; when it relies on the immediate number as the data source, the immediate number is determined according to the jump address of the register jump instruction, so that when the register jump instruction performs an instruction jump according to its source register data, it can jump to the corresponding jump address. Among them, the jump address corresponding to the register jump instruction can be generated according to a certain instruction address generation rule, or it can be selected from the first instruction stream and / or the second instruction stream, or it can be selected from other test instruction streams, and the embodiment of the present invention does not make specific limitations.

[0031] For example, if there is a register jump instruction "JUMP_REG rd rs1 rs2", the corresponding jump address is 60, the source register codes of the source registers rs1 and rs2 of the register jump instruction are 14 and 26 respectively, and the prefix opcode set corresponding to the register jump instruction is [ADD, SUB]. If the prefix opcodes in the prefix opcode set only use the source register as the data source, the destination register codes corresponding to the prefix opcodes ADD and SUB can be determined as 14 and 16 respectively (corresponding to the source register code of the register jump instruction), and the corresponding source register codes are randomly generated for the prefix opcodes ADD and SUB, so that the second instruction corresponding to the prefix opcode ADD is "ADD 14 17 25" (where 17 and 25 are the randomly generated source register codes corresponding to the prefix opcode ADD), and the second instruction corresponding to the prefix opcode SUB is "SUB 16 19 35". According to the jump address 60 of the register jump instruction, corresponding register data can be generated for the source registers of the preceding operation code ADD (i.e., register 17, register 25) and the source registers corresponding to the preceding operation code SUB (i.e., register 19, register 35), and written into the corresponding registers, so that after the actual execution results obtained by executing the preceding operation codes ADD and SUB are written into their registers 14 and 16, the register jump instruction can jump to the jump address 60 of the register jump instruction based on the register data in registers 14 and 16 to continue execution.

[0032] It should be noted that, continuing with the above example, since the prefix opcode set corresponding to the register jump instruction includes immediate value loading instructions such as LOAD_IMM, for example, the prefix opcode set can be [LOAD_IMM, LOAD_IMM], the destination register codes corresponding to the two prefix opcodes LOAD_IMM can be determined as 14 and 16 respectively, and the corresponding immediate value can be generated for each prefix opcode according to the jump address 60 of the register jump instruction, so that after the actual execution results obtained by executing the two prefix opcodes LOAD_IMM are written into their destination registers 14 and 16, the register jump instruction can jump to its jump address 60 based on the register data in registers 14 and 16 to continue execution. For example, the second instructions corresponding to each prefix opcode in the prefix opcode set may be "LOAD_IMM 14 7" and "LOAD_IMM 16 8", respectively, where 7 and 8 represent their immediate values, and 14 and 16 represent their destination register codes. After the second instructions corresponding to the above prefix opcodes are executed, 7 and 8 may be written into registers 14 and 16, respectively, so that when the register jump instruction is executed, it may jump to the instruction corresponding to the jump address 60 according to the register data of registers 14 and 16 to continue execution. It should be noted that, according to different instruction jump rules of register jump instructions, the method of generating the immediate value corresponding to the prefix opcode and the register data of the source register may be different. For example, if the register jump instruction accumulates the register data of its source register and multiplies the accumulated result by the address step (for example, 4) to obtain the jump address, the accumulated result of the immediate values ​​corresponding to each prefix opcode generated in the above example is 60 / 4=15.

[0033] Step 104, inserting the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test a central processing unit.

[0034] In an embodiment of the present invention, the second instructions corresponding to all the preceding opcodes of a register jump instruction may constitute a second instruction stream corresponding to the register jump instruction. The second instruction stream may be inserted into the first instruction stream to obtain a target instruction stream. Thus, during the execution of the target instruction stream, the first instruction stream may prepare and provide input data for the corresponding register jump instruction, ensuring that after executing the register jump instruction, the corresponding jump address may be correctly jumped to for continued execution. This not only ensures that each instruction in the first instruction stream is correctly executed, but also improves the complexity and randomness of the instruction stream used to test the CPU, which helps to improve the test effect.

[0035] Specifically, the second instruction stream can be directly inserted into the sequence position before the corresponding register jump instruction in the first instruction stream to obtain the target instruction stream, so that when the target instruction stream is executed sequentially, its corresponding second instruction stream can be executed first before the register jump instruction is executed, so that the corresponding input data can be prepared in its source register before the register jump instruction is executed.

[0036] In summary, in an instruction stream generation method provided by an embodiment of the present invention, a register jump instruction is determined from a first instruction stream; based on the number of source registers corresponding to the register jump instruction, a prefix opcode set corresponding to the register jump instruction is determined; based on the source register encoding and prefix opcode set of the register jump instruction, a second instruction stream is generated; wherein the second instruction stream is used to provide a jump address to the register jump instruction; and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream. A corresponding second instruction stream can be generated for the register jump instruction in the first instruction stream, and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream, so that when the CPU is tested through the target instruction stream, the jump address can be provided for the corresponding register jump instruction through the second instruction stream in the target instruction stream, so that the jump controllability of the register jump instruction in the target instruction stream can be improved, thereby improving the test stability when the CPU is tested through the target instruction stream.

[0037] Optionally, in some embodiments, the prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and the step of determining the prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction may specifically include: Step 1021: randomly select a first preceding opcode from a preset opcode library based on the number of source registers corresponding to the register jump instruction.

[0038] Step 1022: Based on the number of source registers corresponding to the first preceding operation code, randomly select a second preceding operation code corresponding to the first preceding operation code from a preset operation code library.

[0039] In the embodiment of the present invention, the prefix opcode set may include a first prefix opcode that directly generates input data of a corresponding register jump instruction, and a second prefix opcode that is used to generate data input for the first prefix opcode. That is, the prefix opcodes in the prefix opcode set may be divided into multiple levels, and the instructions generated by the prefix opcodes of different levels may perform data transfer level by level, and finally the first prefix opcode provides input data for the corresponding register jump instruction.

[0040] Specifically, based on the number of source registers corresponding to the register jump instruction, a first prefix opcode can be randomly selected from a preset opcode library, so that the number of first prefix opcodes is equal to the number of source registers corresponding to the register jump instruction; and for each first prefix opcode, based on the number of source registers corresponding to the first prefix opcode, a second prefix opcode corresponding to the first prefix opcode can be randomly selected from the preset opcode library, so that the number of second prefix opcodes corresponding to the first prefix opcode is equal to the number of source registers corresponding to the first prefix opcode.

[0041] For example, if there is a register jump instruction "JUMP_REG rd rs1 rs2", its corresponding prefix opcode set may include two first prefix opcodes for writing register data into the source registers rs1 and rs2 of the register jump instruction respectively, and each first prefix opcode may also have a corresponding second prefix opcode, and these second prefix opcodes may be used to write register data into the source register of the corresponding first prefix opcode. If the above two first prefix opcodes are ADD and SUM, respectively, the first prefix opcode ADD may correspond to two second prefix opcodes LOAD_IMM, and the first prefix opcode SUM may also correspond to two second prefix opcodes LOAD_IMM. The second prefix opcode LOAD_IMM may be used to write an immediate value into the source register of the first prefix opcode as the input data of the first prefix opcode.

[0042] It should be noted that the above-mentioned first prefix operation code and the second prefix operation code corresponding to the first prefix operation code can be randomly selected from a preset operation code library that can write data to the register. The second prefix operation code corresponding to the first prefix operation code can be an operation code that uses an immediate number as data input, or an operation code that uses a source register as data input. In the case that the second prefix operation code corresponding to the first prefix operation code uses the source register as data input, a corresponding second prefix operation code can be further selected for the second prefix operation code to write data to its source register, thereby forming multiple levels of second prefix operation codes.

[0043] Furthermore, in order to prevent the second preceding opcode level from expanding indefinitely, the maximum level of the second preceding opcode can be limited (for example, 2 levels). Then, when selecting the second preceding opcode of the maximum level, only the opcodes that use immediate numbers as data inputs can be selected from the preset opcode library.

[0044] In an embodiment of the present invention, a first pre-opcode can be randomly selected from a preset opcode library based on the number of source registers corresponding to the register jump instruction; and a second pre-opcode corresponding to the first pre-opcode can be randomly selected from the preset opcode library based on the number of source registers corresponding to the first pre-opcode. Not only can different types and numbers of pre-opcodes be generated for different register jump instructions, but also the same register jump instruction can also correspond to different types and numbers of pre-opcodes, which helps to provide a richer instruction combination method for register jump instruction input data in the target instruction stream generated subsequently, thereby improving the complexity and test accuracy of the target instruction stream.

[0045] Optionally, in some embodiments, the step of randomly selecting a second preceding opcode corresponding to the first preceding opcode from a preset opcode library based on the number of source registers corresponding to the first preceding opcode may specifically include: Step A1: based on the input data type corresponding to the first preceding operation code, determine a candidate operation code having an output data type that is the same as the input data type from the preset operation code library.

[0046] Step A2: based on the number of source registers corresponding to the first preceding operation code, randomly select a second preceding operation code corresponding to the first preceding operation code from the candidate operation codes.

[0047] In an embodiment of the present invention, since the input data types required by different first preceding operation codes may be different, when selecting the corresponding second preceding operation code for the first preceding operation code, it is also possible to select an operation code of the corresponding output data type from a preset operation code library as its candidate operation code based on the input data type of the first preceding operation code, and then select the corresponding second preceding operation code from the candidate operation code based on the number of source registers of the first preceding operation code, so that the input data type of the first preceding operation code is the same as the output data type of the corresponding second preceding operation code.

[0048] Exemplarily, if the input data type required by the first preceding opcode is an integer type, all integer opcodes whose output data type is an integer can be selected from a preset opcode library as candidate opcodes, and an integer opcode can be selected from these candidate opcodes as the corresponding second preceding opcode.

[0049] Accordingly, since the input data types required by different register jump instructions may be different, when selecting the corresponding first preceding opcode for the register jump instruction, it is also possible to select an opcode of the corresponding output data type from a preset opcode library as its candidate opcode based on the input data type of the register jump instruction, and then select the first preceding opcode of the source register number from the candidate opcodes based on the source register number of the register jump instruction, so that the input data type of the register jump instruction is the same as the output data type of the corresponding first preceding opcode.

[0050] In an embodiment of the present invention, based on the input data type corresponding to the first preceding operation code, a candidate operation code with the same output data type as the input data type can be determined from a preset operation code library; based on the number of source registers corresponding to the first preceding operation code, a second preceding operation code corresponding to the first preceding operation code is randomly selected from the candidate operation codes. The ability to select a second preceding operation code with the same output data type for first preceding operation codes with different input data types helps to improve the execution stability of a second instruction stream subsequently generated based on the preceding operation code set.

[0051] Optionally, in some embodiments, the prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and the step of generating a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set may specifically include: Step 1031 : Determine the destination register code corresponding to each first preceding operation code in the preceding operation code set based on the source register code of the register jump instruction.

[0052] In the embodiment of the present invention, since the first prefix operation code is used to write register data to the source register of the corresponding register jump instruction, the source register code of the register jump instruction corresponding to the first prefix operation code can be directly used as the destination register code corresponding to the first prefix operation code.

[0053] Step 1032, based on the destination register code corresponding to each first prefix operation code and the source register code randomly generated for each first prefix operation code, determine the second instruction corresponding to each first prefix operation code, and based on the source register code corresponding to each first prefix operation code, generate the second instruction corresponding to the second prefix operation code of each first prefix operation code.

[0054] In the embodiment of the present invention, a source register code may be randomly generated for the first preceding operation code, and a corresponding second instruction may be generated based on the destination register code and the source register code corresponding to the first preceding operation code.

[0055] Exemplarily, it is assumed that the randomly generated first instruction stream has a total of 24 instructions, wherein the 10th instruction is a register jump instruction JUMP_REG, and the register jump instruction JUMP_REG has a destination register JUMP_REG_rd, the destination register JUMP_REG_rd is encoded as 31, and has two source registers JUMP_REG_rs1 and JUMP_REG_rs2, the encoding of JUMP_REG_rs1 is 10, and the encoding of JUMP_REG_rs2 is 20. Then, for JUMP_REG_rs1 and JUMP_REG_rs2, the corresponding first preceding opcodes ADD and SUB can be randomly selected from the preset opcode library, respectively. If the first prefix operation code ADD has a destination register ADD_rd, two source registers ADD_rs1 and ADD_rs2, the destination register ADD_rd of the first prefix operation code ADD can be set to 10, and the source registers ADD_rs1 and ADD_rs2 of the first prefix operation code ADD can be set to random values ​​3 and 17 respectively, so as to obtain the second instruction "ADD 10 3 17" corresponding to the first prefix operation code ADD. If the first prefix operation code SUB has a destination register SUB_rd, two source registers SUB_rs1 and SUB_rs2, the destination register SUB_rd of the first prefix operation code SUB can be set to 20, and the source registers SUB_rs1 and SUB_rs2 of the first prefix operation code SUB can be set to random values ​​14 and 26 respectively, so as to obtain the second instruction "SUB 2014 26" corresponding to the first prefix operation code SUB.

[0056] In an embodiment of the present invention, the prefix operation code set may also include a second prefix operation code corresponding to the first prefix operation code, and each second prefix operation code may correspond to a source register of a first prefix operation code. For each second prefix operation code, the source register code of the corresponding first prefix operation code may be used as the destination register code of the second prefix operation code, and a source register code may be randomly generated for the second prefix operation code, thereby generating a second instruction corresponding to the second prefix operation code according to the destination register code and source register code corresponding to the second prefix operation code.

[0057] Optionally, in the case where the second preceding operation code is an immediate value load operation code, the immediate value of the second preceding operation code can be calculated according to the target execution result and operation mode of the corresponding first preceding operation code, and the corresponding second instruction can be generated according to the immediate value and destination register encoding corresponding to the second preceding operation code. The target execution result of the first preceding operation code indicates the value expected to be written in the destination register of the second instruction after the second instruction generated according to the first preceding operation code is executed.

[0058] Continuing with the above example, the prefix opcode set may further include second prefix opcodes corresponding to each first prefix opcode. Assuming that the source register of each first prefix opcode corresponds to a second prefix opcode, and these second prefix opcodes are all immediate load opcodes LOAD_IMM, then the destination registers of the second prefix opcodes LOAD_IMM1 to 4 may be set to 3, 17, 14, and 26, respectively, corresponding to a source register of a first prefix opcode, respectively. If the jump address of the register jump instruction JUMP_REG is 60, and the instruction jump rule of the register jump instruction JUMP_REG is to add the register data of JUMP_REG_rs1 and the register data of JUMP_REG_rs2, and use the product of the accumulated result and the address step 4 as the jump address, then the sum of the target execution result of the second instruction "ADD 10 3 17" and the target execution result of the second instruction "SUB 2014 26" can be taken as 60 / 4=15 as a condition to randomly generate the target execution result of the second instruction "ADD 10 3 17" = 30, and the target execution result of the second instruction "SUB 2014 26" = 30. 26" target execution result = -15, and further taking the sum of the immediate values ​​of the two second preceding operation codes LOAD_IMM1 to 2 corresponding to the first preceding operation code ADD as 30 as a condition, the immediate values ​​of the second preceding operation codes LOAD_IMM1 to 2 are randomly generated as 12 and 18 respectively, so that the sum of the two immediate values ​​is 30; taking the difference of the immediate values ​​of the two second preceding operation codes LOAD_IMM3 to 4 corresponding to the first preceding operation code SUB as -15 as a condition, the immediate values ​​of the second preceding operation codes LOAD_IMM3 to 4 are randomly generated as 37 and 52 respectively, so that the difference of the two immediate values ​​is equal to -15. Therefore, according to the destination register codes and immediate values ​​corresponding to the second preceding operation codes LOAD_IMM1 to 4, four second instructions can be generated, namely "LOAD_IMM 3 12", "LOAD_IMM 17 18", "LOAD_IMM 1437", and "LOAD_IMM 26 52".

[0059] Step 1033: Arrange the second instructions based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

[0060] In the embodiment of the present invention, since the source register of the second instruction corresponding to the first pre-opcode serves as the destination register of the second instruction corresponding to the second pre-opcode, and the source register of the second instruction corresponding to the second pre-opcode can also serve as the destination register of the second instruction corresponding to other second pre-opcodes, these second instructions can form different instruction levels, and there can be a read-after-write dependency relationship between the instructions of adjacent instruction levels. The second instructions can be arranged according to the read-after-write dependency relationship between the second instructions, so that in the second instruction pair (a pair of second instructions with the same destination register code and source register code) with the read-after-write dependency relationship, the second instruction that writes data to the same register is located before the second instruction that reads data from the same register, and the second instruction stream is obtained. It should be noted that the second instructions can be randomly arranged under the condition of satisfying the above constraints to obtain the second instruction stream, thereby improving the complexity and randomness of the second instruction stream, and improving the test accuracy of the target instruction stream obtained based on the second instruction stream.

[0061] Continuing with the above example, the second instruction may include "SUB 20 14 26", "ADD 10 3 17", "LOAD_IMM 312", "LOAD_IMM 17 18", "LOAD_IMM 14 37", and "LOAD_IMM 26 52". Among them, the source register code 14 of "SUB 20 14 26" is the same as the destination register code 14 of "LOAD_IMM 14 37", then "SUB 20 14 26" and "LOAD_IMM 14 37" may constitute a second instruction pair with a read-after-write dependency relationship; the source register code 26 of "SUB 20 14 26" is the same as the destination register code 26 of "LOAD_IMM 26 52", then "SUB 20 14 26" and "LOAD_IMM26 52" may constitute a second instruction pair with a read-after-write dependency relationship, and so on. According to the read-after-write dependency relationship between the second instructions, the above-mentioned 6 second instructions may generate the second instruction stream ["LOAD_IMM 26 52", "LOAD_IMM 1437", "SUB 20 14 26", "LOAD_IMM 3 12", "LOAD_IMM 17 18", "ADD 10 3 17"]; may also generate the second instruction stream ["LOAD_IMM 3 12", "LOAD_IMM 17 18", "LOAD_IMM 26 52", "LOAD_IMM 1437", "ADD 10 3 17", "SUB 20 14 26"]; may also generate the second instruction stream in other arrangement orders, which is not specifically limited in the embodiment of the present invention.

[0062] In the embodiment of the present invention, the second instruction corresponding to each first preceding operation code is determined based on the destination register code corresponding to each first preceding operation code and the source register code randomly generated for each first preceding operation code; the second instruction corresponding to the second preceding operation code of each first preceding operation code is generated based on the source register code corresponding to each first preceding operation code; the second instructions are arranged based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream. The second instructions in the second instruction stream can be executed sequentially according to the read-after-write dependency relationship, which helps to improve the execution stability of the instruction stream.

[0063] Optionally, in some embodiments, the step of generating a second instruction corresponding to a second preceding operation code of each first preceding operation code based on a source register code corresponding to each first preceding operation code may specifically include: Step B1, based on the jump address of the register jump instruction and the instruction jump rule corresponding to the register jump instruction, determine the target execution result of each first preceding operation code in the preceding operation code set.

[0064] In an embodiment of the present invention, the target execution result of each first preceding operation code in the corresponding preceding operation code set can be determined based on the jump address of the register jump instruction and the instruction jump rule corresponding to the register jump instruction. The target execution result of the first preceding operation code of the register jump instruction is the input data of the register jump instruction, and the instruction jump rule is used to describe how the register jump instruction calculates and jumps to the corresponding jump address based on the input data.

[0065] For example, if the instruction jump rule of the register jump instruction is: add the register data of the two source registers of the register jump instruction, and use the product of the accumulated result and 4 as the jump address. Then, when the jump address corresponding to the register jump instruction is 60, the target execution results of the two first prefix opcodes corresponding to the register jump instruction can be randomly generated as -15 and 30, respectively, so that the calculation result of ((-15)+30)×4 is equal to the jump address 60.

[0066] Step B2, based on the target execution result of each first preceding operation code and the operation rule of each first preceding operation code, determine the immediate value corresponding to the second preceding operation code of each first preceding operation code.

[0067] In an embodiment of the present invention, each first pre-opcode may correspond to a second pre-opcode for providing input data therefor, and the second pre-opcode may be an immediate number load opcode and a non-immediate number load opcode. In the case where the second pre-opcode is an immediate number load opcode, an immediate number may be generated for the second pre-opcode corresponding to the first pre-opcode according to the target execution result of the first pre-opcode, so that the calculation result obtained by calculating the immediate numbers of all second pre-opcodes corresponding to the first pre-opcode using the calculation rule corresponding to the first pre-opcode is equal to the target execution result corresponding to the first pre-opcode. Among them, different pre-opcodes may correspond to different calculation rules, for example, the calculation rule of the ADD opcode is register data addition, and the calculation rule of the SUB opcode is register data subtraction. The above calculation rules may include but are not limited to addition, subtraction, multiplication, division, etc., which are not specifically limited in the embodiment of the present invention.

[0068] Exemplarily, if the target execution results of the first prefix operation code SUB and the first prefix operation code ADD are -15 and 30 respectively, the sum of the immediate numbers of the two second prefix operation codes LOAD_IMM1 and LOAD_IMM2 corresponding to the first prefix operation code ADD can be taken as a condition that the immediate numbers of the second prefix operation codes LOAD_IMM1 and LOAD_IMM2 are 12 and 18 respectively, so that the sum of the two immediate numbers is 30; the difference between the immediate numbers of the two second prefix operation codes LOAD_IMM3 and LOAD_IMM4 corresponding to the first prefix operation code SUB is -15 as a condition, the immediate numbers of the second prefix operation codes LOAD_IMM3 and LOAD_IMM4 are randomly generated as 37 and 52 respectively, so that the difference between the two immediate numbers is equal to -15.

[0069] Step B3, based on the source register code corresponding to each first preceding operation code and the immediate value, generate a second instruction corresponding to the second preceding operation code of each first preceding operation code.

[0070] In an embodiment of the present invention, the target execution result of each first preceding operation code in the preceding operation code set can be determined based on the jump address of the register jump instruction and the instruction jump rule corresponding to the register jump instruction; the immediate number corresponding to the second preceding operation code of each first preceding operation code is determined based on the target execution result of each first preceding operation code and the operation rule of each first preceding operation code; and the second instruction corresponding to the second preceding operation code of each first preceding operation code is generated based on the source register code and the immediate number corresponding to each first preceding operation code. By configuring the immediate number in the second instruction, the jump address of the corresponding register jump instruction can be controlled, so that the register jump instruction can jump to the correct instruction to continue execution, which helps to improve the execution stability of the target instruction stream generated subsequently.

[0071] Optionally, in some embodiments, the jump address of the register jump instruction may be selected from a set of instruction addresses corresponding to the target instruction stream.

[0072] In an embodiment of the present invention, each instruction in the target instruction stream has a corresponding instruction address. In order to improve the operational stability of the target instruction stream and avoid jumping to an unreasonable address during the execution of the target instruction stream, the jump address of the register jump instruction can be selected from the instruction address set corresponding to the target instruction stream. Among them, the above instruction address set may include the instruction addresses corresponding to all instructions in the target instruction stream, and the above selection method may include but is not limited to random selection, sequential selection, reverse selection, alternating selection, etc., which is not specifically limited in the embodiment of the present invention.

[0073] It should be noted that the jump address corresponding to the register jump instruction may also be selected from some instruction addresses in the instruction address set of the target instruction stream. For example, the jump address of the register jump instruction may be selected from the instruction addresses corresponding to the first instructions in the first instruction stream of the instruction address set.

[0074] Exemplarily, if the instruction start address of the first instruction stream is 0, and the address difference between adjacent instructions is 4, and the first instruction stream contains 24 instructions, then the corresponding instruction address set can be {0, 4, 8, ..., 92, 96}. If the instruction address of a register jump instruction contained in the first instruction stream is 40, and the second instruction stream corresponding to the register jump instruction contains 8 instructions, which are inserted before the above-mentioned register jump instruction, the instruction address set corresponding to the second instruction stream obtained can be {0, 4, 8, ..., 124, 128}. The jump address of the register jump instruction can be randomly selected from the instruction address set corresponding to the second instruction stream, for example, the jump address can be selected to be 60. After determining the corresponding jump address for the register jump instruction, the immediate value or source register data corresponding to the second instruction in the corresponding second instruction set can be determined according to its jump address.

[0075] In the embodiment of the present invention, by selecting the jump address of the register jump instruction from the instruction address set corresponding to the target instruction stream, the target instruction stream can always jump between instructions within the instruction stream during re-execution, thus avoiding instruction jump errors and helping to improve the operation stability of the target instruction stream.

[0076] For example, if a register jump instruction is "JUMP_REG 48 10 20", its corresponding second instruction stream may be ["LOAD_IMM 3 12", "LOAD_IMM 17 18", "LOAD_IMM 26 52", "LOAD_IMM 14 37", "ADD10 3 17", "SUB 20 14 26"]. By executing the above second instruction stream, -15 can be written into register 20 and 30 can be written into register 10, so that after the above register jump instruction is executed, it jumps to the jump address ((-15) + 30) × 4 = 60, and the addition result of register 10 and register 20 is written into register 48 to record the instruction number corresponding to the jump address. The instruction numbers of the register jump instruction and the corresponding second instruction stream in the target instruction stream may be continuous, so that the second instruction stream prepares data in the source register corresponding to the register jump instruction before the corresponding register jump instruction is executed. For example, the instruction numbers of the second instruction stream and the corresponding register jump instruction in the above example may be as shown in Table 1 below: Table 1

[0077] Optionally, in some embodiments, the step of inserting the second instruction stream into the first instruction stream to obtain a target instruction stream may specifically include: Step 1041, determining the execution order corresponding to each first instruction in the first instruction stream.

[0078] In the embodiment of the present invention, due to the presence of register jump instructions or other jump instructions in the first instruction stream, the actual execution order of the first instructions in the first instruction stream may be different from their order in the first instruction stream. In order to enable the second instruction stream to be executed before the corresponding register jump instruction and improve the accuracy and stability of providing the jump address to the corresponding register jump instruction through the second instruction stream, the execution order corresponding to each first instruction in the first instruction stream can be determined.

[0079] Specifically, the first instruction stream may be simulated and run, and the running order of each first instruction in the first instruction stream during the simulation may be recorded. The operation code and operand of each first instruction in the first instruction stream may also be analyzed to determine the running order of each first instruction in the first instruction stream, which is not specifically limited in the embodiment of the present invention.

[0080] Step 1042: Select a target instruction from the first instructions whose execution order is less than or equal to the register jump instruction.

[0081] In an embodiment of the present invention, a first instruction whose execution order is less than or equal to the register jump instruction can be determined from the first instruction stream, that is, the first instruction whose execution order is less than or equal to the register jump instruction can include the first instruction whose execution order is less than the register jump instruction, and the register jump instruction itself. Then, from the first instructions whose execution order is less than or equal to the register jump instruction, a first instruction is selected as the target instruction corresponding to the register jump instruction. The above selection method may include but is not limited to random selection, rule selection, etc., and the embodiment of the present invention does not make specific limitations.

[0082] Step 1043: insert the second instruction stream before the target instruction in the first instruction stream to obtain a target instruction stream.

[0083] In an embodiment of the present invention, the second instruction stream of the register jump instruction can be inserted before the target instruction corresponding to the register jump instruction in the first instruction stream, thereby obtaining a target instruction stream composed of the first instruction stream and the second instruction stream. It should be noted that before the target instruction in the first instruction stream can refer to a position adjacent to the target instruction, or can refer to a position separated from the target instruction by one or more instructions, which is not specifically limited in the embodiment of the present invention.

[0084] In an embodiment of the present invention, since the first instruction stream may include multiple register jump instructions, each register jump instruction may generate a corresponding second instruction stream. Therefore, the target instruction stream generated based on the first instruction stream and the second instruction stream may include second instruction streams corresponding to multiple register jump instructions.

[0085] In an embodiment of the present invention, the target instruction stream is obtained by determining the execution order corresponding to each first instruction in the first instruction stream; selecting a target instruction from the first instructions whose execution order is less than or equal to the register jump instruction; and inserting the second instruction stream before the target instruction in the first instruction stream. Under the condition of ensuring the stable and accurate execution of the target instruction stream, the randomness of the insertion of the second instruction stream into the first instruction stream can be improved, which helps to improve the diversity and variability of the obtained target instruction stream, thereby improving the test accuracy and test efficiency of testing the CPU core through the target instruction stream.

[0086] Reference Figure 2 , shows a block diagram of an instruction stream generating device provided by an embodiment of the present invention, such as Figure 2 As shown, the device may specifically include: An instruction determination module 201, configured to determine a register jump instruction from a first instruction stream; An operation code determination module 202, configured to determine a set of preceding operation codes corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction; An instruction stream module 203, configured to generate a second instruction stream based on the source register encoding of the register jump instruction and the preceding opcode set; wherein the second instruction stream is used to provide a jump address to the register jump instruction; The insertion module 204 is used to insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test the central processing unit.

[0087] Optionally, the pre-opcode set includes a first pre-opcode and a second pre-opcode corresponding to the first pre-opcode, and the opcode determination module includes: A first pre-opcode submodule, configured to randomly select a first pre-opcode from a preset opcode library based on the number of source registers corresponding to the register jump instruction; The second pre-opcode submodule is used to randomly select a second pre-opcode corresponding to the first pre-opcode from a preset opcode library based on the number of source registers corresponding to the first pre-opcode.

[0088] Optionally, the second pre-operation code submodule includes: A candidate operation code unit, configured to determine a candidate operation code having an output data type that is the same as the input data type from the preset operation code library based on the input data type corresponding to the first preceding operation code; The second preceding operation code selection unit is used to randomly select a second preceding operation code corresponding to the first preceding operation code from the candidate operation codes based on the number of source registers corresponding to the first preceding operation code.

[0089] Optionally, the pre-opcode set includes a first pre-opcode and a second pre-opcode corresponding to the first pre-opcode, and the instruction stream module includes: a destination register encoding submodule, configured to determine, based on the source register encoding of the register jump instruction, the destination register encoding corresponding to each first preceding operation code in the preceding operation code set; an instruction determination submodule, configured to determine a second instruction corresponding to each first preceding operation code based on a destination register code corresponding to each first preceding operation code and a source register code randomly generated for each first preceding operation code, and to generate a second instruction corresponding to a second preceding operation code of each first preceding operation code based on the source register code corresponding to each first preceding operation code; The instruction stream determination submodule is used to arrange the second instructions based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

[0090] Optionally, the instruction determination submodule includes: a target execution result unit, configured to determine a target execution result of each first preceding operation code in the preceding operation code set based on a jump address of the register jump instruction and an instruction jump rule corresponding to the register jump instruction; An immediate value unit, for determining an immediate value corresponding to a second preceding operation code of each first preceding operation code based on a target execution result of each first preceding operation code and an operation rule of each first preceding operation code; The instruction generation unit is used to generate a second instruction corresponding to a second preceding operation code of each first preceding operation code based on a source register code corresponding to each first preceding operation code and the immediate value.

[0091] Optionally, the device further comprises: A jump address module is used to select a jump address of the register jump instruction from an instruction address set corresponding to the target instruction stream.

[0092] Optionally, the insertion module includes: An execution order submodule, used to determine the execution order corresponding to each first instruction in the first instruction stream; A target instruction submodule, used for selecting a target instruction from the first instruction whose execution order is less than or equal to the register jump instruction; The instruction stream insertion submodule is used to insert the second instruction stream before the target instruction in the first instruction stream to obtain a target instruction stream.

[0093] In summary, in the instruction stream generation device provided by the embodiment of the present invention, a register jump instruction is determined from the first instruction stream; based on the number of source registers corresponding to the register jump instruction, a prefix opcode set corresponding to the register jump instruction is determined; based on the source register encoding and prefix opcode set of the register jump instruction, a second instruction stream is generated; wherein the second instruction stream is used to provide a jump address to the register jump instruction; and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream. A corresponding second instruction stream can be generated for the register jump instruction in the first instruction stream, and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream, so that when the CPU is tested through the target instruction stream, the jump address can be provided for the corresponding register jump instruction through the second instruction stream in the target instruction stream, so that the jump controllability of the register jump instruction in the target instruction stream can be improved, thereby improving the test stability when the CPU is tested through the target instruction stream.

[0094] Reference Figure 3 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 3As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the instruction stream generation method of the above embodiment. The executable instructions can form a program.

[0095] An embodiment of the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the instruction stream generation method of the aforementioned embodiment.

[0096] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0097] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. It should be noted that all actions of acquiring signals, information or data in the present invention are carried out under the premise of complying with the corresponding data protection laws and policies of the country of residence and with the authorization given by the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0098] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0099] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0100] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0101] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0102] The above is a detailed introduction to an instruction stream generation method, an instruction stream generation device, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for generating an instruction stream, characterized in that: The method comprises: determining a register jump instruction from the first instruction stream; Determining a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction; Generate a second instruction stream based on the source register encoding of the register jump instruction and the preceding opcode set; wherein the second instruction stream is used to provide a jump address to the register jump instruction; Insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test a central processing unit.

2. The instruction stream generation method according to claim 1, characterized in that: The prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and determining the prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction includes: Based on the number of source registers corresponding to the register jump instruction, randomly select a first preceding opcode from a preset opcode library; Based on the number of source registers corresponding to the first preceding operation code, a second preceding operation code corresponding to the first preceding operation code is randomly selected from a preset operation code library.

3. The instruction stream generation method according to claim 2, characterized in that: The randomly selecting a second preceding opcode corresponding to the first preceding opcode from a preset opcode library based on the number of source registers corresponding to the first preceding opcode includes: Based on the input data type corresponding to the first preceding operation code, determining a candidate operation code having an output data type that is the same as the input data type from the preset operation code library; Based on the number of source registers corresponding to the first preceding operation code, a second preceding operation code corresponding to the first preceding operation code is randomly selected from the candidate operation codes.

4. The instruction stream generation method according to claim 1, characterized in that: The prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and the generating a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set includes: Determining, based on the source register code of the register jump instruction, the destination register code corresponding to each first preceding operation code in the preceding operation code set; Determine a second instruction corresponding to each first preceding operation code based on a destination register code corresponding to each first preceding operation code and a source register code randomly generated for each first preceding operation code, and generate a second instruction corresponding to a second preceding operation code of each first preceding operation code based on a source register code corresponding to each first preceding operation code; The second instructions are arranged based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

5. The instruction stream generation method according to claim 4, characterized in that: The generating, based on the source register code corresponding to each first preceding operation code, a second instruction corresponding to the second preceding operation code of each first preceding operation code comprises: Determining a target execution result of each first preceding opcode in the preceding opcode set based on a jump address of the register jump instruction and an instruction jump rule corresponding to the register jump instruction; Determine an immediate value corresponding to a second preceding operation code of each first preceding operation code based on a target execution result of each first preceding operation code and an operation rule of each first preceding operation code; Based on the source register code corresponding to each first preceding operation code and the immediate value, a second instruction corresponding to the second preceding operation code of each first preceding operation code is generated.

6. The instruction stream generation method according to claim 5, characterized in that: The method further comprises: A jump address of the register jump instruction is selected from an instruction address set corresponding to the target instruction stream.

7. The instruction stream generation method according to claim 1, characterized in that: Inserting the second instruction stream into the first instruction stream to obtain a target instruction stream includes: Determining an execution order corresponding to each first instruction in the first instruction stream; Selecting a target instruction from the first instruction whose execution order is less than or equal to the register jump instruction; The second instruction stream is inserted before the target instruction in the first instruction stream to obtain a target instruction stream.

8. An instruction stream generating device, characterized in that: The device comprises: An instruction determination module, used for determining a register jump instruction from a first instruction stream; An operation code determination module, configured to determine a set of preceding operation codes corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction; An instruction stream module, configured to generate a second instruction stream based on the source register encoding of the register jump instruction and the preceding opcode set; wherein the second instruction stream is configured to provide a jump address to the register jump instruction; The insertion module is used to insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test the central processing unit.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the instruction stream generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Instructions are stored thereon, and when executed by one or more processors, the processors are caused to execute the instruction stream generation method according to any one of claims 1 to 7.

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