An instruction stream generation method, apparatus, electronic device, and storage medium

Abstract

An embodiment of the present invention provides an instruction stream generation method, apparatus, electronic device, and storage medium, which relate to the field of computer technologies, and include: obtaining instruction stream description information generated based on a preset opcode sequence; determining a first register code corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information; the first register codes corresponding to the same register identifier are the same; generating a first instruction corresponding to each instruction description entry based on the first register code and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtaining a first instruction stream composed of the first instructions corresponding to each instruction description entry. Through this solution, an instruction stream with a fixed instruction order and register dependencies can be generated, which helps to accurately locate problems in the processor core when testing with these instruction streams and helps to improve the test accuracy when the instruction stream is used for testing the processor core.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technologies, and particularly to an instruction stream generation method, apparatus, electronic device, and storage medium. Background Art

[0002] Currently, with the continuous development of computer technologies, the design of the Central Processing Unit (CPU) is becoming increasingly complex. How to verify it during the design and development process of the CPU is of increasing importance in the CPU development process.

[0003] In related technologies, an instruction generator is usually used to randomly generate a continuous stream of instructions and input them into an emulated CPU core or a physical CPU core, and the CPU is tested by observing its processing and response to these instruction streams. Among these instruction streams, there need to be not only instructions with different operation codes, but also instruction pairs composed of operation code pairs with dependency relationships, so as to test whether the CPU can correctly process different instructions and instruction combinations.

[0004] However, when testing by randomly selecting operation codes and randomly generating instruction streams, due to the complexity of the processor core, completely random instruction streams will result in non-reproducible test results, making it impossible to accurately locate occasional errors and difficult to accurately locate defects in the processor core. Therefore, there is a problem of poor test accuracy when using the instruction streams generated by the prior art to test the processor core. Summary of the Invention

[0005] Embodiments of the present invention provide an instruction stream generation method, apparatus, electronic device, and storage medium, which can generate instruction streams with relatively high test accuracy when testing a processor core.

[0006] To solve the above problems, embodiments of the present invention disclose an instruction stream generation method, which includes:

[0007] Obtain instruction stream description information generated based on a preset operation code sequence; wherein, the instruction stream description information includes instruction description entries composed of the operation code identifiers and register identifiers corresponding to each preset operation code in the preset operation code sequence;

[0008] Based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, determine the first register encoding corresponding to each instruction description entry; wherein, the first register encodings corresponding to the same register identifier are the same;

[0009] Generate a first instruction corresponding to each instruction description entry based on the first register encoding and opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein, the first instruction stream is used to test a central processing unit.

[0010] On the other hand, an embodiment of the present invention discloses an instruction stream generation device, and the device includes:

[0011] An acquisition module, configured to acquire instruction stream description information generated based on a preset opcode sequence; wherein, the instruction stream description information includes instruction description entries composed of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence;

[0012] An encoding module, configured to determine a first register encoding corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information; wherein, the first register encodings corresponding to the same register identifier are the same;

[0013] An instruction stream module, configured to generate a first instruction corresponding to each instruction description entry based on the first register encoding and opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein, the first instruction stream is used to test a central processing unit.

[0014] In yet another aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete mutual communication through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the foregoing method.

[0015] An embodiment of the present invention further discloses a computer-readable storage medium, on which instructions are stored, and when executed by one or more processors, cause the processors to execute the method as described above.

[0016] The embodiments of the present invention have the following advantages: In the instruction stream generation method provided in the embodiments of the present invention, instruction stream description information generated based on a preset opcode sequence is obtained; wherein, the instruction stream description information includes instruction description entries composed of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence; based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, a first register code corresponding to each instruction description entry is determined; wherein, the first register codes corresponding to the same register identifier are the same; based on the first register code and opcode identifier corresponding to each instruction description entry in the instruction stream description information, a first instruction corresponding to each instruction description entry is generated, and a first instruction stream composed of the first instructions corresponding to each instruction description entry is obtained. In this way, an instruction stream with a fixed instruction order can be automatically generated through the preset opcode sequence, and the instructions in the generated instruction stream can share the same register code, so that the same register corresponding to the same register code can be operated on by the same or different instructions in the instruction stream with a fixed instruction order, generating a register dependency relationship. Therefore, through this solution, an instruction stream with a fixed instruction order and a register dependency relationship can be generated, which helps to accurately locate problems in the processor core when testing with these instruction streams, and helps to improve the test accuracy when the instruction stream is used for testing the processor core. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings according to these drawings without creative efforts.

[0018] Figure 1 is a flowchart of the steps of an instruction stream generation method provided by an embodiment of the present invention;

[0019] Figure 2 is a block diagram of an instruction stream generation device provided by an embodiment of the present invention;

[0020] Figure 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0022] Reference Figure 1 , which shows the step flowchart of an instruction stream generation method provided by an embodiment of the present invention. As shown in Figure 1 , the method may specifically include the following steps:

[0023] Step 101, obtain instruction stream description information generated based on a preset opcode sequence; wherein, the instruction stream description information includes instruction description entries formed by opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence.

[0024] In an embodiment of the present invention, the preset opcode sequence represents a sequence formed by arranging multiple opcodes in a certain order. The preset opcode sequence may consist only of opcodes, or the preset opcode sequence may be determined by extracting the opcodes corresponding to each instruction in a preset instruction stream. Exemplarily, a preset opcode sequence consisting of 3 opcodes may be [ADD, SUB, ADD]. Among them, the preset instruction stream may represent an already generated instruction stream. For example, if a user generates an instruction stream in other ways and hopes to continue generating a similar instruction stream according to the instruction order of this instruction stream for further testing, then this instruction stream can be used as the preset instruction stream.

[0025] In an embodiment of the present invention, corresponding instruction stream description information can be generated according to the preset opcode sequence. The instruction stream description information includes instruction description entries corresponding one-to-one to those in the preset opcode sequence, and each instruction description entry may be composed of an opcode identifier and a register identifier. Among them, the opcode identifier is used to indicate the opcode corresponding to the instruction description entry in the preset opcode sequence.

[0026] According to different opcode identifiers corresponding to the instruction description entries, the number and types of register identifiers corresponding to the instruction description entries may also be different. For example, the register identifier can be further divided into a destination register identifier and a source register identifier. Exemplarily, since the opcode identifier ADD can be used to add the register data in two source registers and store the added result in a destination register, the instruction description entry corresponding to the opcode identifier ADD may have 2 source register identifiers (rs0, rs1) and 1 destination register identifier (rd); since the opcode identifier LUI (Load Upper Immediate) is used to load an immediate number into the high bit of a register, its corresponding instruction description entry may only have 1 destination register identifier (rd).

[0027] Continuing with the above example, the instruction stream description information corresponding to the preset opcode sequence [ADD, SUB, ADD] may be as described in Table 1 below:

[0028] Table 1

[0029]

[0030] As described in Table 1 above, the opcode identifier corresponding to the first instruction description entry in the instruction stream description information is ADD, and the three register identifiers are respectively rd = udf_str0, rs0 = 12, rs1 = 20. Among them, udf_str0 is the register identifier of the destination register rd, and 12 and 20 are the register identifiers of the source registers rs0 and rs1 respectively; the opcode identifier corresponding to the second instruction description entry is SUB, and the three register identifiers are respectively rd = udf_str1, rs0 = 32, rs1 = 7. Among them, udf_str1 is the register identifier of the destination register rd, and 32 and 7 are the register identifiers of the source registers rs0 and rs1 respectively; the opcode identifier corresponding to the third instruction description entry is ADD, and the three register identifiers are respectively rd = 3, rs0 = udf_str0, rs1 = udf_str1. Among them, 3 is the register identifier of the destination register rd, and udf_str0 and udf_str1 are the register identifiers of the source registers rs0 and rs1 respectively. It should be noted that the above register identifiers are represented in forms such as numbers, strings, etc., and the embodiments of the present invention do not make specific limitations.

[0031] Step 102: Based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, determine the first register code corresponding to each instruction description entry; wherein, the first register codes corresponding to the same register identifier are the same.

[0032] In the embodiments of the present invention, the instruction stream description information may include one or more groups of the same register identifiers, that is, different instruction description entries in the instruction stream description information may have the same register identifier, and the same instruction description entry may also have the same register identifier. As shown in Table 1 above, the rd register identifier of the first instruction description entry in the instruction stream description information may be the same as the rs0 register identifier of the third instruction description entry.

[0033] In the embodiments of the present invention, for each register identifier in the instruction stream description information, a corresponding register code can be generated, so as to obtain the first register code corresponding to each instruction description entry. During the generation process, the first register codes generated for the same register identifier can be made the same.

[0034] In the embodiments of the present invention, the same register identifier of different instruction description entries can be used to indicate that the instructions to be generated by different instruction description entries use the same register, so that there can be a dependency relationship between the registers operated by the instructions generated by different or the same instruction description entries. These dependency relationships can include, but are not limited to, read-after-write dependency relationships, write-after-read dependency relationships, write-after-write dependency relationships, read-after-read dependency relationships, and so on. Exemplarily, a read-after-write dependency relationship means that during the execution of an instruction stream, the source register used in the execution of a subsequent instruction is the same as the destination register of a previous instruction, that is, the execution of the subsequent instruction uses the output data of the previous instruction as its input data.

[0035] Specifically, the method of generating the corresponding first register code according to the register identifier can be rule-based calculation. For example, the register identifier can be used as the input of an encoding function, and the output of the encoding function can be used as the first register code corresponding to the register identifier; it can also be randomly generated. For example, a number can be randomly generated for each register identifier as the corresponding first register code; it can also be randomly selected within a preset encoding range. For example, a register code library can be preset in advance, and then for each register identifier, a code can be randomly selected from the above register code library as the corresponding first register code; when the register identifier is a number, the register identifier can also be directly used as the corresponding first register code. The embodiments of the present invention do not specifically limit the method of generating the first register code.

[0036] Exemplarily, for the instruction stream description information shown in Table 1 above, the digital register identifier can be directly used as the first register code of the corresponding register identifier, and a corresponding first register code can be randomly generated for the string register identifier, so that the first register codes corresponding to the same register identifier are the same, that is, the first register codes determined according to the same register identifier are the same. The first register codes corresponding to each instruction description entry shown in Table 2 below can be obtained:

[0037] Table 2

[0038]

[0039] Step 103: Generate a first instruction corresponding to each instruction description entry based on the first register code and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein, the first instruction stream is used to test the central processing unit.

[0040] In an embodiment of the present invention, after obtaining the first register encoding and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, the opcode identifier can be used as the opcode, and the first register encoding can be used as the operand to generate a first instruction corresponding to each instruction description entry. Thus, the first instructions can be arranged in the order of the corresponding instruction description entries to form a first instruction stream. Therefore, in this first instruction stream, there can be dependency instruction pairs that share the same register.

[0041] Exemplarily, according to the first register encoding and the opcode identifier corresponding to each instruction description entry shown in Table 2 above, the first instructions corresponding to each instruction description entry can be generated as shown in Table 3 below:

[0042] Table 3

[0043]

[0044] The three first instructions shown in Table 3 above can form a first instruction stream. In the first instruction stream, first execute the first instruction 1, write the execution result into register 25, then execute the first instruction 2, write the execution result into register 13, and finally execute the first instruction 3 to perform calculations based on the data in register 25 and register 13, and write the execution result into register 3. Thus, the first instruction 1 and the first instruction 3 form a dependency instruction pair with a read-after-write dependency relationship, and the first instruction 2 and the first instruction 3 also form a dependency instruction pair with a read-after-write dependency relationship.

[0045] Through the above operations, the instruction order of the first instructions in the first instruction stream is the same as the preset opcode sequence, and the first instruction stream can contain dependency instruction pairs that share the same register. Therefore, a first instruction stream containing dependency instruction pairs with a specific instruction order can be quickly generated. This first instruction stream can be used to test the processor core, which helps to improve the test efficiency of processor testing based on the instruction stream.

[0046] In summary, in the instruction stream generation method provided by the embodiments of the present invention, instruction stream description information generated based on a preset opcode sequence is obtained; wherein, the instruction stream description information includes instruction description entries composed of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence; based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, a first register code corresponding to each instruction description entry is determined; wherein, the first register codes corresponding to the same register identifier are the same; based on the first register codes and opcode identifiers corresponding to each instruction description entry in the instruction stream description information, a first instruction corresponding to each instruction description entry is generated, and a first instruction stream composed of the first instructions corresponding to each instruction description entry is obtained. In this way, an instruction stream with a fixed instruction order can be automatically generated through the preset opcode sequence, and the instructions in the generated instruction stream can share the same register code, so that the same register corresponding to the same register code can be operated on by the same or different instructions in the instruction stream with a fixed instruction order, generating a register dependency relationship. Therefore, through this solution, an instruction stream with a fixed instruction order and a register dependency relationship can be generated, which helps to accurately locate problems in the processor core when testing with these instruction streams, and helps to improve the test accuracy of the instruction stream for processor core testing.

[0047] Optionally, in some embodiments, the preset opcode sequence may include dependent opcode pairs, and the step of obtaining the instruction stream description information generated based on the preset opcode sequence may specifically include:

[0048] Step 1011, based on the dependency relationship of the dependent opcode pair, determine the dependent registers corresponding to each opcode in the dependent opcode pair.

[0049] In the embodiments of the present invention, among the opcodes in the preset opcode sequence, dependent opcode pairs can be formed. A dependent opcode pair represents an opcode pair that can generate a pair of instructions with a dependency relationship. The pair of instructions with a dependency relationship can operate on the same register during execution, and the above operations can include reading and writing.

[0050] In one implementation manner, the dependent opcode pair can be set by a technician for the opcodes in the preset operation sequence, that is, the dependent opcode pair can be specified in the preset opcode sequence, so as to form dependent opcode information as additional information of the preset opcode sequence. The dependent opcode information can indicate the dependent opcode pairs in the preset opcode sequence and the type of dependency relationship of each dependent opcode pair.

[0051] In another embodiment, the preset opcode sequence can be traversed, and according to the sequence order and register types among the opcodes in the preset opcode sequence, the opcodes are automatically paired to form dependent opcode pairs, and the type of the dependency relationship of each dependent opcode pair is determined. Specifically, during the traversal of the preset opcode sequence, an opcode can be selected as the pre-order opcode, and a dependency relationship is determined. Then, an opcode having the above dependency relationship with the pre-order opcode is selected from the opcodes after the pre-order opcode in the preset opcode sequence as the post-order opcode of the pre-order opcode, and a dependent opcode pair composed of the pre-order opcode and the post-order opcode is obtained. It should be noted that the selected dependent opcode pairs from the preset opcode sequence can be all or part. For example, a preset quantity can be set, and a preset quantity of dependent opcode pairs are selected from the preset opcode sequence. In order to enable two registers corresponding to the same instruction description entry (for example, a source register and a destination register of the same instruction description entry) to also form a dependent register pair, the opcode of the same instruction description entry can also be used to construct a dependent opcode pair.

[0052] In the embodiments of the present invention, each dependent opcode pair can correspond to a dependency relationship, and this dependency relationship is used to indicate the register shared by the dependent opcode pair, that is, the dependent register. Multiple types of dependency relationships can be preset, and different types of dependency relationships can correspond to different dependent registers. Exemplarily, the dependency relationship can include type 1, type 2, and type 3; among them, type 1 can indicate that the destination register of the pre-order opcode in the dependent opcode pair and the first source register of the post-order opcode are dependent registers; type 2 can indicate that the destination register of the pre-order opcode in the dependent opcode pair and the second source register of the post-order opcode are dependent registers; type 3 can indicate that the destination register of the pre-order opcode in the dependent opcode pair and the third source register of the post-order opcode are dependent registers. The embodiments of the present invention do not specifically limit the types of the dependency relationship, and those skilled in the art can flexibly set the types of the dependency relationship according to actual needs and set the corresponding dependent register determination methods for different types of dependency relationships.

[0053] Exemplarily, if the preset opcode sequence is as shown in Table 4 below:

[0054] Table 4

[0055]

[0056] Among them, the dependent opcode pairs may include (opcode 1 - opcode 2), (opcode 2 - opcode 5), (opcode 4 - opcode 5), (opcode 7 - opcode 8). The dependency relationships of all the above dependent opcode pairs can be of type 1. Then, the destination register corresponding to the previous opcode and one source register corresponding to the subsequent opcode of the above dependent opcode pairs can be determined as a dependent register pair. For example, it can be determined that the rd of opcode 1 and rs0 of opcode 2 form a dependent register pair, the rd of opcode 2 and rs1 of opcode 5 form a dependent register pair, the rd of opcode 4 and rs0 of opcode 5 form a dependent register pair, and the rd of opcode 7 and rs0 of opcode 8 form a dependent register pair.

[0057] It should be noted that the dependent registers corresponding to each opcode in the preset opcode sequence can be determined in the above manner, or can be directly specified and set by those skilled in the art. The embodiments of the present invention do not make specific limitations.

[0058] Optionally, in some embodiments, the dependency relationship may include a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship. Based on the dependency relationship of the dependent opcode pair, the steps of determining the dependent registers corresponding to each opcode in the dependent opcode pair may specifically include:

[0059] Step A1, when the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, use the destination register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and use one source register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode.

[0060] In the embodiments of the present invention, the dependency relationship may also include a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship. If the dependency relationship of the dependent opcode pair is a read-after-write dependency relationship, it means that the register into which the previous opcode in the dependent opcode pair writes data should be the same as the register from which the subsequent opcode in the dependent opcode pair reads data. That is, the destination register of the previous opcode and one source register of the subsequent opcode can be used as dependent registers to form the dependent register pair of the dependent opcode pair.

[0061] Exemplarily, in the dependent opcode pair (opcode 1 - opcode 2) of the preset opcode sequence shown in Table 4 above, opcode 1 is the previous opcode and opcode 2 is the subsequent opcode. If the dependency relationship of the dependent opcode pair is a read-after-write dependency relationship, the rd register of opcode 1 can be used as its dependent register, and the rs0 or rs1 register of opcode 2 can be used as its dependent register.

[0062] Step A2, when the dependency relationship of the dependent opcode pair is the write-after-write dependency relationship, use the destination register of the preceding opcode in the dependent opcode pair as the dependency register of the preceding opcode, and use the destination register of the succeeding opcode in the dependent opcode pair as the dependency register of the succeeding opcode.

[0063] In the embodiment of the present invention, if the dependency relationship of the dependent opcode pair is the write-after-write dependency relationship, it means that the register to which the preceding opcode in the dependent opcode pair writes data should be the same as the register to which the succeeding opcode in the dependent opcode pair writes data. That is, the destination register of the preceding opcode and the destination register of the succeeding opcode can be used as the dependency registers to form the dependency register pair of the dependent opcode pair.

[0064] Exemplarily, in the dependent opcode pair (opcode 2 - opcode 5) of the preset opcode sequence shown in Table 4 above, opcode 2 is the preceding opcode and opcode 5 is the succeeding opcode. If the dependency relationship of this dependent opcode pair is the write-after-write dependency relationship, the rd register of opcode 2 can be used as its dependency register, and the rd register of opcode 5 can be used as its dependency register.

[0065] Step A3, when the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, use one source register of the preceding opcode in the dependent opcode pair as the dependency register of the preceding opcode, and use the destination register of the succeeding opcode in the dependent opcode pair as the dependency register of the succeeding opcode.

[0066] In the embodiment of the present invention, if the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, it means that the register from which the preceding opcode in the dependent opcode pair reads data should be the same as the register to which the succeeding opcode in the dependent opcode pair writes data. That is, one source register of the preceding opcode and the destination register of the succeeding opcode can be used as the dependency registers to form the dependency register pair of the dependent opcode pair.

[0067] Exemplarily, in the dependent opcode pair (opcode 7 - opcode 8) of the preset opcode sequence shown in Table 4 above, opcode 7 is the preceding opcode and opcode 8 is the succeeding opcode. If the dependency relationship of this dependent opcode pair is the read-after-write dependency relationship, the rs0 or rs1 register of opcode 7 can be used as its dependency register, and the rd register of opcode 8 can be used as its dependency register.

[0068] Step A4, in the case that the dependency relationship of the dependent opcode pair is the read-after-read dependency relationship, use one source register of the preceding opcode in the dependent opcode pair as the dependency register of the preceding opcode, and use one source register of the succeeding opcode in the dependent opcode pair as the dependency register of the succeeding opcode.

[0069] In the embodiments of the present invention, if the dependency relationship of the dependent opcode pair is the read-after-read dependency relationship, it means that the register from which the preceding opcode in the dependent opcode pair reads data should be the same as the register from which the succeeding opcode in the dependent opcode pair reads data. That is, one source register of the preceding opcode and one source register of the succeeding opcode can be used as the dependency registers to form the dependency register pair of the dependent opcode pair.

[0070] Exemplarily, in the dependent opcode pair (opcode 1 - opcode 2) of the preset opcode sequence shown in Table 4 above, opcode 1 is the preceding opcode and opcode 2 is the succeeding opcode. If the dependency relationship of the dependent opcode pair is the read-after-read dependency relationship, then the rs0 or rs1 register of opcode 1 can be used as its dependency register, and the rs0 or rs1 register of opcode 2 can be used as its dependency register.

[0071] In the embodiments of the present invention, the dependency registers of each opcode in the dependent opcode pair can be automatically determined according to the dependency relationship of the dependent opcode pair, which helps to improve the efficiency of generating the instruction stream of this solution. And in the case where an opcode corresponds to multiple source registers or destination registers, a register can be randomly selected from multiple registers as the dependency register, which helps to improve the randomness of the subsequent generated instruction stream. Furthermore, when testing the processor core with an instruction stream with higher randomness, the test accuracy can be improved.

[0072] Step 1012, generate register identifiers corresponding to the dependency registers of each opcode in the dependent opcode pair; wherein, the register identifiers corresponding to the dependency registers of each opcode in a dependent opcode pair are the same.

[0073] In the embodiments of the present invention, the preset opcode sequence may include dependent opcodes that form a dependent opcode pair, and independent opcodes that do not belong to any dependent opcode pair. Dependent opcodes can correspond to dependency registers, while independent opcodes correspond to independent registers. In the embodiments of the present invention, for the dependency registers of the two opcodes in each dependent opcode pair, the same register identifier can be generated.

[0074] Exemplarily, if in the dependent opcode pair (opcode 1 - opcode 2) shown in Table 4 above, the registers corresponding to each opcode are as shown in Table 5 below:

[0075] Table 5

[0076]

[0077] Among them, the dependent register pair of the dependent opcode pair includes rd of opcode 1 (LUI) and rs0 of opcode 2 (MOVE). For these two dependent register pairs, the same register identifier can be generated, such as 33 or udf_str1. For the independent register rd of opcode 2 (MOVE), the corresponding register identifier can be randomly generated separately, such as 10 or udf_str10.

[0078] Step 1013, generate the instruction stream description information based on the opcode identifier and register identifier corresponding to each opcode in the preset opcode sequence.

[0079] In the embodiment of the present invention, different register identifiers can be generated for the independent registers corresponding to each opcode in the preset opcode sequence. For the dependent registers of each dependent opcode pair in the preset opcode sequence, the same register identifier can be generated. Thus, the register identifiers of all registers corresponding to each opcode in the preset opcode sequence are obtained. Furthermore, the instruction stream description information can be generated based on the opcode identifier and register identifier corresponding to each opcode in the preset opcode sequence.

[0080] Optionally, the generation process of the above register identifier can be random generation, or randomly selected within a preset identifier range, or sequentially selected from a dataset. For example, positive integers are sequentially selected from 1 in the set of positive integers as the register identifier. The embodiment of the present invention does not make specific limitations.

[0081] In the embodiment of the present invention, based on the dependency relationship of the dependent opcode pair, determine the dependent registers corresponding to each opcode in the dependent opcode pair; generate the register identifiers corresponding to the dependent registers of each opcode in the dependent opcode pair; among them, the register identifiers corresponding to the dependent registers of each opcode in the dependent opcode pair are the same; generate the instruction stream description information based on the opcode identifier and register identifier corresponding to each opcode in the preset opcode sequence. The corresponding instruction stream description information can be automatically generated according to the preset opcode sequence, which helps to improve the efficiency of generating the instruction stream based on the preset opcode sequence.

[0082] Optionally, in some embodiments, the step of determining the first register encoding corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information may specifically include:

[0083] Step 1021, determine the encoding rule corresponding to each register identifier in each instruction description entry.

[0084] In the embodiments of the present invention, the operation codes in the preset operation code sequence may have different attributes, such as dependent operation codes and independent operation codes. Therefore, different methods can be used to generate the corresponding register encodings for different types of operation codes, that is, different encoding rules can be adopted when generating the register encodings corresponding to different register identifiers. Moreover, since there are differences in the types or ranges of registers corresponding to operation codes with different functions, different encoding rules can be adopted for the register encodings corresponding to different operation codes to ensure the stable operation of the subsequent generated instruction stream.

[0085] In one embodiment, different types of register identifiers can be set for the dependent operation codes and the independent operation codes respectively, so that the encoding rules corresponding to each register identifier can be determined according to the identifier types of the register identifiers in the instruction description entry.

[0086] In another embodiment, different types of register identifiers can be set for operation codes with different functions, so that different encoding rules can be adopted for operation codes with different functions to generate more reasonable register encodings for them. For example, for the ADD operation code, the corresponding encoding rule can be set as Rule 1; for the SUB operation code, the corresponding encoding rule can be set as Rule 2, etc., which are not specifically limited in the embodiments of the present invention.

[0087] Optionally, in some embodiments, the identifier types of the register identifiers include numerical types and string types. The step of determining the encoding rules corresponding to each register identifier in each instruction description entry may specifically include:

[0088] Step B1, for the register identifier with the identifier type of the numerical type, determine that the encoding rule corresponding to the register identifier is the first rule.

[0089] Step B2, for the register identifier with the identifier type of the string type, determine that the encoding rule corresponding to the register identifier is the second rule.

[0090] In the embodiments of the present invention, the identifier types of the register identifiers may include numerical types and string types. For example, numerical type register identifiers can be generated for independent operation codes, and string type register identifiers can be generated for dependent operation codes. Thus, when generating the first instruction stream according to the instruction stream description information, the register identifiers in each instruction description entry can be analyzed. For the register identifiers of the numerical type, it is determined that the corresponding encoding rule is the first rule; for the register identifiers of the string type, it is determined that the corresponding encoding rule is the second rule.

[0091] The embodiments themselves can generate different types of register identifiers and determine their encoding rules according to the identifier types of the register identifiers. Specifically, the register identifiers can be generated as numerical types and string types, which helps to improve the efficiency of distinguishing the encoding rules corresponding to the register identifiers, and the register identifiers of the numerical type can also directly participate in the generation process of subsequent register encodings, which helps to improve the generation efficiency of subsequent register encodings.

[0092] Step 1022, based on each register identifier and the encoding rule corresponding to each register identifier, generate the first register encoding corresponding to each register identifier in each instruction description entry.

[0093] In the embodiments of the present invention, the encoding rule can include an encoding generation method and can also include an encoding selection range. Exemplarily, one encoding rule can be: randomly select a positive integer from the set A of positive integers as the register encoding; another encoding rule can be: randomly select a positive integer from the set B of positive integers as the register encoding; still another encoding rule can include: input the register identifier into a preset equation and obtain the value output by the preset equation as the register encoding; the encoding rule can be flexibly set according to actual needs, and the embodiments of the present invention do not make specific limitations.

[0094] In the embodiments of the present invention, by determining the encoding rule corresponding to each register identifier in each instruction description entry; based on each register identifier and the encoding rule corresponding to each register identifier, generate the first register encoding corresponding to each register identifier in each instruction description entry. This helps to improve the adaptation degree of the first register encoding and the corresponding operation code, and helps to improve the execution stability of the first instruction stream generated subsequently.

[0095] Optionally, in some embodiments, the step of generating the first register encoding corresponding to each register identifier in each instruction description entry based on each register identifier and the encoding rule corresponding to each register identifier may specifically include:

[0096] Step C1, when the encoding rule of the register identifier corresponding to the instruction description entry is the first rule, use the register identifier as the first register encoding corresponding to the register identifier.

[0097] In the embodiments of the present invention, the encoding rule may specifically include a first rule and a second rule. If the encoding rule of the register encoding corresponding to the instruction description entry is the first rule, the register flag can be directly used as the first register encoding corresponding to the instruction description entry, that is, the encoding method of the first rule is direct encoding based on the register identifier. The encoding rule corresponding to the register identifier of the numerical type can be determined as the first rule.

[0098] Step C2, when the encoding rule of the register identifier corresponding to the instruction description entry is the second rule, obtain a random number generated for the register identifier as the first register encoding corresponding to the register identifier.

[0099] In the embodiment of the present invention, if the encoding rule of the register encoding corresponding to the instruction description entry is the second rule, a random number corresponding to the register identifier can be generated, and the random number is used as the first register encoding corresponding to the corresponding instruction description entry. It should be noted that in each round of instruction generation process, the first register encoding determined for the same register identifier is the same, that is, if the instruction stream description information contains multiple identical register identifiers corresponding to the second rule, then for these identical register identifiers, 1 random number generation can be performed, and the generated random number is used as the first register encoding of these identical register identifiers, so as to determine the first register encoding corresponding to multiple identical register identifiers through 1 random number generation, improving the encoding efficiency.

[0100] In the embodiment of the present invention, the encoding rule corresponding to the register identifier of the string type can be determined as the second rule, or the encoding rule corresponding to the register identifier of the numerical type can be determined as the second rule, and the embodiment of the present invention does not make specific limitations.

[0101] Exemplarily, if there is a preset opcode sequence Seq as shown in Table 4, the source registers and destination registers required for each opcode in the preset opcode sequence Seq are as shown in Table 6 below:

[0102] Table 6

[0103]

[0104] Among them, opcode 1 and opcode 2 can be set as a dependent opcode pair, opcode 2 and opcode 5 can be set as a dependent opcode pair, opcode 4 and opcode 5 can be set as a dependent opcode pair, opcode 7 and opcode 8 can be set as a dependent opcode pair, and the dependency relationships of all the above dependent opcode pairs are write-after-read dependency relationships. Then, the destination register corresponding to the previous opcode of the above dependent opcode pair and a source register corresponding to the subsequent opcode can be determined as a dependent register pair. For example, it can be determined that rd of opcode 1 and rs0 of opcode 2 form a dependent register pair, rd of opcode 2 and rs1 of opcode 5 form a dependent register pair, rd of opcode 4 and rs0 of opcode 5 form a dependent register pair, and rd of opcode 7 and rs0 of opcode 8 form a dependent register pair.

[0105] For each dependent register in Table 6 above, a register identifier of the string type can be generated, and for each independent register, a register identifier of the numerical type can be generated, obtaining the instruction stream description information as shown in Table 7 below:

[0106] Table 7

[0107]

[0108] For the register identifiers of numerical types, the corresponding encoding rule can be set as the first rule, that is, directly use the register identifier as its corresponding register code. For the register identifiers of string types, the corresponding encoding rule can be set as the second rule, that is, use the random number generated for the register identifier as its corresponding register code. It should be noted that the above instruction stream description information can be stored in a file, for example, record the instruction stream description information through a txt format file.

[0109] The file corresponding to the instruction stream description information can be read, and each register identifier of string type can be extracted from the instruction stream description information shown in Table 7: udf_str1, udf_str2, udf_str3, udf_str4. The random library of python can be used to randomly generate a random number for each of the above 4 register identifiers. For example, udf_str1 = 6, udf_str2 = 34, udf_str3 = 27, udf_str4 = 12. Then the mapping relationship can be established using a dictionary in python. For example, define a dictionary named reg_idx, use the above 4 register identifiers as keys, and use their corresponding random numbers as values, to obtain the reg_idx dictionary shown as follows:

[0110] reg_idx={}

[0111] reg_idx[udf_str1]=6;

[0112] reg_idx[udf_str2]=34;

[0113] reg_idx[udf_str3]=27;

[0114] reg_idx[udf_str4]=12.

[0115] Then each instruction description entry in the above instruction stream description information shown in Table 7 can be parsed, the opcode identifier and register identifier of each instruction description entry can be extracted, the register identifier of numerical type can be directly determined as the corresponding register code, for the register identifier of string type, read the corresponding random number from the above reg_idx dictionary as the corresponding register code, and according to the opcode identifier and register code of each instruction description entry, generate the first instruction corresponding to each instruction description entry, so as to generate the first instruction stream shown in Table 8 as follows.

[0116] Table 8

[0117]

[0118] It should be noted that, in addition to the register operands corresponding to the registers in the above first instruction, other operands may also be required, such as immediate numbers. For other operands, they can be supplemented by randomly generating or by preset values. The embodiments of the present invention do not make specific limitations.

[0119] Optionally, in some embodiments, after the step of determining the first register encoding corresponding to each instruction description entry based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, the following steps may further be executed:

[0120] Step D1, determining the second register encoding corresponding to each instruction description entry based on the register identifiers corresponding to each instruction description entry in the instruction stream description information; wherein, the second register encodings corresponding to the same register identifier are the same.

[0121] Step D2, generating the second instruction corresponding to each instruction description entry based on the second register encoding and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtaining a second instruction stream composed of the second instructions corresponding to each instruction description entry.

[0122] In the embodiments of the present invention, after each corresponding instruction stream is generated based on the instruction stream description information, the register encoding corresponding to the instruction description entry can be regenerated based on the instruction stream description information again, and a corresponding instruction stream can be generated again based on the regenerated register encoding. Thus, the batch generation operation of the instruction stream based on the instruction stream description information is realized.

[0123] Specifically, after the first instruction stream is generated, the second register encoding corresponding to each instruction description entry can be determined based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, and the second register encodings corresponding to the same register identifier are kept the same. The manner of generating the second register encoding is the same as that of generating the first register encoding, and the embodiments of the present invention will not be elaborated herein. A corresponding second instruction stream can be further generated according to the second register encoding.

[0124] It should be noted that since the register encoding can be obtained by randomly selecting or generating random numbers during the generation process, some or all of the second register encodings may be different from the corresponding first register encodings. Therefore, the second instruction stream composed of the second instructions generated based on the second register encodings is different from the first instruction stream.

[0125] In the embodiments of the present invention, based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, the second register encoding corresponding to each instruction description entry can be determined; wherein, the second register encodings corresponding to the same register identifier are the same; based on the second register encoding and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, the second instruction corresponding to each instruction description entry is generated, and a second instruction stream composed of the second instructions corresponding to each instruction description entry is obtained. Thus, an instruction stream with a fixed instruction order and realizing dependency relationships through different dependent registers can be generated in batches, which helps to improve the efficiency of generating the instruction stream for testing, and further can improve the testing efficiency of the processor core.

[0126] Optionally, in some embodiments, after the step of obtaining the second instruction stream composed of the second instructions corresponding to each instruction description entry, the first instruction stream and the second instruction stream can be concatenated to obtain a target instruction stream, or each second instruction in the second instruction stream can be inserted into the first instruction stream to obtain a target instruction stream. Thus, multiple instruction streams generated in batches are combined into a longer target instruction stream. Through the target instruction stream, a large number of different dependent register combination methods can be tested at one time under a fixed instruction order, which helps to improve the efficiency of testing the processor core.

[0127] Refer to Figure 2 , which shows a block diagram of an instruction stream generation device provided by an embodiment of the present invention. As Figure 2 shown, the device may specifically include:

[0128] An acquisition module 201, configured to acquire instruction stream description information generated based on a preset opcode sequence; wherein, the instruction stream description information includes instruction description entries composed of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence;

[0129] An encoding module 202, configured to determine the first register encoding corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information; wherein, the first register encodings corresponding to the same register identifier are the same;

[0130] An instruction stream module 203, configured to generate the first instruction corresponding to each instruction description entry based on the first register encoding and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein, the first instruction stream is used to test the central processing unit.

[0131] Optionally, the preset opcode sequence includes dependent opcode pairs, and the acquisition module includes:

[0132] A relationship sub-module, configured to determine dependent registers corresponding to each opcode in the dependent opcode pair based on the dependency relationship of the dependent opcode pair;

[0133] A register identification sub-module, configured to generate register identifications corresponding to the dependent registers of each opcode in the dependent opcode pair; wherein, the register identifications corresponding to the dependent registers of each opcode in one dependent opcode pair are the same;

[0134] A description information sub-module, configured to generate the instruction stream description information based on the opcode identifications and register identifications corresponding to each opcode in the preset opcode sequence.

[0135] Optionally, the dependency relationship includes a write-after-read dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship. The relationship sub-module includes:

[0136] A first relationship unit, configured to, when the dependency relationship of the dependent opcode pair is the write-after-read dependency relationship, use the destination register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and use one source register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode;

[0137] A second relationship unit, configured to, when the dependency relationship of the dependent opcode pair is the write-after-write dependency relationship, use the destination register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and use the destination register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode;

[0138] A third relationship unit, configured to, when the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, use one source register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and use the destination register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode;

[0139] A fourth relationship unit, configured to, when the dependency relationship of the dependent opcode pair is the read-after-read dependency relationship, use one source register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and use one source register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode.

[0140] Optionally, the encoding module includes:

[0141] An encoding rule sub-module, configured to determine the encoding rules corresponding to each register identification in each instruction description entry;

[0142] The first register encoding sub-module is used to generate the first register encoding corresponding to each register identifier in each instruction description entry based on each register identifier and the encoding rule corresponding to each register identifier.

[0143] Optionally, the identifier type of the register identifier includes a numerical type and a string type, and the encoding rule sub-module includes:

[0144] The first rule unit is used to determine that the encoding rule corresponding to the register identifier with the identifier type of the numerical type is the first rule.

[0145] The second rule unit is used to determine that the encoding rule corresponding to the register identifier with the identifier type of the string type is the second rule.

[0146] Optionally, the first register encoding sub-module includes:

[0147] The first encoding unit is used to use the register identifier as the first register encoding corresponding to the register identifier when the encoding rule of the register identifier corresponding to the instruction description entry is the first rule.

[0148] The second encoding unit is used to obtain a random number generated for the register identifier as the first register encoding corresponding to the register identifier when the encoding rule of the register identifier corresponding to the instruction description entry is the second rule.

[0149] Optionally, the encoding module is further used to determine the second register encoding corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information; wherein, the second register encodings corresponding to the same register identifier are the same;

[0150] The instruction stream module is further used to generate the second instruction corresponding to each instruction description entry based on the second register encoding and the operation code identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a second instruction stream composed of the second instructions corresponding to each instruction description entry.

[0151] In summary, in the instruction stream generation device provided by the embodiment of the present invention, instruction stream description information generated based on a preset opcode sequence is obtained; wherein, the instruction stream description information includes instruction description entries formed by opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence; based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, a first register code corresponding to each instruction description entry is determined; wherein, the first register codes corresponding to the same register identifier are the same; based on the first register code and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, a first instruction corresponding to each instruction description entry is generated, and a first instruction stream composed of the first instructions corresponding to each instruction description entry is obtained. In this way, an instruction stream with a fixed instruction order can be automatically generated through the preset opcode sequence, and the instructions in the generated instruction stream can share the same register code, so that the same register corresponding to the same register code can be operated on by the same or different instructions in the instruction stream with a fixed instruction order, generating a register dependence relationship. Therefore, through this solution, an instruction stream with a fixed instruction order and a register dependence relationship can be generated, which helps to accurately locate problems in the processor core when testing with these instruction streams, and helps to improve the test accuracy when the instruction stream is used for processor core testing.

[0152] Referring to Figure 3 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. As Figure 3 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete mutual communication through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the instruction stream generation method of the foregoing embodiment. The executable instructions can form a program.

[0153] An embodiment of the present invention provides a computer-readable storage medium, on which instructions are stored. When executed by one or more processors, the instructions enable the processor to execute the instruction stream generation method of the foregoing embodiment.

[0154] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same and similar parts among the embodiments can be referred to each other.

[0155] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. It should be noted that all actions of obtaining signals, information, or data in the present invention are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where it is located and obtaining authorization from the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of processes and / or blocks in the flowchart and / or block diagram can also be implemented. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in one process Figure 1 or more processes and / or blocks Figure 1 or a device for implementing the functions specified in one block or more blocks.

[0156] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in one process Figure 1 or more processes and / or blocks Figure 1 or a device for implementing the functions specified in one block or more blocks.

[0157] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process. Therefore, the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one process Figure 1 or more processes and / or blocks Figure 1 or a device for implementing the functions specified in one block or more blocks.

[0158] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be interpreted to include the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0159] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the said element.

[0160] The above has introduced in detail a method for generating an instruction stream, an apparatus for generating an instruction stream, an electronic device and a storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An instruction stream generation method, characterized in that, The method includes: Obtaining instruction stream description information generated based on a preset opcode sequence; wherein, the instruction stream description information includes instruction description entries formed by opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence, and the preset opcode sequence represents a sequence formed by arranging multiple opcodes in a certain order; Determining a first register code corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information; wherein, the first register codes corresponding to the same register identifier are the same; Generating a first instruction corresponding to each instruction description entry based on the first register code and opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtaining a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein, the instruction order of the first instruction stream is fixed, and the first instruction stream is used to test a central processing unit.

2. The instruction stream generation method according to claim 1, wherein The preset opcode sequence includes dependent opcode pairs, and obtaining the instruction stream description information generated based on the preset opcode sequence includes: Determining dependent registers corresponding to each opcode in the dependent opcode pair based on the dependency relationship of the dependent opcode pair; Generating register identifiers corresponding to the dependent registers of each opcode in the dependent opcode pair; wherein, the register identifiers corresponding to the dependent registers of each opcode in one dependent opcode pair are the same; Generating the instruction stream description information based on the opcode identifiers and register identifiers corresponding to each opcode in the preset opcode sequence.

3. The instruction stream generation method according to claim 2, characterized in that, The dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship. Determining the dependent registers corresponding to each opcode in the dependent opcode pair based on the dependency relationship of the dependent opcode pair includes: In the case where the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, using the destination register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and using one source register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode; In the case where the dependency relationship of the dependent opcode pair is the write-after-write dependency relationship, using the destination register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and using the destination register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode; In the case where the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, using one source register of the previous opcode in the dependent opcode pair as the dependent register of the previous opcode, and using the destination register of the subsequent opcode in the dependent opcode pair as the dependent register of the subsequent opcode; When the dependency relationship of the dependency opcode pair is the read-after-read dependency relationship, use a source register of the pre-order opcode in the dependency opcode pair as the dependency register of the pre-order opcode, and use a source register of the post-order opcode in the dependency opcode pair as the dependency register of the post-order opcode.

4. The instruction stream generation method according to claim 1, wherein The determining of the first register encoding corresponding to each instruction description entry based on the register identifiers corresponding to the instruction description entries in the instruction stream description information includes: Determine the encoding rules corresponding to each register identifier in each instruction description entry; Generate the first register encoding corresponding to each register identifier in each instruction description entry based on each register identifier and the encoding rules corresponding to each register identifier.

5. The instruction stream generation method according to claim 4, wherein The identifier types of the register identifiers include a numerical type and a string type. The determining of the encoding rules corresponding to each register identifier in each instruction description entry includes: For a register identifier of the numerical type, determine that the encoding rule corresponding to the register identifier is the first rule; For a register identifier of the string type, determine that the encoding rule corresponding to the register identifier is the second rule.

6. The instruction stream generation method according to claim 5, characterized in that The generating of the first register encoding corresponding to each register identifier in each instruction description entry based on each register identifier and the encoding rules corresponding to each register identifier includes: When the encoding rule of the register identifier corresponding to the instruction description entry is the first rule, use the register identifier as the first register encoding corresponding to the register identifier; When the encoding rule of the register identifier corresponding to the instruction description entry is the second rule, obtain a random number generated for the register identifier as the first register encoding corresponding to the register identifier.

7. The instruction stream generation method according to claim 1, wherein After the determining of the first register encoding corresponding to each instruction description entry based on the register identifiers corresponding to the instruction description entries in the instruction stream description information, the method further includes: Determine the second register encoding corresponding to each instruction description entry based on the register identifiers corresponding to the instruction description entries in the instruction stream description information; wherein, the second register encodings corresponding to the same register identifier are the same; Generate the second instruction corresponding to each instruction description entry based on the second register encoding and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a second instruction stream composed of the second instructions corresponding to each instruction description entry.

8. An instruction stream generation device, characterized in that, The apparatus includes: An obtaining module, configured to obtain instruction stream description information generated based on a preset opcode sequence; wherein, the instruction stream description information includes instruction description entries composed of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence, and the preset opcode sequence represents a sequence formed by arranging a plurality of opcodes in a certain order; An encoding module, configured to determine the first register encoding corresponding to each instruction description entry based on the register identifiers corresponding to the instruction description entries in the instruction stream description information; wherein, the first register encodings corresponding to the same register identifier are the same; An instruction stream module, configured to generate a first instruction corresponding to each instruction description entry based on the first register encoding and the opcode identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein, the instruction order of the first instruction stream is fixed, and the first instruction stream is used to test a central processing unit.

9. An electronic device, characterized in that, Comprising: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store executable instructions, and the executable instructions cause the processor to execute the instruction stream generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Instructions are stored thereon, which, when executed by one or more processors, cause the processor to execute the instruction stream generation method according to any one of claims 1 to 7.

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