Dynamic memory management system based on FPGA

Abstract

The invention discloses a dynamic memory management system based on an FPGA (Field Programmable Gate Array). The dynamic memory management system comprises a data caching module, a data frame counting module and a memory management module, the data frame counting module receives data frames from each data channel, stores the data frames in the data caching module, counts the stored data frames, and sends a data transmission completion signal to the data caching module when the counting reaches a specific condition; after receiving the data transmission completion signal, the data caching module reads out cached data, sends the cached data to the next level and sends a cache release signal to the memory management module; and the memory management module dynamically plans cache resources for the cache data, allocates a storage address, and releases a corresponding cache space after receiving a cache release signal. According to the dynamic memory management system based on the FPGA, centralized distribution of storage resources needed by FPGA multichannel data caching is achieved through FPGA hardware logic, the problem caused by instantaneous fluctuation of data channel bandwidth is avoided, and the utilization rate of caching resources is increased.

Description

Technical Field

[0001] The present invention specifically relates to a dynamic memory management system based on FPGA. Background Art

[0002] At present, FPGA data cache usually adopts a static pre-allocation strategy, which requires applying for storage resources in advance and planning cache space. When FPGA needs to collect multi-channel data and multi-channel data has cache requirements, independent cache resources are usually allocated to each data channel.

[0003] However, the transmission bandwidth of multi-channel data is not the same. The static memory allocation strategy cannot adapt to the problems of unbalanced bandwidth and instantaneous bandwidth fluctuations of multi-channel data. It often leads to data loss in high-bandwidth data paths due to insufficient buffers, while low-bandwidth data paths have idle buffers.

[0004] Specifically, when the data bandwidth of a channel is small or the data channel is not open, its pre-allocated storage space is idle, resulting in a waste of storage resources, especially when the overall storage space of the system is limited. When the cache space of each data transmission channel is pre-allocated in proportion to the average bandwidth of data transmission, although the utilization rate of the cache space can be improved to a certain extent, when there is an instantaneous fluctuation in data transmission, there is still a situation where data is lost due to insufficient cache space. Summary of the invention

[0005] The present invention provides a dynamic memory management system based on FPGA to solve the above-mentioned technical problems, and specifically adopts the following technical solutions:

[0006] A dynamic memory management system based on FPGA, comprising: a data cache module, a data frame counting module and a memory management module;

[0007] The data frame counting module is used to receive data frames from each data channel, store the data frames in the data cache module according to the storage address assigned by the memory management module, and count the stored data frames, and send a data transmission completion signal to the data cache module when the count reaches a specific condition;

[0008] After receiving the data transmission completion signal, the data cache module automatically reads out the cached data, sends it to the next level, and sends a cache release signal to the memory management module;

[0009] The memory management module dynamically plans cache resources and allocates storage addresses for cache data, and releases the corresponding cache space after receiving a cache release signal.

[0010] Furthermore, when the cached data reaches a predetermined size, the data frame counting module sends a data transmission completion signal to the data cache module.

[0011] Furthermore, the data frame counting module includes a timer, and sends a data transmission completion signal to the data cache module when the cached data reaches a preset time.

[0012] Furthermore, the memory management module implements cache allocation and release based on a binary tree.

[0013] Furthermore, the memory management module represents the cache usage status based on a binary tree data structure. Each leaf node of the binary tree contains two data nodes as child nodes, wherein each data node represents an available cache unit. The state value of the binary tree node represents the state of its left and right subtrees. According to the state value of the binary tree node, the first available leaf node can be found, and then the first available data node can be found. When an available data node is successfully found, the memory management module returns the address corresponding to the data node, updates the leaf node state, and recursively updates the state of its parent node to maintain the consistency of the binary tree node state.

[0014] Furthermore, the specific method of the memory management module for performing memory allocation is:

[0015] The memory management module reads the node value of the root node, determines the node state, and points the address pointer to its empty child node;

[0016] Repeat the above operation until the address pointer points to the leaf node of the binary tree, read the node value of the leaf node, select the available data node, and update the leaf node status;

[0017] If the node is still not full after the leaf node status is updated, the cache allocation process is completed and the corresponding address of the data node is directly sent to the data frame counting module;

[0018] If the leaf node is a full node after the node status is updated, the address pointer points to the parent node of the leaf node and updates the node status of the parent node;

[0019] If the parent node is still not full after the node status is updated, the cache allocation process is completed and the corresponding address of the data node is sent to the data frame counting module;

[0020] If the parent node is a full node after the node status is updated, the address pointer points to the parent node of the parent node, and the above operation is repeated until a node with a status of not full is encountered or the root node is updated.

[0021] Furthermore, the specific method for the memory management module to release memory is:

[0022] After receiving the cache release instruction, the memory management module points the address pointer to the corresponding leaf node and reads the node status;

[0023] If the corresponding data node is not allocated, it will directly return that the current address is not allocated;

[0024] If the address pointer points to a leaf node that is not full, only the leaf node status needs to be updated;

[0025] If the address pointer points to a full leaf node, update the current node state and point the address pointer to the parent node of the leaf node;

[0026] If the parent node is a non-full node, update the node state;

[0027] If the parent node is a full node, the current node state is updated and the address pointer points to the parent node of the parent node;

[0028] Repeat the above operation until the address pointer points to the root node of the binary tree or the node pointed to by the current address pointer is not a full node.

[0029] Furthermore, the data cache module stores the data from the data frame counting module into the cache resources by means of DMA. When receiving the data transmission completion signal, the cache data is read from the cache resources by means of DMA and sent outwardly, and a cache release request is sent to the memory management module.

[0030] Furthermore, the memory management module dynamically allocates and releases cache resources through a state machine.

[0031] The benefit of the present invention lies in the FPGA-based dynamic memory management system provided, which realizes the centralized allocation of storage resources required for FPGA multi-channel data caching through FPGA hardware logic, and dynamically allocates cache resources according to the principle of first request first allocation, effectively avoiding the problems of idle storage resources and cache data loss caused by instantaneous fluctuations in the bandwidth of each data channel, thereby greatly improving the utilization efficiency of cache resources.

[0032] The present invention is also beneficial in that the provided FPGA-based dynamic memory management system characterizes the usage of FPGA cache resources through a binary tree data structure and implements centralized management of cache resources on the FPGA, thereby greatly improving the allocation efficiency of cache resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0034] Figure 1 is a schematic diagram of a FPGA-based dynamic memory management system of the present invention;

[0035] Figure 2 It is a schematic diagram of a binary tree data structure for characterizing a cache occupancy state according to the present invention;

[0036] Figure 3 It is a schematic diagram of memory allocation implemented by the memory management module of the present invention;

[0037] Figure 4 It is a schematic diagram of memory release realized by the memory management module of the present invention;

[0038] Figure 5 It is a schematic diagram of the process of dynamically allocating and releasing cache resources by a memory management module through a state machine of the present invention. DETAILED DESCRIPTION

[0039] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0040] like Figure 1 The figure shows a FPGA-based dynamic memory management system of the present application, which includes: a data cache module, a data frame counting module and a memory management module, wherein the memory management module is responsible for completing the dynamic allocation of memory resources.

[0041] Specifically, the data frame counting module is used to receive data frames from each data channel, and store the data frames in the data cache module according to the storage address assigned by the memory management module. The data frame counting module also counts the stored data frames, and when the count reaches a specific condition, it sends a data transmission completion signal to the data cache module. It is understandable that the data frame counting module can send a data transmission completion signal to the data cache module when the cached data reaches a predetermined size (for example, a frame of data frame is agreed to be 4KB, and a single request data is 4MB, that is, when the count is equal to 1024). In order to avoid the data frame count failing to reach the threshold for a long time and affecting the data cache efficiency, the data frame counting module design includes a timer, and the data cache is timed by the timer. When the cache data timing reaches the preset time, a data transmission completion signal will also be sent to the data cache module.

[0042] After receiving the data transmission completion signal, the data cache module completes the cache data, then automatically reads out the cache data, sends it to the next level, and sends a cache release signal to the memory management module.

[0043] The memory management module is responsible for dynamically planning cache resources and allocating storage addresses for cache data. When the memory management module receives a cache release signal, it releases the corresponding cache space.

[0044] In the implementation of the present application, the memory management module implements cache allocation and release based on a binary tree. Specifically, the memory management module represents the cache usage status based on a binary tree data structure. Each leaf node of the binary tree contains two data nodes as child nodes, where each data node represents an available cache unit, and the state of its left and right subtrees is represented by the state value of the binary tree node. Therefore, according to the state value of the binary tree node, the first available leaf node can be found, and then the first available data node can be found. When the available data node is successfully found, the memory management module returns the address corresponding to the data node, updates the leaf node state, and recursively updates the state of its parent node to maintain the consistency of the binary tree node state.

[0045] like Figure 2 The following is a simple binary tree, which is used to illustrate the process of dynamic allocation of cache resources by the memory management module. Figure 2 The binary tree data structure shown is used to represent the cache occupancy status, and stores the status value of each node through on-chip storage and reads and writes it. Figure 2 , we can calculate:

[0046] The address of the left child node is 2*parent node address + 1, and the address of the right child node is 2*parent node address + 2.

[0047] It is agreed that the node value is used to characterize the occupancy of the node subnodes, where 00 means that both the left and right subnodes are not occupied, 10 means that the left subnode is occupied, 01 means that the right subnode is occupied, and 11 means that both the left and right subnodes are occupied. At the time of initialization, the state values ​​of all nodes in the binary tree are 00. When receiving the cache allocation instruction, its address pointer first points to the root node of the binary tree, reads the node value of the root node of the binary tree, and determines whether the binary tree is completely full. If the binary tree is completely full, it means that the storage space has been used up, and no available space is returned. If the binary tree is not full, that is, there is an empty node, then the address pointer points to the empty subnode. If the left and right subnodes of the root node are both empty, it will preferentially point to its left subnode.

[0048] like Figure 3 As shown, in the implementation manner of the present application, the specific method for the memory management module to perform memory allocation is:

[0049] The memory management module reads the node value of the root node and determines the node status. If the node is full, it means that the storage space has been used up and it directly returns that there is no available space. Otherwise, the address pointer points to its empty child node (if both the left and right child nodes of the node are empty, it will preferentially point to its left child node).

[0050] The above operation is repeated repeatedly until the address pointer points to the leaf node of the binary tree, the node value of the leaf node is read, an available data node is selected, and the leaf node status is updated.

[0051] If the node is still not full after the leaf node status is updated, the cache allocation process is completed and the corresponding address of the data node is sent directly to the data frame counting module.

[0052] If the leaf node is a full node after the node status is updated, the address pointer points to the parent node of the leaf node and updates the node status of the parent node.

[0053] If the parent node is still not full after the node status is updated, the cache allocation process is completed and the corresponding address of the data node is sent to the data frame counting module.

[0054] If the parent node is a full node after the node status is updated, the address pointer points to the parent node of the parent node, and the above operation is repeated until a node with a non-full status is encountered or the root node is updated.

[0055] like Figure 4 As shown, in the implementation manner of the present application, the specific method for the memory management module to release memory is:

[0056] After receiving the cache release instruction, the memory management module points the address pointer to the corresponding leaf node and reads the node status.

[0057] If the corresponding data node is not allocated, it will directly return that the current address is not allocated.

[0058] If the address pointer points to a leaf node that is not full, only the leaf node status needs to be updated;

[0059] If the address pointer points to a full leaf node, update the current node state and point the address pointer to the parent node of the leaf node;

[0060] If the parent node is a non-full node, update the node state;

[0061] If the parent node is a full node, the current node state is updated and the address pointer points to the parent node of the parent node;

[0062] Repeat the above operation until the address pointer points to the root node of the binary tree or the node pointed to by the current address pointer is not a full node.

[0063] like Figure 5 As shown, in the implementation of the present application, the process of dynamically allocating and releasing cache resources by the memory management module is implemented by a state machine. The semaphores used are described in Table 1 below.

[0064] Table 1 Meaning of semaphores used by the state machine

[0065] Signal meaning cmd_tvalid_i Command valid signal. When cmd_valid_i is set, it indicates that the current command is valid. allocate_i Command type signal, when allocate_i is set, it indicates that the current command is a cache allocation command; when allocate_i is not set, it indicates that the current command is a cache release command. node_value_i Node status value signal, two-bit node status value, indicating the current node status; when node_value_i[1]=1, it indicates that the left child node of the current node is full; when node_value_i[0]=1, it indicates that the right child node of the current node is full. leaf_layer_reached_i Node type judgment signal: when leaf_layer_reached_i is set, it indicates that the node pointed to by the current address pointer is a leaf node. root_reached_i Node type judgment signal, when root_reached_i is set, it indicates that the node pointed to by the current address pointer is a leaf node. free_done_i Release completion signal, when free_done_i is set already_free_i The memory has been released signal. When already_free_i is set, it indicates that the corresponding cache resource is already in an idle state before the cache release operation is performed. resl_tready_i Command receive ready signal. When the resl_tready_i signal is set, it indicates that the system is ready to receive the state machine return command. cmd_tready_o Command receive ready signal. When the cmd_tready_o signal is set, it indicates that the state machine is ready to receive commands. resl_tvalid_o Return valid signal. When the resl_tvalid_o signal is set, it indicates that the return command sent by the state machine is valid. rd_en_o Read enable signal. When the read enable signal is set, the state value of the node pointed to by the address pointer is written into the register. wr_en_o Write enable signal. When the write enable signal is set, the value in the register is written to the state value of the node pointed to by the address pointer. fail_o Allocation failure signal. When memory allocation fails, the fail_o signal is set. succeed_o Memory resource release success signal. When the cache release operation is completed normally, the succeed_d_o signal is set. succeed_d_o Memory resource release success signal. When the corresponding cache resource is idle before the cache release operation is performed, the succeed_d_o signal is set. rst_addr_o Address register reset signal: When the state machine receives a memory allocation command, it sets the rst_addr_o signal to reset the address register and ensure that the address pointer points to the root node. left_en_o The address pointer indicates the signal. When the left_en_o signal is set, the address pointer will point to the left child node of the current node. right_en_o The address pointer indicates the signal. When the right_en_o signal is set, the address pointer will point to the right child node of the current node. parent_en_o The address pointer indicates the signal. When the parent_en_o signal is set, the address pointer will point to the parent node of the current node. load_addr_o Load address signal. When the load_addr_o signal is set, the address information of the cache resource required to release the cache release command is loaded. update_o Node status update signal. When the update_o signal is set, the current node status value will be updated according to the cache allocation / release situation. load_resl_o Load return command signal. When the load_resl_o signal is set, the load return command is loaded according to the cache allocation / release situation. load_already_free_o Load cache resource status signal. When the load_already_free_o signal is set, check whether the cache resource to be released is currently occupied.

[0066] The S_IDLE state is the initialization state. Whether the command is valid is determined based on the command format. When a valid command is received, the cmd_valid_i signal is set and the state machine jumps to the S_LOAD_CMD state; otherwise, it remains in the initial state.

[0067] The S_LOAD_CMD state is used to determine the command type. The memory management module determines the command type as an allocation command or a release command according to the preset command format. If the allocate_i signal is set, it indicates that the current command is an allocation command. The state machine performs a cache resource allocation operation and jumps to the S_SEARCH_ADDR state. Otherwise, the state machine performs a cache resource release operation and jumps to the S_RD state.

[0068] The S_SEARCH_ADDR state is used to determine whether the node pointed to by the current address pointer is a leaf node. Since the node addresses are stored sequentially in the chip, the memory management module can determine whether the node pointed to by the current address pointer is a leaf node based on the address interval pointed to by the current address pointer. If the leaf_layer_reached_i signal is set, it indicates that the currently selected node is a leaf node, and jumps to the S_UPDATE state, otherwise the state machine jumps to the S_SEARCH_VALUE state.

[0069] The S_SEARCH_VALUE state is used to find available child nodes according to the current node state value provided by the node_value_i signal, and point the address pointer to the corresponding child node. The state machine jumps to the S_SEARCH_ADDR state. For example: if node_value_i[1]=0, it indicates that the left child node of the current node is empty, the left_en_o signal is set, and the address pointer will point to its left child node. Otherwise, if node_value_i[0]=0, it indicates that the right child node of the current node is empty, the right_en_o signal is set, and the address pointer will point to its right child node. If all bits of the node_value_i signal are 1, it indicates that there are no available child nodes, indicating that the binary tree is completely full, and the state machine jumps to the S_RESL state.

[0070] The S_UPDATE state is used to update the state value of the node pointed to by the current address pointer. Set the update_o signal to update the node value. If the root_reached_i signal is set, indicating that the address pointer points to the root node, or the node_value_i signal is all zero before the update, that is, the node is completely empty (that is, the node will not be full after the update), the state machine jumps to the S_RESL state, otherwise the state machine will jump to the S_RD state.

[0071] The S_RD state sets the rd_en_o signal to read the current node state value and input it into the node state value register for system judgment. Check the current command type. If the current allocate_i signal is set, the module is in the memory allocation state, and the state machine jumps to the S_UPDATE state, otherwise the state machine jumps to the S_ALREADY_FREE state.

[0072] The S_ALREADY_FREE state sets the load_already_free_o signal to determine whether the corresponding memory resource is in an idle state before the memory is released, and jumps to the S_FREE state.

[0073] The S_FREE state is used for memory release, and the current address pointer is cleared to point to the node value to indicate the release of cache resources. If the already_free_i signal is set, it indicates that the node corresponding to the current address pointer has been released in advance, and the state machine sets the succeed_d_o signal, and sets the resl_tvalid_o signal and jumps to the S_RESL state. Or if the root_reached_i signal is set, that is, the address pointer has pointed to the root node of the binary tree, or the node_value_i signal indicates that the node value of the node pointed to by the current address pointer does not need to be updated, the state machine sets the succeed_o signal and the wr_en_o signal to update the node status value, and sets the resl_tvalid_o signal and jumps to the S_RESL state. Otherwise, it indicates that the current node is full, that is, it is necessary to traverse and update the node value of its parent node, and the state machine jumps to the S_RD state.

[0074] The S_RESL state is used to output the return value. When the resl_tready_i signal is set, indicating that the return value is successfully sent, the state machine jumps to the S_IDLE state.

[0075] In an implementation manner of the present application, the data cache module stores the data from the data frame counting module into the cache resources via DMA. When a data transmission completion signal is received, the cache data is read from the cache resources via DMA and sent outward, and a cache release request is sent to the memory management module.

[0076] The FPGA-based dynamic memory management system of this application uses RTL language to implement a binary tree data structure on the FPGA at the hardware level. The binary tree is used to represent the current usage status of cache resources, which reduces the time complexity of data storage and reduces the time complexity of data cache from o(N) of sequential storage to o(logN), thereby improving efficiency. More importantly, the centralized allocation improves the efficiency of system storage.

[0077] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A dynamic memory management system based on FPGA, characterized in that: Contains: data cache module, data frame counting module and memory management module; The data frame counting module is used to receive data frames from each data channel, store the data frames in the data cache module according to the storage address assigned by the memory management module, and count the stored data frames, and send a data transmission completion signal to the data cache module when the count reaches a specific condition; After receiving the data transmission completion signal, the data cache module automatically reads out the cached data, sends it to the next level, and sends a cache release signal to the memory management module; The memory management module dynamically plans cache resources and allocates storage addresses for cache data, and releases the corresponding cache space after receiving a cache release signal.

2. The FPGA-based dynamic memory management system according to claim 1, characterized in that: When the cached data reaches a predetermined size, the data frame counting module sends a data transmission completion signal to the data cache module.

3. The FPGA-based dynamic memory management system according to claim 1, characterized in that: The data frame counting module includes a timer, and sends a data transmission completion signal to the data buffer module when the buffered data reaches a preset time.

4. The FPGA-based dynamic memory management system according to claim 1, characterized in that: The memory management module implements cache allocation and release based on a binary tree.

5. The FPGA-based dynamic memory management system according to claim 4, characterized in that: The memory management module represents the cache usage status based on a binary tree data structure. Each leaf node of the binary tree contains two data nodes as child nodes, where each data node represents an available cache unit. The state value of the binary tree node represents the state of its left and right subtrees. According to the state value of the binary tree node, the first available leaf node can be found, and then the first available data node can be found. When an available data node is successfully found, the memory management module returns the address corresponding to the data node and updates the leaf node state, and recursively updates the state of its parent node to maintain the consistency of the binary tree node state.

6. The FPGA-based dynamic memory management system according to claim 5, characterized in that: The specific method for the memory management module to perform memory allocation is: The memory management module reads the node value of the root node, determines the node state, and points the address pointer to its empty child node; Repeat the above operation until the address pointer points to the leaf node of the binary tree, read the node value of the leaf node, select the available data node, and update the leaf node status; If the node is still not full after the leaf node status is updated, the cache allocation process is completed and the corresponding address of the data node is directly sent to the data frame counting module; If the leaf node is a full node after the node status is updated, the address pointer points to the parent node of the leaf node, and the node status of the parent node is updated; If the parent node is still not full after the node status is updated, the cache allocation process is completed and the corresponding address of the data node is sent to the data frame counting module; If the parent node is a full node after the node status is updated, the address pointer points to the parent node of the parent node, and the above operation is repeated until a node with a non-full status is encountered or the root node is updated.

7. The FPGA-based dynamic memory management system according to claim 5, characterized in that: The specific method for the memory management module to release memory is: After receiving the cache release instruction, the memory management module points the address pointer to the corresponding leaf node and reads the node status; If the corresponding data node is not allocated, it will directly return that the current address is not allocated; If the address pointer points to a leaf node that is not full, only the leaf node status needs to be updated; If the address pointer points to a full leaf node, update the current node state and point the address pointer to the parent node of the leaf node; If the parent node is a non-full node, update the node state; If the parent node is a full node, the current node state is updated and the address pointer points to the parent node of the parent node; Repeat the above operation until the address pointer points to the root node of the binary tree or the node pointed to by the current address pointer is not a full node.

8. The FPGA-based dynamic memory management system according to claim 1, characterized in that: The data cache module stores the data from the data frame counting module into the cache resource by means of DMA, and when receiving the data transmission completion signal, reads the cache data from the cache resource by means of DMA and sends it outward, and sends a cache release request to the memory management module.

9. The FPGA-based dynamic memory management system according to claim 4, characterized in that: The memory management module dynamically allocates and releases cache resources through a state machine.

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