Data caching method, device and equipment based on RISC-V processor and storage medium

Abstract

The invention discloses a data caching method, device and equipment based on an RISC-V processor and a storage medium, and belongs to the technical field of edge computing. The method comprises the steps of performing address generation based on data cache task information to obtain a first data cache address; performing address conversion on the first data cache address based on the current configuration information to obtain a second data cache address; and performing data caching according to the second data caching address. According to the method, the address is generated according to the data caching task information, then the generated first data caching address is subjected to address conversion, and finally data caching is performed according to the second data caching address obtained through conversion, so that the data caching efficiency is improved, and the calculation efficiency of a system is improved.

Description

Technical Field

[0001] The present invention relates to the field of edge computing technology, and in particular to a data caching method, device, equipment and storage medium based on a RISC-V processor. Background Art

[0002] In the existing technology, the integration of heterogeneous computing architecture based on RISC-V general-purpose processors can usually meet the requirements of IoT application terminal systems for flexibility and computing efficiency. However, deep neural network models generally operate on data in units of tensors, so large amounts of data need to be read and written in parallel.

[0003] Traditional cache-based caching methods cannot meet the requirements of parallel reading and writing of data and conflict-free data access, so it may cause the computing unit to be idle while waiting for calculation data, thereby reducing the overall computing efficiency of the system.

[0004] In view of this, there is an urgent need for a data caching method based on RISC-V processor to improve data caching efficiency and thus improve the computing efficiency of the system.

[0005] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0006] The main purpose of the present invention is to provide a data caching method, device, equipment and storage medium based on a RISC-V processor, aiming to solve the technical problem of how to perform data caching based on a RISC-V processor in the prior art.

[0007] To achieve the above object, the present invention provides a data caching method based on a RISC-V processor, the method comprising the following steps:

[0008] Generate an address based on the data cache task information to obtain a first data cache address;

[0009] Performing address conversion on the first data cache address based on current configuration information to obtain a second data cache address;

[0010] Data caching is performed according to the second data cache address.

[0011] Optionally, performing address generation based on the data cache task information to obtain a first data cache address specifically includes:

[0012] Get data cache task information;

[0013] A virtual address is generated based on the data cache task information to obtain the first data cache address.

[0014] Optionally, performing address conversion on the first data cache address based on current configuration information to obtain a second data cache address specifically includes:

[0015] Get current configuration information;

[0016] Generate a strategy based on the current configuration information to obtain a current cache partition strategy;

[0017] The first data cache address is converted based on the current cache partitioning strategy to obtain a second data cache address.

[0018] Optionally, generating a strategy based on the current configuration information to obtain a current cache partition strategy specifically includes:

[0019] Parsing the current configuration information to obtain a system configuration parsing result;

[0020] Based on the system configuration analysis result, the storage units to be used are identified and numbered to obtain a numbered set of storage units to be used.

[0021] A strategy is generated based on the current configuration information and the numbered set of storage units to be used to obtain a current cache partitioning strategy.

[0022] Optionally, performing address conversion on the first data cache address based on the current cache partitioning strategy to obtain a second data cache address specifically includes:

[0023] Reorganize the numbered storage unit set to be used based on the current cache partitioning strategy to obtain a reorganized cache unit set to be used;

[0024] The first data cache address is converted based on the reorganized cache unit set to be used to obtain the second data cache address.

[0025] Optionally, performing data caching according to the second data cache address specifically includes:

[0026] Get data cache instructions;

[0027] Parsing the data cache instruction to obtain a cache strategy result;

[0028] Data caching is performed based on the cache policy result and the second data cache address.

[0029] Optionally, caching data on the second data cache address based on the cache timing result specifically includes:

[0030] If the cache policy result is a priority cache policy result, data caching is performed according to the priority cache policy result and the second data cache address;

[0031] If the cache policy result is a sequential cache policy result, data caching is performed according to the sequential cache policy result and the second data cache address.

[0032] In addition, to achieve the above-mentioned purpose, the present invention further proposes a data cache device based on a RISC-V processor, and the data cache device based on a RISC-V processor comprises:

[0033] Address generation module: generates an address based on the data cache task information to obtain a first data cache address;

[0034] An address conversion module: performs address conversion on the first data cache address based on current configuration information to obtain a second data cache address;

[0035] Data cache module: performs data cache according to the second data cache address.

[0036] In addition, to achieve the above-mentioned purpose, the present invention also proposes a data caching device based on a RISC-V processor, wherein the data caching device based on a RISC-V processor comprises: a memory, a processor, and a data caching program based on a RISC-V processor stored in the memory and executable on the processor, wherein the data caching program based on the RISC-V processor is configured to implement the steps of the data caching method based on the RISC-V processor as described above.

[0037] In addition, to achieve the above-mentioned purpose, the present invention also proposes a computer-readable storage medium storing a computer program, wherein a data caching program based on a RISC-V processor is stored on the storage medium, and when the data caching program based on the RISC-V processor is executed by the processor, the steps of the data caching method based on the RISC-V processor as described above are implemented.

[0038] The present invention generates an address based on data cache task information to obtain a first data cache address; performs address conversion on the first data cache address based on current configuration information to obtain a second data cache address; and performs data caching according to the second data cache address. The present invention first generates an address based on data cache task information, then performs address conversion on the generated first data cache address, and finally performs data caching according to the second data cache address obtained by conversion, thereby improving data caching efficiency and further improving the computing efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1It is a structural diagram of a data cache device based on a RISC-V processor in a hardware operating environment involved in an embodiment of the present invention;

[0040] Figure 2 This is a flow chart of a first embodiment of a data caching method based on a RISC-V processor according to the present invention;

[0041] Figure 3 This is a flow chart of a second embodiment of a data caching method based on a RISC-V processor according to the present invention;

[0042] Figure 4 This is a flow chart of a third embodiment of a data caching method based on a RISC-V processor according to the present invention;

[0043] Figure 5 This is a structural block diagram of the first embodiment of the data cache device based on the RISC-V processor of the present invention.

[0044] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0046] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a data cache device based on a RISC-V processor in the hardware operating environment involved in an embodiment of the present invention.

[0047] like Figure 1As shown, the data cache device based on the RISC-V processor may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, Wi-Fi) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM), or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk storage. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0048] Those skilled in the art will understand that Figure 1 The structure shown in does not constitute a limitation on the data cache device based on the RISC-V processor, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0049] like Figure 1 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a data cache program based on a RISC-V processor.

[0050] exist Figure 1 In the data caching device based on the RISC-V processor shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the data caching device based on the RISC-V processor of the present invention can be set in the data caching device based on the RISC-V processor, and the data caching device based on the RISC-V processor calls the data caching program based on the RISC-V processor stored in the memory 1005 through the processor 1001, and executes the data caching method based on the RISC-V processor provided in the embodiment of the present invention.

[0051] The embodiment of the present invention provides a data caching method based on a RISC-V processor, referring to Figure 2 , Figure 2This is a flow chart of a first embodiment of a data caching method based on a RISC-V processor of the present invention.

[0052] In this embodiment, the data caching method based on the RISC-V processor includes the following steps:

[0053] Step S10: generating an address based on the data cache task information to obtain a first data cache address;

[0054] It should be noted that in the specific implementation, the edge computing system represented by the Internet of Things will generate corresponding data caching tasks based on different computing needs, and generate virtual storage addresses according to the data caching task information.

[0055] It should also be noted that in the specific implementation, the data caching task information includes the data information to be cached (type, size and computing requirements) and the algorithm requirement information for executing the data caching task (algorithm type, computing rules, computing units and system functional modules involved).

[0056] Step S20: performing address conversion on the first data cache address based on the current configuration information to obtain a second data cache address;

[0057] It should be noted that in a specific implementation, the current configuration information may include the system's hardware specification information, hardware status information (such as the current storage capacity of the storage module and the usage percentage of each type of memory, etc.) and current system operation status information.

[0058] It should also be noted that, in a specific implementation, the address conversion process is specifically implemented by the system's address conversion module, and the process includes the address conversion module first obtaining the virtual address (first data cache address) generated by the system processor or the co-accelerator, and then based on the virtual storage address translation (address translation) strategy in the system processor, converting the virtual address in the vector instruction into a selection signal for a physical storage unit (bank) and an intra-block address (second data cache address).

[0059] Step S30: caching data according to the second data cache address.

[0060] It can be understood that, in a specific implementation, the second data cache address refers to the selection signal and the intra-block address for a physical storage unit (bank), wherein each physical storage unit (bank) may correspond to a 64-bit register, and records the starting physical address and the amount of stored data of the two operation units corresponding to the physical storage unit (bank) (both addresses and data amounts are represented by 16-bit data).

[0061] This embodiment generates an address based on the data cache task information to obtain a first data cache address; performs address conversion on the first data cache address based on the current configuration information to obtain a second data cache address; and performs data caching according to the second data cache address. This embodiment first generates an address based on the data cache task information, then performs address conversion on the generated first data cache address, and finally performs data caching according to the second data cache address obtained by conversion, thereby improving the data cache efficiency and thus improving the computing efficiency of the system.

[0062] refer to Figure 3 , Figure 3 This is a flow chart of a second embodiment of a data caching method based on a RISC-V processor of the present invention.

[0063] Based on the above first embodiment, in this embodiment, step S10 specifically includes:

[0064] Step S11: Obtain data cache task information;

[0065] It should be noted that in the specific implementation, the data cache task information includes the data information to be cached (type, size and computing requirements) and the algorithm requirement information for executing the data cache task (algorithm type, computing rules, computing units and system functional modules involved).

[0066] Step S12: Generate a virtual address based on the data cache task information to obtain a first data cache address.

[0067] It should be noted that, in a specific implementation, the process of generating a virtual address based on data cache task information is implemented by the system's processor or co-accelerator, and the first data cache address (virtual storage address) obtained also includes virtual address size information, virtual address request information, and virtual address storage information, etc.

[0068] This embodiment first caches the data task information, and then generates a virtual address based on the data cache task information to obtain a first data cache address, thereby providing a basis for subsequent address conversion.

[0069] refer to Figure 4 , Figure 4 This is a flow chart of a third embodiment of a data caching method based on a RISC-V processor of the present invention.

[0070] Based on the above first embodiment, in this embodiment, step S20 specifically includes:

[0071] Step S21: Obtain current configuration information;

[0072] It should be noted that in a specific implementation, the current configuration information may include the system's hardware specification information, hardware status information (such as the current storage capacity of the storage module and the usage percentage of each type of memory, etc.) and current system operation status information.

[0073] Step S22: Generate a strategy based on the current configuration information to obtain a current cache partition strategy;

[0074] It should be noted that, in a specific implementation, the process of generating a policy based on the current configuration information is used to obtain a virtual storage address translation policy, thereby realizing the address translation function.

[0075] It should also be noted that, in a specific implementation, the virtual storage address translation strategy also includes an on-chip cache partitioning strategy generated based on system control module instructions, which is used to combine multiple physical storage units (banks) into a specific cache area (for example, an input buffer, an output buffer, or a weight buffer) through a dynamic reorganization method.

[0076] Step S23: performing address conversion on the first data cache address based on the current cache partitioning strategy to obtain a second data cache address.

[0077] It can be understood that in a specific implementation, in the process of performing address conversion on the first data cache address based on the current cache partitioning strategy, it is also necessary to receive the "buffer configuration instruction (bank config)" issued by the system control module, so as to obtain the on-chip cache partitioning strategy for this data cache task and finally complete the address conversion operation.

[0078] This embodiment obtains current configuration information, and then generates a strategy based on the current configuration information, and finally converts the first data cache address according to the generated current cache partitioning strategy to obtain the second data cache address, thereby realizing the generation of the storage address and providing a basis for subsequent data caching.

[0079] Furthermore, a strategy is generated based on the current configuration information to obtain a current cache partition strategy, which specifically includes: parsing the current configuration information to obtain a system configuration parsing result; identifying and numbering the storage units to be used based on the system configuration parsing result to obtain a numbered set of storage units to be used; and generating a strategy based on the current configuration information and the numbered set of storage units to be used to obtain the current cache partition strategy.

[0080] It should be noted that in the specific implementation, each physical storage unit (bank) in the system will be identified and numbered, and then according to the on-chip cache partition strategy (current cache partition strategy) generated by the control module, multiple physical storage units will be combined into a specific cache area through dynamic reorganization.

[0081] Furthermore, based on the current cache partitioning strategy, the first data cache address is converted to obtain a second data cache address, specifically including: storage reorganization of the numbered set of storage units to be used based on the current cache partitioning strategy to obtain a reorganized set of cache units to be used; based on the reorganized set of cache units to be used, the first data cache address is converted to obtain a second data cache address.

[0082] Furthermore, data caching is performed according to the second data cache address, specifically including: obtaining a data cache instruction; parsing the data cache instruction to obtain a cache policy result; and data caching is performed based on the cache policy result and the second data cache address.

[0083] It should be noted that, in a specific implementation, the cache policy result obtained based on the data cache instruction analysis is essentially used to indicate the data cache method specifically applied to this data cache task.

[0084] Furthermore, data caching is performed on the second data cache address based on the cache timing result, specifically including: if the cache policy result is a priority cache policy result, data caching is performed according to the priority cache policy result and the second data cache address; if the cache policy result is a timing cache policy result, data caching is performed according to the timing cache policy result and the second data cache address.

[0085] It can be understood that, in a specific implementation, the priority cache policy result is essentially a data reading and storage rule of a preset priority, which enables the data to be cached to be stored in each memory of the system storage module in accordance with a preset (memory) priority order; the timing cache policy result is essentially a data reading and storage rule based on timing, which enables the data to be cached to be stored in each memory of the system storage module in accordance with the order of data reading and storage (using an internal polling counter to achieve first-come-first-served storage).

[0086] In addition, an embodiment of the present invention further proposes a computer-readable storage medium storing a computer program, wherein a data caching program based on a RISC-V processor is stored on the storage medium, and when the data caching program based on the RISC-V processor is executed by the processor, the steps of the data caching method based on the RISC-V processor as described above are implemented.

[0087] Since the storage medium adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0088] Reference Figure 5 , Figure 5 This is a structural block diagram of the first embodiment of the data cache device based on the RISC-V processor of the present invention.

[0089] like Figure 5 As shown, the data cache device based on the RISC-V processor proposed in an embodiment of the present invention includes:

[0090] Address generation module 10: generates an address based on the data cache task information to obtain a first data cache address;

[0091] Address conversion module 20: performs address conversion on the first data cache address based on current configuration information to obtain a second data cache address;

[0092] The data cache module 30 performs data cache according to the second data cache address.

[0093] This embodiment generates an address based on the data cache task information to obtain a first data cache address; performs address conversion on the first data cache address based on the current configuration information to obtain a second data cache address; and performs data caching according to the second data cache address. This embodiment first generates an address based on the data cache task information, then performs address conversion on the generated first data cache address, and finally performs data caching according to the second data cache address obtained by conversion, thereby improving the data cache efficiency and thus improving the computing efficiency of the system.

[0094] It should be understood that the above is only an example and does not constitute any limitation on the technical solution of the present invention. In specific applications, technicians in this field can make settings as needed, and the present invention does not limit this.

[0095] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of the present invention. In practical applications, technicians in this field can select part or all of them according to actual needs to achieve the purpose of the present embodiment, and no limitation is made here.

[0096] In addition, for technical details not described in detail in this embodiment, please refer to the data caching method based on RISC-V processor provided in any embodiment of the present invention, which will not be repeated here.

[0097] In addition, it should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0098] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0099] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory (ROM) / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0100] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A data caching method based on a RISC-V processor, characterized in that: include: Generate an address based on the data cache task information to obtain a first data cache address; Performing address conversion on the first data cache address based on current configuration information to obtain a second data cache address; Data caching is performed according to the second data cache address.

2. The data caching method based on the RISC-V processor according to claim 1, characterized in that: Generating an address based on the data cache task information to obtain a first data cache address specifically includes: Get data cache task information; A virtual address is generated based on the data cache task information to obtain the first data cache address.

3. The data caching method based on RISC-V processor according to claim 1, characterized in that: Performing address conversion on the first data cache address based on the current configuration information to obtain a second data cache address specifically includes: Get the current configuration information; Generate a strategy based on the current configuration information to obtain a current cache partition strategy; The first data cache address is converted based on the current cache partitioning strategy to obtain a second data cache address.

4. The data caching method based on RISC-V processor according to claim 3 is characterized in that: Based on the current configuration information, a strategy is generated to obtain a current cache partition strategy, which specifically includes: Parsing the current configuration information to obtain a system configuration parsing result; Based on the system configuration analysis result, the storage units to be used are identified and numbered to obtain a numbered set of storage units to be used. A strategy is generated based on the current configuration information and the numbered set of storage units to be used to obtain a current cache partitioning strategy.

5. The data caching method based on RISC-V processor according to claim 3 is characterized in that: Performing address conversion on the first data cache address based on the current cache partitioning strategy to obtain a second data cache address specifically includes: Reorganize the numbered storage unit set to be used based on the current cache partitioning strategy to obtain a reorganized cache unit set to be used; The first data cache address is converted based on the reorganized cache unit set to be used to obtain the second data cache address.

6. The data caching method based on a RISC-V processor according to any one of claims 1 to 5, characterized in that: The step of performing data caching according to the second data cache address specifically includes: Get data cache instructions; Parsing the data cache instruction to obtain a cache strategy result; Data caching is performed based on the cache policy result and the second data cache address.

7. The data caching method based on RISC-V processor according to claim 6, characterized in that: The method further comprises: performing data caching on the second data cache address based on the cache timing result; If the cache policy result is a priority cache policy result, data caching is performed according to the priority cache policy result and the second data cache address; If the cache policy result is a sequential cache policy result, data caching is performed according to the sequential cache policy result and the second data cache address.

8. A data cache device based on a RISC-V processor, characterized in that: The data cache device based on the RISC-V processor includes: Address generation module: generates an address based on the data cache task information to obtain a first data cache address; An address conversion module: performs address conversion on the first data cache address based on current configuration information to obtain a second data cache address; Data cache module: performs data cache according to the second data cache address.

9. A data cache device based on a RISC-V processor, characterized in that: The data caching device based on the RISC-V processor includes: a memory, a processor, and a data caching program based on the RISC-V processor stored in the memory and executable on the processor, wherein the data caching program based on the RISC-V processor is configured to implement the data caching method based on the RISC-V processor according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it can implement the steps in the data caching method based on the RISC-V processor as described in any one of claims 1 to 7.

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