Generalized inverse matrix solution circuit based on block matrix and working method

Abstract

The application provides a generalized inverse matrix solving circuit based on a block matrix and a working method, and belongs to the fields of semiconductors, analog computation and integrated circuits. Small-scale matrices obtained by dividing the original matrix are respectively mapped to resistance memory arrays of two small-scale generalized inverse matrix solving circuits, and a two-step generalized inverse matrix solving operation of the block matrix is completed by adjusting circuit analog switches arranged between circuit devices. In the implementation process, only one analog computation system is needed, hardware resource consumption is reduced in a multiplexing array mode, the number of array devices needed is consistent with a direct mapping matrix element mode, but the size of a matrix solved by an actual circuit is reduced, so that the solving performance and circuit construction feasibility are improved, the implementability of analog memory-in-computation in a large-scale computation scene is improved, and the advantages of the analog memory-in-computation technology are further exerted.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, analog computing and integrated circuit, and relates to a method for implementing the solution of the generalized inverse matrix of a block matrix in an analog computing circuit, in particular to a method for designing and working an analog circuit for solving the generalized inverse matrix of a block matrix suitable for resistive memory (such as resistive random access memory, phase change memory, magnetic memory, ferroelectric memory, etc.), including its working principle and operation method. BACKGROUND

[0002] With the surge in data volume and the increase in computing demand, traditional digital computers are limited by serial digital algorithms and separate architecture, and face the dual challenges of efficiency and energy consumption in processing large-scale matrix operations, which are difficult to meet today's huge and complex computing tasks. In order to improve the operation efficiency and reduce the energy consumption, developing new computing paradigms has gradually become a research hotspot. The analog computing circuit based on resistive memory array can perform in-situ matrix operations such as matrix-vector multiplication, matrix inversion, matrix generalized inverse and matrix eigenvector, which benefits from the high parallelism of the analog computing paradigm, providing a strong guarantee for improving the computing efficiency, and is widely studied and applied in the field of artificial intelligence reasoning and training accelerator.

[0003] In the field of modern computing, the solution of the generalized inverse matrix is a key computing component in the fields of scientific computing, artificial intelligence and regression problem solving. However, in the actual computing environment, the super large matrix size will cause difficulties in matrix element write mapping and circuit construction for the generalized inverse solution circuit based on the analog computing paradigm, resulting in a large circuit operation complexity; at the same time, the large matrix size will increase the circuit noise, causing serious loss of solution accuracy and error; in addition, the solution of the analog computing circuit is highly dependent on the loop stability characteristics based on the operational amplifier, and the large solution matrix size is not conducive to the stability of the circuit. All the above problems will seriously limit the application of the generalized inverse solution circuit, and will offset the advantages of low power consumption and high efficiency brought by the analog computing. Therefore, a generalized inverse matrix solution method that can effectively reduce the solution matrix size is urgently needed to be developed. SUMMARY

[0004] The purpose of the present application is to develop a generalized inverse matrix solution circuit based on block matrix based on resistive memory array, to reduce the size of resistive memory array through block method, and to complete the generalized inverse matrix solution through the working method developed by the present application, thereby improving the circuit solution performance and reducing the hardware resource consumption.

[0005] The generalized inverse matrix solving problem of the block matrix faced by the present application is described as follows:

[0006] For an over-determined linear equation system y = Ax, A is a matrix with size m x n, where m > n, y is a known vector with size m x 1, and x is an unknown vector with size n x 1. There is no strict solution x for the over-determined problem, such that y - Ax = 0. However, there is a specific vector x, such that the Euclidean distance || y - Ax || 2 between Ax and y is minimum, and in this case, x = A + y, where A + = (A T A) -1 A T is called the left inverse matrix of A. The column of A is divided into blocks, i.e. A = [BC], B has a size of m x p, C has a size of m x q, and p + q = n. Based on the Sherman-Morrison-Woodbury formula, the following can be obtained:

[0007]

[0008] where P B1 and P C1 are respectively represented as P B1 = I - B (B T B) -1 B T and P C1 = I - C (C T C) -1 C T .

[0009] For an under-determined linear equation system y = Ax, A is a matrix with size m x n, where m < n, y is a known vector with size m x 1, and x is an unknown vector with size n x 1. If the solution of the under-determined equation system has no additional constraints, then there are infinite vectors x satisfying y = Ax. If the solution vector x is limited to satisfy the L2 norm minimization, i.e. min (|| x || 2), then in this case, x = A + y, where A + = A T (AA T ) -1 is called the right inverse matrix of A. The row of A is divided into blocks, i.e. A = [B T C T ] T , B has a size of p x n, C has a size of q x n, and p + q = m. The row of y is divided into blocks, i.e. y = [y1 T y2 T ] T, the size of y1 vector is p x 1, and the size of y2 vector is q x 1. Based on the Sherman-Morrison-Woodbury formula, the following can be obtained:

[0010]

[0011] wherein P B2 and P C2 respectively represent P B2 = I - B T (BB T ) -1 B and P C2 = I - C T (CC T ) -1 C.

[0012] The left inverse matrix and the right inverse matrix described above are collectively referred to as a generalized inverse matrix, and the generalized inverse matrix of the block matrix is solved, so that the size of the resistive memory array is reduced, and the operation is further accelerated.

[0013] The technical scheme of the present application is as follows:

[0014] A generalized inverse matrix solving circuit based on a block matrix is used for generalized inverse matrix solving of column block matrices M and N of a target real number matrix A (the size is m x n and m > n), A = [M N] (the size of the matrix M is m x p, the size of the matrix N is m x q, and p + q = n), characterized in that the circuit is composed of two circuits connected through two groups of analog switches, one of which is used for mapping and processing the block matrix M, and the other is used for mapping and processing the block matrix N.

[0015] The matrix M is expressed as M = M (+) -M (-) , wherein M (+) = (M + |M|) / 2, M (-) = (|M| - M) / 2, M (+) and M (-) are actual mapped matrix values, representing positive and negative elements of the original matrix, respectively; the matrix N is expressed as N = N (+) -N (-) , wherein N (+) = (N + |N|) / 2, N (-) = (|N| - N) / 2, N (+) and N (-) are actual mapped matrix values, representing positive and negative elements of the original matrix, respectively.

[0016] The circuit of the mapping matrix M includes four groups of resistive memory arrays, multiple analog inverters (INV), multiple trans-impedance amplifiers (TIA), multiple operational amplifiers (OPA), multiple input reference resistors, multiple analog switches, and eight input and output ports; the four groups of resistive memory arrays are arranged in a field layout, the first two groups of resistive memory arrays respectively map M (+) and M (-) , the last two groups respectively map M (-) and M (+) ; the column lines of the arrays mapping M (+) in the first two groups are connected to the column lines of the arrays mapping M (-) through analog inverters, the two array row lines are connected, and the array row lines of M (-) are connected to the input ends of the trans-impedance amplifiers through analog switches, the output ends of the trans-impedance amplifiers are connected to the row lines of the arrays mapping M (+) in the last two groups of arrays through analog switches, and then connected to the row lines of the arrays mapping M (-) in the last two groups of arrays through analog inverters, the column lines of the last two groups of arrays are connected and connected to the positive input ends of the operational amplifiers through analog switches, the reverse input ends of the operational amplifiers are grounded, and the output ends are connected to the column lines of the first two groups of arrays through analog switches; the input and output ports are connected through the input reference resistors G0 in the commonly connected row lines of the first two groups of arrays and the commonly connected column lines of the last two groups of arrays, respectively, and the input and output ports are directly connected in the column lines of the arrays mapping M (+) in the first two groups of arrays and the row lines of the arrays mapping M (+) in the last two groups of arrays, to complete the calculation operation; meanwhile, the circuit mapping the matrix M is vertically flipped in layout, wherein the mapping matrix is a corresponding vertically flipped matrix, and the matrix M f after the vertical flipping operation has the same size as M but the row order is reversed;

[0017] The circuit of the mapping matrix N is completely consistent with the topology of the circuit of the mapping matrix M, and the difference lies in the size difference in the number of columns of the resistive memory arrays, the first two groups of resistive memory arrays respectively map N (-) and N (+) , and the last two groups respectively map N (+) and N (-) ;

[0018] The circuit of the mapping matrix M and the circuit of the mapping matrix N are connected through two groups of analog switches, one group of analog switches is used to control the connection of the row lines of the first two groups of arrays in the two circuits, and the other group of analog switches is used to control the connection of the row lines of the last two groups of arrays in the two circuits.

[0019] Further, the resistive memory arrays of the circuit for mapping the processing matrix M and the circuit for mapping the processing matrix N are both of size m x p and m x q, respectively, and satisfy m > (p + q).

[0020] The application further provides a left inverse matrix solving method of a generalized inverse matrix solving circuit based on a block matrix. + y, A + T -1 A T , whose column and row block matrix is B and C, the solving problem is converted into + y = [(P C1 B) + y(P B1 C) + y] T , wherein P B1 = I - B(B T B) -1 B T , P C1 = I - C(C T C) - 1 C T , characterized by comprising the following steps.

[0021] Firstly, mapping the block matrix B and C to the resistive memory arrays of the circuit for solving the generalized inverse matrix of the block matrix, adjusting the circuit analog switch, and solving all element values of the matrix P C1 B and the matrix P B1 C.

[0022] Secondly, mapping the matrix P C1 B and P B1 C to the resistive memory arrays of the circuit for solving the generalized inverse matrix of the block matrix, adjusting the circuit analog switch, and solving the vector values (P C1 B) + y and (P B1 C) + y.

[0023] Further, the first step of mapping the block matrix is specifically mapping the positive and negative matrix values B (+) , B (-) of the matrix B to the resistive memory arrays in the circuit for mapping the processing matrix M, and mapping the positive and negative matrix values C (+) , C (-) of the matrix C to the resistive memory arrays in the circuit for mapping the processing matrix N.

[0024] ​​The second step of the step is to map the matrix, specifically, map P C1 The positive and negative value matrix of the B matrix (P C1 B) (+) 、(P C1 B) (-) To the first step of mapping the B matrix in the resistive memory array, map P B1 The positive and negative value matrix of the C matrix (P B1 C) (+) 、(P B1 C) (-) To the resistive memory array of the first step mapping C matrix.

[0025] Furthermore, in the first step, the circuit analog switch is adjusted to solve the matrix P C1 B and matrix P B1 C, specifically, turning off all analog switches of the circuit of mapping processing matrix B and the analog switches between the row lines of the last two groups of arrays of the two circuits, connecting all analog switches of the circuit of mapping processing matrix C and the analog switches between the row lines of the first two groups of arrays of the two circuits; mapping B in the first two groups of arrays of the circuit of mapping processing matrix B (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix C is mapped in the last two arrays of the circuit. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. C1 Each column vector of B; in completing the matrix P C1 After the calculation of B, all analog switches of the circuit of the mapping processing matrix C and the analog switches between the row lines of the last two groups of arrays of the two circuits are turned off, and all analog switches of the circuit of the mapping processing matrix B and the analog switches between the row lines of the first two groups of arrays of the two circuits are turned on; in the first two groups of arrays of the circuit of the mapping processing matrix C, mapping C is turned on. (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix B is mapped in the last two arrays of the circuit of the mapping matrix B. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. B1 The column vectors of C.

[0026] Furthermore, in the second step, the analog switches of the circuit are adjusted to solve the vector value, specifically, the analog switches between the row lines of the first two groups of arrays of the two circuits and the analog switches between the row lines of the last two groups of arrays are turned off, and the mapping processing matrix P is connected. C1 B's circuit and mapping processing matrix P B1 All analog switches of the circuit C; respectively to the mapping processing matrix P C1B's circuit and mapping processing matrix P B1 The input and output ports on the common row lines of the first two arrays of the circuit C input the known vector y through the input reference resistor, then the voltage output by the input and output ports on the row lines of the arrays with positive values ​​in the mapping matrix of the first two arrays of the two circuits are respectively expressed as (P C1 B) + y and (P B1 C) + y, and then the final left inverse matrix calculation result is A + y=[(P C1 B) + y(P B1 C) + y] T .

[0027] On the other hand, the present invention proposes a right inverse matrix solving method based on a generalized inverse matrix solving circuit of a block matrix, for a target solving matrix A, solving its right inverse matrix vector product A + y, A + =A T (AA T ) -1 , after the rows are divided into blocks, they are represented as A=[B T C T ] T , the y vector row is divided into blocks y = [y1 T y2 T ] T , solve the problem and convert it into A + y=(BP C2 ) + y1+(CP B2 ) + y2, where P B2 =IB T (BB T ) -1 B.P C2 =IC T (CC T ) -1 C, characterized in that it comprises the following steps:

[0028] The first step is to transform the matrix B T and C T Mapped to the resistive memory array of the block matrix generalized inverse matrix solving circuit, the matrix BP is solved C2 and CP B2 ;

[0029] The second step is mapping (BP C2 ) T and (CP B2 )T Matrix to block matrix generalized inverse matrix solver circuit resistive memory array, solve vector (BP C2 ) + y and (CP B2 ) + y.

[0030] Furthermore, the first step of the step is to map the block matrix, specifically, B T The positive and negative values ​​of the matrix matrix value B T (+) 、B T (-) The resistive memory array in the circuit mapped to the mapping processing matrix M is mapped to C T The positive and negative values ​​of the matrix matrix C T (+) 、C T (-) Mapping to the resistive memory array in the circuit of the mapping processing matrix N; the second step of the mapping matrix, specifically, mapping (BP C2 ) T The positive and negative values ​​of the matrix (BP C2 ) T (+) , (BP C2 ) T (-) To the first step mapping B T In the resistive memory array of the matrix, the mapping (CP B2 ) T The positive and negative values ​​of the matrix (CP B2 ) T (+) 、(CP B2 ) T (-) To the first step mapping C T In a matrix resistive memory array.

[0031] Furthermore, the first step of the step is to adjust the circuit analog switch, specifically, to turn off the mapping processing matrix B T All analog switches of the circuit and the analog switches between the rows of the first two groups of arrays of the two circuits are connected to the mapping processing matrix C T All analog switches of the circuit and the analog switches between the row lines of the two groups of arrays after the two circuits; in the mapping processing matrix C T The input and output ports on the common row lines of the first two arrays of the circuit sequentially input the voltage signal in the form of a one-hot code through the input reference resistor, and after each input, the mapping processing matrix B TThe input and output ports on the common column line in the last two groups of arrays of the circuit of the matrix BP are scaled by the output voltage obtained by the reference resistance, to obtain the matrix BP C2 . After the calculation of the matrix BP C2 , all the analog switches of the circuit of the mapping processing matrix C T and the analog switches between the row lines of the first two groups of arrays of the two circuits are turned off, and all the analog switches of the circuit of the mapping processing matrix B T and the analog switches between the row lines of the last two groups of arrays of the two circuits are turned on; the input and output ports on the common row line in the first two groups of arrays of the circuit of the mapping processing matrix B T are sequentially inputted with voltage signals in the form of one-hot code through the input reference resistance, and the output voltage obtained by the reference resistance is scaled by the input and output ports on the common column line in the last two groups of arrays of the circuit of the mapping processing matrix C T , to obtain the matrix CP B2 .

[0032] Further, the second step of adjusting the circuit analog switch to solve the vector value is specifically to turn off the analog switches between the row lines of the first two groups of arrays and the analog switches between the row lines of the last two groups of arrays of the two circuits, and turn on all the analog switches of the circuit of the mapping processing matrix P C1 B and the circuit of the mapping processing matrix P B1 C; the input and output ports on the common column line of the last two groups of arrays of the circuit of the mapping processing matrix P C1 B and the circuit of the mapping processing matrix P B1 C are inputted with the known vectors y1 and y2 through the reference resistance, and the voltage outputted by the input and output ports on the row line of the positive value array of the mapping matrix of the last two groups of arrays of the two circuits respectively represents (BP C2 ) + y1 and (CP B2 ) + y2, and the final right inverse matrix calculation result is A + y=(BP C2 ) + y1 + (CP B2 ) + y2.

[0033] The technical effects of the present application are as follows:

[0034] The application provides a simulation calculation circuit implementation scheme for solving a generalized inverse matrix of a block matrix, and can solve a large-scale matrix generalized inverse solution task in a block matrix form. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 FIG. 1 is a generalized inverse matrix solving circuit schematic diagram based on a block matrix provided by an embodiment of the application;

[0036] Figure 2 FIG. 2 is a left inverse matrix solving operation method flowchart of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the application;

[0037] Figure 3 FIG. 3 is a right inverse matrix solving operation method flowchart of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the application;

[0038] Figure 4 FIG. 4 is a specific implementation mode schematic diagram of the first step operation of the left inverse matrix solving operation method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the application;

[0039] Figure 5 FIG. 5 is a specific implementation mode schematic diagram of the second step operation of the left inverse matrix solving operation method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the application;

[0040] Figure 6 FIG. 6 is a specific implementation mode schematic diagram of the first step operation of the right inverse matrix solving operation method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the application;

[0041] Figure 7It is a schematic diagram of a specific implementation method of the second step of the right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0043] Figure 1 This is a schematic diagram of a generalized inverse matrix solving circuit based on a block matrix provided by an embodiment of the present invention. The circuit is composed of two similar circuits connected by two sets of analog switches. The two circuits respectively map and process the matrices M and N of size m×p and m×q after the blocks are completed (m>p+q). For a resistive memory array, the actual mapped matrix element value is a ij =G ij / G0, where G ij is the device conductance value of the resistive memory array at the corresponding position, and G0 is the conductance value of the reference resistor. For the circuit of the mapping matrix M, it includes 4 groups of variable resistor crossbar arrays with m rows and p columns, m+p analog inverters (INV), m transimpedance amplifiers (TIA, with a transimpedance of 1 / cG0), p operational amplifiers (OPA), m+p input reference resistors, and 2(m+p) analog switches. For the real number matrix M, since the actual circuit conductance can only map positive values, the matrix M is expressed as M=M (+) -M (-) , where M (+) =(M+|M|) / 2, M (-) =(|M|-M) / 2, M (+) and M (-) is the actual mapped matrix element value, and the positive and negative elements of the original matrix are expressed by connecting analog inverters (i.e. Figure 1 Mapping M in (+) and M (-) Mapping N between arrays (+) and N (-) In the circuit structure of the mapping matrix M (i.e. Figure 1 The first two groups of resistive memory arrays map M (+) and M (-) , mapping M (+) The column lines of the array are connected to the mapping M through analog inverters (-) The column lines of the array, the two array row lines are connected and connected through analog switches ( Figure 1 S1 in the figure is connected to the input of the transimpedance amplifier, and the output of the transimpedance amplifier is connected to the analog switch ( Figure 1 S3) is connected to the last two arrays and mapped to M (+)The row lines of the array are connected by analog inverters and then the two groups of arrays are mapped into M (-) The row lines of the array, the column lines of the latter two groups of arrays are connected through analog switches ( Figure 1 S3) is connected to the positive input of the operational amplifier, the negative input of the operational amplifier is grounded, and the output is connected to the analog switch ( Figure 1 The common row lines of the first two arrays and the common column lines of the last two arrays are connected to the input and output ports through reference resistors, respectively, and the M is mapped in the first two arrays. (+) The column lines of the array and the last two groups of arrays are mapped in M (+) The input and output ports are directly connected to the rows of the array. As for the circuit structure of the mapping matrix N, it includes 4 groups of variable resistor crossbar arrays with m rows and q columns, m+q analog inverters (INV), m transimpedance amplifiers (TIA), q operational amplifiers (OPA), m+q input reference resistors, 2(m+q) analog switches, and 8 ports. For the real number matrix N, the method is the same as that of the mapping matrix M, and the matrix N is expressed as N=N (+) -N (-) , where N (+) =(N+|N|) / 2, N (-) =(|N|-N) / 2, N (+) and N (-) is the actual mapped matrix value, representing the positive and negative elements of the original matrix (subscript (+) and (-) Represent the above calculation operations respectively). The topological structures of the circuit of the mapping matrix N and the circuit of the mapping matrix M are exactly the same, and the only difference is the number of columns of the actual resistive memory array (the M matrix has p columns, and the N matrix has q columns). Based on the circuits of the mapping matrix M and the mapping matrix N, m analog switches are used to control the row lines connecting the first two groups of arrays and the row lines of the last two groups of arrays in the two circuits. At the same time, in order to optimize the circuit layout and facilitate line connection, the upper half of the circuit is vertically flipped (described by the subscript f). The two parts of the circuit are connected through the analog switch groups S5 and S6. At the same time, the connection inside the circuit can be controlled by adjusting the analog switch groups S1, S2, S3, and S4 in the transimpedance amplifier and operational amplifier set inside the two parts of the circuit. In the actual process of solving the generalized inverse matrix, it is necessary to use Figure 1 Among the input and output ports P1, P2, P3, P4, P5, P6, P7, and P8 shown, P3, P4, P5, and P6 need to be connected to an input reference resistor (with a conductance of G0).

[0044] The vertical flip operation of the mapping process M matrix is: for the original matrix M, the matrix M after the vertical flip operation fwhich has the same size as M but the row order is reversed, in mathematical expression, if the elements of M are denoted as m ij , the elements of matrix M f may be denoted as m ij,f , where i and j represent the indices of rows and columns respectively. ij,f (m+1-i)j

[0045] Figure 2 is a left inverse matrix solving working method flowchart of the generalized inverse matrix solving circuit based on block matrix provided by the embodiment of the present application. Firstly, for a target solving matrix A with a size of m x n, in order to solve the left inverse matrix vector product A + y, where A + = (A T A) -1 A T , firstly, column block processing is performed on it, that is, A = [B C], where the size of matrix B is m x p, the size of matrix C is m x q, and p + q = n, then the block matrices B and C are mapped to resistive memories in the circuit respectively. Secondly, by adjusting the circuit analog switch and inputting a specific voltage signal, the matrices P C1 B and P B1 C are solved respectively. Then, the obtained P C1 B and P B1 C matrix information is remapped to the resistive memories in the original circuit to realize array multiplexing. Finally, the circuit analog switch is adjusted again, and the original signal y is inputted, so that the solving of (P C1 B) + y and (P B1 C) + y is completed, and (P C1 B) + y and (P B1 C) + y are the row block matrices of A + y, that is, A + y = [(P C B) + y (P B C) + y] T .

[0046] Figure 3 is a right inverse matrix solving working method flowchart of the generalized inverse matrix solving circuit based on block matrix provided by the embodiment of the present application. Firstly, for a target solving matrix A with a size of m x n, in order to solve the right inverse matrix vector product A + y, where A + = A T (AA T ) -1 ​​, first row partitioning is performed, i.e. A = [B T C T ] T , where the size of matrix B is p x n, the size of matrix C is q x n, and p + q = m, then the block matrix B T and C T are mapped into resistive memories in the circuit respectively. Secondly, by adjusting the circuit analog switches and inputting specific voltage signals, the matrix BP C2 and CP B2 are solved respectively. Then, the obtained BP C2 and CP B2 matrix information is remapped to the resistive memories of the original circuit to realize array multiplexing. Finally, the known vector y is row partitioned, i.e. y = [y1 T y2 T ] T , the size of y1 vector is p x 1, the size of y2 vector is q x 1, and the circuit analog switches are adjusted again, and the original signals y1 and y2 are inputted, so that the solution of (BP C2 ) + y1 and (CP B2 ) + y2 is completed, and the final result is A + y = (BP C2 ) + y1 + (CP B2 ) + y2.

[0047] Figure 4 is a specific implementation mode schematic diagram of the first step operation of the left inverse matrix solving working method of the generalized inverse matrix solving circuit based on block matrix provided by the embodiment of the application. Considering a matrix A with the size of m x n, and m > n, after column partitioning, it is expressed as A = [BC], the size of matrix B is m x p, the size of matrix C is m x q, and the matrix B and the matrix C are mapped into the arrays of two similar circuits of the mapping matrix M and N as described in Figure 1 , and p + q = n (the subscripts (+) and (-) represent positive and negative matrices respectively, and the subscript f represents a vertical flip matrix). Figure 4 (a) and Figure 4 (b) can solve P C1 B and P B1 C respectively. In Figure 4 (a), the circuit analog switch groups S2, S4 and S5 are turned on, and the circuit analog switch groups S1, S3 and S6 are turned off. For the circuit at this time, when the voltage vector x is inputted at the port P1, the current output vector I t obtained on the common connection line after the array is -G B x, G BTo map the conductance value matrix of B matrix (including positive and negative), the current vector continues to input the subsequent circuit, and then the voltage output vector V can be obtained at port P8 out = -G0 -1 c -1 P C1 I t = c -1 P C1 Bx, wherein c is the ratio of the transconductance of the transimpedance amplifier to the reference conductance. Based on the above analysis, by sequentially inputting the scanning voltage in the form of a one-hot code at port P1 (if the number of column lines is 3, that is, sequentially inputting the voltage signals of [0 0 1V], [0 1V 0] and [1V 0 0]), for the ith input, the vector composed of the ith column element of c -1 P C1 B can be obtained at the output port P8, and by sequentially inputting the voltage, the element values of all elements of c -1 P C1 B can be obtained, and the element information of matrix P C1 B can be obtained by coefficient scaling. For Figure 4 (b), the solving operation logic of P B1 C is consistent with the above description, except that when solving P B1 C, the gating circuit analog switch groups S1, S3 and S5 are turned on, and the gating circuit analog switch groups S2, S4 and S6 are turned off, and the scanning voltage needs to be input at port P2, and the final result is output by port P7.

[0048] Figure 5 is a specific implementation mode diagram of the second step operation of the left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the application. Based on Figure 4 the calculation results of P C1 B and P B1 C described above, the matrix P C1 B and P B1 C are respectively mapped to the arrays previously mapped by B and C (the subscripts (+) and (-) respectively represent positive and negative matrices, and the subscript f represents the vertical flip operation), and the gating circuit analog switch groups S1, S2, S3 and S4 are turned on, and the gating circuit analog switches S5 and S6 are turned off, at this time the whole system is changed into two independent small-scale matrix generalized inverse matrix solving circuits, and the required calculation vectors y are respectively input at ports P5 and P6, that is, the output voltage vectors (P C1 B) + y and (P B1 C) + y can be respectively obtained at ports P1 and P2, and then the final left inverse matrix calculation result A + y = [(P C1B) + y(P B1 C) + y] T To solve all elements of matrix A + the input vector y can be replaced with a one-hot encoded scanning voltage, and the voltage scanning operation demonstrated in the first step can be performed sequentially to obtain matrix A + .

[0049] Figure 6 is a schematic diagram of the specific implementation of the first step of the right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the present invention. Considering a matrix A of size m×n, and m < n, after row partitioning it is expressed as A = [B T C T T , the size of matrix B is p×n, the size of matrix C is q×n, and matrices B T and C T are respectively mapped to arrays of two similar circuits of mapping matrices M and N described as Figure 1 , and p + q = m. The known vector y is row partitioned, i.e., y = [y1 T y2 T T , the size of vector y1 is p×1, and the size of vector y2 is q×1 (subscripts (+) and (-) represent positive and negative matrices respectively, and subscript f represents a vertically flipped matrix). Figure 6 (a) and Figure 6 (b) can solve BP C2 and CP B2 respectively. In Figure 6 (a), the circuit analog switch groups S2, S4, and S6 are selected, and the circuit analog switch groups S1, S3, and S5 are turned off. For the circuit at this time, when the voltage vector x is input at port P6, the voltage output vector obtained on the array row lines after passing through the lower part of the circuit is V t =-c -1 P C2 x, and this voltage vector is continuously input to the subsequent circuit, and then the voltage output vector V out =-G0 -1 G B V t =c -1 BP C2 ​​x, where c is the ratio of the transconductance of the transimpedance amplifier to the reference conductance. Based on the above analysis, by sequentially inputting the scanning voltage in the form of a one-hot code at port P6 (if the number of column lines is 3, that is, inputting the voltage signals of [0 01V], [0 1V0], [1V 0 0] in sequence), for the i-th input, c can be obtained at the output port P3. -1 BP C2 The vector composed of the elements in the i-th column of , c can be obtained by inputting voltages in sequence -1 BP C2 All element values ​​of , and then the matrix BP can be obtained by scaling the coefficients C2 Element information. Figure 6 (b), CP B2 The solution operation logic is consistent with the above description, except that in solving CP B2 When the circuit analog switch group S1, S3 and S6 need to be turned on, the circuit analog switch group S2, S4 and S5 need to be turned off. At the same time, the scan voltage needs to be input at port P5, and the final result is output by port P4.

[0050] Figure 7 This is a schematic diagram of a specific implementation method of the second step of the right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the present invention. Figure 6 BP described C2 and CP B2 The calculation results of the matrix (BP C2 ) T and (CP B2 ) T Map them to B respectively T and C T The array is in (the superscript T represents the transposition operation, the subscripts (+) and (-) represent the positive and negative matrices respectively, and the subscript f represents the vertical flip operation), and the circuit analog switch group S1, S2, S3, and S4 are turned on, and the circuit analog switches S5 and S6 are turned off. At this time, the entire system is transformed into two independent small-scale matrix generalized inverse matrix solving circuits. The vectors y1 and y2 after the block calculation of the required calculation vector y are input to ports P3 and P4 respectively, and the output voltage vector (BP) can be obtained at ports P7 and P8 respectively. C2 ) + y1 and (CP B2 ) + y2, and then the final right inverse matrix calculation result can be obtained as A + y=(BP C2 ) + y1+(CP B2 ) + y2. If you need to solve the matrix A +The input vector y can be replaced by the scanning voltage in the form of one-hot code and then input in blocks, and the voltage scanning operation demonstrated in the first step is performed in turn, so that the matrix A + .

[0051] Finally, it is important to note that the purpose of the embodiments disclosed herein is to illustrate the inventive concepts further, but it will be appreciated by those skilled in the art that various alternatives and modifications can be made without departing from the spirit and scope of the present application and the appended claims. Accordingly, the present application should not be limited to the embodiments disclosed herein, but should be given the full scope defined by the claims.

Claims

1. A generalized inverse matrix solving circuit based on block matrix, for solving generalized inverse matrices of column block matrices M, N of a target real number matrix A, A = [M N], the matrix A has a size of m x n and m > n, the matrix M has a size of m x p, the matrix N has a size of m x q, and p + q = n, characterized by, The circuit is composed of two circuits connected by two groups of analog switches, one of which is used for mapping and processing the block matrix M, and the other is used for mapping and processing the block matrix N; Let the matrix M be represented as M = M (+) - M (-) , where M (+) = (M + |M|) / 2, M (-) = (|M| - M) / 2, M (+) and M (-) are the actual mapped matrix values representing the positive and negative elements of the original matrix, respectively; and let the matrix N be represented as N = N (+) - N (-) , where N (+) = (N + |N|) / 2, N (-) = (|N| - N) / 2, N (+) and N (-) are the actual mapped matrix values representing the positive and negative elements of the original matrix, respectively. The circuit of the mapping matrix M includes four groups of resistive memory arrays, multiple analog inverters INV, multiple trans-impedance amplifiers TIA, multiple operational amplifiers OPA, multiple input reference resistors, multiple analog switches and eight input and output ports; the four groups of resistive memory arrays are arranged in a field layout, the first two groups of resistive memory arrays respectively map M (+) and M (-) , the last two groups respectively map M (-) and M (+) , the column lines of the arrays mapping M (+) in the first two groups are connected to the column lines of the arrays mapping M (-) through analog inverters, the two array row lines are connected, and the array row lines of M (-) are connected to the input ends of the trans-impedance amplifiers through analog switches, the output ends of the trans-impedance amplifiers are connected to the row lines of the arrays mapping M (+) in the last two groups of arrays through analog switches, and then the row lines of the arrays mapping M (-) in the last two groups of arrays are connected through analog inverters, the column lines of the last two groups of arrays are connected and connected to the positive input ends of the operational amplifiers through analog switches, the reverse input ends of the operational amplifiers are grounded, and the output ends are connected to the column lines of the first two groups of arrays through analog switches; the input and output ports are connected through the input reference resistors G0 in the commonly connected row lines of the first two groups of arrays and the commonly connected column lines of the last two groups of arrays, respectively, and the input and output ports are directly connected in the column lines of the arrays mapping M (+) in the first two groups of arrays and the row lines of the arrays mapping M (+) in the last two groups of arrays, to complete the calculation operation; meanwhile, the circuit mapping the matrix M is vertically flipped in layout, wherein the mapping matrix is a corresponding vertically flipped matrix, the matrix M f after the vertical flipping operation has the same size as M but the row order is reversed; The circuit of the mapping matrix N and the circuit of the mapping matrix M have the same topology, and the difference is that the number of columns of the resistive memory array is different. The first two groups of resistive memory arrays respectively map N (-) and N (+) , and the last two groups respectively map N (+) and N (-) . The circuit for mapping matrix M and the circuit for mapping matrix N are connected by two groups of analog switches, one group of analog switches is used to control the connection of the row lines of the first two groups of arrays in the two circuits, and the other group of analog switches is used to control the connection of the row lines of the last two groups of arrays in the two circuits.

2. The block matrix-based generalized inverse matrix solving circuit of claim 1, wherein, The resistive memory arrays of the circuit for mapping and processing matrix M are all m×p in size, and the resistive memory arrays of the circuit for mapping and processing matrix N are all m×q in size, and m>(p+q) is satisfied.

3. A method of solving a left inverse matrix vector product A y for a target solution matrix A based on a block matrix based generalized inverse matrix solving circuit as claimed in claim 1 or 2, solving its left inverse matrix vector product A y for a target solution matrix A + y, A + = (A T A) -1 A T whose column and row block partitioned matrix is B, C, solving problem is converted to A + y = [(P C1 B) + y (P B1 C) + y] T wherein, P B1 = I - B (B T B) -1 B T 、P C1 = I - C (C T C) -1 C T characterized in that it comprises the following steps: The first step is to map the block matrices B and C to the generalized inverse of the block matrix to solve the resistive memory array of the circuit, adjust the analog switches of the circuit, and solve the matrix P C1 B and matrix P B1 All element values ​​of C; Second step, mapping matrix P C1 B and P B1 C to a block matrix generalized inverse matrix solution circuit resistive memory array, conditioning circuit analog switch, solution vector value (P C1 B) + y and (P B1 C) + y.

4. The method of claim 3, wherein the left inverse matrix solution of the block matrix-based generalized inverse matrix solution circuit is performed by: The first step of the steps maps the block matrix, specifically, positive and negative matrix values B (+) , B (-) of the B matrix are mapped to a resistive memory array in a circuit of a mapping processing matrix M, positive and negative matrix values C (+) , C (-) of the C matrix are mapped to a resistive memory array in a circuit of a mapping processing matrix N; The second step of the mapping matrix, specifically, mapping P C1 The positive and negative value matrix (P C1 B) of the B matrix (+) , (P C1 B) (-) to the resistive memory array of the first step of mapping the B matrix, mapping P B1 The positive and negative value matrix (P B1 C) of the C matrix (+) , (P B1 C) (-) to the resistive memory array of the first step of mapping the C matrix.

5. The left inverse matrix solving operation method of the generalized inverse matrix solving circuit based on a block matrix according to claim 3, wherein The first step is to adjust the circuit analog switch to solve the matrix P C1 B and matrix P B1 C, specifically, turning off all analog switches of the circuit of mapping processing matrix B and the analog switches between the row lines of the last two groups of arrays of the two circuits, connecting all analog switches of the circuit of mapping processing matrix C and the analog switches between the row lines of the first two groups of arrays of the two circuits; mapping B in the first two groups of arrays of the circuit of mapping processing matrix B (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix C is mapped in the last two arrays of the circuit. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. C1 The column vectors of B; After the calculation of the matrix P C1 After the calculation of the matrix B, all analog switches of the circuit mapping the matrix C are turned off and the analog switches between the row lines of the last two groups of arrays of the two circuits are turned on, while the analog switches of the circuit mapping the matrix B are turned on and the analog switches between the row lines of the first two groups of arrays of the two circuits are turned off. Mapping C in the first two arrays of the circuit that maps the processing matrix C (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix B is mapped in the last two arrays of the circuit of the mapping matrix B. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. B1 The column vectors of C.

6. The left inverse matrix solving operation method of the block matrix-based generalized inverse matrix solving circuit according to claim 3, wherein The second step of the step, adjust the circuit analog switch to solve the vector value, specifically, turn off the analog switch between the row lines of the first two groups of arrays of the two circuits and the analog switch between the row lines of the last two groups of arrays, and connect the mapping processing matrix P C1 The circuit of B and the mapping processing matrix P B1 All analog switches of the circuit of C; respectively to the mapping processing matrix P C1 The circuit of B and the mapping processing matrix P B1 The input and output ports on the common row lines of the first two groups of arrays of the circuit of C are inputted with the known vector y through the input reference resistance, then the voltage outputted by the input and output ports on the row lines of the array of positive values of the mapping matrix of the first two groups of arrays of the two circuits respectively represent (P C1 B) + y and (P B1 C) + y, and finally the final left inverse matrix calculation result is A + y = [(P C1 B) + y (P B1 C) + y] T .

7. A right inverse matrix solving method based on the block matrix based generalized inverse matrix solving circuit as claimed in claim 1 or 2, for solving a right inverse matrix vector product A + y, A + = A T (AA T ) -1 , which is expressed as A = [B T C T ] T after row blocking, and y vector row blocking is y = [y1 T y2 T ] T , and the solving problem is converted into A + y = (BP C2 ) + y1 + (CP B2 ) + y2, wherein, P B2 = I - B T (BB T ) -1 B, P C2 = I - C T (CC T ) -1 C, characterized by the steps of: First, the matrices B T and C T are mapped into the resistive memory array of the block matrix generalized inverse matrix solving circuit, respectively, to solve the matrices BP C2 and CP B2 ; Second step, mapping (BP C2 ) T and (CP B2 ) T Matrix to block matrix generalized inverse matrix solving circuit in resistive memory array, solving vector (BP C2 ) + y and (CP B2 ) + y.

8. The method for solving a right inverse matrix of a generalized inverse matrix solving circuit based on a block matrix according to claim 7, wherein: The first step of the steps maps the block matrix, specifically, B T The positive and negative matrix values of the matrix B T (+) B T (-) The resistive memory array in the circuit mapping to the mapping processing matrix M maps C T The positive and negative matrix values of the matrix C T (+) C T (-) The resistive memory array in the circuit mapping to the mapping processing matrix N The second step of the mapping matrix, specifically, mapping (BP C2 ) T The positive and negative value matrix of the matrix (BP C2 ) T (+) , (BP C2 ) T (-) To the first step of the mapping B T The resistive memory array of the matrix, mapping (CP B2 ) T The positive and negative value matrix of the matrix (CP B2 ) T (+) , (CP B2 ) T (-) To the first step of the mapping C T The resistive memory array of the matrix.

9. The method of claim 7, wherein the right inverse matrix solution operation of the block matrix-based generalized inverse matrix solution circuit is performed by the following steps of: (a) calculating the right inverse matrix solution of the block matrix-based generalized inverse matrix solution circuit by using the following equation: ###0003### (b) calculating the right inverse matrix solution of the block matrix-based generalized inverse matrix solution circuit by using the following equation: ###0004### The first step of the step adjusts the analog switch of the circuit, specifically, turns off all analog switches of the circuit of the mapping processing matrix B T and the analog switches between the row lines of the first two groups of arrays of the two circuits, connects all analog switches of the circuit of the mapping processing matrix C T and the analog switches between the row lines of the last two groups of arrays of the two circuits; the input and output ports on the common row lines in the first two groups of arrays of the circuit of the mapping processing matrix C T sequentially input voltage signals in the form of one-hot code through input reference resistors, and the output voltage obtained through the reference resistors of the input and output ports on the common column lines in the last two groups of arrays of the circuit of the mapping processing matrix B T is scaled by a coefficient to obtain each column vector of the matrix BP C2 ; After the calculation of the matrix BP C2 , all the analog switches of the circuit of the mapping processing matrix C T and the analog switches between the row lines of the first two groups of arrays of the two circuits are turned off, all the analog switches of the circuit of the mapping processing matrix B T and the analog switches between the row lines of the last two groups of arrays of the two circuits are turned on; the input and output ports on the common row lines in the first two groups of arrays of the circuit of the mapping processing matrix B T are sequentially inputted with voltage signals in the form of one-hot code through input reference resistors, and after each input, the output voltage obtained by the input and output ports on the common column lines in the last two groups of arrays of the circuit of the mapping processing matrix C T is scaled by the reference resistors to obtain each column vector of the matrix CP B2 .

10. The method for solving a right inverse matrix of a generalized inverse matrix solving circuit based on a block matrix according to claim 7, wherein: The second step of the step adjusts the circuit analog switch solution vector value, specifically, turn off the analog switch between the row lines of the first two groups of arrays of the two circuits and the analog switch between the row lines of the last two groups of arrays, and connect the mapping processing matrix P C1 The circuit of B and the mapping processing matrix P B1 All analog switches of the circuit of C; respectively to the mapping processing matrix P C1 The circuit of B and the mapping processing matrix P B1 The input and output ports on the common column lines of the last two groups of arrays of the circuit of C input the known vectors y1 and y2 through the reference resistance, then the voltage output by the input and output ports on the row lines of the array of positive values of the mapping matrix of the last two groups of arrays of the two circuits respectively represent (BP C2 ) + y1 and (CP B2 ) + y2, and the final right inverse matrix calculation result is A + y=(BP C2 ) + y1+(CP B2 ) + y2.

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