Power electronic converter simulation method and system based on binary resistance model

Abstract

The invention belongs to the related technical field of simulation modeling, and discloses a power electronic converter simulation method and system based on a binary resistance model, and the whole steps are divided into three stages: at the moment k, at the stage 1, a predicted state vector xc (k) is updated, and at the stage 2, the state vector xc (k) is updated; the predicted half-bridge natural switching state combination # imgabs0 #, the flag signal (k) and the real half-bridge natural switching state combination [sigma] hd (k) are sequentially updated in a phase 2. And finally, completing the combination of vectors flag (k), sigma hd (k) and # imgabs1 # in a stage 3, and updating a state vector x (k). According to the method, the state combination switching time of the half-bridge of the natural switch can be accurately recognized, the half-bridge natural switch state combination can be updated only through simple logical operation, the state equation only needs to be calculated once in the whole calculation process, and therefore the modeling calculation amount is extremely low.

Description

Technical Field

[0001] The present invention belongs to the technical field related to simulation modeling, and more specifically, relates to a power electronic converter simulation method and system based on a binary resistance model. Background Art

[0002] With the widespread application of wide bandgap semiconductors, power electronic converters are gradually developing towards high switching frequencies. Therefore, studying real-time simulation technology that can be applied to high switching frequencies is currently a research hotspot in the field of real-time simulation.

[0003] The power electronic converter has a series of half-bridge structures, each of which includes an upper switch tube and a lower switch tube. It is the most commonly used switch network unit for high-frequency power electronic converters. The binary resistance switch model is one of the most commonly used switch models in the field of real-time simulation modeling. This model treats the switch as a small on-resistance R when the switch is turned on. on , to simulate the short-circuit state; when the switch is turned off, it is equivalent to a large off resistance R off , to simulate the open circuit state. Therefore, the binary resistance switch model is also called R on / R off Switch model. Existing literature points out that using R on / R off The power electronic converter model established by the switch model has higher accuracy than the power electronic converter model established by other switch models.

[0004] Under normal circumstances, the half-bridge has three operating modes, namely forward conduction mode, reverse conduction mode and blocking mode (that is, the mode in which both diodes on the half-bridge are turned off). on / R off There is a problem of difficulty in determining the blocking mode when modeling the switch model. Because the real-time simulation uses a fixed-step solver, the half-bridge input current cannot be accurately calculated to zero, and the blocking mode cannot be identified. Failure to identify the blocking mode will lead to zero-crossing oscillation problems and oscillation problems of the resonant converter during the resonance process. For example, when the series load resonant (SLR) converter works in the resonance process, because the blocking mode cannot be identified, the real-time simulation will produce obvious oscillation phenomena, but this oscillation phenomenon will not appear in the actual hardware circuit. Failure to determine the blocking mode will reduce the reliability and accuracy of the real-time simulation.

[0005] The existing literature ("Modeling Method for the Real-Time Simulation of Bridge-Based High-Switching-Frequency Power Electronic Converters," in IEEE Transactions on Power Electronics, vol. 39, no. 9, pp. 11723-11731, Sept. 2024, doi: 10.1109 / TPEL.2024.3402428) proposed a prediction correction method to realize the judgment of blocking mode. By predicting the state vector, it is judged whether the state of the diode on the half-bridge has changed, and the switch state combination of the half-bridge at the current moment is updated according to the direction of the current at the previous moment. However, this prediction correction method needs to calculate the state equation twice, which significantly increases the amount of modeling calculations.

[0006] Therefore, studying simulation methods with low computational complexity and guaranteed simulation accuracy is of great significance for the reliable simulation of high-frequency power electronic converters. Summary of the invention

[0007] In view of the above defects or improvement needs of the prior art, the present invention provides a power electronic converter simulation method and system based on a binary resistance model, which aims to reduce the amount of calculation and ensure the simulation accuracy.

[0008] To achieve the above object, the present invention provides a power electronic converter simulation method based on a binary resistance model, which comprises:

[0009] Get the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half-bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gate signal of its forced switch;

[0010] Determine the state matrix and input matrix. If the flags flag(k-1) of all natural switch half bridges at time k-1 are unchanged, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of Δt. Otherwise, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of 2Δt. Construct the state equation at time k based on the state matrix, input matrix, actual state vector x(k-1) at time k-1 and input vector u(k) at time k to obtain the predicted state vector x at time k. c (k);

[0011] According to xc (k) Update the predicted switching state combination of the natural switching half bridge to

[0012] Determine the actual switching state combination σ of each natural switching half bridge at time k hd (k) If or hd (k-1)=σ h0 , then σ hd (k) = σ h c d (k), otherwise, σ hd (k) = σ h0 , σ h0 is the switch state combination in half-bridge blocking mode;

[0013] Record the flag(k) of each natural switch half bridge at time k. If flag(k-1) is a change mark or Then flag(k) is recorded as no change mark, otherwise, flag(k) is recorded as a change mark;

[0014] Correction obtains the actual state vector x(k) at the current time k. If the flag(k-1) of all natural switch half-bridges is unchanged and there is a natural switch half-bridge satisfying Then x(k)=x(k-1), otherwise, x(k)=x c (k).

[0015] Optionally, the signal flag takes a first value as a mark of change and a second value as a mark of no change.

[0016] Optionally, construct a flag vector flag(k-1) at time k-1, where the flag vector flag(k-1) contains flags of all natural switch half-bridges at time k-1;

[0017] Determine whether the marks of all natural switch half bridges at time k-1 are all unchanged marks, including:

[0018] It is determined whether the marking vector flag(k-1) at time k-1 is the second value vector. If so, it is determined that the markings of all natural switch half bridges at time k-1 are unchanged markings.

[0019] Optionally, the flag vector flag(k-1) further includes flags of all forced switching half-bridges at time k-1, and the flags of the forced switching half-bridges are directly assigned to the second value.

[0020] Optionally, the first value is 1 and the second value is 0.

[0021] Optionally, the switch used by the natural switch half-bridge is a diode or a gate-controlled switch whose gate control signals are all 0, and the switch used by the forced switch half-bridge is a gate-controlled switch and at least one gate control signal is not 0.

[0022] Optionally, the power electronic converter is any one of an LLC resonant converter, a series load resonant converter, a dual active bridge converter, and a three-phase inverter.

[0023] The present invention also provides a power electronic converter simulation system based on a binary resistance model, which comprises:

[0024] The switch state prediction module is used to obtain the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half-bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gate signal of its forced switch;

[0025] The state vector prediction module is used to determine the state matrix and the input matrix. If the flag(k-1) of all natural switch half bridges at time k-1 is a non-changing flag, the state matrix and input matrix simulated based on σ*(k) with a step size of Δt are obtained. Otherwise, the state matrix and input matrix simulated based on σ*(k) with a step size of 2Δt are obtained. The state equation at time k is constructed based on the state matrix, the input matrix, the actual state vector x(k-1) at time k-1 and the input vector u(k) at time k to obtain the predicted state vector x at time k. c (k);

[0026] The switch state prediction update module is used to update the switch state according to x c (k) Update the predicted switching state combination of the natural switching half bridge to

[0027] The switch state determination module is used to correct the actual switch state combination σ of each natural switch half bridge at time k hd (k) If or hd (k-1)=σ h0 ,but Otherwise, σ hd (k) = σ h0 , σ h0 is the switch state combination in half-bridge blocking mode;

[0028] The marking module is used to record the flag(k) of each natural switch half bridge at time k. If flag(k-1) is a no-change mark or Then flag(k) is recorded as no change mark, otherwise, flag(k) is recorded as a change mark;

[0029] The state vector correction module is used to correct the actual state vector x(k) at the current time k. If the flag(k-1) of all natural switch half bridges is unchanged and there is a natural switch half bridge that satisfies Then x(k)=x(k-1), otherwise, x(k)=x c (k).

[0030] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0031] The present invention also provides a computer program product, comprising a computer program or instructions, characterized in that when the computer program or instructions are executed by a processor, the steps of any of the methods described above are implemented.

[0032] In general, compared with the prior art, the above technical solutions conceived by the present invention mainly have the following beneficial effects:

[0033] The power electronic converter simulation method based on the binary resistance model proposed in the present invention realizes the decoupling of updating the state variables and updating the switch state combination by the overall prediction and correction method, and realizes the prediction and correction of the switch state of the natural switch half-bridge by analyzing the switching principle of the natural switch half-bridge. At the same time, when updating the state vector, if a state combination change occurs in a natural switch half-bridge from the k-2 moment to the k-1 moment, the present invention will force the state variable at the k-1 moment to remain the same as the k-2 moment, and then update the state vector at the k moment from the k-2 moment with twice the simulation step size 2Δt at the k moment. Therefore, the present invention can accurately identify the state combination switching moment of the natural switch half-bridge, and only needs to use simple logical operations to update the half-bridge natural switch state combination. Only one state equation needs to be calculated in the entire calculation process, so it has extremely low modeling calculation amount. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a flowchart of the steps of a power electronic converter simulation method based on a binary resistance model in one embodiment of the present invention;

[0035] Figure 2 It is the state interval division diagram of the diode half bridge;

[0036] Figure 3 is a flow chart of a simulation method in one embodiment of the present invention;

[0037] Figure 4is a schematic diagram of the topology of an SLR converter circuit in one embodiment of the present invention;

[0038] Figure 5 It is an offline simulation waveform comparison between the constructed SLR converter model in one embodiment and the MATLAB / Simulink reference model;

[0039] Figure 6 It is a real-time simulation waveform of an SLR converter model in one embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0041] In order to facilitate the understanding of the present invention, the traditional method of simulating a power electronic converter based on a binary resistance model is first introduced. The power electronic converter can be an LLC resonant converter, a series load resonant converter, a dual active bridge converter, a three-phase inverter, etc.

[0042] Based on R on / R off The system network equation of the switch model is described by the time domain state equation shown in formula (1):

[0043]

[0044] In the formula, x is the state vector, u is the input vector, and A σ is the time domain system state matrix, B σ is the input matrix of the time domain system. The state vector is composed of the inductor current and capacitor voltage of the converter. The input vector is composed of the excitation signal source of the converter. The state matrix and input matrix can be obtained by deriving the KVL equation of the inductor voltage in the circuit and the KCL equation of the capacitor current in the circuit.

[0045] In order to ensure the numerical stability of the model, equation (1) is discretized using the backward Euler discretization method. The discretized system state equation is shown in equation (2):

[0046]

[0047] Where k is the discrete system sampling time, I is the unit matrix, Δt is the simulation step size, and F σ is the discrete system state matrix, H σ is the input matrix of the discrete system, and σ is the combination of system switch states.

[0048] To solve the system state equation as shown in formula (2), it is necessary to determine the system switch state combination σ. Based on the system switch state combination σ, the state matrix F is determined. σ And the input matrix H σ .

[0049] The system switch state combination σ is composed of each half-bridge switch state combination σ h The half-bridge switch state combination reflects the on or off state of the upper switch tube and the lower switch tube of the half-bridge. Assuming that the system contains m half-bridges, the system switch state combination σ is updated using formula (3):

[0050] σ=4 0 σ h1 +4 1 σ h2 +....4 m-1 σ hm (3)

[0051] For the upper tube S a And down tube S b The half bridge formed has only four switch state combinations σ shown in formula (4) h0-3 , corresponding to blocking mode, reverse conduction mode, forward conduction mode and error mode respectively:

[0052]

[0053] In order to solve the system switching state combination σ shown in equation (3), it is necessary to determine the switching state combination of each half bridge.

[0054] Half-bridges are divided into natural switching half-bridges and forced switching half-bridges according to their control methods. Natural switching half-bridges are switches controlled by current direction, such as diode switches or gated switches with gate signals of 0. Forced switching half-bridges are switches controlled by gate signals, such as IGBT half-bridges with gate signals not equal to 0. Different types of half-bridges have different ways of updating their switch state combinations. The switch state combination of the forced switching half-bridge is denoted as the forced switching state combination σ hc , the switching state combination of the natural switching half bridge is recorded as σ hd , as shown in formula (5):

[0055]

[0056] Half-bridge forced switching state combination σ hc and the natural switch state combination σ hd Update using equation (6) and equation (7) respectively:

[0057]

[0058]

[0059] Update the mandatory switch state combination σ at time k hc (k) Only the gate signal g a and b Sampling completes the update.

[0060] However, from equation (7), we can see that the update of the half-bridge natural switch state combination σ at time k hd (k) It is necessary to know the half-bridge input current i at time k in advance h (k) and the half-bridge input voltage v h (k). However, from formula (2), we can see that updating i h (k) and v h (k) also needs to know σ in advance h (k), so the update of the state variables and the update of the switch status are coupled.

[0061] Existing research uses the predictive correction method to achieve the decoupling of the two calculation processes. First, the switch state combination of the half-bridge is determined by predictive correction, and then the state vector is updated. However, the predictive correction stage also requires the calculation of the state equation once, so the state equation needs to be calculated twice in the entire modeling process. This significantly increases the amount of modeling calculations and calculation delays. The large calculation delay makes it impossible to meet the requirements of gate signal oversampling at high switching frequencies, thereby reducing the reliability of real-time simulation.

[0062] The present invention provides a power electronic converter simulation method based on a binary resistance model. By correcting the predicted state variables, the state equation only needs to be calculated once, thus reducing the amount of modeling calculation.

[0063] like Figure 1 The figure shows a flow chart of the steps of a power electronic converter simulation method based on a binary resistance model in one embodiment of the present invention. It should be noted that the sequence of the steps is only an example, but not limited to this. Each step is described in detail below.

[0064] Step S1: Obtain the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half-bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gating signal of its forced switch.

[0065] In the traditional method, the half-bridge forced switch state combination and the natural switch state combination are updated using the above formula (6) and formula (7) respectively, where the forced switch state combination at time k only needs to be updated for the gate signal g a and b The prediction can be completed by sampling, while the natural switching state combination of the half-bridge at time k is difficult to determine directly due to its coupling with the state vector.

[0066] In the present invention, the forced switching half bridge It is also determined according to the gate control signal of the forced switch, specifically, according to formula (7) to determine σ hc,j (k) As

[0067] In the present invention, the actual switch state combination σ at the previous moment is directly hd,j (k-1) is the predicted state combination at the current moment

[0068] therefore, It can be expressed as:

[0069]

[0070] Among them, the natural switching half-bridge is a switch controlled by the current direction, such as a diode switch or a gated switch whose gate signals are all 0, and the forced switching half-bridge is a switch controlled by a gate signal, such as an IGBT half-bridge whose gate signal is not 0.

[0071] The converter system contains m half-bridges, and the predicted switching state combination σ*(k) of the system is updated in the same way as equation (3), as follows:

[0072]

[0073] Step S2: Determine the state matrix and the input matrix. If the flags flag(k-1) of all natural switch half bridges at time k-1 are unchanged, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of Δt. Otherwise, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of 2Δt. Construct the state equation at time k based on the state matrix, the input matrix, the actual state vector x(k-1) at time k-1, and the input vector u(k) at time k to obtain the predicted state vector x at time k. c (k).

[0074] In step S1, the predicted switch state combination σ*(k) of the system has been preliminarily predicted. Based on this σ*(k), the state matrix and input matrix under different simulation steps can be calculated. The state matrix and input matrix are the coefficient matrices for constructing the system state equation shown in formula (2).

[0075] In the present invention, a flag is set to reflect whether the natural switch state combination has changed compared to the previous moment. The simulation step size at the current moment is determined based on the flag at the previous moment. Specifically, if the flag (k-1) of all natural switch half bridges at the k-1 moment is a non-change flag, the state matrix and input matrix simulated based on σ*(k) with a step size of Δt are obtained, otherwise, the state matrix and input matrix simulated based on σ*(k) with a step size of 2Δt are obtained. Among them, the flag at the previous moment is determined and recorded at the previous simulation moment.

[0076] In one embodiment, for the convenience of recording, the first value is used as a change mark, and the second value is used as a no-change mark. For example, the first value is 1 and the second value is 0. That is, if flag=1, it indicates that the switching state combination of the half bridge has changed. If flag=0, it indicates that the switching state combination of the half bridge has not changed.

[0077] Furthermore, for the convenience of comparison, the marking flags of all natural switching half-bridges at the same time at time k-1 are combined together to form a marking flag. For example, the marking vector flag(k-1) contains the markings of all natural switching half-bridges at time k-1. By judging whether the marking vector flag(k-1) at time k-1 is the second value vector, it is judged whether the markings of all natural switching half-bridges at time k-1 are unchanged markings.

[0078] Considering that there may be a type conversion between the natural switch half-bridge and the forced switch half-bridge, for example, when using a gated switch, if the gate control signals of the upper and lower bridge arms are both 0, it is a natural switch half-bridge, otherwise, it is a forced switch half-bridge. For the half-bridge using this type of switch, the gate control signal is different, which may change the type of the half-bridge. Therefore, in order to coordinate the overall situation and facilitate comparison, all forced switch half-bridges are also marked, and the mark of the forced switch half-bridge is directly assigned to the second value. In this way, the mark vector flag comprehensively represents the mark of the global half-bridge of the system. Regardless of whether the half-bridge type changes, the vector flag can be directly called for judgment.

[0079] For example, the state matrix and input matrix of the simulation based on σ*(k) with a step size of Δt are respectively recorded as and The state matrix and input matrix of the simulation based on σ*(k) with a step size of 2Δt are respectively recorded as and The final selected state matrix and input matrix are recorded as and

[0080] matrix And the matrix Updated by the following equations (10) and (11):

[0081]

[0082] In determining the state matrix and the input matrix After that, we can refer to the above formula (2) to construct the system state equation as follows:

[0083]

[0084] By solving the state equation of the system, the state vector at time k is predicted, that is, the predicted state vector x at time k is obtained. c (k).

[0085] Step S3: According to x c (k) Update the predicted switching state combination of the natural switching half bridge to

[0086] Through step S2, the state vector x is predicted c (k), based on the predicted state vector x c (k), according to the formula (7) introduced above, the switching state combination of the natural switching half bridge is re-predicted and updated to

[0087] Step S4: Determine the actual switch state combination σ of each natural switch half bridge at time k hd (k) If or hd (k-1)=σ h0 ,but Otherwise, σ hd (k) = σ h0 , σ h0 is the switch state combination in half-bridge blocking mode.

[0088] Specifically, according to the updated prediction results Determine the actual switch state combination of the half bridge, which can be expressed as:

[0089]

[0090] Step S5: Record the flag(k) of each natural switch half bridge at time k. If flag(k-1) is a change mark or Then flag(k) is recorded as a no-change flag, otherwise, flag(k) is recorded as a change flag.

[0091] Specifically, the update formula of flag(k) can be expressed as follows:

[0092]

[0093] Step S6: Correct the actual state vector x(k) at the current time k. If the flag(k-1) of all natural switch half bridges is unchanged and there is a natural switch half bridge that satisfies Then x(k)=x(k-1), otherwise, x(k)=x c (k).

[0094] Specifically, the update formula of the actual state vector x(k) can be expressed as follows:

[0095]

[0096] In the formula, is a vector consisting of the natural switching state combinations of all natural switching half-bridges at time k.

[0097] The principle of the above scheme is explained below.

[0098] First, the prediction and correction methods of the natural half-bridge switching state are explained.

[0099] In the present invention, there is a coupling problem between the updating of the state variables and the updating of the switch state combination. The present invention also uses a predictive correction method to achieve the decoupling of the two calculation processes. When making a prediction in step S1, it is assumed that the switching state of the natural switch half bridge at time k has not changed compared to time k-1, that is, Based on this assumption, the state equation is constructed to obtain the predicted state vector x based on this assumption. c (k), and then analyze the state vector x c (k) The switching state of the natural switching half-bridge under the above assumptions. If the switching state obtained based on the above assumptions is consistent with the assumed switching state, that is, if This indicates that the prediction is accurate and the actual switching state combination of the natural switching half bridge at time k

[0100] At the same time, by analyzing the switching principle of the natural switching half-bridge, if the above prediction results are not met, the prediction results can also be corrected.

[0101] Take the diode half bridge as an example. Figure 2 The figure shows the state interval division diagram of the diode half bridge. The state switching principle of the diode half bridge is: due to the half bridge input current i h and the half-bridge input voltage v h are all continuously changing, for example, i h is the inductor current of the half bridge, v his the capacitor voltage of the half-bridge or the input DC voltage. These variables cannot change suddenly. Therefore, for the diode half-bridge, from the forward conduction mode (σ h2 ) or reverse conduction mode (σ h1 ) must enter blocking mode when a state change occurs (σ h0 ); when a state change occurs from blocking mode, as long as v h If it is greater than zero, it will definitely enter any conduction mode. Therefore, the prediction correction method is used to predict in advance whether the state of the diode half bridge will change and correct the switch state combination based on the above state change principle.

[0102] If the half-bridge is in blocking mode at time k-1 (σ h0 ), the half bridge may enter any mode at time k. The prediction result at this time is usually more accurate. Therefore, the prediction result is directly used as the actual result without correction. That is, if σ hd (k-1)==σ h0 , then it is believed that

[0103] The predictions outside the above two cases are considered to have problems, that is, the half bridge is not in blocking mode at time k-1 (σ h0 ), and the prediction result reflects that the switching state of the half-bridge at time k is different from the switching state at time k-1, which means that the switching state of the half-bridge at time k has changed. Based on the above analysis of the half-bridge state interval, the half-bridge can only enter the blocking mode from the non-blocking mode at time k-1, so it needs to be corrected to the blocking mode (σ h0 ), that is, σ hd (k) = σ h0 .

[0104] Thus, the switch state prediction and correction formula of formula (13) in the above step S4 is obtained.

[0105] Next, the determination of the state vector is described.

[0106] In the present invention, if a state combination change occurs in a natural switch half bridge from time k-2 to time k-1, the present invention will force the state variable at time k-1 to remain the same as that at time k-2, that is, x(k-1)=x(k-2), and then update the state vector x(k) at time k from time k-2 at twice the simulation step length 2Δt. This method can reduce the amount of calculation.

[0107] For ease of representation, the state vector updated with a simulation step length of Δt is represented as x p (k), the state vector updated with twice the simulation step size 2Δt is represented as x 2Δt, the system switch state combination predicted at time k is recorded as

[0108] If the switch state predicted at time k-1 has changed, that is, if Then at time k, the state vector x(k) at time k is updated from time k-2 with twice the simulation step length 2Δt, that is, x(k) = x 2Δt (k).

[0109] If the switch state predicted at time k-1 does not change, but the switch state predicted at time k changes, that is, if and Then the state variables at time k are forced to remain the same as those at time k-1, that is, x(k)=x(k-1).

[0110] If the switch state predicted at time k-1 does not change, and the switch state predicted at time k does not change, that is, if and Then the predicted x obtained by normal simulation at time k with double the simulation step length is p (k) is the state vector x(k) at time k, that is, x(k) = x p (k).

[0111] In summary, the state vector at time k is updated as shown in the following formula (16):

[0112]

[0113] Predict x with double simulation step length Δt p The system state equation expression of (k) is as follows:

[0114]

[0115] In the formula, the matrix And the matrix is the coefficient matrix corresponding to the switch state combination σ* at one simulation step Δt.

[0116] Update x with twice the step size 2Δt The system state equation expression of (k) is as follows:

[0117]

[0118] In the formula, the matrix And the matrix is the coefficient matrix corresponding to the switching state combination σ* at twice the simulation step length 2Δt.

[0119] It can be seen that the update x in formula (16) p (k) and x2Δt (k) The corresponding system state equation is different, so the state equation needs to be calculated twice. Compared with the traditional method, its calculation amount has no obvious advantage.

[0120] However, since the present invention proposes that when the state combination switches from time k-1 to time k, the algorithm of formula (15) forces x(k) to be equal to x(k-1), therefore, when condition 3 in formula (16) When it is satisfied, x(k-1)=x(k-2). Therefore, formula (18) can be rewritten as shown in formula (19):

[0121]

[0122] Since x in the update formula (17) p (k) and x in formula (19) 2Δt (k) both need to use x(k-1) and u(k), that is, update x p (k) and x 2Δt (k) The corresponding system state equation has the same form, that is, the function is the same. The only difference is that the coefficient matrix substituted into the function is different. Therefore, the corresponding coefficient matrix can be selected at different times according to whether the state change occurs at the current time and the previous time, and the same function can be substituted, thereby calculating the system state equation only once.

[0123] Therefore, x can be p (k) and x 2Δt (k) is uniformly represented as the state vector x c , the coefficient matrix under different step lengths is uniformly expressed as a matrix And the matrix x p (k) and x 2Δt (k) The corresponding system state equation is uniformly expressed as the following form of equation (20) above:

[0124]

[0125] At the same time, the flag signal is used to indicate whether the switch state combination of the natural switch half bridge has changed. Therefore, the final formula (16) can be rewritten as the following form of the above formula (21):

[0126]

[0127] It can be seen that at each moment, it is only necessary to select the corresponding coefficient matrix in step S2 according to whether a state change has occurred at the current moment and the previous moment to solve the state equation. Therefore, the system state equation is only calculated once for each simulation, which greatly reduces the amount of calculation. Moreover, when determining the state matrix and the input matrix, the system switch state combination σ*(k) based on it takes into account the influence of the gate signal at the k moment. Compared with the traditional prediction and correction method that does not consider the influence of the gate signal at the k moment on the state variable, the prediction method of the present invention has higher accuracy.

[0128] like Figure 3 The flowchart of the simulation method in one embodiment of the present invention is shown. The whole process is divided into three stages: at time k, in stage 1, the predicted state vector x is updated. c (k), and then in stage 2 the predicted half-bridge switch state combinations are updated sequentially And the flag signal flag(k) and the half-bridge switch state combination σ hd (k), where the flag signal flag(k) and the half-bridge switch state combination σ hd (k) can be calculated in parallel. Finally, in stage 3, the vector flag(k), σ hd (k) and update the state vector x(k).

[0129] The significant advantages of the present invention are: 1) It can accurately identify the state combination switching moment of the natural switch half-bridge, and only needs simple logical operations to update the half-bridge natural switch state combination. 2) The state equation only needs to be calculated once in the entire calculation process, so it has extremely low modeling calculation amount. 3) The calculation path of modeling is short, which greatly improves the calculation efficiency of modeling, thereby ensuring oversampling of the gate signal at high switching frequency.

[0130] Accordingly, the present invention also relates to a power electronic converter simulation system based on a binary resistance model, comprising:

[0131] The switch state prediction module is used to obtain the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half-bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gate signal of its forced switch;

[0132] The state vector prediction module is used to determine the state matrix and the input matrix. If the flag(k-1) of all natural switch half bridges at time k-1 is a non-changing flag, the state matrix and input matrix simulated based on σ*(k) with a step size of Δt are obtained. Otherwise, the state matrix and input matrix simulated based on σ*(k) with a step size of 2Δt are obtained. The state equation at time k is constructed based on the state matrix, the input matrix, the actual state vector x(k-1) at time k-1 and the input vector u(k) at time k to obtain the predicted state vector x at time k. c (k);

[0133] The switch state prediction update module is used to update the switch state according to x c (k) Update the predicted switching state combination of the natural switching half bridge to

[0134] The switch state determination module is used to correct the actual switch state combination σ of each natural switch half bridge at time k hd (k) If or hd (k-1)=σ h0 ,but Otherwise, σ hd (k) = σ h0 , σ h0 is the switch state combination in half-bridge blocking mode;

[0135] The marking module is used to record the flag(k) of each natural switch half bridge at time k. If flag(k-1) is a no-change mark or Then flag(k) is recorded as no change mark, otherwise, flag(k) is recorded as a change mark;

[0136] The state vector correction module is used to correct the actual state vector x(k) at the current time k. If the flag(k-1) of all natural switch half bridges is unchanged and there is a natural switch half bridge that satisfies Then x(k)=x(k-1), otherwise, x(k)=x c (k).

[0137] It can be understood that the above system can be used to implement the simulation method mentioned above, and each module therein can be used to implement the corresponding steps in the simulation method. For details, please refer to the above introduction and will not be repeated here.

[0138] The present invention also relates to a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps of the above method when executed by a processor.

[0139] Specifically, the storage medium may be an FPGA chip.

[0140] The present invention also provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of the method of the above embodiment of the present invention.

[0141] In order to verify the practicability of the method proposed in the present invention, the present invention simulates an SLR converter, such as Figure 4 shown. Figure 4 The SLR converter shown in the figure includes a resonant inductor L r , a resonant capacitor C r , an output capacitor C o , a load R o The primary side full bridge of the constructed SLR converter model includes a first switch tube S1, a second switch tube S2, a third switch tube S3 and a fourth switch tube S4, and the secondary side full bridge of the constructed SLR converter model includes a first diode d1, a second diode d2, a third diode d3 and a fourth diode d4. Lr is the current flowing through the resonant inductor L r The current, u Cr is the resonant capacitor C r The voltage on o is the output capacitor C o The voltage on in is the input DC voltage. g 1-4 For switch S 1-4 The gate signal of the switching frequency is f s The control strategy of the model is switch control, and the switching frequency is f s The frequency is 100kHz, the gate signals g1 and g2 are complementary and have a 300ns dead time, and the gate signals g3 and g4 are complementary and have a 300ns dead time.

[0142] The circuit parameters of the SLR converter model are set as shown in the following table:

[0143]

[0144]

[0145] Figure 5 The waveform comparison between the SLR model established by writing m language code in System generator software and the MATLAB / Simulink reference model is given. The simulation model established by the present invention is recorded as "model" and the MATLAB / Simulink reference model is recorded as "reference". The model simulation step size is 20ns. Figure 5(a), (b), (c), and (d) show the resonant current i of the constructed model and the MATLAB / Simulink reference model respectively. Lr The comparison of the resonant capacitor voltage v Cr The comparison of the resonant current i Lr The absolute error of the resonant capacitor voltage v Cr The absolute error of .

[0146] Can be obtained from Figure 5 It can be seen that the model constructed by the present invention not only does not have the zero-crossing oscillation problem caused by ignoring the blocking mode, but also achieves extremely high accuracy, and the resonant current i Lr And the resonant capacitor voltage v Cr The absolute error is less than 0.18A and 0.11V.

[0147] In order to further verify the reliability of the method proposed in the present invention, real-time simulation verification was carried out. The model built by real-time simulation is realized by writing Verilog code in Vivado software. The real-time simulation platform of this experiment is composed of an AX7325B FPGA development board of Alinx Company. The FPGA model is XC7K325TFFG900-2, with 203800 lookuptables (LUTs), 840 DSP48slices (DSP48s), 445 Block RAMs (BRAMs) and 407600 Flipflops. The digital signal generated by FPGA generates analog variables through AD9767 digital-to-analog chip and is displayed on the oscilloscope.

[0148] Figure 6 The real-time simulation test waveform is given, including the resonant current i Lr And the resonant capacitor voltage v Cr The simulation step size can be as low as 20ns, with a switching frequency of 100kHz.

[0149] Can be obtained from Figure 6 It can be seen that the model can run normally under the simulation step size of 20ns and the real-time simulation is consistent with the offline simulation. The reliability of the model built by the present invention is verified. The simulation step size of 20ns also far guarantees the oversampling requirement of the switching frequency of 100kHz.

[0150] The test results of the SLR converter real-time simulation model resources are shown in the following table:

[0151] parameter Numeric Total resources LUTs 2107(1.03％) 203800 DSP48s 36(4.29％) 840 BRAMs 0 445 Flipflops 683(0.17％) 407600

[0152] It can be seen from the above table that the constructed SLR converter model has extremely low resource consumption.

[0153] In summary, the blocking mode recognition method proposed in the present invention can not only accurately determine the half-bridge blocking mode switching time, but also greatly reduce the modeling calculation amount because the state equation is only calculated once, so that the computing resource consumption of FPGA is greatly reduced. At the same time, the built model can also run normally at a simulation step of 20ns, indicating that the method proposed in the present invention can also ensure the oversampling of the gate signal at a high switching frequency, thereby improving the computing efficiency of FPGA.

[0154] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. It should be noted that "in one embodiment", "for example", "for example", etc. of the present invention are intended to illustrate the present invention, rather than to limit the present invention.

[0155] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A power electronic converter simulation method based on a binary resistance model, characterized in that: include: Get the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half-bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gate signal of its forced switch; Determine the state matrix and input matrix. If the flags flag(k-1) of all natural switch half bridges at time k-1 are unchanged, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of △t. Otherwise, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of 2△t. Construct the state equation at time k based on the state matrix, input matrix, actual state vector x(k-1) at time k-1 and input vector u(k) at time k to obtain the predicted state vector x at time k. c (k); According to x c (k) Update the predicted switching state combination of the natural switching half bridge to Determine the actual switching state combination σ of each natural switching half bridge at time k hd (k) If or hd (k-1)=σ h0 ,but Otherwise, σ hd (k) = σ h0 , σ h0 is the switch state combination in half-bridge blocking mode; Record the flag(k) of each natural switch half bridge at time k. If flag(k-1) is a change mark or Then flag(k) is recorded as no change mark, otherwise, flag(k) is recorded as a change mark; Correction obtains the actual state vector x(k) at the current time k. If the flag(k-1) of all natural switch half-bridges is unchanged and there is a natural switch half-bridge satisfying Then x(k)=x(k-1), otherwise, x(k)=x c (k).

2. The simulation method according to claim 1, characterized in that: The signal flag takes the first value as a mark of change and the second value as a mark of no change.

3. The simulation method according to claim 2, characterized in that: Construct a flag vector flag(k-1) at time k-1, where the flag vector flag(k-1) contains the flags of all natural switch half-bridges at time k-1; Determine whether the marks of all natural switch half bridges at time k-1 are all unchanged marks, including: It is determined whether the marking vector flag(k-1) at time k-1 is the second value vector. If so, it is determined that the markings of all natural switch half bridges at time k-1 are unchanged markings.

4. The simulation method according to claim 3, characterized in that: The flag vector flag(k-1) also includes flags of all forced switching half-bridges at time k-1, and the flags of the forced switching half-bridges are directly assigned to the second value.

5. The simulation method according to any one of claims 2 to 4, characterized in that: The first value is 1 and the second value is 0.

6. The simulation method according to claim 1, characterized in that: The switch used by the natural switch half-bridge is a diode or a gate-controlled switch whose gate control signals are all 0, and the switch used by the forced switch half-bridge is a gate-controlled switch and at least one gate control signal is not 0.

7. The simulation method according to claim 1, characterized in that: The power electronic converter is any one of an LLC resonant converter, a series load resonant converter, a dual active bridge converter, and a three-phase inverter.

8. A power electronic converter simulation system based on a binary resistance model, characterized in that: include: The switch state prediction module is used to obtain the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half-bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gate signal of its forced switch; The state vector prediction module is used to determine the state matrix and the input matrix. If the flags flag(k-1) of all natural switch half bridges at time k-1 are unchanged, the state matrix and input matrix simulated based on σ*(k) with a step size of △t are obtained. Otherwise, the state matrix and input matrix simulated based on σ*(k) with a step size of 2△t are obtained. The state equation at time k is constructed based on the state matrix, the input matrix, the actual state vector x(k-1) at time k-1 and the input vector u(k) at time k to obtain the predicted state vector x at time k. c (k); The switch state prediction update module is used to update the switch state according to x c (k) Update the predicted switching state combination of the natural switching half bridge to The switch state determination module is used to correct the actual switch state combination σ of each natural switch half bridge at time k hd (k) If or hd (k-1)=σ h0 ,but Otherwise, σ hd (k) = σ h0 , σ h0 is the switch state combination in half-bridge blocking mode; The marking module is used to record the flag(k) of each natural switch half bridge at time k. If flag(k-1) is a no-change mark or Then flag(k) is recorded as no change mark, otherwise, flag(k) is recorded as a change mark; The state vector correction module is used to correct the actual state vector x(k) at the current time k. If the flag(k-1) of all natural switch half bridges is unchanged and there is a natural switch half bridge that satisfies Then x(k)=x(k-1), otherwise, x(k)=x c (k).

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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