Multi-FPGA collaborative deep neural network parallel acceleration method

Abstract

The invention discloses a multi-FPGA collaborative deep neural network parallel acceleration method, and the method comprises the steps: obtaining the resource quantity of a master control FPGA unit and each calculation FPGA unit, and each layer of parameters of a to-be-deployed deep neural network model; judging whether the calculation resource quantity required by the network layer of the to-be-deployed deep neural network model for completely expanding the calculation task on the output channel reaches the resource quantity of the master control FPGA unit or not, and if not, mapping the calculation task of the network layer to a calculation engine of the master control FPGA unit and executing the calculation task; and if the number of the calculation tasks reaches and is greater than or equal to the number of the calculation FPGA units, splitting the calculation tasks of the network layer according to the number of the calculation FPGA units, and mapping the split calculation tasks to a calculation engine of each calculation FPGA unit and executing the split calculation tasks. According to the method, the channel of the model network layer is segmented according to the splitting strategy determined by the calculation amount and the resource amount, then the calculation task is mapped to the calculation engine in each FPGA, and parallel acceleration can be realized by utilizing the performance gain brought by multiple FPGAs.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and more specifically to a multi-FPGA collaborative deep neural network parallel acceleration method. Background Art

[0002] Currently, deep neural networks (DNNs) have been widely used in many fields, such as image recognition, speech recognition, natural language processing, etc. However, the complexity and huge amount of computation of deep neural networks place extremely high demands on hardware resources. Traditional central processing units (CPUs) and graphics processing units (GPUs) still have shortcomings in terms of energy efficiency, real-time performance, and flexibility when running DNN models.

[0003] As a high-energy-efficiency hardware computing platform, field-programmable gate arrays (FPGAs) have great potential in accelerating deep neural networks due to their high parallel processing capabilities and programmability. FPGAs can be optimized for specific neural network models through customized hardware design, thereby greatly improving computing efficiency and energy efficiency. However, most existing FPGA-based deep neural network acceleration solutions are limited to a single FPGA, with limited computing performance, making it difficult to support deep neural network models with a large number of parameters. Therefore, how to use multiple FPGAs to collaborate on deep neural network acceleration has attracted attention.

[0004] By dividing the neural network model into multiple parts and processing them in parallel on multiple FPGAs, the parallel computing capabilities of FPGAs can be fully utilized to improve computing performance and energy efficiency. However, multi-FPGA collaborative processing also brings a series of new challenges. How to effectively divide and distribute the neural network model to multiple FPGAs, how to ensure data communication and synchronization between multiple FPGAs, and how to flexibly adjust the FPGA's computing resources and pipeline levels according to the characteristics and requirements of the neural network are all problems that need to be solved.

[0005] Among the existing methods, the Chinese patent "Convolutional neural network acceleration based on multi-FPGA ring communication" (application number: CN201810168597) uses multiple FPGAs to form a closed-loop structure connected end to end, and reduces communication bandwidth overhead and accelerates network training through data iteration, data exchange, and calculation of the average value of gradient error descent. The Chinese patent "A dual-FPGA collaborative working method for deep neural networks" (application number: CN202210749104) discloses a CNN neural network acceleration design method based on a multi-FPGA heterogeneous architecture, which divides the convolutional neural network into serial or parallel divisions and deploys it on multiple FPGAs to improve parallelism.

[0006] There are still two problems with the existing methods: First, all existing methods act as hierarchical accelerators to map the entire network layer in sequence, resulting in resource limitation bottlenecks and low resource utilization when facing large-scale networks; second, the existing methods divide all network layers, lack appropriate model splitting strategies, and cannot measure whether the network layer needs to be split. While utilizing the bandwidth benefits brought by multiple FPGAs, it also causes unnecessary transmission delays.

[0007] Therefore, the present invention proposes a multi-FPGA collaborative deep neural network parallel acceleration method, designs an efficient multi-FPGA data communication and synchronization mechanism, divides the channels of the model network layer at the software level according to the splitting strategy determined by the amount of computation and the amount of resources, and then maps the computing tasks to the computing engines in each FPGA, utilizing the performance gains brought by multiple FPGAs for parallel acceleration. Summary of the invention

[0008] In view of this, the present invention provides a multi-FPGA collaborative deep neural network parallel acceleration method and related system.

[0009] In order to achieve the above object, the present invention adopts the following technical solution:

[0010] On one hand, the present invention discloses a multi-FPGA collaborative deep neural network parallel acceleration method, comprising the following steps:

[0011] Obtain the resource amount of the main control FPGA unit and each computing FPGA unit, as well as the parameters of each layer of the deep neural network model to be deployed, and obtain the computing resource amount of each network layer to perform computing tasks;

[0012] If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing task on the output channel is less than the amount of resources of the master control FPGA unit, the computing task of the network layer is mapped to the computing engine of the master control FPGA unit and executed;

[0013] If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing tasks on the output channel is greater than or equal to the resources of the main control FPGA unit, the computing tasks of the network layer are divided into blocks on the output channel according to the number of computing FPGA units, and the split computing tasks are mapped to the computing engine of each computing FPGA unit and executed.

[0014] Furthermore, in the above method, the computing engine includes functional operators in the main control FPGA unit or the computing FPGA unit for computing reasoning tasks at each layer of the network.

[0015] Furthermore, in the above method, the amount of resources includes the number of DSPs in the main control FPGA unit or the computing FPGA unit used to execute computing tasks.

[0016] Another aspect of the present invention discloses a parallel acceleration system based on multi-FPGA collaborative deep neural network, which is used to execute the above method, including: a master control FPGA unit, several computing FPGA units, and a host;

[0017] The host performs the following operations:

[0018] Obtain the resource amount of the main control FPGA unit and each computing FPGA unit, as well as the parameters of each layer of the deep neural network model to be deployed, and obtain the computing resource amount of each network layer to perform computing tasks;

[0019] If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing task on the output channel is less than the amount of resources of the master control FPGA unit, the computing task of the network layer is mapped to the computing engine of the master control FPGA unit and executed;

[0020] If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing tasks on the output channel is greater than or equal to the resources of the main control FPGA unit, the computing tasks of the network layer are divided into blocks on the output channel according to the number of computing FPGA units, and the split computing tasks are mapped to the computing engine of each computing FPGA unit and executed.

[0021] Preferably, in the above system, the host is connected to each computing FPGA unit and the main control FPGA unit via a high-speed communication bus.

[0022] Preferably, in the above system, the master control FPGA unit supports an Internet interconnection protocol for multi-channel synchronous data transmission and reception.

[0023] Preferably, in the above system, each computing FPGA unit supports an Internet interconnection protocol for synchronously sending and receiving data on a single channel.

[0024] Preferably, in the above system, each computing FPGA unit is configured with an independent dynamic random access memory.

[0025] Preferably, in the above system, the host includes a compiler and a caller;

[0026] The compiler is used to identify the resource amount of the main control FPGA unit and each computing FPGA unit, as well as the parameters of each layer of the deep neural network model to be deployed; and determine whether the computing resource amount required for the network layer of the deep neural network model to be deployed to fully launch the computing task on the output channel is greater than or equal to the resource amount of the main control FPGA unit;

[0027] The scheduler is used to construct and execute the tasks of the deep neural network model to be deployed on each FPGA unit in a collaborative manner according to the parameters of each layer of the deep neural network model to be deployed and the model splitting results into an instruction set.

[0028] Preferably, in the above system, the host is also used for:

[0029] Receive the return status generated after executing the computing task of each network layer of the deep neural network model in each computing FPGA unit, and perform synchronous verification on the return status. After the verification is qualified, the next task execution instruction is sent to each computing FPGA unit, and the execution is cyclically executed in sequence until the deep neural network model reasoning is completed.

[0030] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a multi-FPGA collaborative deep neural network parallel acceleration method and system, which has the following beneficial effects:

[0031] The present invention can not only realize efficient data communication and parallel acceleration of multiple FPGAs, but also flexibly schedule resources according to the characteristics of computing tasks and the computing requirements of the network layer, and can perform reasoning on different deep neural networks with only one deployment without reconstruction. Therefore, it can effectively reduce the difficulty of deploying collaborative acceleration of deep neural networks on multiple FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0033] Figure 1 It is an overall flow chart of a method for implementing parallel acceleration of a multi-FPGA collaborative deep neural network in an embodiment of the present invention.

[0034] Figure 2 It is a schematic diagram of the overall system structure of the method for implementing multi-FPGA collaborative deep neural network parallel acceleration in an embodiment of the present invention.

[0035] Figure 3It is a flow chart of the data communication synchronization steps in the method described in the embodiment of the present invention.

[0036] Figure 4 The invention discloses a star-shaped logic structure diagram of interconnection between FPGAs in the method described in the embodiment of the invention.

[0037] Figure 5 It is a flow chart of the network model splitting steps in the method described in an embodiment of the present invention.

[0038] Figure 6 It is a specific schematic diagram of model splitting in the method described in an embodiment of the present invention.

[0039] Figure 7 It is a flowchart of the hardware mapping steps in the method described in an embodiment of the present invention.

[0040] Figure 8 It is a schematic diagram of the systolic array structure in the method described in an embodiment of the present invention.

[0041] Fig. 9 It is a flow chart of the system scheduling operation steps in the method described in the embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In general, an embodiment of the present invention discloses a multi-FPGA collaborative deep neural network parallel acceleration method, which mainly includes: obtaining the resource amount of the main control FPGA unit and each computing FPGA unit, as well as the parameters of each layer of the deep neural network model to be deployed, and obtaining the computing resource amount of each network layer to perform computing tasks;

[0044] If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing task on the output channel is less than the amount of resources of the master control FPGA unit, the computing task of the network layer is mapped to the computing engine of the master control FPGA unit and executed;

[0045] If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing tasks on the output channel is greater than or equal to the resources of the main control FPGA unit, the computing tasks of the network layer are divided into blocks on the output channel according to the number of computing FPGA units, and the split computing tasks are mapped to the computing engine of each computing FPGA unit and executed.

[0046] like Figure 1 As shown, in specific practice, the multi-FPGA collaborative deep neural network parallel acceleration method disclosed in the present invention may include steps such as data communication synchronization, network model splitting, hardware mapping, and model scheduling and operation. The following describes in detail each step in the specific implementation process in combination with the specific content.

[0047] S101: Data communication synchronization: This step is mainly used to connect multiple FPGA chips or mainboards through a high-speed communication interface, use one FPGA as the master FPGA, and the remaining FPGAs as computing FPGAs; connect a host with a compiler and a scheduler to all FPGAs through a bus;

[0048] S102: Network model splitting: using the compiler in the host Host and judging whether each layer of the network needs to be split according to the amount of FPGA resources and the parameters of each layer of the model to be deployed, the network layer data and computing tasks to be split are divided into blocks in the output channel dimension based on the number of FPGA calculations. When the number of output channels is surplus, the weight data of the group of channels is filled with 0;

[0049] S103: Hardware mapping: According to the splitting results of each layer of the network model, the split network layer computing tasks and weight parameters are mapped to the computing engine and off-chip memory of each computing FPGA respectively. In this step, the on-chip cache capacity of the FPGA is small and it is difficult to cache all network parameters, while the external memory capacity is very large and is more suitable for caching weight data; the network layer computing tasks and parameters that do not need to be split are mapped to the computing engine and off-chip memory of the master FPGA respectively.

[0050] S104: Model scheduling and operation: Based on the splitting and mapping results of each layer of the model to be deployed, the scheduler in the Host generates control instructions corresponding to the model reasoning, sends instructions and parameters through the bus, and schedules the FPGA to implement the reasoning of each model in turn.

[0051] The multi-FPGA collaborative deep neural network parallel acceleration method described in the present invention is implemented based on a multi-FPGA system. Figure 2 The figure shows the overall structure of a multi-FPGA system.

[0052] In step S101, the high-speed communication interface refers to a high-speed communication interface such as QSFP+, SFP+, PCIE, etc. that connects multiple FPGAs; the master control FPGA refers to an FPGA with a multi-channel communication module that can read and exchange data from other FPGAs; the computing FPGA refers to an FPGA with a computing engine for implementing partial channel calculations at the network layer; the compiler refers to a program running in the Host that can compile the input model, identify the specific type and parameters of the network, and split the computing tasks; the scheduler refers to a program running in the Host that can generate scheduling instructions for a multi-FPGA system based on the model splitting results of the compiler.

[0053] More specifically, Figure 3 As shown, the method for data communication synchronization in step S101 includes the following steps:

[0054] S1011: Physical layer connection: Connect multiple FPGAs using a high-speed communication interface, use one FPGA as the master FPGA, and the remaining FPGAs as computing FPGAs; connect the Host to each FPGA through a bus.

[0055] For example, the main control FPGA and multiple computing FPGAs are connected using a QSFP+ to SFP+ interface. When the number of computing FPGAs is 4, Figure 4 As shown in FIG. 1 , a star-shaped logic structure diagram of interconnection between FPGAs is given. In the star-shaped logic structure, the FPGA in the center of the structure is used as the main control FPGA, and the other peripheral node FPGAs are used as computing FPGAs.

[0056] In the step, the host Host can be a CPU of ARM (or X86, etc.) architecture, and the instruction / parameter transmission bus between each FPGA can adopt AXI bus. S1012: Communication interface design: Design IP supporting multi-channel synchronous data transmission and reception in the main control FPGA, and design IP supporting single-channel synchronous data transmission and reception in each computing FPGA. Each computing FPGA occupies a data transmission and reception channel to exchange data with the main control FPGA.

[0057] For example, a single-channel data transceiver IP in an FPGA can be implemented using GTX and SERDES modules.

[0058] S1013: Data flow control: The data communication IP of FPGA is controlled by the scheduler of Host. When Host transmits sending instructions to computing FPGA synchronously and transmits receiving instructions to master FPGA, computing FPGA sends data to master FPGA together. When Host transmits sending instructions to master FPGA and transmits receiving instructions to computing FPGA synchronously, master FPGA transmits data to computing FPGA through different data channels.

[0059] In step S102: the FPGA resource amount refers to the computing unit resource amount in the FPGA, such as the number of DSPs in the main control FPGA unit or the computing FPGA unit used to perform computing tasks; the splitting on the output channel refers to splitting the calculation of a network layer in the output channel dimension, and obtaining the number of sub-computation channels by dividing the number of output channels by the number of computing FPGAs and rounding up, and merging the calculations of consecutive sub-computation channels into one computing FPGA task. When the number of output channels is in excess, the weight data of the group of channels is filled with 0.

[0060] More specifically, Figure 5 As shown, the method for splitting the network model in step S102 includes the following steps:

[0061] S1021: Model parameter extraction: The compiler in the host analyzes the deep neural network to be deployed, identifying the network type, network layer type and parameters, size parameters of input features, etc.

[0062] S1022: Network splitting determination: The compiler in the Host determines whether the network layers need to be split based on the FPGA resource amount and the parameters of each layer of the model to be deployed. If the computing resources required for the network layer to fully carry out the computing task on the output channel are greater than or equal to the resources of the main control FPGA, it is determined that the network layer needs to be split and a split mark is added.

[0063] Taking the VGG16 network as an example, the computing resources of a single FPGA can support a maximum of 128 parallel output channels of a 3×3 systolic array, 128 parallel channels of fully connected operators and pooling units. When the number of channels in a network layer is greater than 128, the network layer is split.

[0064] S1023: Data and computation splitting: The network layer weight parameters and computation tasks that need to be split in the model are evenly split by blocks in the output channel dimension. The weight parameters follow the computation tasks of the corresponding output channels. When the computation tasks are assigned to a certain FPGA, the parameters are initialized by the DDR of the computation FPGA where the computation tasks are located. When the network is deployed, the computation FPGA can load weight parameters in parallel. In this embodiment, an average splitting strategy is adopted to evenly split the computation tasks into each computation FPGA unit. The number of splits is consistent with the number of computation FPGAs, where the weight parameters are mapped to the DRAM of the FPGA where the corresponding computation tasks are located. The above splitting process can also be referred to. Figure 6 shown.

[0065] Taking 4 computing FPGAs as an example, the split results of the VGG16 network model are as follows:

[0066] Network Layer Number of output channels Whether the calculation task / parameter is split Calculate the number of FPGA processing channels CONV1, CONV2 64 no - MAXPOOL1 64 no - CONV3, CONV4 128 no - MAXPOOL2 128 no - CONV5, CONV6, CONV7 256 yes 64 MAXPOOL3 256 yes 64 CONV8, CONV9, CONV10 512 yes 128 MAXPOOL3 512 yes 128 CONV11, CONV12, CONV13 512 yes 128 FC1 4096 yes 1024 FC2 4096 yes 1024 FC3 1024 yes 256

[0067] According to the splitting results, the CONV1, CONV2, CONV3, and CONV4 network layers in VGG16 are mapped to the 128-channel 3×3 systolic array in the main control FPGA, and the MAXPOOL1 and MAXPOOL2 network layers are mapped to the 128-channel pooling units in the main control FPGA; the remaining network layers that need to be split are split into 4 blocks according to the channel order, and the computing tasks are executed in parallel by the systolic arrays and pooling units inside the 4 computing FPGAs.

[0068] More specifically, Figure 7 As shown, the method for hardware mapping in step S103 includes the following steps:

[0069] S1031: Weight parameter mapping: configure an independent DRAM for each FPGA and initialize all weight parameters in the DRAM. According to the weight parameter splitting result, store the unsplit weight parameters in the DRAM corresponding to the master FPGA; store the split weight parameters in the DRAM corresponding to the calculation FPGA in the order of channel blocks.

[0070] S1032: Computation engine mapping: Map the computational tasks that need to be split to the corresponding computational engines inside each computational FPGA. If the computational tasks after splitting are still greater than or equal to the parallel computational scale of the FPGA on the output channel, they can be processed by computational engine reuse. Map the computational tasks that do not need to be split to the corresponding computational engines in the master FPGA.

[0071] In the above steps, the computing engine refers to the functional operators in the FPGA used to calculate each layer of the network; for example, the convolution operator proposed in the document "Li Wei, Chen Yi, Chen Tao, et al. Research and design of reconfigurable CNN coprocessor for edge computing [J]. Journal of Electronics and Information Technology, 2024, 46(04): 1499-1512." or the systolic array in the document "Chang Jingtao, Wang Renping. Design of neural network hardware accelerator based on graph convolution [J]. China Integrated Circuits, 2024, 33(Z1): 24-29+50." can be used as the implementation method of the computing engine; Figure 8 The systolic array used to implement the 3×3 convolution operation in the VGG16 network is given. The systolic array is a network composed of multiple identical processing units (PEs) according to certain interconnection rules. The split results of each layer of the VGG16 network model refer to whether each layer of the network model needs to be split and the number of splits.

[0072] In step S104: the bus refers to the bus such as AXI, AHB, etc. for communication between the Host and the FPGA; the instructions and parameters refer to the instructions for controlling the collaborative computing and communication of multiple FPGA systems to realize model reasoning and the parameters for configuring the computing engine IP core in each FPGA.

[0073] More specifically, Fig. 9 As shown, the method for model scheduling operation in step S104 includes the following steps:

[0074] S1041: System instruction construction: The scheduler in the Host constructs the process of collaborative acceleration of the entire network on each FPGA into an instruction set for each FPGA based on the network parameters and model splitting results.

[0075] S1042: System scheduling execution: The Host transmits instructions to each FPGA according to the model reasoning logic to implement the corresponding communication and computing tasks, and receives the corresponding return status. After verifying the status synchronization, it sends the next instruction to each FPGA, and executes it in a loop in sequence until the model reasoning is completed.

[0076] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0077] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-FPGA collaborative deep neural network parallel acceleration method, characterized in that: The following steps are involved: Obtain the resource amount of the main control FPGA unit and each computing FPGA unit, as well as the parameters of each layer of the deep neural network model to be deployed, and obtain the computing resource amount of each network layer to perform computing tasks; If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing task on the output channel is less than the amount of resources of the master control FPGA unit, the computing task of the network layer is mapped to the computing engine of the master control FPGA unit and executed; If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing tasks on the output channel is greater than or equal to the resources of the main control FPGA unit, the computing tasks of the network layer are divided into blocks on the output channel according to the number of computing FPGA units, and the split computing tasks are mapped to the computing engine of each computing FPGA unit and executed.

2. The multi-FPGA collaborative deep neural network parallel acceleration method according to claim 1 is characterized in that: The computing engine includes functional operators in the main control FPGA unit or the computing FPGA unit for computing reasoning tasks at each layer of the network.

3. The multi-FPGA collaborative deep neural network parallel acceleration method according to claim 1 is characterized in that: The resource amount includes the number of DSPs in the main control FPGA unit or the computing FPGA unit used to execute computing tasks.

4. A parallel acceleration system based on multi-FPGA collaborative deep neural network, characterized in that: include: A master control FPGA unit, several computing FPGA units, and a host computer; The host performs the following operations: Obtain the resource amount of the main control FPGA unit and each computing FPGA unit, as well as the parameters of each layer of the deep neural network model to be deployed, and obtain the computing resource amount of each network layer to perform computing tasks; If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing task on the output channel is less than the amount of resources of the master control FPGA unit, the computing task of the network layer is mapped to the computing engine of the master control FPGA unit and executed; If the amount of computing resources required for the network layer of the deep neural network model to be deployed to fully expand the computing tasks on the output channel is greater than or equal to the resources of the main control FPGA unit, the computing tasks of the network layer are divided into blocks on the output channel according to the number of computing FPGA units, and the split computing tasks are mapped to the computing engine of each computing FPGA unit and executed.

5. The multi-FPGA collaborative deep neural network parallel acceleration system according to claim 4 is characterized in that: The host is connected to each computing FPGA unit and the main control FPGA unit via a high-speed communication bus.

6. The multi-FPGA collaborative deep neural network parallel acceleration system according to claim 4 is characterized in that: The master control FPGA unit supports an internet interconnection protocol for synchronously sending and receiving data through multiple channels.

7. The parallel acceleration system based on multi-FPGA collaborative deep neural network according to claim 4 is characterized in that: Each computing FPGA unit supports the Internet interconnection protocol of single-channel synchronous transmission and reception of data.

8. The multi-FPGA collaborative deep neural network parallel acceleration system according to claim 4 is characterized in that: Each computing FPGA unit is configured with independent dynamic random access memory.

9. The multi-FPGA collaborative deep neural network parallel acceleration system according to claim 4 is characterized in that: The host includes a compiler and a caller; The compiler is used to identify the resource amount of the main control FPGA unit and each computing FPGA unit, as well as the parameters of each layer of the deep neural network model to be deployed; and determine whether the computing resource amount required for the network layer of the deep neural network model to be deployed to fully launch the computing task on the output channel is greater than or equal to the resource amount of the main control FPGA unit; The scheduler is used to construct and execute the tasks of the deep neural network model to be deployed on each FPGA unit in a collaborative manner according to the parameters of each layer of the deep neural network model to be deployed and the model splitting results into an instruction set.

10. The multi-FPGA collaborative deep neural network parallel acceleration system according to claim 4 is characterized in that: The host is also used to: Receive the return status generated after executing the computing task of each network layer of the deep neural network model in each computing FPGA unit, and perform synchronous verification on the return status. After the verification is qualified, the next task execution instruction is sent to each computing FPGA unit, and the execution is cyclically executed in sequence until the deep neural network model reasoning is completed.

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