Apparatus and methods for single and multiple memory cell architectures

Abstract

The invention relates to an apparatus and method for single and multiple memory cell architectures. Single (1T) and multiple (MT) memory cell architectures may be included in the same memory array. In some embodiments, individual memory cells of the MT memory cells may have the same polarity. In some embodiments, individual memory cells of the MT memory cells may have complementary polarities. In some examples, digital lines at memory pads and edge memory pads may be folded for MT memory cells. In some examples, the digital lines may be rerouted through a local input-output line breakpoint of the MT memory cell. In some examples, LIO lines from MT memory cells may be stranded. In some examples, a larger sense amplifier may be used for MT memory cells.

Description

Technical Field

[0001] The present disclosure relates to memory devices, and in particular, to apparatus and methods for single and multiple memory cell architectures. Background Art

[0002] Information may be stored on memory cells of a memory device. Memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). During an access operation, the word lines may be activated and data may be read out from the memory cells along the bit lines to sense amplifiers, which may detect the information stored in the memory cells. The memory may be volatile memory, and the physical signals may decay over time (which may degrade or destroy the information stored in the memory cells). The information in the memory cells may need to be periodically refreshed, such as by rewriting the information, to restore the physical signals to the initial values.

[0003] As memory components decrease in size, the density of memory cells has greatly increased. An auto-refresh operation may be performed in which a sequence of memory cells is periodically refreshed. Repeated accesses to a particular memory cell or group of memory cells (commonly referred to as a 'row hammer' attack) may result in an accelerated rate of data degradation in nearby memory cells. The memory may include circuitry for tracking the number of accesses and / or access durations for each row, for example, as described in U.S. Pat. Nos. 10,770,127 and 11,462,291, which are incorporated herein by reference for any purpose. However, writing a count value representing the number of accesses and / or access durations to the memory requires additional time, which may degrade the performance of the memory. Therefore, it is desirable to minimize the timing effects of access tracking. Summary of the invention

[0004] One aspect of the present disclosure discloses an apparatus comprising: a word line coupled to a first plurality of memory cells and a second plurality of memory cells; a first peripheral region comprising a first plurality of local input-output (LIO) lines and a first group of sense amplifiers on a first side of the word line; a first plurality of bit lines coupled to some of the first plurality of memory cells and the first group of sense amplifiers, wherein the first plurality of bit lines extend through breakpoints in the first plurality of LIO lines; and a second plurality of bit lines coupled to some of the second plurality of memory cells and the first group of sense amplifiers, wherein the second plurality of bit lines extend over the first plurality of LIO lines.

[0005] Another aspect of the present disclosure discloses an apparatus comprising: a word line coupled to a first plurality of memory cells and a second plurality of memory cells; a first peripheral region comprising a plurality of local input-output (LIO) lines disposed in a metal layer; a first plurality of bit lines coupled to some of the first plurality of memory cells disposed in the metal layer; and a second plurality of bit lines coupled to some of the second plurality of memory cells, wherein the second plurality of bit lines are routed out from a diffusion layer adjacent to the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure.

[0007] Figure 2 is a schematic diagram of a portion of a memory array in accordance with at least one embodiment of the present disclosure.

[0008] Figure 3 is a schematic diagram of a portion of a memory array in accordance with at least one embodiment of the present disclosure.

[0009] Figure 4 is a schematic diagram of a portion of a memory array in accordance with at least one embodiment of the present disclosure.

[0010] Figure 5A is a schematic diagram of a portion of a memory array in accordance with at least one embodiment of the present disclosure.

[0011] Figure 5B According to at least one embodiment of the present disclosure Figure 5A Schematic diagram of a sub-portion of the memory array shown in .

[0012] Figure 6 is a schematic diagram of a portion of a memory array in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] The following description of certain embodiments is merely exemplary and is by no means intended to limit the scope of the present disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form a part of the present disclosure and are illustrated to show specific embodiments in which the described systems and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the sake of clarity, when certain features are obvious to those skilled in the art, their detailed description will not be discussed so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be considered as intended to be limiting, and the scope of the present disclosure is defined solely by the appended claims.

[0014] Information in a memory array may be accessed by one or more access operations, such as a read or write operation. During a read operation, a word line is activated and data is read from a memory cell along the word line along a bit line coupled to the corresponding memory cell. A sense amplifier coupled to the bit line detects whether the voltage along the bit line represents a logic high or a logic low, and drives the voltage along the bit line to an appropriate voltage level. Then, one or more bit lines may be coupled to a corresponding local input / output (I / O) line (e.g., an LIO line) to read the voltage on the bit line. Similarly, during a write operation, a bit line may be coupled to an LIO line and a sense amplifier (SA) may provide the data along the bit line to be written to the memory cell. It takes time for the memory to access a memory cell along a given word line. In some applications, it may be useful for different memory cells to have different access speeds. One limiting factor in determining the access speed may be the time required to sense the relatively small voltage generated by the charge stored in a single memory cell.

[0015] The memory device may have a hybrid memory cell architecture. A given word line may have several memory cells along it. On the one hand, each memory cell may be coupled to a separate sense amplifier along a corresponding bit line, which may be referred to as a 1T architecture. In some embodiments, individual memory cells may store bits. On the other hand, each sense amplifier is coupled to more than one memory cell (e.g., two or more), which may be referred to as an MT architecture, where M is an integer greater than 1. In an MT architecture, multiple memory cells are used to store bits (e.g., two memory cells may be used to store 1 bit). Compared to a 1T architecture, an MT architecture may have an increased access speed because two memory cells contribute charge to the voltage read by the sense amplifier. For example, various implementations of a hybrid memory cell architecture have been described in U.S. Patent Application Nos. 17 / 186,797, 17 / 732,885, 17 / 551,095, and 11,545,205, which are incorporated herein by reference for any purpose.

[0016] An example application in which this architecture may be used is a memory in which the access count associated with each row is stored in the memory cells of the row. Repeated accesses to a word line of a memory (e.g., a "row hammer" attack) may result in an accelerated rate of memory degradation for memory cells of nearby word lines. To mitigate this, the memory may store the access count associated with the row in a designated counter memory cell along each row. Since the counter memory cell must undergo a read-modify-write cycle (e.g., read the count, update the count, and then write the updated count back to the counter memory cell) in each access operation, it may be useful for the counter memory cell to operate with faster timing than the memory cells of the rest of the word line. Thus, the counter memory cell may use an MT architecture, while the rest of the memory cells along the word line may use an IT architecture. Example implementations of the present application are described in the aforementioned '095 application.

[0017] While using an MT architecture for memory cells dedicated to storing access counts for a row can reduce the time required to read and / or write access counts, implementing an MT architecture, and in particular, implementing a hybrid IT and MT architecture in the same array, presents process and layout issues. For example, it is desirable that the IT and MT cells have the same physical type to avoid requiring different portions of the array to be manufactured by different processes. However, having memory cells of the same type requires the IT and MT cells to be coupled to other components (e.g., LIO, SA, bit lines, etc.) in different ways. This requires changing the layout of the conductive lines and / or increasing the number of conductive lines, which in turn increases the layout area of ​​the array.

[0018] The present disclosure provides various techniques for incorporating both 1T and MT memory cells into a memory array. In some embodiments, the techniques do not require different processes for different regions. In some embodiments, individual memory cells in an MT memory cell may have the same polarity. In some embodiments, individual memory cells of an MT memory cell may have complementary (e.g., opposite) polarities. The same polarity means that all memory cells maintain charges associated with the same logical value in the 1T region (e.g., two or more memory cells store charges associated with '1' or '0' to encode a '1' or '0' bit). Complementary polarity means that memory cells maintain charges associated with different logical values ​​in the 1T region, and the combination is used to encode bits. For example, a first memory cell may store a charge associated with '1' and a second memory cell may store a charge associated with '0' to encode '1', and a first memory cell may store a charge associated with '0' and a second memory cell may store a charge associated with '1' to encode '0'.

[0019] In some embodiments, the bit lines at the memory pads and edge memory pads may be folded for MT memory cells. In some embodiments, the bit lines may be rerouted through local input-output (LIO) line breaks of the MT memory cells. In some embodiments, the LIO lines from the MT memory cells may be twisted. In some embodiments, larger sense amplifiers may be used for the MT memory cells. Various embodiments may provide MT memory cells with reduced access times compared to 1T cells. Which embodiment is preferred may be based on various factors, including, but not limited to, available layout space, available manufacturing precision, and the layout of other components of the memory array, or a combination of factors.

[0020] Although many of the examples disclosed herein illustrate a 2T architecture for the MT portion of the array, the disclosure is not limited to 2T and the principles of the disclosure can be extended to other architectures (e.g., 2T, 3T, 4T, 6T). In addition, although the examples disclosed herein relate to MT cells used as counter cells for tracking row accesses, MT cells can be used for other purposes (e.g., metadata, error correction code data).

[0021] Figure 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0022] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown to include a plurality of memory banks BANK0 to BANKN. In some embodiments, the memory array 118 may include 8 or 16 memory banks, but more or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC arranged at the intersection of the plurality of word lines WL and the plurality of bit lines BL. Some of the memory cells MC along the word lines may be MT memory cells 126. The MT memory cells 126 may be similar to other memory cells (e.g., 1T memory cells) of the memory array 118, except that the MT memory cells 126 are organized so that a plurality of memory cells are coupled together to store the same bit. For example, two MT memory cells 126 may have bit lines shorted together. In other example embodiments, other arrangements of linking the MT memory cells 126 may be used.

[0023] In some embodiments, the memory device 100 may use the MT memory cells 126 to store a count value XCount associated with a number of accesses to a word line. For example, the memory cells along the MT memory cells 126 may be used to store bits of the number XCount, and the memory cells along the MT memory cells 126 may be counter memory cells. For example, if the number XCount is an N-bit binary number, then there may be MN memory cells 126 shorted together along the MT region to store the N bits. The data bus associated with the MT memory cells 126 may be coupled to the refresh address control circuit 116. However, in other embodiments where the MT memory cells 126 are used to store different information (e.g., metadata) rather than the count value XCount, the data bus associated with the MT memory cells 126 may be coupled to another component of the memory device 100. In some embodiments, the data bus associated with the counter memory cells 126 may be separate from the data bus that couples other memory cells to the IO circuit 122. In some embodiments, the count value XCount may be used to refresh both the address control circuit 116 and the IO circuit 122.

[0024] The selection of the word line WL is performed by the row decoder 108 and the selection of the bit line BL / BLF is performed by the column decoder 110. Figure 1 In the embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory bank and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit lines BL / BLF are coupled to corresponding sense amplifiers ( Figure 1 The data read from the bit lines BL / BLF are amplified by the sense amplifier and transmitted through the complementary local data lines (LIO / F, Figure 11, 2, and 3. In the embodiment in which the MT memory cell 126 stores a count value XCount, the data in the MT memory cell 126 is read and written by the refresh address control circuit 116.

[0025] The semiconductor device 100 may employ a plurality of external terminals, including a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses, a clock terminal receiving clocks Ck_t and Ck_c, a data terminal DQ providing data, and a power supply terminal receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. In some embodiments, certain signals such as commands and addresses, clock signals, and / or data may be provided by a controller such as the memory controller 101.

[0026] The clock terminal is supplied with external clocks Ck_t and Ck_c provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the Ck_t and Ck_c clocks. The ICLK clock is provided to the command decoder 110 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 for the operation timing of the circuit included in the input / output circuit 122, for example, provided to the data receiver for the reception timing of write data.

[0027] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded memory bank address BADD, which may indicate the memory bank of the memory array 118 containing the decoded row address XADD and the column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the memory cells to be accessed.

[0028] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuits that decode the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0029] The device 100 may receive an access command as a row activation command ACT. When the row activation command ACT is received, a bank address BADD and a row address XADD are supplied in time with the row activation command ACT.

[0030] The device 100 may receive an access command as a read command. When the read command is received, the bank address BADD and the column address YADD are promptly supplied together with the read command, and the read data is read from the memory cell corresponding to the row address XADD and the column address YADD in the memory array 118. The read command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the data read from the memory array 118 is provided to the read / write amplifier 120. The read data is output to the outside from the data terminal DQ via the input / output circuit 122. The access count XCount stored in the MT memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value of the access count Xcount' is written back to the MT memory cell 126 of the row XADD.

[0031] The device 100 may receive an access command as a write command. When the write command is received, the bank address BADD and the column address YADD are supplied in time with the write command, and the write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the write data is received by the data receiver in the input / output circuit 122. A write clock may also be provided to the external clock terminal for timing the reception of the write data by the data receiver of the input / output circuit 122. The write data is supplied to the read / write amplifier 120 via the input / output circuit 122, and passes through the read / write amplifier 120 to the memory array 118 to be written into the memory cell MC. Similar to the above-mentioned read operation, the access count Xcount stored in the MT memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value of the access count Xcount' is written back to the MT memory cell 126 of the row XADD.

[0032] The device 100 may also receive a command that causes it to perform an automatic refresh operation. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating an automatic refresh command. In some embodiments, the automatic refresh command may be issued to the memory device 100 from the outside. In some embodiments, the automatic refresh command may be periodically generated by a component of the device. In some embodiments, when an external signal indicates a self-refresh entry command, the refresh signal AREF may also be activated. The refresh signal AREF may be activated once immediately after the command is input and periodic activation of the internal timing may be expected thereafter. Therefore, the refresh operation may continue automatically. The self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to the IDLE state.

[0033] The refresh signal AREF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which can refresh the word line WL indicated by the refresh row address RXADD. The refresh address control circuit 116 can control the timing of the refresh operation and can generate and provide the refresh address RXADD. The refresh address control circuit 116 can be controlled to change the details of the refresh address RXADD (e.g., how to calculate the refresh address, the timing of the refresh address), or can be based on internal logic operations.

[0034] The refresh address control circuit 116 may selectively output a target refresh address (e.g., a victim address) or an auto-refresh address (auto-refresh address) as the refresh address RXADD. The auto-refresh address may be an address sequence provided based on activation of the auto-refresh signal AREF. The refresh address control circuit 116 may cycle through the auto-refresh address sequence at a rate determined by AREF. In some embodiments, the auto-refresh address sequence may include all addresses in the memory bank 118. In some embodiments, the auto-refresh signal AREF may be issued at a certain frequency so that most or all addresses in the memory bank 118 are refreshed within a certain period of time, which may be based on the expected rate of information decay in the memory cells MC.

[0035] The refresh address control circuit 116 may also determine a target refresh address, which is an address that needs to be refreshed (e.g., a victim address corresponding to a victim row), based on access patterns of nearby addresses in the memory array 118 (e.g., an aggressor address associated with an aggressor row). The refresh address control circuit 116 may monitor accesses to different word lines WL of a memory bank. When the row decoder 108 sends an access command to a particular row, the MT memory cells 126 along the row may have their information read to the refresh address control circuit 116 as an access count Xcount. The refresh address control circuit 116 may determine the access count for the row based on the value stored in the MT memory cell 126 of the accessed row.

[0036] The refresh address control circuit 116 may determine whether the access row is an aggressor row based on the access count from the MT memory unit 126. If the current row is not an aggressor row, the value of the access count may be changed and then the refresh address control circuit may write the new value of the access count back to the counter memory unit 126 of the access row. If the refresh address control circuit 116 determines that the access row is an aggressor, the refresh address control circuit 116 may use the row address XADD of the accessed row to determine one or more victim row addresses and provide them as refresh addresses RXADD as part of the target refresh operation. When the access row is determined to be an aggressor, the access count Xcount associated with the row may be reset (e.g., reset to a minimum value, such as 0). In some embodiments, the refresh address control circuit 116 may queue the identified aggressor address (e.g., in a register) for later use in the target refresh operation.

[0037] The refresh address RXADD may be provided at a timing based on the timing of the refresh signal AREF. The refresh address control circuit 116 may have time slots corresponding to the timing of AREF and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the target refresh address may be issued in a time slot that is originally assigned to the auto-refresh address (e.g., "stolen") . In some embodiments, certain time slots may be reserved for the target refresh address, and the refresh address control circuit 116 may determine whether to provide the target refresh address, not provide the address during the time slot, or instead provide the auto-refresh address during the time slot.

[0038] The target refresh address may be based on the access characteristics over time of the row address XADD received from the address decoder 104. For example, the access characteristics may be determined based on the value of the access count Xcount stored in the MT memory unit 126. The refresh address control circuit 116 may use different methods to calculate the target refresh address based on the row address XADD, which is identified as an aggressor address based on the access count. For example, the refresh address control circuit 116 may determine whether a given row is an aggressor address and then calculate and provide the address of the victim address corresponding to the aggressor address as the target refresh address. In some embodiments, more than one victim address may correspond to a given aggressor address. In this case, the refresh address control circuit may queue a plurality of target refresh addresses and sequentially provide the target refresh addresses when it is determined that the target refresh address should be provided. The refresh address control circuit 116 may immediately provide the target refresh address or may queue the target refresh address to be provided at a later time (e.g., in the next time slot available for target refresh).

[0039] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminal. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0040] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 is not propagated to other circuit blocks.

[0041] Figure 2 2 is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. Memory array 200 may represent an exemplary portion of a memory array, such as Figure 1 1. The memory array 200 may be divided into pads (e.g., memory pads, memory array pads, array pads) including pads 203 (e.g., full array pads) and edge pads 205 (so called because they are at the edge of the memory array 200) separated by a peripheral region 207 including sense amplifiers (SA) and LIOs. The memory array 200 includes a plurality of word lines WL (rows) 202 and bit lines (BLE and BLO) (columns) 204. A plurality of memory cells 206 (MC) are located at the intersections of the rows and columns. A portion of the memory cells 206 along a given word line may be arranged using an MT architecture, such as in an MT region 226 on the left side of the line 201 (from the reader's perspective), while the remainder of the memory cells along the word line use a IT architecture in a region 227 on the right side of the line 201. The memory cells 206 of both regions 226 and 227 may be substantially similar or identical to each other, except that they may be coupled differently as described herein. Memory array 200 includes a number of sense amplifier groups 232a-b and 234a-b, each of which includes a number of sense amplifiers SA0 to 3. Sense amplifier groups 232 and 234 may be substantially similar to each other, except that sense amplifier group 234 is coupled to bit lines in the IT region, while sense amplifier group 232 is coupled to bit lines in the MT region 226. Sense amplifier groups 232 and 234 may be coupled to local I / O lines LIO 208 and LIOF 210.

[0042] To make it clear, Figure 2 Only one edge array pad and only one full array pad are shown in FIG. 2. Memory array 200 may include multiple full array pads, with edge array pads at both ends of the array. In addition, Figure 2Only a few word lines WL and bit lines BL (and their corresponding memory cells 206) and their corresponding sense amplifiers and LIOs are shown in FIG. More word lines WL, bit lines BL (and their corresponding memory cells), sense amplifiers and LIOs may be provided in the memory cell array of the present disclosure.

[0043] Each of the memory cells 206 can store information. In some embodiments, the information can be stored as binary code, and each memory cell 206 in the MT region can store a bit, while a pair of memory cells 206 in the MT region 226 can store a bit that can be at a logic high or logic low level. Figure 2 In the example shown in , the pair of memory cells 206 in the MT region 226 can have the same polarity.

[0044] The sense amplifiers in sense amplifier groups 232 and 234 can read or write the value of a bit of information along bit line 204 to memory cell 206 at access word line 202. The sense amplifiers in sense amplifier groups 232 and 234 can convert the signal along the bit line into a signal that is 'readable' by other elements of the memory device (e.g., by amplifying the voltage). The bit line can be coupled to input / output circuits (e.g., Figure 1 The column selection switch may be a column selection transistor activated by a column selection signal CS. Figure 2 In the example shown in , each CS can access 8 bits per word line 202 in region 227 and can access 4 bits per word line in region 226 .

[0045] In the example read operation of region 227, when word line 202 is accessed, memory cell 206 may provide its charge onto coupled bit line 204, which may cause a change in voltage and / or current along bit line 204. Sense amplifiers of group 234 may determine the logic level of the accessed memory cell 206 based on the resulting voltage and / or current along bit line 204, and may provide a signal corresponding to the logic level to input / output circuitry through a column select transistor.

[0046] In an example write operation of region 227, sense amplifiers SA0-3 of sense amplifier group 234 may receive a signal from an input / output circuit indicating a logic level to be written to an access memory cell 206. Sense amplifiers SA0-3 of sense amplifier group 234 may provide a voltage and / or current along a coupled bit line 204 (e.g., along a bit line having an active column select transistor) at a level corresponding to the logic level to be written. The voltage and / or current along the bit line 204 may charge the memory cell 206 at the intersection of the bit line 204 and the access word line 202 to a charge level associated with the write logic level. In this manner, by specifying the row being accessed and which bit lines to record data from (and / or which bit lines to write data to), a specific memory cell 206 may be accessed during one or more operations of the memory device.

[0047] Certain memory cells along each of the word lines may be set as MT memory cells in region 226. Figure 2 , the MT memory cells have a 2T architecture. The 2T memory cells 206 in region 226 can be substantially similar to the other 1T memory cells of region 227. In some embodiments, the 2T memory cells of region 226 can be physically identical to the other memory cells 206. However, instead of each sense amplifier SA0-3 in sense amplifier group 232 being coupled to a single memory cell, in the 2T region, each sense amplifier SA0-3 in sense amplifier group 232 is coupled to multiple memory cells (e.g., a pair of memory cells).

[0048] Reference area 226 in the full array pad 203, bit line BLO <0> Two memory cells 206 in each of the half of the word line 202 of the full array pad 203 and coupled to SAO of the sense amplifier group 232a. <0> is further coupled to the LIOF associated with sense amplifier group 232a. <3> . Bit line BLO <1> Two memory cells 206 in each of the half of the word lines 202 of the full array pad 203 and are coupled to the SA1 of the sense amplifier group 232a. <1> is further coupled to the LIOF associated with sense amplifier group 232a. <1> . Bit line BLO <2> Two memory cells 206 in each of the half of the word lines 202 of the full array pad 203 and are coupled to the sense amplifier group 232a. <2> is further coupled to the LIOF associated with sense amplifier group 232a. <2> . Bit line BLO <3> Two memory cells 206 in each of the half of the word lines 202 of the full array pad 203 are coupled to SA3 of the sense amplifier group 232a. <3> is further coupled to the LIOF associated with sense amplifier group 232a. <0> .

[0049] Still referring to the full array pad 203 in region 226, the bit line BLE <0> Two memory cells 206 in each of the half of the word lines 202 of the full array pad 203 and coupled to SAO of the sense amplifier group 232b. <0> is further coupled to the LIO associated with sense amplifier group 232b. <2> . Bit line BLE <1> Two memory cells 206 in each of the half of the word lines 202 of the full array pad 203 and coupled to the SA1 of the sense amplifier group 232b. <1> is further coupled to the LIO associated with sense amplifier group 232b. <0> . Bit line BLE <2> Two memory cells 206 in each of the half of the word lines 202 of the full array pad 203 and are coupled to sense amplifier group 232b. <2> is further coupled to the LIO associated with sense amplifier group 232b. <3> . Bit line BLE <3> Two memory cells 206 in each of the half of the word lines 202 of the full array pad 203 and are coupled to sense amplifier group 232b. <3> is further coupled to the LIO associated with sense amplifier group 232b. <1> .

[0050] Turn edge pad 205, bit line BLE <0> Two memory cells 206 in each of the word lines 202 coupled to SAO of sense amplifier group 232a and edge pad 205. BLE <0> is further coupled to the LIO associated with sense amplifier group 232a. <2> . Bit line BLE <1> Two memory cells 206 in each of the word lines 202 coupled to SA1 of sense amplifier group 232a and edge pad 205. BLE <1> is further coupled to the LIO associated with sense amplifier group 232a. <1> . Bit line BLE <2> Two memory cells 206 in each of the word lines 202 coupled to SA2 of sense amplifier group 232a and edge pad 203. BLE <2> is further coupled to the LIO associated with sense amplifier group 232a. <3> . Bit line BLE <3> Two memory cells 206 in each of the word lines 202 coupled to SA3 of sense amplifier group 232a and edge pad 205. BLE <3> is further coupled to the LIO associated with sense amplifier group 232a. <1> .

[0051] The coupling of the bit line 204 to the full array pad 203, the sense amplifiers in the IT region 227, and the LIO lines is the same as in the MT region 226. However, each bit line 204 is extended to couple to one memory cell 206 in all word lines 202 of the full array pad 203. In some embodiments (e.g., Figure 2 In the embodiment shown in FIG. 2 ), some portions of the 1T region 227 may include some sub-portions having a 2T architecture. Figure 2, memory cell 206 in edge pad 205 may have a folded architecture and a coupling arrangement to memory cells of region 226. More details of a folded bit line architecture in an edge pad are disclosed in U.S. Patent Application No. 17 / 565,187, which is incorporated herein by reference for any purpose.

[0052] In some embodiments (e.g. Figure 2 ), the bit lines may be "folded" to couple multiple memory cells 206 in region 226 together. Box 214 shows an enlarged view of the region indicated by box 212. As shown, bit line 204a extends from SA3 of sense amplifier group 232a and couples memory cell 206a with memory cell 206b. Bit line 204a may have a "fold" 216a, where instead of continuing straight along pad 203 (such as bit line 204 in region 227), bit line 204a turns back to couple memory cell 206a with memory cell 206b. Similarly, bit line 204b extends from SA3 of sense amplifier group 232b and has a fold 216b to couple memory cells 206c with 206d. In some embodiments, folds 216a and 216b may be formed using a pitch doubling process and using spacers at the ends of the bit line 204 pattern. In Figure 2 In the example shown in FIG. 1 , folds 216a, 216b include straight lines extending perpendicularly between two parallel straight line portions of bit lines 204a and 204b, respectively. However, in other embodiments, folds 216a, 216b may have different shapes (eg, a curved "U" shape).

[0053] In some embodiments, the bit lines of the MT memory cells 206 of coupling region 226 may have the same or substantially the same (e.g., within 10%) length as the bit lines of the 1T memory cells 206 of coupling region 227. Each of the sense amplifier groups 232a and 232b of the MT memory cell region 227 will have only half of the segment's word lines 202 coupled thereto, compared to the sense amplifier groups 234a and 234b in the 1T memory cell region 227. Two sense amplifiers (e.g., SA0 and SA1) may be used for access. For example, to<n / 2+1> Memory cell 206 is accessed using sense amplifiers SA0 through SA3 of sense amplifier group 232b (but none from sense amplifier group 232a). In contrast, to access memory cell 206 along WL in region 227<n / 2+1> Memory cell 206 is accessed using SA0-3 of sense amplifier groups 234a and 234b.

[0054] In some embodiments, to accommodate the folding of the bit lines 204 in the memory pad 203 in the region 226, a dummy word line 218 may be included in the memory pad 203. In some embodiments, one dummy word line 218 may be provided. In some embodiments, two to four dummy word lines 218 may be provided. In some embodiments, the edge pad 205 may be less crowded than the memory pad 203, and no dummy word line 218 may be needed to accommodate the folded bit lines 204.

[0055] In some embodiments, the layout area increase caused by the dummy word lines in the MT region may be less than 1%. In some embodiments, the layout area increase caused by the dummy word lines may be about 0.27% to 0.34%.

[0056] In some embodiments, providing the same polarity MT memory cell may provide a reduced write recovery time (tWR) for the MT memory cell compared to a 1T cell. In some applications, tWR may be approximately 53% of the tWR of a 1T cell.

[0057] While the same polarity MT architecture provides reduced tWR and an acceptably low layout area increase compared to a 1T-only memory cell array, in some applications the complementary polarity MT architecture may provide further reduction in tWR and / or layout area increase.

[0058] Figure 3 is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. Memory array 300 may represent an exemplary portion of a memory array, such as Figure 1 118 of the memory array 118. The memory array 300 can be divided into pads, including pads 303 and edge pads 305 (so called because they are at the edge of the memory array 300) separated by a peripheral region 307 including sense amplifiers (SA) and LIO. The memory array 300 includes a plurality of word lines WL (rows) 302 and bit lines BL / BLF (columns) 304. A plurality of memory cells 306 (MC) are located at the intersection of the rows and columns. A portion of the memory cells 306 along a given word line can be arranged using an MT architecture, while the remainder of the memory cells along the word line use a IT architecture in another region. The memory cells 306 of both MT and IT can be substantially similar or identical to each other, except that they can be coupled differently as described herein. The region including the IT architecture can be similar to Figure 2 Therefore, the 1T area and its interpretation are as follows: Figure 3 Omit.

[0059] Memory array 300 includes sense amplifier groups 332a and 332b, each of which includes a number of sense amplifiers SA0 through 3. Sense amplifier groups 332a and 332b may be coupled to local I / O lines LIO 208 and LIOF 210. The sense amplifiers in sense amplifier groups 332a and 332b may be similar or identical to the sense amplifiers and groups located in a 1T region (not shown) of memory array 300, except that they may be coupled to memory cells differently as described herein.

[0060] To make it clear, Figure 3 Only one edge array pad and only one full array pad are shown in FIG. 300 . The memory array 300 may include multiple full array pads, with edge array pads at both ends of the array. In addition, Figure 3 Only a few word lines WL and bit lines BL (and their corresponding memory cells 306) and their corresponding sense amplifiers and LIOs are shown in FIG. More word lines WL and bit lines BL / BLF (and their corresponding memory cells), sense amplifiers and LIOs may be provided in the memory cell array of the present disclosure.

[0061] Each of the memory cells 306 can store information. In some embodiments, the information can be stored as binary code. Figure 3 In the embodiment shown in , a pair of memory cells 306 in the full array pad 303 can store a bit that can be at a logic high or logic low level and 4 memory cells 306 in the edge pad 305 can store a bit. Figure 3 In the example shown in , the pair of memory cells 306 in the full array pad 303 may have complementary polarities. In the edge pad 305, each pair of memory cells 306 may have the same polarity, but both pairs of memory cells 306 may have complementary polarities.

[0062] The sense amplifiers in sense amplifier groups 332a and 332b can read or write the value of a bit of information along bit line 304 to memory cell 206 at access word line 302. The sense amplifiers in sense amplifier groups 332a and 332b can convert the signal along the bit line into a signal that is 'readable' by other elements of the memory device (e.g., by amplifying the voltage). The bit line can be coupled to input / output circuits (e.g., Figure 1 The column selection switch may be a column selection transistor activated by a column selection signal CS. Figure 3 In the example shown in FIG. 1 , each CS can access 4 bits per word line. In some embodiments, in the 1T region (not shown, see FIG. 1 ) of the memory array 300, Figure 2In region 227 in the MT region, each CS can access 8 bits per word line. Thus, in some embodiments, a CS in the MT region can access half the number of bits of a CS in the IT region. In other embodiments where more memory cells are coupled to the sense amplifier per sensing operation, the ratio may be different.

[0063] exist Figure 2 In the embodiment shown in FIG. 1 , folding of the bit lines is provided at the expense of the placement of the dummy word lines 218 in order to couple the MT memory cell 206 to the sense amplifier. Figure 3 , the bit lines BL / BLF and LIO / LIOF are rerouted at the expense of the placement of dummy bit lines 318 in order to couple the MT memory cells 306 to the sense amplifiers. The routing of the bit lines BL and BLF of the full array pad 303 will be explained with reference to 4 pairs of memory cells 306 corresponding to bits <0-3> (8 memory cells 306 in total). Each bit <0-3> is stored by two memory cells 306 having complementary polarities to each other.

[0064] Bit <0> The first memory cell 306 of can be coupled to the bit line 304a, which is routed through the LIO breakpoint 330 and coupled to the SAO of the sense amplifier group 332b. The routing through the LIO breakpoint 330 can be accommodated by the dummy bit line 318. Figure 3 In the example shown, two dummy bit lines 318 are used, but in other embodiments, more or fewer dummy bit lines 318 (eg, 0, 1, 4) may be used. <0> The second memory cell 306 may be routed “normally” and coupled to SAO of sense amplifier group 332b.

[0065] Bit <0> The first memory cell 306 of can be coupled to the bit line 304a, which is routed through the LIO breakpoint 330 and coupled to the SAO of the sense amplifier group 332b. The routing through the LIO breakpoint 330 can be accommodated by the dummy bit line 318. Figure 3 In the example shown, two dummy bit lines 318 are used, but in other embodiments, more or fewer dummy bit lines 318 (eg, 0, 1, 4) may be used. <0> The second memory cell 306 may be coupled to a bit line 304b that is routed over LIO and is also coupled to SAO of sense amplifier group 332b.

[0066] Bit <2> The first memory cell 306 may be coupled to a bit line 304c, which is routed through a LIO breakpoint 330 and coupled to SA2 of a sense amplifier group 332b. <2> The second memory cell 306 of can be coupled to a bit line 304d, which is routed over LIO and is also coupled to SA2 of sense amplifier group 332b. Thus, in the example shown, even bits associated with CS can be associated with sense amplifiers on the same side of the sense amplifier group.

[0067] Bit <1> The first memory cell 306 may be coupled to a bit line 304e, which is routed through a LIO breakpoint 330 and coupled to SA3 of a sense amplifier group 332a. <1> The second memory cell 306 may be coupled to a bit line 304f, which is routed over LIO and is also coupled to SA3 of sense amplifier group 332a.

[0068] Bit <3> The first memory cell 306 may be coupled to a bit line 304g, which is routed through a LIO breakpoint 330 and coupled to SA1 of a sense amplifier group 332a. <3> The second memory cell 306 of can be coupled to a bit line 304h, which is routed over LIO and is also coupled to SA1 of sense amplifier group 332a. Thus, in the example shown, odd bits associated with CS can be associated with sense amplifiers on the same side of the sense amplifier group, similar to even bits associated with CS. However, even bits and odd bits are associated with different sense amplifier groups on opposite sides of the full array pad 303.

[0069] Turning to edge pad 305, bit line 304 may be folded, similar to bit line 204 in edge pad 205. In this embodiment, memory cells 306 of edge pad 305 may have a 4T structure instead of a 2T structure. That is, four memory cells 306 may be used to store a single bit. Box 301 shows an enlarged view of memory cells 306 of word line 302 in edge pad 305. The bit lines 304 are labeled as <0> and position <2> The curved arrows indicate two pairs of memory cells 306 for storing each bit. The memory cells 306 of the edge pad 305 associated with CS can provide 2 bits instead of 4 bits. In some embodiments, odd bits can be stored in another edge pad (not shown) at the other end of the memory array 300.

[0070] Similar to the full array pad 303 bit, for bit <0> The first pair of memory cells 306 may be coupled to bit line 304i routed to SAO of sense amplifier group 332a through LIO breakpoint 330 and used for bit <0> The second pair of memory cells 306 may be coupled to a bit line 304j that is routed over LIO to couple to SAO of sense amplifier group 332a. <2> The first pair of memory cells 306 may be coupled to bit line 304k routed to SA2 of sense amplifier group 332a through LIO breakpoint 330 and used for bit <2> The second pair of memory cells 306 may be coupled to a bit line 304m that is routed over LIO to couple to SA2 of sense amplifier group 332a.

[0071] Returning to the sense amplifier, SA0 of sense amplifier group 332a is connected to BL <0> Coupling to LIO <0> And through BLF <0> Coupling to LIOF <0> , BLF <0> It is the cut-off portion of the bit line that has been extended into the array pad 303 in the 1T region. SA2 is connected to the array pad 303 through BL <2> Coupling to LIO <2> And through BLF <2> Coupling to LIOF <2> , BLF <2> It is also the cut-off portion of the bit line that has been extended into the array pad 303 in the 1T region. SA1 of the sense amplifier group 332a is connected to the BLF <1> Coupling to LIOF <1> And through BL <1> Coupling to LIO <1> , B.L. <1> It is the cut-off portion of the bit line that has been extended to the edge pad 305 in the 1T region. SA3 is connected to the edge pad 305 by BLF <3> Coupling to LIOF <3> And through BLF <3> Coupling to LIO <3> , BLF <3> It is also the truncated portion of the bit line that has been extended into the edge pad 303 in the 1T region. The sense amplifiers of the sense amplifier group 332b have corresponding coupling structures between the bit line 304 and the LIO lines 308, 310. Therefore, the "original" portion of the bit line rerouted through the LIO breakpoint 330 can be "retained" for coupling to the LIO lines 308, 310.

[0072] Compare Figure 2 , for each sense amplifier SA0-3 of sense amplifier groups 332a and 332b in the MT region of the memory array 300, both BL and BLF are at the same side of SA, compared to the 1T array region where BL and BLF are at different sides of SA. Figure 3 In the 2T example shown in , each full pad 303 in the MT region uses only half of the sense amplifiers from the odd and even SAs. In some embodiments, such as the one shown, the original skipped bit line may be routed to the opposite CS region, but is truncated before entering the core of the memory array pad.

[0073] In some embodiments, two of the four bit lines may be placed on the metal M0 layer of the die and the other two bit lines may be routed out of the diffused Li1 layer. For example, in some embodiments, the bit lines routed through the LIO breakpoint 330 may be placed on the metal M0 layer and the bit lines routed over the LIO / F line may be routed out of the diffused Li1 layer. In some embodiments, the diffused layer may be adjacent to the metal layer.

[0074] Figure 3 The embodiment shown in provides one column select CS. However, in some applications, more than one column select in the column plane may be desired.

[0075] Figure 4 4 is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. Memory array 400 may represent an exemplary portion of a memory array, such as Figure 1 118 of the memory array 118. The memory array 400 can be divided into pads, including pads 403 and edge pads 405 (so called because they are at the edge of the memory array 400) separated by a peripheral region 407 including sense amplifiers (SA) and LIOs. The memory array 400 includes a plurality of word lines WL (rows) 402 and bit lines BL / BLF (columns) 404. A plurality of memory cells 406 (MC) are located at the intersection of the rows and columns. A portion of the memory cells 406 along a given word line can be arranged using an MT architecture, while the remainder of the memory cells along the word line use a IT architecture in another region. The memory cells 406 of both MT and IT can be substantially similar or identical to each other, except that they can be coupled differently as described herein. The region including the IT architecture can be similar to Figure 2 Therefore, the 1T area and its interpretation are as follows: Figure 4 Omit.

[0076] Memory array 400 includes sense amplifier groups 432a-d, each of which includes a number of sense amplifiers SA0-3. Sense amplifier groups 432a-d may be coupled to local I / O lines LIO 408 and LIOF 410. The sense amplifiers in sense amplifier groups 432a-d may be similar or identical to the sense amplifiers and groups located in the 1T region (not shown) of memory array 300, except that they may be coupled to memory cells differently as described herein.

[0077] To make it clear, Figure 4 Only one edge array pad and only one full array pad are shown in FIG. 400 . The memory array 400 may include multiple full array pads, with edge array pads at both ends of the array. In addition, Figure 4Only a few word lines WL and bit lines BL (and their corresponding memory cells 406) and their corresponding sense amplifiers and LIOs are shown in FIG. More word lines WL and bit lines BL / BLF (and their corresponding memory cells), sense amplifiers and LIOs may be provided in the memory cell array of the present disclosure.

[0078] Region 426 of memory array 400 on one side of LIO breakpoint 430 may be associated with one column select signal and region 429 on the other side of LIO breakpoint 430 may be associated with another column select signal. In some embodiments, only one column select may be associated on one side of LIO breakpoint 430. The layout and operation of region 426 may be similar to Figure 3 The operation of region 429 may be substantially the same as the operation of region 426 and Figure 3 4. However, the layout of region 429 may be a mirror image of the layout of region 426.

[0079] In some embodiments (e.g. Figure 4 ), additional dummy bit lines 418 may be provided in memory array 400 compared to memory array 300 to accommodate routing of bit lines 404 through LIO breakpoints 430. In the example shown, four dummy bit lines 418 are provided. However, in other embodiments, more or fewer dummy bit lines 418 may be provided.

[0080] In some embodiments, 16 bits are required to provide sufficient storage for the access count Xcount. Figure 3 and 4 , 4 column selects can be used to access 16 bits (e.g., 1 column select accesses 8 memory cells and 4 bits per memory cell in the full array pad). Various layouts can be used to accommodate MT memory cells and column selects for storing Xcount. For example, memory cells for 2 column selects can be located in the column plane associated with error correction code and global column redundancy. In some embodiments, the 2 column selects associated with Xcount can be used Figure 4 . The memory cells of the third column selection associated with Xcount may be placed in another column plane, and the memory cells of the fourth column selection associated with Xcount may be placed in a separate column plane. For example, the other two column planes may be associated with DQ3 and DQ4. In another example, the other two column planes may be associated with DQ1 and DQ2. Other column planes may be used in other examples.

[0081] In some embodiments, the layout area increase caused by the dummy bit line can be less than 1%. In some embodiments, the layout area increase caused by the dummy bit line can be about 0.23%. In some embodiments, this layout area loss is less than the layout loss of the dummy word line.

[0082] In some embodiments, providing complementary polarity MT memory cells can provide a reduced write recovery time (tWR) for the MT memory cells compared to a 1T cell. In some applications, tWR can be about 47% of the tWR of a 1T cell. In some embodiments, complementary polarity MT memory cells can provide a lower tWR than the same polarity MT memory cells.

[0083] Although the folded bit lines (as shown in reference Figure 2 described) and rerouting bit lines (as described in reference Figure 3 and 4 Although some techniques (described above) provide minimal layout penalty for incorporating MT architectures into the same array as 1T cells, in some applications these techniques may increase layout complexity and / or increase defect risk. Depending on various factors (e.g., processing equipment, process type, and / or desired robustness against defects), other techniques may be desirable, even though the layout penalty may be higher in some cases.

[0084] Figure 5A is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. Memory array 500 may represent an exemplary portion of a memory array, such as Figure 1 Although the memory array 500 may include Figure 1 5 , only the peripheral region 507 of the memory array 500 is shown. In some embodiments, the memory array 500 may include multiple peripheral regions that are substantially the same as the peripheral region 507. Furthermore, although only a few bit lines, sense amplifiers, and LIOs are shown for clarity, more or fewer lines BL, LIO, and sense amplifiers may be included in the memory array 500 in some embodiments.

[0085] A portion of the memory cells (not shown) of the memory array 500 along a given word line may have an MT architecture, such as in the MT region 526 on the right side (from the reader's perspective) of line 501b. The MT architecture may use memory cells of the same polarity or complementary polarity. The remainder of the memory cells along the word line use a IT architecture in region 527 on the left side of line 501a. The memory cells of both regions 526 and 527 may be substantially similar or identical to each other, except that they may be coupled differently as described herein. The memory array 500 includes a number of sense amplifier groups 532 and 534, each of which includes a number of sense amplifiers SA0-3 and SA0-7, respectively. The sense amplifier groups 532 and 534 may be substantially similar to each other, except that the sense amplifier group 534 is coupled to the bit lines in the IT region, while the sense amplifier group 532 is coupled to the bit lines in the MT region 526. The sense amplifier groups 532 and 534 may be coupled to local I / O lines LIO 508 and LIOF 510.

[0086] Column select switches 536 and 538 may provide CS signals (eg, CS <0> and CS <1> ), column selection switches 540 and 542 may be implemented by transistors, as shown in FIG5 . Switches 540 and 542 may be controlled by a CS signal to activate corresponding sense amplifiers of sense amplifier groups 532 and 534. In some embodiments, sense amplifier group 534 may include two sense amplifier groups (e.g., SA0-3 and SA4-7).

[0087] Turn to 1T area 227, and CS <1> The associated first group of CS switches 540 are coupled to LIO lines <0-3> and bit lines BL<0-7>. Switch 540a is coupled to LIO <0> With BL <0> Switch 540b is coupled to LIO <1> With BL <1> Switch 540c is coupled to LIO <2> With BL <2> and switch 540d is coupled to LIO <3> With BL <3> between.

[0088] With CS <1> The associated second group of CS switches 540 are coupled to LIOF lines <0-3> and bit lines BLF<4-7>. Switch 540e is coupled to LIOF <1> With BLF <6> Switch 540f is coupled to LIOF <0> With BLF <7> Switch 540g is coupled to LIOF <3> With BLF <4> Switch 540h is coupled to LIOF <2> With BLF <5> between.

[0089] With CS <0> The associated first group of CS switches 540 are coupled to LIO lines <0-3> and bit lines BL<4-7>. Switch 540i is coupled to LIO <0> With BL <4> Switch 540j is coupled to LIO <3> With BL <5> Switch 540k is coupled to LIO <2> With BL <6> and switch 540m is coupled to LIO <1> With BL <7> between.

[0090] With CS <0> The associated second group of CS switches 540 are coupled to the LIOF lines <0-3> and the bit lines BLF<0-3>. Switch 540n is coupled to the LIOF lines <0-3> and the bit lines BLF<0-3>. <3> With BLF <2> Switch 540p is coupled to LIOF <2> With BLF <3> Switch 540q is coupled to LIOF <1> With BLF <0> Switch 540r is coupled to LIOF <0> With BLF <1> between.

[0091] Regarding the bit line, BL <0> Coupled to SA7, BL <1> Coupled to SA6, BL <2> Coupled to SA5, BL <3> Coupled to SA4, BL <4> Coupled to SA3, BL <5> Coupled to SA2, BL <6> coupled to SA1, and BL <7> Coupled to SAO of sense amplifier group 534. BLF <7> Coupling to SA7, BLF <6> Coupling to SA6, BLF <5> Coupled to SA5, BLF <4> Coupling to SA4, BLF <3> Coupling to SA3, BLF <2> Coupling to SA2, BLF <1> coupled to SA1, and BLF <0> SAO coupled to sense amplifier group 534. The coupling of the bit lines, sense amplifiers, and column select switches in IT region 527 may allow access to 8 bits per column selection.

[0092] Turning to the MT region 526, which is a 2T architecture in the example shown in FIG. 5, compared to the 1T region 527, the LIOF <0> and LIOF <2> has been shifted to the side of sense amplifier group 532 opposite to sense amplifier group 534. In both regions, LIOF <2> Similarly, the LIO in the MT region 526 is closer to the sense amplifier group 534 than in the IT region 527. <1> and LIO <3> is the opposite side of the sense amplifier group 532, and LIO <3> The LIO is disposed closer to the sense amplifier in the two regions. As shown in region 544 between lines 501a and 501b, <1> and LIO <3> and LIOF <0> and LIOF <2> The LIO wires are "twisted" to accommodate the changed routing. <1> and LIO <3> Extending from the "upper" portion of the memory array 500 (from the viewer's perspective) to the "lower" portion and switching which of the two LIO lines is closer to the upper portion of the memory array 500. Similarly, the LIOF <0> and LIOF <2> Extends from the lower portion to the upper portion of the memory array 500 and switches which of the two LIO lines is closer to the lower portion of the memory array 500. In some embodiments, in region 544, there may be a break in the horizontal metal layer to allow the upper metal layer to provide a twist 548 of the LIO line. In some embodiments, the twist 548 may allow for a typical IO break 531 in the column plane.

[0093] CS with column selection 538 <0> The associated first group of CS switches 542 is coupled to the LIO lines LIO<0,2> and LIOF<0,2> and the bit lines BL<4,6> and BLF<4,6>. Switch 542a is coupled to the LIO <0> and BLF <4> and switch 542b is coupled to LIOF <0> and BL <4> . Switch 542c is coupled to LIO <2> and BLF <6> and switch 542d is coupled to LIOF <2> and BL <6> .

[0094] CS with column selection 538 <0> The associated second group of CS switches 542 is coupled to the LIO lines LIO<1,3> and LIOF<1,3> and the bit lines BL<5,7> and BLF<5,7>. Switch 542e is coupled to LIOF <3> and BLF <5> and switch 542f is coupled to LIO <3> and BL <5> . Switch 542g is coupled to LIOF <1> and BLF <7> and switch 542h is coupled to LIO <1> and BLF <7> .

[0095] Bit line BL <4> and BLF <4> Both are coupled to SA3, and BL <6> and BLF <6> Both are coupled to SA1. Bit line BL <5> and BLF <5> Both are coupled to SA2, and BL <7> and BLF <7> Both are coupled to SAO of sense amplifier group 532. Thus, the BL and BLF bit lines are on both sides of sense amplifier group 532 in MT region 526, while in IT region 527, all BL lines are on one side of sense amplifier group 534 and all BLF lines are on a different side of sense amplifier group 534. The coupling of the bit lines, sense amplifiers, and column select switches in MT region 526 can allow access to 4 bits stored in 8 memory cells per column select in MT region 526 (e.g., 1 bit stored in a pair of memory cells).

[0096] For the 4 bits encoded in the MT region 526, some bit lines may be folded. Figure 5B According to at least one embodiment of the present disclosure Figure 5A Schematic diagram of a sub-portion of a memory array shown in . Sub-portion 500B shows an example die layout of twist 548 in region 544. It also illustrates an example of a folded bit line in MT region 526. Centerline 551 indicates the middle of memory array 500 from top (e.g., top of the page from the viewer's perspective) to bottom. In some embodiments, half of the sense amplifiers in a sense amplifier group can be above centerline 551 and the other half can be below centerline 551. Figure 5B In the example shown in <4> and BLF <6> Rather than extending beyond centerline 551, BL is folded back toward the "top" of memory array 500 as indicated by folds 516a and 516b, respectively. <5> and BL <7> Rather than extending beyond centerline 551 , it folds back toward the "bottom" of memory array 500 as indicated by folds 516c and 516d, respectively.

[0097] The twisting 548 of the LIO lines and the rearrangement of the BL and BLF lines between the MT and 1T regions may allow for identical connections at the column selects. Which LIO lines are twisted depends on the difference in bit line to LIO coupling between the MT region 526 and the 1T region 527 of the array 500. In some embodiments, the LIO lines may be twisted at both ends of the MT region 526. For example, there may be a 1T region 527 on both sides of the MT region 526, and there may be a region 544 on both sides of the MT region 526. The twisting 548 may not require dummy bit lines and / or dummy word lines. In addition, the bit lines may not need to be extended compared to other layout techniques. However, in some embodiments, the twisting 548 may use a width equal to or similar to (e.g., within 10%) the width of a sense amplifier group including 4 sense amplifiers, as indicated by the "dummy" sense amplifier group 518 shown in FIG.

[0098] Although Figure 2 The embodiments shown in Figures 5 and 6 provide routing techniques for bit lines and LIO lines to facilitate MT and 1T memory cells in a memory array, but other components of the memory may also be modified in addition to or in lieu of the aforementioned techniques. For example, for MT memory cells, since multiple memory cells store bits, fewer connections are required between bit lines and LIO lines than for 1T memory cells. In some applications, this may allow larger sense amplifiers to be used in the MT region of the memory array than sense amplifiers used in the 1T region of the memory array. In some embodiments, this may reduce or eliminate any layout increase penalty for integrating MT and 1T regions in the same memory array.

[0099] Figure 6 6 is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. Memory array 600 may represent an exemplary portion of a memory array, such as Figure 1 1. The memory array 600 may be divided into pads, including pads 603 and edge pads 605 separated by a peripheral region 607 including sense amplifiers (SA) and LIOs. The memory array 600 includes a plurality of word lines WL (rows) 602 and bit lines (BLE and BLO) (columns) 604. A plurality of memory cells 606 (MC) are located at the intersections of the rows and columns. A portion of the memory cells 606 along a given word line may be arranged using an MT architecture, such as in an MT region 626 on the left side of the line 601 (from the reader's perspective), while the remainder of the memory cells along the word line use a IT architecture in a region 627 on the right side of the line 601. The memory cells 606 of both regions 626 and 627 may be substantially similar or identical to each other, except that they may be coupled differently as described herein.

[0100] Memory array 600 includes several sense amplifier groups 632a-b and 634a-b. Sense amplifier groups 632a-b are different from sense amplifier groups 634a-b compared to other embodiments. Sense amplifier modules 634a-b each include four sense amplifiers SA0-3. Sense amplifier groups 632a-b each include two sense amplifiers SA0 and SA1. However, the sense amplifiers SA0 and SA1 in sense amplifier groups 632a-b are twice the size of the sense amplifiers SA0-3 in sense amplifier groups 634a-b. Sense amplifier groups 632a-b and 634a-b may be coupled to local I / O lines LIO 608 and LIOF 610.

[0101] To make it clear, Figure 66 shows only one edge array pad and only one full array pad. The memory array 600 may include multiple full array pads, with edge array pads at both ends of the array. In addition, Figure 6 Only a few word lines WL and bit lines BL (and their corresponding memory cells 606) and their corresponding sense amplifiers and LIOs are shown in FIG. More word lines WL and bit lines BL (and their corresponding memory cells), sense amplifiers and LIOs may be provided in the memory cell array of the present disclosure.

[0102] Each of the memory cells 606 can store information. In some embodiments, the information can be stored as binary code, and each memory cell 206 in the MT region can store a bit, while a pair of memory cells 206 in the MT region 226 can store a bit that can be at a logic high or logic low level. Figure 2 In the example shown in , the pair of memory cells 206 in the MT region 226 can have complementary polarities. Certain memory cells along each of the word lines can be set as MT memory cells in region 626. Figure 6 , the MT memory cells have a 2T architecture. The 2T memory cells 606 in region 626 can be substantially similar to the other 1T memory cells of region 627. In some embodiments, the 2T memory cells of region 626 can be physically identical to the other memory cells 606.

[0103] In MT region 626, for full array pad 603, coupled to BLO <0> and BLO <2> The memory cell 606 is coupled to the SAO of the sense amplifier group 632a and is coupled to the BLO. <1> and BLO <3> Memory cell 606 is coupled to SA1 of sense amplifier group 632a. <0> and BLE <2> The memory cell 606 is coupled to the SA0 of the sense amplifier group 632b and is coupled to the BLE <1> and BLE <3> Memory cell 606 is coupled to SA1 of sense amplifier group 632b. <2> Further coupling to LIOF <2> And BLO <3> coupled to the LIOF associated with sense amplifier group 632a <0> . BLE <0> Further coupling to LIO <2> And BLE <1> is further coupled to the LIO associated with sense amplifier group 632b. <1> It should also be noted that some memory cells and bit lines from the other full array pad 603 are coupled in a similar manner as the sense amplifiers and associated LIOF lines in sense amplifier group 632b.

[0104] For edge pad 605, coupled to BLE <0> and BLE <2> The memory cell 606 is coupled to the SA0 of the sense amplifier group 632a and the BLE <1> and BLE <3> SA1 coupled to sense amplifier group 632a. BLE <0> Further coupling to LIO <2> And BLE <1> Coupled to the LIO associated with sense amplifier group 632a <1> It should be noted that similar to Figure 2 In the embodiment shown in , the bit line 604 is folded in the edge pad 605 and couples two memory cells 606 .

[0105] The coupling between the memory cell 606, the bit line 604, the sense amplifier and the LIO lines 608 and 610 in the 1T region 627 is Figure 2 The coupling shown in the 1T region 227 shown in FIG.

[0106] The bit line length is twice the bit line length in the 1T region 627, except that the sense amplifiers in the sense amplifier group 632a-b are twice the size of the sense amplifiers in the sense amplifier group 634a-b. Figure 2 In contrast to the illustrated embodiment, rather than having each bit line 604 coupled to multiple memory cells 606 per word line 602, each bit line 604 is coupled to memory cells 606 in multiple word lines 602. Figure 6 In the example shown in FIG. 6 , word lines 602 including memory cells 606 coupled to the same bit line 204 are in different memory pads 605, 603. However, the bit line 604 is coupled to the LIO on one side of the sense amplifier group. Two LIO / LIOF pairs are used for each sense amplifier group in the MT region 626, while two LIO / LIOF pairs are used in the IT region 627 and the MT region 628. Figure 2 Four LIO / LIOF pairs are used in both the MT and 1T regions of the embodiment shown in FIG.

[0107] When reading 4 bits (8 memory cells 606) in MT region 626, all sense amplifiers in sense amplifier groups 632a and 632b can be activated, each sense amplifier accessing 1 bit (two memory cells 606). In some embodiments, the drive and / or load of MT region 626 can be twice that of the 1T region. However, the layout size is almost increased and the tWR of MT region 626 is about 47% of the tWR of 1T region 627, and the performance is comparable. Figures 3 to 4 The embodiment shown in is similar.

[0108] Various techniques for incorporating both IT and MT memory cells into a memory array have been disclosed. Various embodiments can provide MT memory cells with reduced access time and low layout area increase compared to IT cells without requiring differential processes between IT and MT regions of a memory array.

[0109] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes or separated and / or performed between separate devices or device portions in accordance with the present systems, devices, and methods.

[0110] Finally, the above discussion is intended only to illustrate the inventive system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the inventive system has been described in particular detail with reference to exemplary embodiments, it should also be understood that a person of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the inventive system as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: a word line coupled to the first plurality of memory cells and the second plurality of memory cells; a first peripheral region including a first plurality of local input-output (LIO) lines and a first group of sense amplifiers on a first side of the word lines; a first plurality of bit lines coupled to some of the first plurality of memory cells and the first group of sense amplifiers, wherein the first plurality of bit lines extend through breakpoints in the first plurality of LIO lines; and A second plurality of bit lines is coupled to some of the second plurality of memory cells and the first group of sense amplifiers, wherein the second plurality of bit lines extends over the first plurality of LIO lines.

2. The apparatus of claim 1, wherein sense amplifiers in the first group of sense amplifiers are coupled to bit lines in the first plurality of bit lines and bit lines in the second plurality of bit lines.

3. The apparatus of claim 1, wherein the first and second pluralities of bit lines are coupled to sense amplifiers in the first sense amplifier group on a same side of the first sense amplifier group.

4. The apparatus of claim 1, wherein the first plurality of memory cells are of a first polarity and the second plurality of memory cells are of a second polarity complementary to the first polarity.

5. The apparatus of claim 1, wherein at least one dummy bit line is disposed in the breakpoint of the LIO.

6. The apparatus of claim 1, further comprising: a second peripheral region including a second plurality of LIO lines and a second group of sense amplifiers on a second side of the word lines; a third plurality of bit lines coupled to others of the first plurality of memory cells and to the second group of sense amplifiers, wherein the third plurality of bit lines extend through breaks in the second plurality of LIO lines; and A fourth plurality of bit lines is coupled to others of the second plurality of memory cells and the second group of sense amplifiers, wherein the fourth plurality of bit lines extends over the second plurality of LIO lines.

7. The apparatus of claim 6, wherein the first and second plurality of memory cells associated with even bits are coupled to the first group of sense amplifiers and the first and second plurality of memory cells associated with odd bits are coupled to the second group of sense amplifiers.

8. The apparatus of claim 1, further comprising column selection on at least one side of the breakpoint in the first plurality of LIO lines.

9. The apparatus of claim 1, further comprising: a second group of sense amplifiers on the first side of the word line, wherein the first group of sense amplifiers and the second group of sense amplifiers are on opposite sides of the breakpoint in the first plurality of LIO lines; a third plurality of bit lines coupled to some of the first plurality of memory cells and the second group of sense amplifiers, wherein the third plurality of bit lines extend through the breakpoints in the first plurality of LIO lines; and A fourth plurality of bit lines is coupled to some of the second plurality of memory cells and the second group of sense amplifiers, wherein the fourth plurality of bit lines extends over the first plurality of LIO lines.

10. The apparatus of claim 9, wherein a layout of the third and fourth pluralities of bit lines is a mirror image of a layout of the first and second pluralities of bit lines.

11. The apparatus of claim 9, further comprising first and second column selects on opposite sides of the breakpoint in the first plurality of LIO lines.

12. A device comprising: a word line coupled to the first plurality of memory cells and the second plurality of memory cells; a first peripheral region including a plurality of local input-output (LIO) lines disposed in a metal layer; a first plurality of bit lines coupled to ones of the first plurality of memory cells disposed in the metal layer; and A second plurality of bit lines are coupled to ones of the second plurality of memory cells, wherein the second plurality of bit lines are routed from a diffusion layer adjacent to the metal layer.

13. The apparatus of claim 12, wherein the first plurality of bit lines extend through a break in the LIO line.

14. The apparatus of claim 12, wherein the second plurality of bit lines extend over the plurality of LIO lines.

15. The apparatus of claim 12, further comprising a plurality of sense amplifiers in the first peripheral region, wherein individual ones of the plurality of sense amplifiers are coupled to at least one of the first plurality of memory cells and at least one of the second plurality of memory cells.

16. The apparatus of claim 15, wherein the plurality of sense amplifiers are located on a same side of a group of sense amplifiers.

17. The apparatus of claim 16, wherein a second plurality of sense amplifiers are coupled to third and fourth pluralities of memory cells, the third and fourth pluralities of memory cells being coupled to a second word line on a side of the first peripheral region opposite the word line.

18. The apparatus of claim 15, further comprising a plurality of truncation bit lines routed from the diffusion layer coupling the plurality of sense amplifiers to the plurality of LIO lines.

19. The apparatus of claim 12, further comprising: a third plurality of memory cells coupled to the word line; and A third plurality of bit lines is coupled to ones of the third plurality of memory cells, wherein the third plurality of bit lines are routed out of the diffusion layer.

20. The apparatus of claim 19, wherein a first portion of the third plurality of bit lines extends to the first peripheral region and a second portion of the third plurality of bit lines extends to a second peripheral region on a second side of the word lines.

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