Read acceleration hardware circuit, SSD controller and data reading method

Abstract

The embodiment of the invention discloses a read acceleration hardware circuit, an SSD controller and a data reading method, and is used for the technical field of solid state disks. In the embodiment of the invention, the read acceleration hardware circuit is applied to the SSD controller, the SSD controller comprises a memory module and a flash memory control module, and the read acceleration hardware circuit comprises an address conversion module, a memory interface module and a read command generation module; the memory interface module is connected with the memory module, and the address conversion module is connected with the memory interface module and the read command generation module; in the SSD data reading process, conversion from a logic address to a physical address is achieved through an address conversion module, a flash memory read command is generated based on the physical address through a read command generation module, and the software running process of a processor in an SSD controller is reduced; the dependence on the software operation capability of a processor in the SSD controller in the SSD data reading process is effectively reduced, and the manufacturing cost and the working power consumption of the SSD controller are reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of solid-state hard disks, and in particular to a read acceleration hardware circuit, an SSD controller, and a data reading method. Background Art

[0002] Solid State Drives (SSD) are hard disks made of solid-state electronic storage chip arrays. SSDs include a control unit and a storage unit (FLASH storage chip or DRAM storage chip). Flash memory chip (NAND Flash) is the main storage unit of SSDs.

[0003] When a user needs to read data from an SSD, the host can send a read request to the SSD controller through the operating system and storage driver. The read request contains the logical address of the data to be read and the data length. The processor (such as the CPU) in the SSD controller converts the logical address to the physical address by running software (running a software algorithm or software program) on the read request and generates a flash read command based on the physical address. The SSD controller uses the flash read command to read data from the flash chip.

[0004] SSD data reading mainly depends on the software running capability of the processor in the SSD controller. When the data reading speed requirement is high, a processor with higher software running capability is required, such as more CPU cores or higher CPU operating frequency, which will greatly increase the manufacturing cost and working power consumption of the SSD controller. Summary of the invention

[0005] The embodiments of the present application provide a read acceleration hardware circuit, an SSD controller, and a data reading method, which effectively reduce the dependence of the SSD reading data on the software running capability of the processor in the SSD controller, and reduce the manufacturing cost and operating power consumption of the SSD controller.

[0006] The embodiment of the present application provides a read acceleration hardware circuit, which is applied to an SSD controller, wherein the SSD controller includes: a memory module and a flash memory control module, wherein the memory module stores an address mapping table, and the read acceleration hardware circuit includes: an address conversion module, a memory interface module, and a read command generation module;

[0007] The memory interface module is connected to the memory module, and the address conversion module is connected to the memory interface module and the read command generation module;

[0008] The address conversion module is used to obtain a read request of a logical address with data, read the address mapping table from the memory module based on the logical address, determine the physical address corresponding to the logical address, and transmit the physical address to the read command generation module;

[0009] The read command generating module is connected to the flash memory control module, and is used to generate a flash memory read command based on the physical address, and transmit the flash memory read command to the flash memory control module, so that the flash memory control module reads data from the SSD flash memory chip.

[0010] Further, the address conversion module includes: a Trim data processing module, a physical address mapping processing module and a block mapping processing module; the memory module also stores: a Trim mapping table and a block remapping table;

[0011] The Trim data processing module is connected to the physical address mapping processing module, and the Trim data processing module is used to read the Trim mapping table from the memory module based on the logical address, determine whether the data block corresponding to the logical address contains valid data; if so, send the read request to the physical address mapping processing module;

[0012] The physical address mapping processing module is connected to the block mapping processing module, and the physical address mapping processing module is used to read the address mapping table from the memory module based on the logical address, determine the physical address corresponding to the data block, and send the physical address corresponding to the data block to the block mapping processing module;

[0013] The block mapping processing module is connected to the read command generating module, and is used to read the block remapping table from the memory module based on the physical address corresponding to the data block, determine the new physical address of the data block when the data block is a bad block, and use the new physical address as the physical address corresponding to the logical address.

[0014] Further, the first submodule of the Trim data processing module is used to receive the read request and send a first memory read command for reading the Trim mapping table to the memory module, wherein the first memory read command includes the logical address;

[0015] The second submodule of the Trim data processing module is used to receive the flag bit of the data block corresponding to the logical address returned by the memory module; parse the flag bit of the data block to determine whether the data block contains valid data, and if so, send the read request to the physical address mapping processing module;

[0016] The first submodule of the physical address mapping processing module is used to receive the read request and send a second memory read command to the memory module to read the address mapping table, where the second memory read command includes the logical address;

[0017] The second submodule of the physical address mapping processing module is used to receive the physical address corresponding to the data block returned by the memory module, and send the physical address corresponding to the data block to the block mapping processing module;

[0018] The first submodule of the block mapping processing module is used to receive the physical address corresponding to the data block, and send a third memory read command for reading the block remapping table to the memory module, wherein the third memory read command includes the physical address corresponding to the data block;

[0019] The second submodule of the block mapping processing module is used to receive the new physical address of the data block returned by the memory module when the data block is a bad block, use the new physical address as the physical address corresponding to the logical address, and send the physical address corresponding to the logical address to the read command generation module.

[0020] Further, the first submodule of the Trim data processing module is divided into a first-level pipeline;

[0021] Divide the second submodule of the Trim data processing module and the first submodule of the physical address mapping processing module into a second-level pipeline;

[0022] Dividing the second submodule of the physical address mapping processing module and the first submodule of the block mapping processing module into a third-level pipeline;

[0023] The second submodule of the block mapping processing module and the read command generating module are divided into a fourth stage pipeline.

[0024] Furthermore, the SSD controller further includes: a data communication module and a processor;

[0025] The data communication module is connected to the host and the processor; the data communication module is used to receive the read request sent by the host and send the read request to the processor;

[0026] The processor is connected to the first submodule of the Trim data processing module; the processor is used to determine whether the read data required by the read request has been cached in the front-end cache of the processor by running software; if so, the required read data is returned to the host; if not, the read request is sent to the first submodule of the Trim data processing module.

[0027] Further, the read acceleration hardware circuit further includes: a software interface module, the software interface module being connected to the processor;

[0028] The second submodule of the Trim data processing module is connected to the software interface module, and the second submodule of the Trim data processing module is further used to notify the processor through the software interface module if the data block does not contain valid data, so as to control the processor to end the read request;

[0029] The second submodule of the physical address mapping processing module is connected to the software interface module. The second submodule of the physical address mapping processing module is also used to, when it is determined that the physical address corresponding to the data block is an invalid address, notify the processor through the software interface module to control the processor to end the read request.

[0030] Furthermore, the memory module also stores: a reading count table;

[0031] The second submodule of the physical address mapping processing module is also used to send a memory write command to the memory module to update the read count of the data block in the read count table of the memory module when it is determined that the physical address corresponding to the data block is a valid address.

[0032] Furthermore, the read acceleration hardware circuit also includes: a command management module;

[0033] The command management module is connected to the Trim data processing module, the physical address mapping processing module and the block mapping processing module, and is used to cache information generated in the connected modules.

[0034] The embodiment of the present application also provides an SSD controller, including: a memory module, a flash memory control module and the read acceleration hardware circuit described above.

[0035] The embodiment of the present application also provides a data reading method of an SSD controller, wherein the SSD controller comprises: a memory module, a flash memory control module, and the read acceleration hardware circuit described above; the read acceleration hardware circuit comprises: an address conversion module, a memory interface module, and a read command generation module; the memory interface module is connected to the memory module, and the address conversion module is connected to the memory interface module and the read command generation module;

[0036] The data reading method comprises:

[0037] Controlling the address conversion module to obtain a read request of a logical address with data, reading the address mapping table from the memory module based on the logical address, determining a physical address corresponding to the logical address, and transmitting the physical address to the read command generation module;

[0038] The read command generation module is controlled to generate a flash memory read command based on the physical address, and the flash memory read command is transmitted to the flash memory control module so that the flash memory control module reads data from the SSD flash memory chip.

[0039] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0040] In an embodiment of the present application, the read acceleration hardware circuit includes an address conversion module and a read command generation module. In the process of SSD reading data, the address conversion module is used to realize the conversion from logical address to physical address, and the read command generation module is used to generate a flash memory read command based on the physical address, thereby reducing the software running process of the processor in the SSD controller; effectively reducing the dependence of the SSD reading data on the software running capability of the processor in the SSD controller, and reducing the manufacturing cost and working power consumption of the SSD controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0042] Figure 1 A structural block diagram of a read acceleration hardware circuit disclosed in an embodiment of the present application;

[0043] Figure 2 A structural block diagram of an address conversion module disclosed in an embodiment of the present application;

[0044] Figure 3 A structural block diagram of another read acceleration hardware circuit disclosed in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of a water flow division disclosed in an embodiment of the present application;

[0046] Figure 5 A structural block diagram of an existing SSD control system disclosed in an embodiment of the present application;

[0047] Figure 6 A structural block diagram of an SSD control system disclosed in an embodiment of the present application;

[0048] Figure 7 A data reading flow chart of an SSD controller disclosed in an embodiment of the present application;

[0049] Figure 8 This is a data reading flow chart of another SSD controller disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] In the description of the embodiments of the present application, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the embodiments of the present application.

[0052] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0053] Currently, when a user needs to read data from a solid-state drive (SSD), a read request is sent to the SSD controller; the processor (such as a CPU) in the SSD controller converts the logical address to the physical address by running software on the read request, and generates a flash read command based on the physical address; the SSD controller uses the flash read command to read data from the flash chip (NAND Flash). SSD reading data mainly depends on the software running capability of the processor in the SSD controller. When the data reading speed requirement is high, a processor with higher software running capability is required, such as more CPU cores or a higher CPU operating frequency, which will greatly increase the manufacturing cost and operating power consumption of the SSD controller. Therefore, an embodiment of the present application provides a read acceleration hardware circuit that effectively reduces the dependence of SSD reading data on the software running capability of the processor in the SSD controller, reduces the manufacturing cost and operating power consumption of the SSD controller, such as Figure 1 As shown, the details are as follows:

[0054] In an embodiment of the present application, the SSD includes an SSD controller and an SSD flash memory chip, which is used to store data; a read acceleration hardware circuit is applied to the SSD controller, and the SSD controller includes: a memory module and a flash memory control module (FC); the memory module can be DDR (double data rate synchronous dynamic random access memory) or SDRAM (synchronous dynamic random access memory), and the specific details are not limited here; the memory module stores an address mapping table (L2P Table), which is used to convert logical addresses to physical addresses, the logical address is a relative address used in the user program, and the physical address is an absolute address in the SSD flash memory chip, pointing to a data block in the SSD flash memory chip.

[0055] The read acceleration hardware circuit includes: an address conversion module, a memory interface module and a read command generation module; the memory interface module is connected to the memory module, and the memory interface module is an interface for the read acceleration hardware circuit to read and write the memory module; the address conversion module is connected to the memory interface module and the read command generation module; the address conversion module is used to obtain a read request with a logical address of data, read an address mapping table from the memory module based on the logical address, determine the physical address corresponding to the logical address, and transmit the physical address to the read command generation module. That is, the read request (i.e., HOST read command) sent by the host (HOST) received by the SSD controller can be transmitted to the address conversion module of the read acceleration hardware circuit, and the read request contains the logical address and data length of the requested read data; the address conversion module can access the memory module based on the logical address to query the address mapping table and obtain the physical address corresponding to the logical address; for example, when the host requests to read data with a logical address of 1000, the address conversion module will query the address mapping table to find the corresponding physical address, such as the physical address 2048 in the flash memory chip.

[0056] The read command generation module is connected to the flash memory control module, and is used to generate a flash memory read command based on the physical address, and transmit the flash memory read command to the flash memory control module, so that the flash memory control module reads data from the SSD flash memory chip. It can be understood that the address conversion module can send the read request and the corresponding physical address to the read command generation module, and the read command generation module can generate a flash memory read command (NAND Flash read command) corresponding to the read request based on the read request and the corresponding physical address; the flash memory control module can generate a read command that meets the flash memory chip timing and send it to the flash memory chip; the flash memory chip receives and executes the read command, locates the data block corresponding to the physical address, returns the data in the data block corresponding to the physical address to the flash memory control module, and returns the data to the host through the flash memory control module.

[0057] It can be seen that in the embodiment of the present application, the read acceleration hardware circuit includes: an address conversion module, a memory interface module and a read command generating module; the memory interface module is connected to the memory module, and the address conversion module is connected to the memory interface module and the read command generating module; in the process of SSD reading data, the conversion of logical address to physical address is realized through the address conversion module, and the flash memory read command is generated based on the physical address through the read command generating module, thereby reducing the software running process of the processor in the SSD controller; effectively reducing the dependence of the SSD reading data on the software running capability of the processor in the SSD controller, that is, the SSD controller does not need a processor with higher software running capability, such as using fewer CPU cores or lower CPU operating frequency, to meet the data reading rate requirements; fewer CPU cores can reduce the area of ​​the SSD controller, can reduce the manufacturing cost of the SSD controller, and a lower CPU operating frequency can reduce the operating power consumption of the SSD controller, and thus the energy consumption ratio of the SSD controller.

[0058] Furthermore, in the embodiment of the present application, during the process of converting the logical address to the physical address, the address conversion module needs to determine whether the corresponding data block contains valid data and whether the data block is a bad block, so as to ensure the normal reading of the SSD data.

[0059] Specifically, Figure 2 As shown, the address conversion module includes: a Trim data processing module, a physical address mapping processing module and a block mapping processing module. Each processing module in the address conversion module is connected to the memory interface module, and is connected to the memory module through the memory interface module; the memory module also stores: a Trim mapping table (Trim Table) and a block remap table (Block Remap Table); wherein Trim is an optimization technology for solid state drives. The Trim technology is used to notify the operating system of the SSD which data blocks are no longer used (i.e., the data blocks do not contain valid data). The operating system can mark these data blocks as erasable (rewritable) and record them in the Trim mapping table. The Trim mapping table consists of a series of entries, each of which corresponds to a data block or a group of continuous data blocks. If the flag bit corresponding to the entry is 1, it means that the data block has been marked as erasable by the Trim instruction and the data block does not contain valid data; if the flag bit corresponding to the entry is 0, it means that the data block has not been marked as erasable by the Trim instruction and the data block still contains valid data. There may be bad blocks in the flash memory chip that cannot store data (factory bad blocks or bad blocks that grow due to erase and write wear). The block remapping table contains a series of entries, each of which corresponds to a possible bad block and records the new physical address of the bad block after remapping.

[0060] Among them, the Trim data processing module is connected to the physical address mapping processing module. The Trim data processing module is used to read the Trim mapping table from the memory module based on the logical address to determine whether the data block corresponding to the logical address contains valid data; if so, the read request is sent to the physical address mapping processing module. That is, when the SSD controller receives the read request, the Trim data processing module accesses the memory module to query the Trim mapping table to determine the flag bit of the entry of the data block corresponding to the logical address. If the flag bit is 1 (that is, the data block is Trim), it is determined that the data block does not contain valid data, and the read request reads invalid data. If the flag bit is 0, it is determined that the data block contains valid data, and the read request is sent to the physical address mapping processing module.

[0061] The physical address mapping processing module is connected to the block mapping processing module. The physical address mapping processing module is used to read the address mapping table from the memory module based on the logical address, determine the physical address corresponding to the data block, and send the physical address corresponding to the data block to the block mapping processing module. That is, when the Trim data processing module determines that the corresponding data block contains valid data, the physical address mapping module accesses the memory module to query the address mapping table and determines the physical address corresponding to the data block.

[0062] The block mapping processing module is connected to the read command generation module. The block mapping processing module is used to read the block remapping table from the memory module based on the physical address corresponding to the data block, determine the new physical address of the data block when the data block is a bad block, and use the new physical address as the physical address corresponding to the logical address. That is, the block mapping processing module uses the physical address of the data block queried by the physical address mapping module to access the memory module to query the block remapping table and determine the final physical address; and then send the final physical address to the read command generation module.

[0063] Further, such as Figure 3 As shown, in the embodiment of the present application, each processing module in the address conversion module can use two sub-modules (pipeline0 and pipeline1), each sub-module is connected to the memory module (DDR) through the memory interface module, and the two sub-modules respectively implement sending a memory read command (axi read) to the memory module and receiving data returned by the memory module; the details are as follows:

[0064] Among them, the first submodule (pipeline0) of the Trim data processing module is mainly used to generate a read Trim mapping table command, that is, to receive a read request transmitted by the host and send a first memory read command to read the Trim mapping table to the memory module, and the first memory read command includes the logical address in the read request.

[0065] The second submodule (pipeline1) of the Trim data processing module is used to receive the flag bit of the data block corresponding to the logical address returned by the memory module; parse the flag bit of the data block to determine whether the data block contains valid data, that is, when the flag bit of the data block is 1, it is determined that the data block does not contain valid data, and when the flag bit of the data block is 0, it is determined that the data block contains valid data; if so, the read request is sent to the physical address mapping processing module.

[0066] The first submodule (pipeline0) of the physical address mapping processing module mainly generates a read address mapping table command, that is, it is used to receive a read request and send a second memory read command of the read address mapping table to the memory module, and the second memory read command includes the logical address in the read request.

[0067] The second submodule (pipeline1) of the physical address mapping processing module is used to receive the physical address corresponding to the data block returned by the memory module, that is, to receive the physical address returned by the memory module based on the logical address in the address mapping table query, and send the physical address corresponding to the data block to the block mapping processing module.

[0068] The first submodule (pipeline0) of the block mapping processing module mainly generates a read block remapping table command, that is, it is used to receive the physical address corresponding to the data block and send a third memory read command for reading the block remapping table to the memory module, and the third memory read command includes the physical address corresponding to the data block.

[0069] The second submodule (pipeline0) of the block mapping processing module mainly processes the data of the block remapping table returned by the memory module, that is, it is used to receive the new physical address of the data block returned by the memory module when the data block is a bad block, use the new physical address as the physical address corresponding to the logical address, and send the physical address corresponding to the logical address to the read command generation module; so as to generate a flash memory read command through the read command generation module and transmit it to the flash memory control module (FC module).

[0070] Among them, the read command generation module includes a programmable module (ca_core), in which a variety of different instructions are defined, such as and, or, add, push, mul, div, shift left, shift_right. Programs are written for these instructions in the programmable module, and the received physical address and read request are processed by the parsing program to generate a flash memory read command. It can be understood that the parsing program is required in the read command generation module, which takes a relatively long time. Preferably, the read command generation module includes multiple programmable modules (ca_core0 and ca_core1), and the multiple programmable modules are used to generate multiple flash memory read commands based on the physical address in parallel. That is, for multiple read requests transmitted by the host, corresponding flash memory read commands are generated in parallel, which effectively shortens the time consumption of the read command generation module and improves the efficiency of SSD reading data.

[0071] Furthermore, the Trim mapping table, address mapping table, and block remapping table are all stored in the memory module (DDR) of the SSD controller. When the processing module in the address conversion module needs to read data from the memory module, there will be a dynamic time delay from initiating a memory read command (DDR read command) to the memory module to waiting for the data returned by the memory module (DDR read data return), which reduces the efficiency of the SSD reading data. Therefore, in the embodiment of the present application, by dividing the module into pipelines, time delays are effectively avoided and the efficiency of the SSD reading data is improved. Figure 4 As shown, the details are as follows:

[0072] In the embodiment of the present application, the first submodule (pipeline0) of the Trim data processing module can be divided into a first-level pipeline; the first-level pipeline mainly receives the input of the read request (HOST command) and generates a read Trim mapping table command. The second submodule (pipeline1) of the Trim data processing module and the first submodule (pipeline0) of the physical address mapping processing module are divided into a second-level pipeline; the second-level pipeline mainly receives and parses the flag bit of the data block corresponding to the logical address returned by the memory module, and generates a read address mapping table command. The second submodule (pipeline1) of the physical address mapping processing module and the first submodule (pipeline0) of the block mapping processing module are divided into a third-level pipeline; the third-level pipeline mainly receives and parses the physical address corresponding to the data block returned by the memory module, and generates a read block remapping table command. The second submodule (pipeline1) of the block mapping processing module and the read command generation module are divided into a fourth-level pipeline; the fourth-level pipeline mainly receives the new physical address of the data block returned by the memory module when the data block is a bad block, and generates a flash memory read command.

[0073] It can be seen that by adopting a four-stage pipeline to parse the read request (HOST read command), each stage of the pipeline completes different command parsing tasks. The logic of each pipeline is simple. When the SSD controller ensures that the command HOST read command and the read performance of the memory module (DDR) meet the system design requirements, the read acceleration hardware circuit only needs to ensure that each stage of the pipeline meets the system design requirements respectively, so as to ensure that the overall design meets the system performance requirements.

[0074] Among them, the starting point of each pipeline is command input (first pipeline) or DDR read data return (second, third, fourth pipeline), and the end point of each pipeline is DDR read command initiation (first, second, third pipeline) or read command generation (fourth pipeline). There is no need to wait for DDR return data in each pipeline, and there is no time delay, which improves the efficiency of SSD data reading.

[0075] Further, such as Figure 5 As shown, the SSD controller also includes: a data communication module (NVME module) and a processor (CPU); the data communication module is connected to the host (HOST) and the processor (CPU); the data communication module (NVME module) is used to receive a read request sent by the host (HOST) and send the read request to the processor (CPU). The data communication module (NVME module) can be connected to the host through a storage interface (PCIE) to standardize data transmission between the host and the SSD. In the figure, blue is hardware and orange is software.

[0076] The existing software run by the processor (CPU) of the SSD controller includes: FE software module (front-end module), FTL software module (flash translation layer module) and BE software module (back-end module). The existing SSD data reading process is: the data communication module (NVME module) receives the read request of the host, sends the read request to the processor (CPU) of the SSD controller, and the processor performs the following processing by running the software:

[0077] The FE software module determines whether the read data required by the read request is cached in the front-end cache of the processor. If so, the required read data is returned to the host; if not, the read request is sent to the FTL software module.

[0078] The FTL software module calculates the storage location of the address mapping table in the memory module of the SSD controller through the FTL algorithm, uses the address mapping table to convert from logical addresses to physical addresses, and sends the physical addresses to the BE software module.

[0079] The BE software module generates a flash read command based on the read request, physical address, and flash chip (flash particle) type, and sends the flash read command to the flash control module (FC module).

[0080] The flash control module generates a read command that meets the flash chip (flash particle) timing based on the flash read command, and sends the read command to the flash chip (flash particle); and receives the data returned by the flash chip (flash particle), performs error correction on the data, and then sends the corrected data to the data communication module (NVME module). The data communication module (NVME module) returns the received data to the host and ends the read request.

[0081] It can be seen that in the existing SSD data reading process, it is necessary to use the FTL software module in the processor of the SSD controller to run the FTL algorithm to convert the logical address to the physical address, and generate the flash memory read command through the BE software module, which is highly dependent on the processor's running software capabilities. Figure 6 As shown, in the processor (CPU), the conversion of logical address to physical address and the generation of flash memory read commands are performed by the read acceleration hardware circuit (read acceleration module). The read acceleration hardware circuit can complete the conversion of logical address to physical address without running the FTL algorithm, reducing the dependence on the processor's operating software capabilities.

[0082] Further, such as Figure 3 As shown, the processor (CPU) is connected to the first submodule (pipeline0) of the Trim data processing module; the processor (CPU) is used to determine whether the read data required by the read request has been cached in the front-end cache of the processor by running the software (i.e., the FE software module); if so, the required read data is returned to the host; if not, the read request is sent to the first submodule (pipeline0) of the Trim data processing module.

[0083] Furthermore, in the embodiment of the present application, the read acceleration hardware circuit can also feed back the abnormal information to the processor (CPU), so that the processor (CPU) ends the read request when the abnormality occurs, effectively avoiding the waste of resources in the process of reading data from the SSD. Specifically, the read acceleration hardware circuit also includes: a software interface module, which is connected to the processor (CPU).

[0084] The second submodule (pipeline1) of the Trim data processing module is connected to the software interface module. The second submodule (pipeline1) of the Trim data processing module is also used to notify the processor (CPU) through the software interface module if the data block does not contain valid data, so as to control the processor to end the read request, that is, the processor can return Unmap data to the host, and the Unmap data is used to indicate that the data has been removed and end the host's read request.

[0085] The second submodule (pipeline1) of the physical address mapping processing module is connected to the software interface module. The second submodule (pipeline1) of the physical address mapping processing module is also used to parse the physical address corresponding to the data block queried in the address mapping table. When it is determined that the physical address corresponding to the data block is an invalid address, the processor (CPU) is notified through the software interface to control the processor (CPU) to end the read request.

[0086] Furthermore, the memory module (DDR) of the SSD controller also stores: a reading count table; the reading count table is used to record the number of times the data block is read. Among them, the second submodule (pipeline1) of the physical address mapping processing module is also used to send a memory write command (axiwrite) to the memory module when it is determined that the physical address corresponding to the data block is a valid address, so as to update the reading count of the data block in the reading count table of the memory module; so as to facilitate the subsequent prediction of the data based on the reading count table that the data will send an erroneous data block, and move the data of the data block in advance.

[0087] Furthermore, in the embodiment of the present application, the read acceleration hardware circuit also includes: a command management module; the command management module is connected to the Trim data processing module, the physical address mapping processing module and the block mapping processing module, and is used to cache the information generated in the connected modules. It is understandable that when data is lost during the data transmission between the processing modules in the read acceleration hardware circuit, the required data can be retrieved from the command management module to ensure the normal reading of the SSD data.

[0088] The embodiment of the present application also provides an SSD controller, including: a memory module, a flash memory control module and the above-mentioned read acceleration hardware circuit.

[0089] The embodiment of the present application also provides a data reading method of an SSD controller, wherein the SSD controller comprises: a memory module, a flash memory control module and the above-mentioned read acceleration hardware circuit; the read acceleration hardware circuit comprises: an address conversion module, a memory interface module and a read command generation module; the memory interface module is connected to the memory module, and the address conversion module is connected to the memory interface module and the read command generation module;

[0090] The data reading method is as follows Figure 7 As shown, the specific steps include:

[0091] 701. Control the address conversion module to read the address mapping table from the memory module based on the logical address, determine the physical address corresponding to the logical address, and transmit the physical address to the read command generation module;

[0092] 702. Control the read command generation module to generate a flash memory read command based on the physical address, and transmit the flash memory read command to the flash memory control module, so that the flash memory control module reads data from the SSD flash memory chip.

[0093] In the embodiment of the present application, the overall process of SSD reading data is as follows: Figure 8 As shown in the figure, blue represents hardware behavior and orange represents software behavior. Specifically, the SSD controller receives a read request (HOST command) transmitted by the host, and the processor of the SSD controller runs the FE software module to search whether the required read data exists in the front-end cache (front-end cache). If so, the data in the front-end cache is returned to the host. If not, the read request is sent to the read acceleration hardware circuit.

[0094] In the Trim data processing module of the read acceleration hardware circuit, the Trim mapping table (Trim Table) is read and the Trim flag is checked; if the data block is marked as erasable by Trim, the processor is notified to return ummap data to the host; if the data block is not marked as erasable by Trim, the read request is sent to the physical address mapping processing module of the read acceleration hardware circuit.

[0095] In the physical address mapping processing module, the address mapping table (L2P Table) is read to obtain the physical address corresponding to the data block. In the block mapping processing module of the read acceleration hardware circuit, the block remapping table (Block Remap Table) is read to obtain the final physical address. In the read command generation module of the read acceleration hardware circuit, a flash memory read command (Nand read command) is generated based on the final physical address. Based on the flash memory read command, the Nand data is read from the flash memory chip and returned to the host (HOST) to complete the SSD data read.

[0096] An embodiment of the present application also provides a non-volatile computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by one or more processors, so that the one or more processors can execute the hybrid storage method based on SCM and SSD in any of the above method embodiments.

[0097] In the embodiment of the present application, the non-volatile computer-readable storage medium may include: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the non-volatile computer-readable storage medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, non-volatile computer-readable storage media do not include electric carrier signals and telecommunication signals.

[0098] The above described device or equipment embodiments are merely illustrative, wherein the unit modules described as separate components may or may not be physically separated, and the components displayed as module units may or may not be physical units, i.e., they may be located in one place, or may be distributed on multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the objectives of the present embodiment.

[0099] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute various embodiments or certain parts of the embodiments.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A read acceleration hardware circuit, applied to an SSD controller, the SSD controller comprising: A memory module and a flash memory control module, wherein the memory module stores an address mapping table, wherein the read acceleration hardware circuit comprises: an address conversion module, a memory interface module and a read command generation module; The memory interface module is connected to the memory module, and the address conversion module is connected to the memory interface module and the read command generation module; The address conversion module is used to obtain a read request of a logical address with data, read the address mapping table from the memory module based on the logical address, determine the physical address corresponding to the logical address, and transmit the physical address to the read command generation module; The read command generating module is connected to the flash memory control module, and is used to generate a flash memory read command based on the physical address, and transmit the flash memory read command to the flash memory control module, so that the flash memory control module reads data from the SSD flash memory chip.

2. The read acceleration hardware circuit according to claim 1, characterized in that: The address conversion module includes: a Trim data processing module, a physical address mapping processing module and a block mapping processing module; the memory module also stores: a Trim mapping table and a block remapping table; The Trim data processing module is connected to the physical address mapping processing module, and the Trim data processing module is used to read the Trim mapping table from the memory module based on the logical address, determine whether the data block corresponding to the logical address contains valid data; if so, send the read request to the physical address mapping processing module; The physical address mapping processing module is connected to the block mapping processing module, and the physical address mapping processing module is used to read the address mapping table from the memory module based on the logical address, determine the physical address corresponding to the data block, and send the physical address corresponding to the data block to the block mapping processing module; The block mapping processing module is connected to the read command generating module, and is used to read the block remapping table from the memory module based on the physical address corresponding to the data block, determine the new physical address of the data block when the data block is a bad block, and use the new physical address as the physical address corresponding to the logical address.

3. The read acceleration hardware circuit according to claim 2, characterized in that: The first submodule of the Trim data processing module is used to receive the read request and send a first memory read command to the memory module to read the Trim mapping table, where the first memory read command includes the logical address; The second submodule of the Trim data processing module is used to receive the flag bit of the data block corresponding to the logical address returned by the memory module; parse the flag bit of the data block to determine whether the data block contains valid data, and if so, send the read request to the physical address mapping processing module; The first submodule of the physical address mapping processing module is used to receive the read request and send a second memory read command to the memory module to read the address mapping table, where the second memory read command includes the logical address; The second submodule of the physical address mapping processing module is used to receive the physical address corresponding to the data block returned by the memory module, and send the physical address corresponding to the data block to the block mapping processing module; The first submodule of the block mapping processing module is used to receive the physical address corresponding to the data block, and send a third memory read command for reading the block remapping table to the memory module, wherein the third memory read command includes the physical address corresponding to the data block; The second submodule of the block mapping processing module is used to receive the new physical address of the data block returned by the memory module when the data block is a bad block, use the new physical address as the physical address corresponding to the logical address, and send the physical address corresponding to the logical address to the read command generation module.

4. The read acceleration hardware circuit according to claim 3, characterized in that: Divide the first submodule of the Trim data processing module into a first-level pipeline; Divide the second submodule of the Trim data processing module and the first submodule of the physical address mapping processing module into a second-level pipeline; Dividing the second submodule of the physical address mapping processing module and the first submodule of the block mapping processing module into a third-level pipeline; The second submodule of the block mapping processing module and the read command generating module are divided into a fourth stage pipeline.

5. The read acceleration hardware circuit according to claim 3, characterized in that: The SSD controller also includes: a data communication module and a processor; The data communication module is connected to the host and the processor; the data communication module is used to receive the read request sent by the host and send the read request to the processor; The processor is connected to the first submodule of the Trim data processing module; the processor is used to determine whether the read data required by the read request has been cached in the front-end cache of the processor by running software; if so, the required read data is returned to the host; if not, the read request is sent to the first submodule of the Trim data processing module.

6. The read acceleration hardware circuit according to claim 5, characterized in that: The read acceleration hardware circuit further includes: a software interface module, the software interface module being connected to the processor; The second submodule of the Trim data processing module is connected to the software interface module, and the second submodule of the Trim data processing module is further used to notify the processor through the software interface module if the data block does not contain valid data, so as to control the processor to end the read request; The second submodule of the physical address mapping processing module is connected to the software interface module. The second submodule of the physical address mapping processing module is also used to, when it is determined that the physical address corresponding to the data block is an invalid address, notify the processor through the software interface module to control the processor to end the read request.

7. The read acceleration hardware circuit according to claim 3, characterized in that: The memory module also stores: a reading count table; The second submodule of the physical address mapping processing module is also used to send a memory write command to the memory module to update the read count of the data block in the read count table of the memory module when it is determined that the physical address corresponding to the data block is a valid address.

8. The read acceleration hardware circuit according to claim 2, characterized in that: The read acceleration hardware circuit also includes: a command management module; The command management module is connected to the Trim data processing module, the physical address mapping processing module and the block mapping processing module, and is used to cache information generated in the connected modules.

9. An SSD controller, characterized in that: include: A memory module, a flash memory control module and a read acceleration hardware circuit as described in any one of claims 1 to 8.

10. A data reading method for an SSD controller, characterized in that: The SSD controller comprises: a memory module, a flash memory control module and the read acceleration hardware circuit according to any one of claims 1 to 8; the read acceleration hardware circuit comprises: an address conversion module, a memory interface module and a read command generation module; the memory interface module is connected to the memory module, and the address conversion module is connected to the memory interface module and the read command generation module; The data reading method comprises: Controlling the address conversion module to obtain a read request of a logical address with data, reading the address mapping table from the memory module based on the logical address, determining a physical address corresponding to the logical address, and transmitting the physical address to the read command generation module; The read command generation module is controlled to generate a flash memory read command based on the physical address, and the flash memory read command is transmitted to the flash memory control module so that the flash memory control module reads data from the SSD flash memory chip.

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