Method for manufacturing heat dissipation substrate and method for manufacturing power semiconductor module

Abstract

The invention relates to a method of manufacturing a heat dissipation substrate and a method of manufacturing a power semiconductor module. Embodiments relate to a ceramic substrate for a heat dissipation substrate, a heat dissipation substrate for a power semiconductor module, a power semiconductor module including the heat dissipation substrate, a power converter including the power semiconductor module, and a method of manufacturing the same. The method of manufacturing a heat dissipation substrate for a power semiconductor module includes the steps of: preparing an insulating substrate; preparing a first metal plate and a second metal plate; laminating the first metal plates; laminating an insulating substrate on the first metal plate; laminating a second metal plate on the insulating substrate; and performing a hot pressing process on the stacked first metal plate, insulating substrate, and second metal plate. The first thickness of the first metal plate may be different from the second thickness of the second metal plate.

Description

Technical Field

[0001] Embodiments relate to a ceramic substrate for a heat dissipation substrate, a heat dissipation substrate for a power semiconductor module, a power semiconductor module including the heat dissipation substrate, a power converter including the power semiconductor module, and a method of manufacturing the same.

[0002] Furthermore, embodiments relate to a ceramic substrate for a heat dissipation substrate having a unique code, a heat dissipation substrate for a power semiconductor module having a unique code, a power semiconductor module including the heat dissipation substrate having a unique code, and a power converter including the power semiconductor module having a unique code. Background Art

[0003] A power converter module is a device that performs power conversion (AC→DC, DC→AC), power transformation (buck, boost), power distribution, or power control. And a power converter module is a key component that improves energy efficiency in the process of sending and controlling power and provides system stability and reliability by controlling voltage changes. And a power converter module is called a power module or a power system.

[0004] The power converter module includes various components such as power semiconductor devices, heat dissipation substrate, base plate, molded silicon, housing and cover, and terminals.

[0005] Recently, environmentally friendly vehicles based on electricity or hydrogen have become the focus of public attention instead of internal combustion engine vehicles based on fossil fuels, and many power semiconductor devices are used in these environmentally friendly vehicles. Environmentally friendly vehicles include hybrid electric vehicles (HEV), plug-in hybrid electric vehicles (PHEV), electric vehicles (EV) and fuel cell vehicles (PCEV).

[0006] In addition, in addition to environmentally friendly vehicles, power semiconductors are also used in various electrical and electronic devices such as electric vehicle chargers, energy storage devices, power supply devices, and railways.

[0007] Previously, silicon (Si) power semiconductor devices have been widely used, but as Si power semiconductors have reached their physical limits, research on WBG (wide bandgap) power semiconductors such as silicon carbide (SiC) or gallium nitride (GaN) is being actively conducted to replace them.

[0008] WBG power semiconductor devices have a bandgap energy about 3 times higher than that of Si power semiconductor devices, a breakdown field about 10 times higher than that of Si power semiconductor devices, and a thermal conductivity about 3 times higher than that of Si power semiconductor devices. Due to these excellent characteristics, WBG power semiconductor devices can operate in high temperature and high voltage environments, and have the advantages of high switching speed and low switching loss.

[0009] For example, it is used to perform power conversion in conventional electric vehicles, hybrid electric vehicles, etc. Si-based power semiconductor modules for motor drive switches and controls operate in a temperature environment of about 150° C. In response to recent demands for improved switching performance and power density, wide bandgap (WBG)-based power semiconductor devices (such as SiC or GaN) that can operate at an operating temperature higher than about 300° C. (e.g., about 300° C. to 700° C.) have been actively studied.

[0010] In addition, the heat generated by the power semiconductor generates thermomechanical stress in various parts of the power semiconductor module, and the life of the power semiconductor device and the joint may be deteriorated due to thermal fatigue of the joint. Therefore, it is very important to design the reliability of the power semiconductor module to properly dissipate the heat generated from the power semiconductor device through the heat dissipation substrate, thereby maintaining the junction temperature of the power semiconductor device below an appropriate temperature.

[0011] Furthermore, the heat dissipation substrate for power semiconductors has not only a function of transferring heat generated during operation of the power semiconductor device to the outside but also an important function of electrically connecting the power semiconductor device by forming a wiring pattern on one side of the heat dissipation substrate.

[0012] Conventional heat dissipation substrates for power semiconductors can be classified into a direct copper bonding (DBC) method and an active metal brazing (AMB) method according to the bonding method. The DBC method is a method of forming an oxide film on a copper (Cu) layer and then bonding it directly to a ceramic. The AMB method is a method of performing brazing by inserting a paste containing metal particles with a relatively low melting point as an intermediate material between a base metal and a ceramic.

[0013] However, recently, 1200V, 200A class high voltage / high power SiC power converter modules are being used to improve the performance of hybrid and electric vehicles and autonomous vehicles. During the operation of these high-performance electric vehicles, the operating temperature of power semiconductor devices is required to be higher than 300°C on average. Specifically, ultra-high temperature use conditions with an instantaneous maximum operating temperature exceeding 350°C are being faced.

[0014] In such an ultra-high temperature, high voltage and high current operating environment, the existing bonding material itself may re-melt, and a heat trap phenomenon may occur due to pores existing in the bonding area. As a result, the life of the power semiconductor module may be rapidly deteriorated.

[0015] For example, Figure 1A This is a SEM image of a heat sink substrate using a conventional AMB bonding method. Figure 1A , cracks occur due to defects caused at the interface between the ceramic substrate and the copper (Cu) sheet of the heat dissipation substrate. The cracks caused in such a heat dissipation substrate may cause thermal runaway, thereby causing damage to the power semiconductor device.

[0016] For example, if the heat dissipation performance is deteriorated due to cracks in the heat dissipation substrate, the temperature of the power semiconductor module housing and the surroundings may increase. At this time, if the heat generation exceeds the heat dissipation performance (thermal state>heat dissipation performance) due to the rapid temperature rise, the thermal balance according to the thermal design (thermal state<heat dissipation performance) cannot be maintained, and the heat generation continues to increase. As a result, the leakage current continues to increase, eventually leading to damage to the power semiconductor module itself.

[0017] Specifically, degradation problems of power semiconductor modules may occur in an ultra-high operating temperature environment. Damage to power semiconductor devices caused by failure of a power semiconductor module mounted on a vehicle may have a serious impact on the safety of the driver.

[0018] Furthermore, in the current heat dissipation substrate field, the thickness of the supplied substrates including ceramic substrates is not constant, and the thickness of the supplied metal plates (such as copper plates) is also not constant. In this case, the final heat dissipation substrate must meet the strict specifications of the heat dissipation substrate delivery standard, but there are many difficulties in producing heat dissipation substrates that can meet the strict thickness specifications.

[0019] also, Figure 1B This is a photograph of a conventional AMB heat dissipation substrate that is warped (WP) after being bonded to a base plate (BP).

[0020] The thermal expansion coefficients (CTE) of the insulating substrate, copper plate, and SiC used as the heat dissipation substrate are significantly different. For example, the thermal expansion coefficient of the AlN insulating substrate SS is 4.5×10 -6 / ℃, the thermal expansion coefficient of copper (T-Cu, B-Cu) is 16.0×10 -6 / ℃, and the thermal expansion coefficient of SiC is 4.0×10 -6 / ℃.

[0021] If warpage (WP) occurs due to differences in thermal expansion coefficients of components constituting the power semiconductor module in an extremely high operating temperature environment of 300° C. or higher, failure of the power semiconductor module may occur.

[0022] In the prior art, methods such as designing a heat sink or controlling the temperature of a coolant are used to prevent warping due to the difference in thermal expansion coefficients.

[0023] In the internal technology, the material selection of the insulating substrate and the metal plate constituting the heat dissipation substrate has been studied. However, no study or consideration has been given to the thickness ratio of the insulating substrate, the upper metal plate, and the lower metal plate constituting the heat dissipation substrate.

[0024] In addition, according to internal research, the problem that the distance between circuit patterns increases as the metal plate on the heat dissipation substrate becomes thicker has been studied. For example, when the thickness of the Cu plate is about 0.2 mm, the separation distance between the circuit patterns is about 0.4 mm. However, when the thickness of the Cu plate is about 0.4 mm, there is a problem that the separation distance between the circuit patterns is about 0.6 mm.

[0025] In the internal technology, the thickness of the metal plates bonded to the top and bottom of the heat dissipation substrate is managed within a specific thickness range, and when etching the metal plates, etching is performed to ensure an even separation distance.

[0026] In addition, in order to realize high-performance power semiconductor devices, complex circuit patterns are required as multiple SiC power semiconductors are mounted on a heat dissipation substrate. In addition, if the separation distance between circuit patterns is wider than required, it is difficult to realize a high-density power semiconductor module.

[0027] In addition, according to internal research, when performing transient liquid phase bonding (TLP), the metal plate material of the heat dissipation substrate may be used up to form IMC (Intermetallic Compound). Therefore, the problem of not properly forming the IMC bonding layer, resulting in lower bonding strength or voids, was studied.

[0028] However, in a power semiconductor module operating at extremely high temperatures, reduced adhesion between the power semiconductor device and the heat dissipation substrate or the presence of voids at the bonding interface may have a significant impact on performance degradation and reliability of the power semiconductor module.

[0029] In addition, in the conventional heat dissipation substrate industry, for each "individual heat dissipation substrate", it is impossible to accurately match and manage all production and quality information and history (such as thickness information of insulating substrates including ceramic substrates, inspection information, copper plate thickness information, surface information, and interface information after the bonding process).

[0030] In addition, specifically, when metal is sputtered on an insulating substrate and then a copper plate and hot press process is performed, even if a predetermined code is marked on the insulating substrate, the code is obscured by the sputtering process and the hot press process, so it is impossible to attempt to mark a separate code for each "separate heat dissipation substrate".

[0031] In addition, the internal technology relies on the manual work of the metal plate lamination process and the insulating substrate. In addition, when the lamination process is performed manually, it is difficult to consider matching the thickness of each insulating substrate and the metal plate, and it is not even easy to control the placement of the metal plate on the upper and lower sides of the ceramic substrate.

[0032] Specifically, in the internal technology, the stacking group of the heat dissipation substrate includes an insulating substrate and metal plates arranged on the top and bottom, and in achieving a high stacking density of several tens to nearly 100 groups, the alignment of the insulating substrate and the metal plates is studied as a difficult technical challenge. Summary of the invention

[0033] One of the technical purposes of the embodiment is to solve the problem that it is difficult to meet the strict thickness specification of the final heat dissipation substrate in a situation where the thickness of the technically challenging insulating substrate is not constant and the thickness of the technically challenging metal plate is also not constant.

[0034] In addition, one of the technical objectives of the embodiment is to solve the problem of warping of the heat dissipation substrate caused by the difference in thermal expansion coefficients of the insulating substrate, the upper metal plate, and the lower metal plate constituting the heat dissipation substrate.

[0035] In addition, in order to realize high-performance power semiconductor devices, a complex circuit pattern is required as multiple SiC power semiconductors are mounted on a heat dissipation substrate. Therefore, one of the technical purposes of the embodiment is to solve the problem that it is difficult to realize a high-density power semiconductor module when the separation distance between circuit patterns is wider than required.

[0036] In addition, during transient liquid phase bonding (TLP), the metal plate material of the heat dissipation substrate may be exhausted to form an intermetallic compound (IMC). Therefore, one of the technical objectives of the embodiment is to solve the problem of reduced bonding strength or generation of voids due to inadequate formation of an IMC bonding layer.

[0037] In addition, one of the technical objectives of the embodiment is to solve the problem of difficulty in accurately matching each heat dissipation substrate by separately collecting all production and quality information and history (such as thickness information of an insulating substrate (such as a ceramic substrate), inspection information, thickness information of a copper plate, surface information, and joint interface information after a bonding process).

[0038] In addition, one of the technical objectives of the embodiment is to automate the process of stacking insulating substrates (such as ceramic substrates and metal substrates) while achieving a high stacking degree of dozens to 100 stacking groups and solving the problem of difficult alignment between insulating substrates (such as ceramic substrates) and metal plates.

[0039] In addition, one of the technical objectives of the embodiment is to solve the problem of cracks occurring at the bonding interface of the heat dissipation substrate.

[0040] Technical objectives of the embodiments are not limited to those described in this section, but include those that can be understood through the description of the present invention.

[0041] A technical solution for solving the technical problem according to an embodiment is as follows.

[0042] According to an embodiment, a method for manufacturing a heat dissipation substrate for a power semiconductor module may include the following steps: preparing an insulating substrate; preparing a first metal plate and a second metal plate; stacking the first metal plate; stacking the insulating substrate on the first metal plate; stacking the second metal plate on the insulating substrate; and performing a hot pressing process on the stacked first metal plate, the insulating substrate, and the second metal plate.

[0043] A first thickness of the first metal plate may be different from a second thickness of the second metal plate.

[0044] A first thickness of the first metal plate may be thinner than a second thickness of the second metal plate.

[0045] The first metal plate may include a circuit pattern electrically connected to a predetermined power semiconductor device.

[0046] The second metal plate may include a marked first unique code.

[0047] The first unique code may include one or more of a DMC (Digital Matrix Code), a QR code, or a barcode, and the first unique code may include thickness information of the insulating substrate.

[0048] The first unique code may include one or more of a DMC (Digital Matrix Code), a QR code, or a barcode, and the first unique code may include thickness information of at least one of the first metal plate and the second metal plate.

[0049] The first unique code may include one or more of a DMC (Digital Matrix Code), a QR code, or a barcode, and the first unique code may include thickness information of the insulating substrate and the first and second metal plates.

[0050] Embodiments may also include a unique ID marked on the first metal plate or the second metal plate.

[0051] A first thickness of the first metal plate may be thicker than a second thickness of the second metal plate.

[0052] The step of preparing the insulating substrate may include: preparing the insulating substrate including an active area and a dummy area disposed outside the active area; and marking the second unique code in the dummy area.

[0053] The step of preparing the insulating substrate may include: cleaning the insulating substrate; and measuring the thickness of the cleaned insulating substrate.

[0054] The second unique code may be stored in a predetermined central server, and the second unique code may include thickness information of the insulating substrate.

[0055] The second unique code may include a rectangular shape or a square shape, and a vertex of the second unique code and a vertex of the valid area may be arranged to face each other.

[0056] The second unique code may include a rectangular shape or a square shape, and a minimum distance between the unique code and the effective area of ​​the insulating substrate may correspond to a distance between a vertex of the unique code and a vertex of the effective area.

[0057] The second unique code may include a rectangular shape or a square shape, and an edge of the second unique code may be arranged to face a vertex of the valid area closest to the unique code.

[0058] A method of manufacturing a power semiconductor module according to an embodiment may include the steps of: arranging a power semiconductor device; and bonding a first heat dissipation substrate and a second heat dissipation substrate to a lower side and an upper side of the power semiconductor device, respectively.

[0059] The bonding step may include bonding the circuit pattern of the first metal plate and the power semiconductor device by any one of sintering bonding, soldering bonding, or ultrasonic bonding.

[0060] A first thickness of the first metal plate may be thinner than a second thickness of the second metal plate.

[0061] The first metal plate may include a circuit pattern electrically connected to a predetermined power semiconductor device, and the second metal plate may include a first unique code.

[0062] The first unique code may include one or more of a DMC (Digital Matrix Code), a QR code, or a barcode, and the first unique code may include thickness information of the insulating substrate.

[0063] The first unique code may include one or more of a DMC (Digital Matrix Code), a QR code, or a barcode, and wherein the first unique code may include thickness information of at least one of the first metal plate and the second metal plate.

[0064] According to an embodiment, a heat dissipation substrate for a power semiconductor module may include: a first metal plate, an insulating substrate bonded to the first metal plate, and a second metal plate bonded to the insulating substrate, and a first thickness of the first metal plate may be different from a second thickness of the second metal plate. The first metal plate or the second metal plate may include a marked unique code.

[0065] A first thickness of the first metal plate may be thinner than a second thickness of the second metal plate.

[0066] The first metal plate may include a circuit pattern electrically connected to a predetermined power semiconductor device, and the second metal plate may include a marked unique code.

[0067] In addition, the heat dissipation substrate for a power semiconductor module according to an embodiment may include: a second metal plate, an insulating substrate bonded to the second metal plate, and a third metal plate bonded to the insulating substrate. The third plate may have a third thickness thicker than the second thickness of the second metal plate.

[0068] The third metal plate or the fourth metal plate may include a marked unique code.

[0069] The third metal plate may include a circuit pattern electrically connected to a predetermined power semiconductor device, and the second metal plate may include a marked unique code.

[0070] The unique code may include one or more of a digital matrix code (DMC), a QR code, or a barcode.

[0071] The unique code may include thickness information of at least one of the insulating substrate or the first and second metal plates.

[0072] This embodiment may also include a unique ID marked on the first metal plate or the second metal plate.

[0073] A power semiconductor module according to an embodiment may include a first heat dissipation substrate, a power semiconductor device disposed on the first heat dissipation substrate, and a second heat dissipation substrate disposed on the power semiconductor device. The first heat dissipation substrate or the second heat dissipation substrate may include any heat dissipation substrate used for a power semiconductor module.

[0074] The first heat dissipation substrate or the second heat dissipation substrate may include a heat dissipation substrate for one of the power semiconductor modules, and the embodiment may further include a power semiconductor device bonded to the circuit pattern of the first metal plate.

[0075] In addition, the embodiment may include a bonding layer bonded between the circuit pattern of the first metal plate and the power semiconductor device by any one of sintering bonding, welding bonding, or ultrasonic bonding.

[0076] The first heat dissipation substrate or the second heat dissipation substrate may include a heat dissipation substrate for one of the power semiconductor modules, and the embodiment may further include a power semiconductor device bonded to the circuit pattern of the third metal plate.

[0077] In addition, the embodiment may include a bonding layer bonded between the circuit pattern of the third metal plate and the power semiconductor device using a phase change bonding method.

[0078] In addition, a power converter according to an embodiment may include any one of the above-described power semiconductor modules.

[0079] In addition, according to an embodiment, an insulating substrate for a heat dissipation substrate may include: an effective area (AA) of the insulating substrate, a dummy area (DA) of the insulating substrate arranged outside the effective area (AA), and the dummy area (DA) of the insulating substrate may include a unique code UC marked on the dummy area.

[0080] The unique code may include one or more of a digital matrix code (DMC), a QR code, or a barcode.

[0081] This embodiment may further include a unique ID marked on a dummy area (DA) of the insulating substrate.

[0082] The unique ID may include a combination of numbers, a combination of letters, or a combination of numbers and letters.

[0083] The unique code UC may comprise a rectangle or a square.

[0084] The vertices of the unique code and the vertices of the valid area may be arranged to face each other.

[0085] The minimum distance between the unique code and the active area (AA) of the insulating substrate may correspond to a distance between a vertex of the unique code and a vertex of the active area.

[0086] The corners of the unique code UC may be arranged to face the vertex closest to the unique code of the active area.

[0087] A heat dissipation substrate according to an embodiment may include a first metal plate, an insulating substrate bonded to the first metal plate, and a second metal plate bonded to the insulating substrate.

[0088] A unique code may be included that is marked on the first metal plate or the second metal plate.

[0089] The second metal plate may be electrically connected to a predetermined power semiconductor device.

[0090] The unique code may be provided on the first metal plate.

[0091] The thickness of the first metal plate and the thickness of the second metal plate may be different from each other.

[0092] In addition, a power semiconductor module according to an embodiment may include a first heat dissipation substrate, a power semiconductor device disposed on the first heat dissipation substrate, and a second heat dissipation substrate disposed on the power semiconductor device.

[0093] The first heat dissipation substrate or the second heat dissipation substrate may include one of heat dissipation substrates for a power semiconductor module.

[0094] The second metal plate is electrically connected to the power semiconductor device, and the unique code may be provided on the first metal plate.

[0095] The thickness of the first metal plate and the thickness of the second metal plate may be different from each other.

[0096] In addition, a power converter according to an embodiment may include any one of the above-described power semiconductor modules.

[0097] The technical effects according to the implementation scheme are as follows.

[0098] According to the embodiment, there is a technical effect of preventing the heat dissipation substrate from being warped by controlling the respective thickness ratios of the insulating substrate, the upper metal plate, and the lower metal plate constituting the heat dissipation substrate.

[0099] In addition, according to the first heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the first side of the insulating substrate SS facing the power semiconductor device 100 can be controlled to be less than or equal to the second thickness T2 of the second metal plate MP2 bonded to the second surface of the insulating substrate.

[0100] According to the second embodiment, since the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor device 100 can be controlled to be thin, there is a technical effect of providing a high-density power semiconductor module by ensuring a compact separation distance PD between the first circuit patterns CP1 of the first metal plate MP1 .

[0101] In addition, according to the third embodiment, the third thickness T3 of the third metal plate MP3 bonded to the power semiconductor device 100 can be controlled to be thick. Therefore, since the third thickness T3 of the third circuit pattern CP3 of the third metal plate MP3 can be controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2, when phase change bonding (transient liquid phase bonding) is performed between the power semiconductor device 100 and the third metal plate MP3, the problem of exhaustion of the metal plate material of the heat dissipation substrate during the IMC formation process can be prevented. Therefore, the third embodiment has a special technical effect in improving the bonding strength and solving the problem of pores appearing at the bonding interface.

[0102] In addition, there is the following technical effect: the heat dissipation substrate is managed by accurately matching and updating all production and quality information and history (such as thickness information of insulating substrates (such as ceramic substrates), inspection information, thickness information of copper plates, surface information, bonding interface information after the bonding process, etc.) for each "individual heat dissipation substrate".

[0103] For example, according to an embodiment, unique information can be marked on a dummy area of ​​an initial insulating substrate during the heat dissipation substrate manufacturing process, and the unique information can be stored and managed on a central server to store all production, so that there is a special technical effect that can accurately match and update all production and quality information and history in the heat dissipation substrate manufacturing process with respect to a "separate insulating substrate", a "separate metal plate", and a "separate heat dissipation substrate".

[0104] In addition, according to the embodiment, even if the position or arrangement of the insulating substrate is changed due to an operator's error during the manufacturing process, the unique information of the individual insulating substrate can be checked in all processes by application of the embodiment. And by verifying the unique information of the insulating substrate, there is a technical effect that the history of all processes including the initial reception, cleaning stage, and heat pressing of the individual insulating substrate can be completely updated and managed.

[0105] In addition, according to an embodiment, it can be confirmed that unique information related to the history of all processes starting from the initial warehousing stage of the product can be perfectly matched with the final product and delivered to the customer, and the customer can also accurately understand and use the product quality and production history through this unique information, or request after-sales service quickly and accurately when necessary.

[0106] Furthermore, simply marking product information on the heat dissipation substrate of the final product cannot perfectly match and manage film formation information such as thickness information of the insulating substrate constituting the product, thickness information of the metal plate, and bonding interface information.

[0107] In addition, according to the embodiment, there is a technical effect of minimizing thickness distribution by classifying the separate insulating substrates and metal plates by thickness and matching them by thickness grade.

[0108] For example, according to an embodiment, the insulating substrates may be classified and loaded into the first to third substrate boxes CM1, CM2, and CM3 according to thickness, and the thickness and classification loading information for "individual insulating substrates" and "individual substrate boxes" may be stored and managed on the upper server. In addition, the unique information UC of each insulating substrate SS may be accurately updated and managed using information about which substrate box the insulating substrate is loaded into.

[0109] Therefore, in the stacking process performed after the sputtering process, by reading the unique IDs of the first to third substrate boxes CM1, CM2 and CM3, there is a technical effect of optimizing the thickness quality of the heat dissipation substrate by matching the stacking process and bonding process for each thickness with the metal plate.

[0110] In addition, the embodiment precisely measures and manages the thickness of insulating substrates and copper plates delivered in various thicknesses to perfectly manage the thickness information so that it can be matched with each product through unique information, and there is a technical effect that the thickness distribution can be minimized based on the unique information.

[0111] For example, according to an embodiment, the thickness of an insulating substrate and a metal plate delivered in various thicknesses can be precisely measured and managed. Therefore, each thickness information can be completely updated and managed through the unique information UC to match the specifications of each product required by each customer. In addition, based on the unique information UC, the optimal stacking group combination of the insulating substrate and the metal plate can be calculated, and hot pressing can be performed after stacking. Therefore, there is a special technical effect in providing a heat dissipation substrate that can perfectly meet strict thickness specifications, a power semiconductor module equipped with the heat dissipation substrate, and a stacking system of an insulating substrate and a copper substrate.

[0112] In addition, the embodiment has a technical effect of providing an automatic alignment lamination device capable of automatically laminating and automatically aligning an insulating substrate and a metal plate.

[0113] For example, according to the “automatic alignment lamination system 800 ” of the embodiment, it is possible to perform several tens to more than one hundred sets of automatic lamination and thermocompression bonding processes.

[0114] Specifically, according to the embodiment, the bottom of the stacking unit 850 has an inclined structure, thereby producing a special technical effect that enables the edges of the sequentially stacked spacers, metal plates, and insulating substrates to be accurately and automatically aligned. For example, according to the embodiment, there is a special technical effect that can innovatively improve the vertical alignment accuracy by using gravity through inclined stacking.

[0115] Therefore, with the automatic lamination of tens of groups to more than 100 groups, accurate automatic alignment can be performed. In addition, even during the hot pressing bonding process exceeding tens of tons, the alignment is accurately maintained and the stacked group is not deformed. Therefore, there is a special technical effect that can achieve a high-quality heat dissipation substrate.

[0116] In addition, according to the embodiment, there is a technical effect of solving the problem of cracks occurring at the bonding interface of the heat dissipation substrate. For example, according to the embodiment, cracks caused at the interface between the insulating substrate and the copper sheet of the heat dissipation substrate can be prevented, thereby improving the reliability of the power semiconductor device.

[0117] The technical effects of the embodiments are not limited to those described in this section, and include those that can be understood through the description of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] Figure 1A This is a SEM photo of a heat dissipation substrate using a conventional AMB bonding method.

[0119] Figure 1B This is a photograph showing that the AMB heat dissipation substrate according to the prior art is warped after being bonded to the base plate (BP).

[0120] Figure 2A is a cross-sectional view of a power semiconductor module 500 including a heat dissipation substrate for a power semiconductor according to an embodiment.

[0121] Figure 2B FIG. 5 is a diagram showing a manufacturing process of a power semiconductor module 501 including a heat dissipation substrate for a power semiconductor according to the first embodiment.

[0122] Figure 2C FIG. 5 is a diagram showing a manufacturing process of a power semiconductor module 502 including a heat dissipation substrate for power semiconductors according to the second embodiment.

[0123] Figure 2D FIG. 5 is a diagram showing a manufacturing process of a power semiconductor module 503 including a heat dissipation substrate for power semiconductors according to the third embodiment.

[0124] Figure 3A is a first cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0125] Figure 3B is a second cross-sectional view of the power semiconductor device 100 according to the embodiment.

[0126] Figure 4 It is a process flow chart of a process for manufacturing a heat dissipation substrate for a power semiconductor according to an embodiment.

[0127] FIG. 5A to FIG. 11 It is a diagram of the pretreatment process of the insulating substrate.

[0128] Figures 12 to 15 is a diagram of a sputtering process of an insulating substrate according to an example.

[0129] Fig.16 This is a view of a metal magazine (MM) loaded with metal sheets classified by thickness.

[0130] Fig.17 and Fig.18FIG. 8 is a schematic diagram of an automatic alignment lamination system 800 for an insulating substrate and a metal plate according to an embodiment.

[0131] Fig.19 This is a flow chart of the lamination process of the insulating substrate and the metal plate.

[0132] Fig. 20 This is a conceptual diagram of a stacking group stacked in a stacking unit.

[0133] Figures 21 to 22B is a diagram of a thermocompression bonding process according to an embodiment.

[0134] Fig.23 This is an example of a heat dissipation substrate after the inspection process and etching process.

[0135] Figure 24 to Figure 26 This is a diagram of the laser scribing process, inspection process, and cutting process of the heat dissipation substrate.

[0136] Fig. 27 is a circuit diagram of a power converter according to an embodiment. DETAILED DESCRIPTION

[0137] Hereinafter, embodiments are described in detail with reference to the accompanying drawings.

[0138] The suffixes "module" and "unit" for the elements used in the following description are simply given in consideration of ease of writing this specification, and they themselves do not give particularly important meanings or roles. Therefore, "module" and "unit" can be used interchangeably.

[0139] Terms including ordinal numbers such as first and second may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.

[0140] Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0141] In the present application, terms such as “includes,” “has,” or “comprising” are intended to specify the presence of features, quantities, steps, operations, components, parts, or a combination thereof described in the specification, and do not exclude the absence of one or other features, quantities, steps, operations, components, parts, or a combination thereof, or any combination thereof.

[0142] In an embodiment, the power semiconductor module can be used in inverters or converters such as automobiles, computers, home appliances, solar energy, and smart grids. In addition, in addition to environmentally friendly vehicles, the power semiconductor module according to the embodiment can also be applied to various electrical and electronic devices such as electric differential vehicle chargers, power supply devices, or railways.

[0143] In addition, in an embodiment, the heat dissipation substrate for power semiconductors can also be used in inverters or converters such as automobiles, computers, home appliances, solar energy, and smart grids. In addition, in addition to environmentally friendly vehicles, the heat dissipation substrate for power semiconductors according to the embodiment can also be applied to various electrical and electronic devices such as electric differential vehicle chargers, power supply devices, or railways.

[0144] In an embodiment, the power semiconductor device may include one power semiconductor module or a plurality of power semiconductor modules. In addition, the power semiconductor module may include a plurality of power semiconductor devices.

[0145] In the following embodiments, the power semiconductor device describes an automotive inverter for driving an electric motor, but the power semiconductor device of the embodiment can be applied to inverters or converters in the above-mentioned various technical fields. Here, the vehicle includes a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vehicle (EV), and a fuel cell vehicle (PCEV). In the description of the following embodiments, the switching device and the power semiconductor device can be used interchangeably.

[0146] <Power semiconductor module including heat dissipation substrate>

[0147] Figure 2A is a cross-sectional view of a power semiconductor module 500 including a heat dissipation substrate for a power semiconductor according to an embodiment. Figure 2B FIG. 5 is a diagram showing a manufacturing process of a power semiconductor module 501 including a heat dissipation substrate for a power semiconductor according to the first embodiment.

[0148] Reference Figure 2A According to the embodiment, the power semiconductor module 500 may include: a first heat dissipation substrate 410, a second heat dissipation substrate 420, a power semiconductor device 100, a first lead frame 310, a second lead frame 320, and may be packaged by a mold 201, but is not limited thereto. The power semiconductor device 100 may include a first power semiconductor device 100a and a second power semiconductor device 100b.

[0149] For example, refer to Figure 2B , after the first lead frame 310, the second lead frame 320, and the single or multiple power semiconductor devices 100a and 100b are disposed between the first heat dissipation substrate 410 and the second heat dissipation substrate 420, the power semiconductor module 501 according to the first embodiment may be manufactured by pressing them.

[0150] The power semiconductor device 100 , the first heat dissipation substrate 410 , and the second heat dissipation substrate 420 may be bonded by a predetermined adhesive member (not shown).

[0151] For example, the first heat dissipation substrate 410 and the second heat dissipation substrate 420 may be bonded to the power semiconductor device 100 by soldering, sintering bonding, transient liquid phase bonding (TLP bonding), or ultrasonic bonding.

[0152] For example, the power semiconductor device 100 may be bonded to the first heat dissipation substrate 410 and the second heat dissipation substrate 420 by sinter bonding.

[0153] For example, the first and second heat dissipation substrates 410 and 420 may be bonded to the power semiconductor device 100 by screen printing a conductive paste such as Ag paste and then performing a sintering process at a temperature of about 150 to 300° C. The conductive paste may include conductive powder such as Ag, a solvent, and a bonding agent.

[0154] The heat dissipation substrate may be subjected to Cu or Ag surface treatment before sinter bonding. In addition, in the sinter bonding process, the bonding strength may be improved by pressure bonding using a predetermined bonding jig.

[0155] Alternatively, the power semiconductor device 100 of the embodiment may be bonded to the first heat dissipation substrate 410 and the second heat dissipation substrate 420 by transient liquid phase (TLP) bonding.

[0156] The transient liquid phase in the embodiment is a bonding technology that forms an IMC (Intermetallic Compound) based on diffusion at a predetermined temperature by inserting a thin metal sheet between metal layers.

[0157] In an embodiment, a material for forming the IMC junction may include a Cu-based, a Ni-based, etc. For example, in an embodiment, the IMC junction may include any one of Cu—Sn, Ni—Sn, and Cu—Ni—Sn.

[0158] Alternatively, the power semiconductor device 100 of the embodiment may be bonded to the first heat dissipation substrate 410 and the second heat dissipation substrate 420 by an ultrasonic bonding technique.

[0159] The ultrasonic bonding technology of the embodiment applies a certain pressure to the power semiconductor device and the heat dissipation substrate to be bonded, and vibrates with a certain amount of ultrasonic waves, such as about 20kHz or higher, and contacts the metals by rubbing the bonding surfaces and generating frictional heat. This is a technology that forms a junction and connects them by using it, etc.

[0160] The ultrasonic bonding technique of the embodiment may include a vertical vibration method and a horizontal vibration method according to the vibration direction.

[0161] Refer again Figure 2AIn the power semiconductor module 500 according to the embodiment, the first power semiconductor device 100a and the second power semiconductor device 100b may form an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may be connected in series through electrodes arranged in opposite directions, but the present invention is not limited thereto. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may be electrically connected in parallel.

[0162] In an embodiment, the first heat dissipation substrate 410 and the second heat dissipation substrate 420 may be disposed at a lower side and an upper side of the power semiconductor module 500 , respectively, but is not limited thereto.

[0163] The first heat dissipation substrate 410 may include a first metal plate MP1 , an insulating substrate SS, and a second metal plate MP2 .

[0164] The insulating substrate SS may electrically insulate the first metal plate MP1 and the second metal plate MP2. The insulating substrate SS may include a polycrystalline insulating substrate made of a ceramic material having high thermal conductivity. For example, the insulating substrate SS may be one of AlN or Si3N4, but is not limited thereto, and the insulating substrate SS may also include Al2O3. In addition, the insulating substrate SS may include a single crystal substrate such as a sapphire substrate.

[0165] Hereinafter, the insulating substrate SS will be described as an example of a polycrystalline substrate made of a ceramic material, but is not limited thereto, and the insulating substrate SS may also include a single crystal substrate.

[0166] The first metal plate MP1 and the second metal plate MP2 may include a Cu-based metal, but are not limited thereto.

[0167] One side of the second metal plate MP2 is in contact with the insulating substrate SS and can radiate heat to the other side. A heat sink including a cooling medium can be disposed near the other side of the second metal plate MP2.

[0168] Reference Figure 2B The first metal plate MP1 disposed at the lower side of the power semiconductor device 100 may include a first circuit pattern CP1 formed by a patterning process such as etching. The first circuit pattern CP1 may be electrically connected to an electrode of the power semiconductor device 100 .

[0169] For example, the first circuit pattern CP1 includes a first-first circuit pattern p11, a first-second circuit pattern p12, and a first-third circuit pattern p13 that are electrically separated, and these circuit patterns may be electrically connected to the first power semiconductor device 100a and the second power semiconductor device 100b, respectively. Figure 2A shown.

[0170] In addition, the second heat dissipation substrate 420 may also include a first metal plate MP1 , an insulating substrate SS, and a second metal plate MP2 . The second heat dissipation substrate 420 may adopt the technical features of the first heat dissipation substrate 410 .

[0171] For example, the first metal plate MP1 disposed on the power semiconductor device 100 may be formed by a patterning process such as etching, and may include an electrically separated second circuit pattern CP2. The second circuit pattern CP2 may include a second-first circuit pattern p21, a second-second circuit pattern p22, and a second-third circuit pattern p23, and may be electrically connected to the first power semiconductor device 100a and the second power semiconductor device 100b, such as Figure 2A shown.

[0172] Continue to refer to Figure 2A , one side of each of the first lead frame 310 and the second lead frame 320 can be electrically connected to the power semiconductor device 100, and the other side of each can be externally connected to a terminal. The external connection terminal may include an input power source, a motor, or an inverter controller.

[0173] For example, the first lead frame 310 and the second lead frame 320 may be electrically connected to the power semiconductor device 100 through the first heat dissipation substrate 410 and the second heat dissipation substrate 420 .

[0174] For example, the first lead frame 310 includes a first-first lead frame 310a electrically connected to the first-first circuit pattern p11 of the lower first metal plate MP1, and may include a first-second lead frame 310b electrically connected to the second-first circuit pattern p21 of the upper first metal plate MP1.

[0175] In addition, the second lead frame 320 includes a second-first lead frame 320a electrically connected to the first-third circuit pattern p13 of the lower first metal plate MP1, and may include a second-second lead frame 320b electrically connected to the second-third circuit pattern p23 of the metal plate MP1.

[0176] Next, Figure 2C FIG. 5 is a diagram showing a manufacturing process of a power semiconductor module 502 including a heat dissipation substrate for power semiconductors according to the second embodiment.

[0177] The power semiconductor module 502 including the heat dissipation substrate for power semiconductors according to the second embodiment may adopt the technical features of the power semiconductor module 501 including the heat dissipation substrate for power semiconductors according to the first embodiment described above, and the following description will focus on the technical features of the second embodiment.

[0178] Based on internal research, the problem of the distance between circuit patterns increasing with the thickness of the metal plate on the heat sink board was studied.

[0179] For example, when the thickness of the Cu board is about 0.2 mm, the separation distance between the circuit patterns is about 0.4 mm, and when the thickness of the Cu board is about 0.4 mm, there is a problem that the separation distance between the circuit patterns is about 0.6 mm.

[0180] In the internal technology, the thickness of the metal plates bonded to the top and bottom of the heat dissipation substrate is managed to be a certain thickness, and etching is performed to ensure an average separation distance when etching the metal plates.

[0181] In addition, in order to realize high-performance power semiconductor devices, complex circuit patterns are required as multiple SiC power semiconductors are mounted on a heat dissipation substrate. And if the separation distance between circuit patterns is wider than required, it is difficult to realize a high-density power semiconductor module.

[0182] Therefore, the inventors of the present application can control the thickness of the metal plate on the side of the heat dissipation substrate where the circuit pattern is formed to be different from the thickness of the metal plate on the other side. The control of the thickness of the metal plate will be described in detail later.

[0183] Reference Figure 2C In the power semiconductor module 502 according to the second embodiment, the first heat dissipation substrate 410B of the second embodiment may include a first metal plate MP1 having a first thickness (T1) on one side of the insulating substrate SS and facing the power semiconductor device 100, and a second metal plate MP2 having a second thickness T2 on the second side of the insulating substrate.

[0184] In the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than or equal to the second thickness T2 of the second metal plate MP2 .

[0185] For example, in the second embodiment, the first thickness T1 of the first metal plate MP1 may be smaller than the second thickness T2 of the second metal plate MP2.

[0186] According to the first heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the first surface of the insulating substrate SS facing the power semiconductor device 100 can be controlled to be less than or equal to the second thickness T2 of the second metal plate MP2 bonded to the second surface of the insulating substrate.

[0187] In addition, the second heat dissipation substrate 420B of the second embodiment may also adopt the technical features of the first heat dissipation substrate 410B of the second embodiment.

[0188] According to the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor device 100 may be controlled to be thin, and thus there is a technical effect of providing a high-density power semiconductor module by ensuring a compact separation distance PD between the circuit patterns CP1 .

[0189] Next, Figure 2D FIG. 5 is a diagram showing a manufacturing process of a power semiconductor module 503 including a heat dissipation substrate for power semiconductors according to the third embodiment.

[0190] The power semiconductor module 503 including the heat dissipation substrate for power semiconductors according to the third embodiment may adopt the technical features of the power semiconductor module 501 including the heat dissipation substrate for power semiconductors according to the first embodiment described above, and the following description will focus on the technical features of the third embodiment.

[0191] According to internal research, during transient liquid phase bonding (TLP), when the metal plate material of the heat dissipation substrate is used up to form IMC (intermetallic compound), the IMC bonding layer is not properly formed. Therefore, there is a problem of reduced bonding strength or the occurrence of voids.

[0192] However, in power semiconductor modules operating at extremely high temperatures, reduced adhesion between the power semiconductor device and the heat dissipation substrate or the presence of voids at the bonding interface can have a significant impact on performance degradation and reliability of the power semiconductor module.

[0193] Therefore, the inventors of the present application can control the thickness of the metal plate on the side of the heat dissipation substrate on which the circuit pattern is formed to be different from the thickness of the metal plate on the other side.

[0194] For example, refer to Figure 2D In the power semiconductor module 503 according to the third embodiment, the third heat dissipation substrate 430 may include a third metal plate MP3 with a third thickness T3 bonded to one side of the insulating substrate SS and facing the power semiconductor device 100, and a second metal plate MP2 with a second thickness T2 bonded to the second side of the insulating substrate.

[0195] In the third embodiment, the third thickness T3 of the third metal plate MP3 may be greater than or equal to the second thickness T2 of the second metal plate MP2.

[0196] For example, in the third embodiment, the third thickness T3 of the third metal plate MP3 may exceed the second thickness T2 of the second metal plate MP2.

[0197] According to the third embodiment, the third thickness T3 of the third metal plate MP3 bonded to the first side of the insulating substrate SS facing the power semiconductor device 100 may be controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2 bonded to the second surface of the substrate.

[0198] According to the third embodiment, the third thickness T3 of the third metal plate MP3 bonded to the power semiconductor device 100 can be controlled to be thick, and therefore, the third thickness T3 of the circuit pattern CP3 is also controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2. Therefore, when transient liquid phase bonding is performed between the power semiconductor device 100 and the third metal plate MP3, the problem of exhaustion of the metal plate material of the heat dissipation substrate during the IMC formation process can be prevented. Therefore, there is a special technical effect that can improve the bonding strength and solve the problem of pores appearing at the bonding interface.

[0199] Next, Figure 3A is a first cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0200] Reference Figure 3A , a power semiconductor device 100 according to an embodiment includes a substrate 110, a first conductive type epitaxial (epi) layer 120, a second conductive type well 130, a first conductive type source region 140, a gate insulating layer 150, a gate electrode 160, and a drain electrode 105. The first conductive type may be an N type, and the second conductive type may be a P type, but are not limited thereto.

[0201] For example, the power semiconductor device 100 includes a first conductive epitaxial layer 120 formed on a predetermined substrate 110, a second conductive well 130 formed in the first conductive epitaxial layer 120, a first conductive type source region 140 formed in the second conductive well 130, a gate insulating layer 150 and a gate electrode 160 located on the first conductive type source region 140, and a drain electrode 105 arranged under the substrate 110.

[0202] The substrate 110 and the first conductive epitaxial layer 120 may include SiC (Silicon Carbide), but are not limited thereto.

[0203] Next, Figure 3B is a second cross-sectional view of the power semiconductor device 100 according to an embodiment, and is based on Figure 3A A schematic diagram of a first cross-sectional view is shown.

[0204] The power semiconductor device 100 according to the embodiment includes a source electrode 145 s disposed above a predetermined semiconductor epitaxial layer 120 , a gate electrode 165 g , and a drain electrode 105 disposed below the semiconductor epitaxial layer 120 .

[0205] In the form of MOSFET, the source electrode 145s or the gate electrode 165g may include an Al-based metal, and the drain electrode 105 may be a Ti / Ni / Ag metal layer including a Ti layer, a Ni layer and an Ag layer, or may include NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0206] <Manufacturing process of heat dissipation substrate for power semiconductor>

[0207] Figure 4 is a schematic process flow chart of a manufacturing process of a heat dissipation substrate for a power semiconductor according to an embodiment.

[0208] According to the embodiment, the manufacturing process of the heat dissipation substrate for power semiconductors may include the following steps: ① pretreatment process of the insulating substrate, ② sputtering process, ③ metal plate pretreatment process, ④ lamination process of the insulating substrate and the metal plate, ⑤ hot pressing process of the insulating substrate and the metal plate, ⑥ etching process of the heat dissipation substrate, ⑦ inspection and cutting process of the heat dissipation substrate, etc.

[0209] The overall manufacturing process of the heat dissipation substrate for power semiconductor according to the embodiment may be controlled by a control unit (not shown) of a central server, and the central server may include a data storage unit (not shown).

[0210] Hereinafter, a main manufacturing process of a heat dissipation substrate for a power semiconductor according to an embodiment will be described with reference to the accompanying drawings.

[0211] (Pretreatment process of insulating substrate)

[0212] An insulating substrate for manufacturing a heat dissipation substrate according to the following example will be described as an example of a polycrystalline ceramic substrate, but is not limited thereto, and may include a single crystal substrate such as a sapphire substrate.

[0213] In the following, reference will be made to FIG. 5A to FIG. 11 To describe the pretreatment process of the insulating substrate.

[0214] In an embodiment, a “pre-treatment process of the insulating substrate” may be performed in a substrate cleaning apparatus (not shown) before a “lamination process” of the insulating substrate and the metal plate.

[0215] The pretreatment process of the insulating substrate may include: ① an insulating substrate loading step, ② a unique code UC marking process, ③ an insulating substrate cleaning process, ④ an insulating substrate thickness measuring process, and ⑤ a loading process into a box for each thickness of the insulating substrate.

[0216] ①Insulating substrate loading steps

[0217] First, if Figure 5AAs shown, a predetermined insulating substrate SS may be prepared and loaded into a ceramic cleaning device (not shown). The insulating substrate SS may be AlN, Si3N4, or Al2O3, but is not limited thereto. The insulating substrate SS may have irregularities R on its surface, but is not limited thereto, and the insulating substrate SS may also include a single crystal substrate such as a sapphire substrate.

[0218] also, Figure 5B is a photograph showing the uneven portion R on the surface of the insulating substrate SS in the internal technology.

[0219] On the surface of the insulating substrate SS, there may be uneven portions R ranging in size from several μm to several hundred μm. When conventional techniques are used, these uneven portions R may cause voids to occur during the bonding process.

[0220] Reference Figure 5B In the prior art or internal technology, the occurrence of pores is considered to be more inevitable due to the unevenness R with a size of several μm to several hundred μm existing on the surface of the insulating substrate. However, considering the extremely high operating temperature environment of the power semiconductor module, a solution must be prepared.

[0221] ② Unique code UC marking process

[0222] In the conventional heat dissipation substrate industry, it is difficult to accurately match the overall production and quality history, such as insulating substrate thickness information, copper plate thickness information, and product information after the bonding process, "for each heat dissipation substrate".

[0223] Specifically, when metal sputtering is performed on an insulating substrate to which the present invention is applied, followed by a copper plate and a hot pressing process, even if a code is marked on the insulating substrate, the code is obscured by the sputtering process and the hot pressing process. Therefore, no attempt is made to mark individual codes for each "individual heat dissipation substrate".

[0224] Reference Figure 6 , a unique code UC may be marked on the insulating substrate SS loaded in the substrate cleaning device. Thereafter, the unique code UC is read, transmitted and stored to the data storage unit of the server by wire or wireless, and detailed information related to the "separate heat dissipation substrate" including the "separate insulating substrate" in subsequent processes may be accurately updated and managed.

[0225] Reference Figure 6 , the insulating substrate SS may include an active area AA and a dummy area DA. The outermost edge of the active area AA may be a boundary (B) between the active area AA and the dummy area DA.

[0226] The active area AA is an area to be used in a final heat dissipation substrate product in the future, and the dummy area DA is an area to be removed. The unique code UC may be marked on the dummy area DA of the insulating substrate SS.

[0227] The unique code UC may include, but is not limited to, a digital matrix code (DMC), a QR code, or a barcode. For example, the unique code UC may include a unique code marked or annotated by a unique code technology that may appear through technical development after applying the present invention.

[0228] In addition, the unique code UC may be marked by a laser marking (LM) technique, but is not limited thereto.

[0229] Figure 7 is a photograph of an insulating substrate SS on which a unique code UC is marked in a dummy area DA according to an embodiment.

[0230] In an embodiment, the unique code UC may be marked on a dummy area DA removed by scribing the insulating substrate SS, and may be spaced apart from the active area AA by a predetermined distance.

[0231] In an embodiment, in addition to the unique code UC, a unique ID may be marked in the dummy area DA of the insulating substrate SS. The unique ID may include a combination of numbers or letters, but is not limited thereto, and may include a serial number that can be recognized by an operator or an imaging device.

[0232] According to an embodiment, after marking the unique code UC and the unique ID for the entire inserted insulating substrate SS, it can be sent to the data storage unit of the upper server and managed, and detailed information related to the "separate insulating substrate" and the "separate heat dissipation substrate" including the "separate insulating substrate" can be accurately updated and managed, and there is also a special technical effect that enables post-management between processes.

[0233] also, Figure 8 are photographs of technical problems that occur when a unique code UCr is marked on an insulating substrate SSr of a comparative example.

[0234] In the heat sink substrate industry, there has been no attention or attempt to manage the process history of the heat sink substrate manufacturing process for separate insulating substrates.

[0235] In addition, the inventors of the present application discovered that in a new research process for process history management of a manufacturing process for a "separate insulating substrate" in the field of heat dissipation substrates, when a unique code UCr was marked on the insulating substrate of a comparative example, a unique problem was discovered that burning HR occurred and spread beyond the dummy area DA to reach the active area AA.

[0236] This unique technical problem was studied: Burning HR will cause sputtering defects in the subsequent sputtering process, which is directly related to the quality of the heat dissipation substrate itself, and can further cause bonding defects in the metal plate and hot pressing process.

[0237] Therefore, not only is it difficult to imagine marking a specific unique code on the insulating substrate itself, but there are also significant technical difficulties in achieving this.

[0238] However, the inventors of the present application independently studied that the burning does not affect the active area when marking the unique code UC, and that the unique code UC is accurately marked in the dummy area DA without the burning.

[0239] Furthermore, in the present invention, marking a unique code on an insulating substrate causes the unique code to be shielded during the sputtering process and the heat pressing process, and thus attempts to mark a unique code on a separate insulating substrate are technically difficult.

[0240] Next, Fig.9A is a signature diagram of the first unique code UC1 according to the first embodiment, and Fig. 9B is a marking diagram of the second unique code UC2 according to the second embodiment.

[0241] The unique code in an embodiment may include a square or rectangular pattern and may include four corners and four vertices.

[0242] Reference Fig.9A , the first unique code UC1 and the active area vertex AE of the adjacent ceramic substrate may be spaced apart by a first distance D1. At this time, the vertex CE1 of the first unique code and the vertex AE of the active area may be arranged to face each other.

[0243] According to the embodiment, there is a special technical effect that the production history and product information of each individual ceramic substrate product can be traced back by marking the unique code UC on the ceramic substrate SS.

[0244] For example, according to the embodiment, a unique code UC and a unique ID can be marked for the entire inserted ceramic substrate SS, and then sent to the data storage unit of the upper server and managed, and detailed information related to the "separate ceramic substrates" and the "separate heat dissipation substrates" containing them can be accurately updated and managed. In addition, there is a special technical effect that enables post-event management between processes.

[0245] However, referring to Fig. 9B Through additional research, the inventors of the present application placed the second unique code vertex CE2 and the vertex AE of the active area at a certain distance from each other, so that even if burns occur, the possibility of the burns spreading to the active area AA is significantly reduced by placing the second unique code vertex CE2 and the vertex AE of the active area far apart.

[0246] For example, by arranging the side edge of the second unique code UC2 and the vertex AE of the active area to face each other, there is a technical effect of significantly reducing the possibility of burning spreading to the active area AA even if burning occurs.

[0247] ③ Cleaning process of insulating substrate and ④ Thickness measurement process

[0248] Next, refer to Fig.10 , a cleaning process and a thickness measurement process for the insulating substrate SS may be performed.

[0249] For example, a CDA (Clean Dry Air) cleaning process CL may be performed on the insulating substrate SS.

[0250] In addition, in this example, after cleaning the insulating substrate SS, the thickness at nine points may be measured using a displacement sensor TM or the like, but is not limited thereto.

[0251] The thickness of the insulating substrate SS may be 200 μm to 1000 μm, but is not limited thereto. Preferably, the thickness of the insulating substrate SS may be 300 μm to 800 μm, but is not limited thereto.

[0252] The insulating substrates SS may be classified into a plurality of groups according to their thicknesses. For example, the insulating substrates SS may be classified into first to third groups of insulating substrates according to the thicknesses of the insulating substrates SS, but are not limited thereto.

[0253] ⑤ Loading process according to the thickness of the insulating substrate

[0254] Fig.11 1 is a diagram of a substrate cassette CM loaded with insulating substrates sorted by thickness after cleaning according to the embodiment.

[0255] For example, the insulation substrates may be classified into first to third group insulation substrates SS1 , SS2 , and SS3 according to the first to third thicknesses T1 , T2 , and T3 .

[0256] For example, the thicknesses of the first group insulating substrate SS1 , the second group insulating substrate SS2 , and the third group insulating substrate SS3 may become thicker in this order, but the thicknesses are not limited thereto.

[0257] The first to third groups of insulating substrates SS1, SS2 and SS3 may be loaded into first to third substrate cassettes CM1, CM2 and CM3, respectively, and then transferred to a predetermined lamination device. The first to third groups of insulating substrates may be referred to as first to third batches.

[0258] In an embodiment, each of the first to third substrate cassettes CM1 , CM2 , and CM3 may also be marked with a predetermined unique ID or a unique code.

[0259] According to an embodiment, insulating substrates may be classified and loaded into first to third substrate boxes CM1 , CM2 , and CM3 according to thickness, and classified loading information and thickness for “separate insulating substrates” and “separate substrate boxes” may be stored and managed on an upper server.

[0260] In addition, the unique code UC of each insulating substrate SS can be accurately updated and managed using information on which substrate cassette the insulating substrate is loaded into.

[0261] Therefore, in the lamination process performed after the sputtering process, by reading the unique IDs of the first to third substrate cassettes CM1, CM2, and CM3, the thickness quality of the heat dissipation substrate can be optimized by matching the lamination and bonding processes for each thickness with the metal plate.

[0262] According to the embodiment, there is a technical effect of minimizing thickness distribution by classifying the individual insulating substrates and metal plates by thickness and matching them by thickness grade.

[0263] Currently, in the field of heat dissipation substrates, the thickness of the supplied insulating substrates is not constant, and the thickness of the supplied metal plates (such as copper plates) is also not constant.

[0264] In this case, the final heat sink substrate must meet the strict specifications of the heat sink substrate delivery standard, but there are many difficulties in producing a heat sink substrate that can meet the strict thickness specifications.

[0265] Therefore, the inventors of the present invention have invented a lamination system for insulating substrates and copper substrates, which precisely measures and manages the thicknesses of insulating substrates and copper plates delivered in various thicknesses and perfectly manages the thickness information so that it can be matched with each product through unique information UC, and based on the unique information UC, the thickness distribution can be minimized.

[0266] (Sputtering process)

[0267] As described above, the insulating substrates classified by thickness can be transferred to the sputtering device while being loaded into the first to third substrate boxes CM1, CM2 and CM3, and unloaded for each individual insulating substrate, and then the insulating substrate can be mounted on the sputtering device and the sputtering process can be performed.

[0268] In the following, reference is made to Figures 12 to 15 , the “sputtering process for insulating substrate” of the embodiment will be described.

[0269] Reference Fig.12 , a bonding metal layer 411 having a first thickness may be formed on one surface of the insulating substrate SS by sputtering.

[0270] At this time, sputtering may not be performed in the unique code UC and unique ID regions. For example, in the sputtering process, the unique code UC and unique ID regions are covered and protected by the sprayed part of PS, etc., and then sputtering may be controlled not to be performed in the unique code UC and unique ID regions.

[0271] For example, with Fig.12 Unlike the example shown, this embodiment can control or even prevent sputtering on a portion of the sprayed PS.

[0272] For example, refer to Fig.13 The insulating substrate SS is mounted on the anode of the PVD device 700, and a bonding metal layer 411 including Ti or TiW may be deposited in an inert atmosphere such as Ar gas. to The first thickness.

[0273] For example, the bonding metal layer 411 may be deposited to approximately to The thickness may be, but not limited to, .

[0274] Next, refer to Fig.14 The bonding metal layer 411 and the diffusion metal layer 412 may be formed by sputtering. The diffusion metal layer 412 may be deposited to a second thickness thinner than the first thickness of the bonding metal layer 411 by sputtering.

[0275] For example, the second thickness of the diffusion metal layer 412 may be in the range of ¼ to ½ of the first thickness of the bonding metal layer 411 .

[0276] For example, the second thickness of the diffusion metal layer 412 may be about to Preferably, the second thickness of the diffusion metal layer 412 may be about to But it is not limited to this.

[0277] The diffusion metal layer 412 may have a melting point lower than the temperature of the hot pressing process used for bonding. For example, the temperature of the hot pressing may be in the range of about 900° C. to 1100° C., and the diffusion metal layer 412 may be a material having a melting point less than 900° C. and having excellent diffusion characteristics. For example, the diffusion metal layer 412 may be any one or more of Al, Ag, Au, and Sn, but is not limited thereto.

[0278] In addition, in an embodiment, it is possible to Fig.13 The sputtering is performed with the anode electrode plate of the bonding metal layer 411 in an inclined state. Thus, the diffusion metal region 412a can be controlled to be formed in the form of islands spaced apart from each other while first filling the bottom and side of the concave portion of the surface irregularity of the bonding metal layer 411.

[0279] The diffusion metal region 412a may be formed to have a third thickness that is much thinner than the first thickness of the bonding metal layer 411, and the third thickness is 1 / 10 to 1 / 4 of the first thickness. For example, the third thickness of the diffusion metal region 412a may be about to Preferably, the third thickness of the diffusion metal region 412a may be about to But it is not limited to this.

[0280] Next, refer to Fig.15 , after the insulating substrate SS on which the diffusion metal layer 412 has been deposited on one surface is turned over, the bonding metal layer 411 and the diffusion metal layer 412 may be sequentially formed on the opposite surface by sputtering.

[0281] In an embodiment, the thickness of the bonding metal layer 411 and the diffusion metal layer 412 of each individual insulating substrate SS is measured after sputtering, and the thickness data of each unique code UC is sent to a server for update management.

[0282] For example, in an embodiment, the thickness of the deposited bonding metal layer 411 and the diffusion metal layer 412 may be measured by measuring a sheet resistance of a separate insulating substrate SS, but the present invention is not limited thereto.

[0283] The individual insulating substrates whose thicknesses of the bonding metal layer 411 and the diffusion metal layer 412 have been measured can be transferred to the stacking device, which is again loaded into the first substrate box to the third substrate box CM1, CM2 and CM3, and the thicknesses of the respective insulating substrates and the respective metal plates can be matched and then stacked in the stacking device.

[0284] (Metal plate pretreatment process)

[0285] Fig.16 FIG. 2 is a diagram of a metal box MM loaded with metal plates classified by thickness after cleaning according to an embodiment.

[0286] The metal plate pretreatment process may be performed separately from the insulating substrate pretreatment process. For example, the metal plate pretreatment process may be performed before, after, or simultaneously with the insulating substrate pretreatment process.

[0287] The metal plate may be a metal plate having excellent electrical conductivity and thermal conductivity. For example, the metal plate may be a Cu plate or a Cu alloy plate, but is not limited thereto. The metal plate may also be referred to as a metal substrate.

[0288] The metal plate preprocessing process may include a cleaning process and a thickness measuring process of the metal plate, and then the metal plates classified by respective thickness categories may be sorted and loaded into a metal box.

[0289] For example, a CDA (clean dry air) cleaning process and a particle exhaust process of the metal plate may be performed.

[0290] In addition, in an embodiment, after cleaning the metal plate, the top / bottom thickness of the metal plate may be measured using a displacement sensor, etc. For example, the thickness of 9 points of the metal plate may be measured, but the method is not limited thereto.

[0291] Furthermore, an embodiment may transmit information about the thickness of the metal plate to an upper server so that information about the individual metal plates may be accurately updated and managed.

[0292] Additionally, in an embodiment, a marking process for metal specific information (not shown) may be performed on a dummy area of ​​the metal plate before cleaning, but the process is not limited thereto.

[0293] In an embodiment, the thickness of the metal plate may be 200 μm to 500 μm, but is not limited thereto. Preferably, the thickness of the metal plate may be 250 μm to 350 μm, but is not limited thereto.

[0294] The metal plates may be classified into a plurality of groups according to their thickness. For example, the metal plates may be classified into first to third metal plates MP1, MP2, and MP3 according to their thickness, but are not limited thereto. The thicknesses of the first metal plate MP1, the second metal plate MP2, and the third metal plate MP3 may increase in this order, but are not limited thereto.

[0295] For example, refer to Fig.16 , the first to third groups of metal plates MP1, MP2 and MP3 classified into the first to third thicknesses T1, T2 and T3 are loaded into the first to third metal boxes MM1, MM2 and MM3, respectively, and then transferred to a predetermined lamination device. The first to third groups of metal plates can be referred to as the first to third batches.

[0296] In an embodiment, each of the first to third metal boxes MM1 , MM2 , and MM3 may be marked with a predetermined unique ID or a unique code.

[0297] According to an embodiment, the metal plates may be classified and loaded into the first to third metal boxes MM1, MM2, and MM3 according to thickness, and thickness and classified loading information for individual metal plates and metal boxes may be stored and managed on an upper server.

[0298] In addition, unique information of each metal plate can be accurately updated and managed using information about which metal box the metal plate is loaded into.

[0299] Therefore, in the subsequent lamination process, the unique IDs of the first to third metal boxes MM1, MM2, and MM3 can be read, and the thickness quality can be optimized by matching and bonding the respective thicknesses with the insulating substrate.

[0300] According to the embodiment, there is a technical effect of classifying not only the individual insulating substrates but also the metal plates by thickness and minimizing the thickness distribution by matching the respective thickness grades.

[0301] Currently, in the field of heat dissipation substrates, not only the thickness of the supplied insulating substrates but also the thickness of the supplied metal plates (such as copper plates) are inconsistent. In this case, the final heat dissipation substrate must meet the strict specifications of the heat dissipation substrate delivery standard, but there are many difficulties in producing heat dissipation substrates that can meet the strict thickness specifications.

[0302] Therefore, the inventors of the present invention precisely measured and managed the thickness of the insulating substrates and copper plates delivered in various thicknesses to perfectly manage the thickness information so that it can be matched with each product through unique information. Based on this unique information, a lamination system of insulating substrates and copper substrates that can minimize thickness distribution was invented.

[0303] For example, according to an embodiment, the strict specifications of the heat dissipation substrate delivery standard can be met by a laminate group including a second insulating substrate SS2 having a second thickness T2, a second metal plate MP2 having a second thickness T2 as an upper plate, and a second metal plate MP2 having a second thickness T2 as a lower plate.

[0304] For example, according to an embodiment, the strict specifications of the heat dissipation substrate delivery standard can be met by providing a laminate group including a second insulating substrate SS2 having a second thickness T2, a first metal plate MP1 having a first thickness T1 as an upper plate, and a second metal plate MP2 having a second thickness T2 as a lower plate.

[0305] Or for example, according to an embodiment, the strict specifications of the heat dissipation substrate delivery standard can be met by providing a laminate group including a second insulating substrate SS2 having a second thickness T2, a first metal plate MP1 having a first thickness T1 as an upper plate, and a third metal plate MP3 having a third thickness T3 as a lower plate.

[0306] Or for example, according to an embodiment, the strict specifications of the heat dissipation substrate delivery standard can be met by providing a laminate group including a first insulating substrate SS1 having a first thickness T1, a first metal plate MP1 having a first thickness T1 as an upper plate, and a third metal plate MP3 having a third thickness T3 as a lower plate.

[0307] Or for example, according to an embodiment, the strict specifications of the heat dissipation substrate delivery standard can be met by providing a laminate group including a first insulating substrate SS1 having a first thickness T1, a second metal plate MP2 having a second thickness T2 as an upper plate, and a third metal plate MP3 having a third thickness T3 as a lower plate.

[0308] Or for example, according to an embodiment, the strict specifications of the heat dissipation substrate delivery standard can be met by providing a laminate group including a third insulating substrate SS3 having a third thickness T3, a first metal plate MP1 having a first thickness T1 as an upper plate, and a first metal plate MP1 having a first thickness T1 as a lower plate.

[0309] Or for example, according to an embodiment, the strict specifications of the heat dissipation substrate delivery standard can be met by providing a laminate group including a third insulating substrate SS3 having a third thickness T3, a first metal plate MP1 having a first thickness T1 as an upper plate, and a second metal plate MP2 having a second thickness T2 as a lower plate.

[0310] According to the embodiment, the thickness of the insulating substrate and the metal plate delivered in various thicknesses can be carefully measured and managed, and the respective thickness information can be completely updated through the unique information UC to match the product specifications required by each customer. Therefore, based on the unique information UC, the optimal stacking group combination of the insulating substrate and the metal plate can be calculated, and the hot pressing process can be performed after stacking. Therefore, there is a special technical effect in providing a heat dissipation substrate that can perfectly meet strict thickness specifications, a power semiconductor module equipped with the heat dissipation substrate, and a stacking system of an insulating substrate and a copper substrate.

[0311] (Lamination process of insulating substrate and metal plate)

[0312] Next, we will refer to Figures 17 to 19 To describe the lamination process of the insulating substrate and the metal plate.

[0313] Fig.17 and Fig.18 is a schematic diagram of an automatic alignment lamination apparatus 800 for an insulating substrate and a metal plate in an embodiment, and Fig.16 This is a flow chart of the lamination process of the insulating substrate and the metal plate.

[0314] Internal technology relies on manual work of the insulating substrate and metal plate lamination process. In addition, when the lamination process is performed manually, it is difficult to consider matching the thickness of the insulating substrate and the metal plate, and it is not even easy to control the placement of the metal plate on the upper and lower sides of the insulating substrate.

[0315] Specifically, in the internal technology, the stacking group of the heat dissipation substrate includes an insulating substrate and metal plates arranged on the top and bottom, and in terms of achieving a high stacking density of stacking groups of dozens to nearly 100 groups, the alignment of the insulating substrate and the metal plates is studied as a very difficult technical challenge.

[0316] In other words, if the alignment of the insulating substrate and the metal plate is even slightly inaccurate, there is a problem of bonding defects occurring in the subsequent heat pressing process performed under a pressure of several tens of tons.

[0317] Therefore, the inventors of the present application invented an “automatic alignment lamination system 800” capable of automatically laminating and aligning an insulating substrate and a metal plate.

[0318] Temporary reference Fig.19, the stacking process of the insulating substrate and the metal plate may include: ① a loading process of the carbon spacer, ② a loading process of the lower metal plate, ③ a loading process of the insulating substrate, ④ a loading process of the upper metal plate, ⑤ a loading process of the carbon spacer, and ⑩ a loading process of graphite.

[0319] First, refer to Fig.17 and Fig.18 The "automatic alignment lamination system 800" of an insulating substrate and a metal plate is described.

[0320] Reference Fig.17 The automatic alignment lamination system 800 in the embodiment may include a spacer port 805 , a first substrate port 800P1 , a second metal port 800P2 , a third metal port 800P3 , a graphite port 840 , and a lamination unit 850 .

[0321] In addition, the automatic alignment lamination system 800 of the embodiment may include a first conveyor belt 800C1 and a particle applying device 807 located on a first shelf 800B1 and a second conveyor belt 800C2 located on a second shelf 800B2.

[0322] In the following, reference will be made to Fig.18 To describe the characteristics of each device in detail.

[0323] The automatic alignment lamination system 800 according to the embodiment may use an automatic transfer device to realize automatic transfer or automatic lamination of various insulating substrates, metal plates, etc. For example, the automatic transfer device may include first to seventh transfer devices 800R1, 800R2, 800R3, 800R4, 800R5, 800R6, 800R7, which include robots equipped with transfer arms and servo motors, etc., but are not limited thereto.

[0324] First, the predetermined spacer 415 (see Fig.17 ) may be loaded into the spacer port 805. The spacer 415 may be a carbon spacer or a ceramic spacer, but is not limited thereto.

[0325] Additionally, embodiments may include a particle application device 807 located on the first conveyor belt 800C1. The operation of the particle application device 807 will be described later.

[0326] Next, the first substrate port 800P1 may include a substrate cassette CM in which sputtered insulating substrates are sorted and loaded by thickness. For example, the first substrate port 800P1 may include first to third substrate cassettes CM1, CM2, and CM3 in which sputtered insulating substrates are sorted and loaded according to thickness.

[0327] Next, the second metal port 800P2 may include metal boxes MM in which metal plates are classified and loaded by thickness. For example, the second metal port 800P2 may include first to third metal boxes MM1, MM2, and MM3 in which metal plates are classified and loaded according to thickness.

[0328] A lower metal plate disposed under the insulation substrate during the lamination process may be loaded in the second metal port 800P2 .

[0329] Next, the third metal port 800P3 may also include metal boxes MM in which metal plates are classified and loaded according to thickness. For example, the third metal port 800P3 may include first to third metal boxes MM1, MM2, and MM3 in which metal plates are classified and loaded according to thickness.

[0330] An upper metal plate disposed on an upper side of the insulation substrate during a lamination process may be loaded into the third metal port 800P3 .

[0331] Next, a certain amount of graphite 480 (see Fig.17 ) can be loaded into the graphite port 840. The graphite 480 can act as a release sheet.

[0332] In the following, reference will be made to Figures 18 to 20 A lamination process using the automatic alignment lamination system 800 according to an embodiment will be described.

[0333] First, the first spacer 415 a may be loaded on the first conveyor belt 800C1 by the first transfer device 800R1 and then moved to the particle applying device 807 .

[0334] Before entering the particle applying device 807 , a cleaning process such as CDA may be performed on the first spacer 415 a .

[0335] After the cleaning process, predetermined particles may be sprayed onto one surface of the first spacer 415a using air through the particle applying device 807 and coated with a roller. Thereafter, it may be turned over and particles may be applied to the surface.

[0336] The particles may include boron nitride (B / N) or the like, and are intended to facilitate separation of the heat sink substrate after a thermocompression bonding process.

[0337] The first spacer 415 a moved by the first conveyor belt 800C1 may be stacked on the stacking unit 850 by the sixth transfer device 800R6 .

[0338] According to an example, by automating and homogenizing the particle application process, the quality of the heat dissipating substrate may be improved and the process time may be reduced.

[0339] Next, the metal plate loaded on the second metal port 800P2 may be unloaded onto the second conveyor belt 800C2 of the second shelf 800B2 through the second transfer device 800R2.

[0340] For example, the second metal plate MP2 loaded on the second metal box MM2 of the second metal port 800P2 may be moved to the second metal plate MP2 on the second shelf 800B2 by the second transfer device 800R2 and may be unloaded on the conveyor belt 800C2.

[0341] Thereafter, the second metal plate MP2 moved by the second conveyor belt 800C2 may be stacked on the stacking unit 850 by the fifth transfer device 800R5. The second metal plate MP2 may be stacked on the first spacer 415a.

[0342] Next, the insulating substrate loaded on the first substrate port 800P1 may be unloaded onto the second conveyor belt 800C2 of the second shelf 800B2 by the third transfer device 800R3.

[0343] For example, the second insulating substrate SS2 loaded in the second substrate cassette CM2 of the second metal port 800P2 may be unloaded on the second conveyor belt 800C2 by the third transfer device 800R3 .

[0344] Thereafter, the second insulating substrate SS2 moved by the second conveyor belt 800C2 may be stacked on the stacking unit 850 by the fifth transfer device 800R5. The second insulating substrate SS2 may be stacked on the second metal plate MP2.

[0345] Next, the metal plate loaded on the third metal port 800P3 may be unloaded onto the second conveyor belt 800C2 of the second shelf 800B2 through the fourth transfer device 800R4.

[0346] For example, the second metal plate MP2 loaded on the second metal box MM2 of the third metal port 800P3 may be unloaded on the conveyor belt 800C2 of the second shelf 800B2 by the fourth transfer device 800R4.

[0347] Thereafter, the second metal plate MP2 moved by the second conveyor belt 800C2 may be stacked on the stacking unit 850 by the fifth transfer device 800R5. The second metal plate MP2 may be stacked on the second insulating substrate SS2.

[0348] Next, the second spacer 415 b may be loaded onto the first conveyor belt 800C1 through the first transfer device 800R1 and then moved to the particle applying device 807 .

[0349] Before entering the particle application device 807, a cleaning process such as CDA may be performed.

[0350] After the cleaning process, predetermined particles may be air-sprayed onto one surface of the second spacer 415b by the particle applying device 807 and coated with a roller. Thereafter, the second spacer 415b may be turned over and particles may be applied to the surface.

[0351] The particles may include boron nitride (B / N) or the like, and are intended to facilitate separation of the heat sink substrate after a thermocompression bonding process.

[0352] The second spacer 415b moved by the first conveyor belt 800C1 may be stacked on the stacking unit 850 by the sixth transfer device 800R6. The second spacer 415b may be stacked on the second metal plate MP2.

[0353] Thus, the heat dissipation substrate 410A (see Fig.22A ) of the first stack ST1 (see Fig. 20 ).

[0354] After that, the heat dissipation substrate 410B (see Fig.22A ) of the second stack ST2 (see Fig. 20 ) stacking process. For example, refer to Fig. 20 , the second metal plate MP2 , the first insulating substrate SS1 , the first metal plate MP1 , and the third spacer 415 c may be sequentially stacked on the second spacer 415 b .

[0355] In an embodiment, the graphite 480 may be stacked after performing 10 stacking groups, but the method is not limited thereto.

[0356] As described above, according to internal research, the problem that the distance between circuit patterns increases as the metal plate on the heat dissipation substrate becomes thicker has been studied. For example, when the thickness of the Cu plate is about 0.2 mm, the separation distance between the circuit patterns is about 0.4 mm. However, when the thickness of the Cu plate is about 0.4 mm, there is a problem that the separation distance between the circuit patterns is about 0.6 mm.

[0357] In the internal technology, the thickness of the metal plates bonded to the top and bottom of the heat dissipation substrate is managed within a specific thickness range, and when etching the metal plates, etching is performed to ensure an even separation distance.

[0358] Furthermore, in order to realize high-performance power semiconductor devices, as multiple SiC power semiconductors are mounted on a heat dissipation substrate, complex circuit patterns are required, and if the separation distance between the circuit patterns is wider than required, it is difficult to realize a high-density power semiconductor module.

[0359] Therefore, the inventors of the present application can control the thickness of the metal plate on the side of the heat dissipation substrate on which the circuit pattern is formed to be different from the thickness of the metal plate on the other side.

[0360] According to the embodiment, the thicknesses of insulating substrates and metal plates delivered in various thicknesses can be precisely measured and managed, and each of these thickness information can be matched with the product specifications required by each customer by perfectly updating it through the unique information UC.

[0361] For example, since a specific unique code UC is marked on the upper side of the insulating substrate, during the lamination process, the upper side marked with the unique code UC can be managed as the upper side of the insulating substrate.

[0362] Therefore, the unique code UC can serve as an alignment function for distinguishing the upper side from the lower side and the product history of each insulating substrate during the lamination process.There is a special technical effect that the hot pressing process can be controlled by laminating metal plates with an optimal thickness combination.

[0363] For example, refer to Fig. 20 The second stacking group ST2, which will become the heat dissipation substrate 410B of the second embodiment, may include a first metal plate MP1 with a first thickness T1 stacked on the first side of the first insulating substrate SS1 facing the predetermined power semiconductor device 100, and a second metal plate MP2 with a second thickness T2 stacked on the second side of the first insulating substrate SS1.

[0364] In the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than or equal to the second thickness T2 of the second metal plate MP2. For example, in the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than the second thickness T2 of the second metal plate MP2.

[0365] In an embodiment, the first thickness T1 of the first metal plate MP1 may be within a range of 50% to 100% of the second thickness T2 of the second metal plate MP2. Alternatively, the first thickness T1 of the first metal plate MP1 may be within a range of 60% to 90% of the second thickness T2 of the second metal plate MP2, but is not limited thereto.

[0366] According to the heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor device 100 can be controlled to be thin, and therefore, the first metal plate MP1 bonded to the power semiconductor device 100 can be controlled to be thin. There is a technical effect of providing a high-density power semiconductor module by ensuring a compact separation distance PD between the first circuit patterns CP1 of the plate MP1.

[0367] Next, Fig. 22B This is a manufacturing process diagram of the heat dissipation substrate 410C according to the third embodiment.

[0368] The manufacturing process of the heat dissipation substrate 410C of the third embodiment may adopt the technical features of the heat dissipation substrate 410A of the first embodiment or the heat dissipation substrate 410B of the second embodiment described above, and hereinafter, the description will focus on the technical features referred to as the third embodiment.

[0369] As mentioned above, according to internal research, during transient liquid phase bonding (TLP), when the metal plate material of the heat dissipation substrate is used up to form the IMC, the IMC bonding layer is not properly formed. Therefore, the problem of reduced bonding strength or porosity is studied.

[0370] However, in power semiconductor modules operating at extremely high temperatures, reduced adhesion between the power semiconductor device and the heat dissipation substrate or the presence of voids at the bonding interface may have a significant impact on performance degradation and reliability of the power semiconductor module.

[0371] Therefore, the inventors of the present application can control the thickness of the metal plate on the side of the heat dissipation substrate on which the circuit pattern is formed to be different from the thickness of the metal plate on the other side.

[0372] For example, refer to Fig. 22B The heat dissipation substrate 410C of the third embodiment may include a third metal plate MP3 having a third thickness T3 bonded on a first side of the first insulating substrate SS1 and a second metal plate MP2 having a second thickness T2 bonded on a second surface of the first insulating substrate SS1.

[0373] The power semiconductor device 100 may be bonded to the third metal plate MP3 .

[0374] In the heat dissipation substrate 410C of the third embodiment, the third thickness T3 of the third metal plate MP3 may be greater than or equal to the second thickness T2 of the second metal plate MP2. For example, in the third embodiment, the third thickness T3 of the third metal plate MP3 may exceed the second thickness T2 of the second metal plate MP2.

[0375] In the third embodiment, the third thickness T3 of the third metal plate MP3 may be in the range of 100% to 200% of the second thickness T2 of the second metal plate MP2. Alternatively, the third thickness T3 of the third metal plate MP3 may be in the range of 120% to 150% of the second thickness T2 of the second metal plate MP2, but is not limited thereto.

[0376] According to the heat dissipation substrate 410C of the third embodiment, the third thickness T3 of the third metal plate MP3 facing the power semiconductor device 100 is joined to the second thickness T3, which can be controlled to be equal to or exceed the second thickness T2 of the second metal plate MP2 stacked on the opposite side of the insulating substrate.

[0377] According to the third embodiment, the third thickness T3 of the third metal plate MP3 bonded to the power semiconductor device 100 can be controlled to be thick, and therefore, the third thickness of the circuit pattern can also be controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2. Therefore, during the transient liquid phase bonding of the power semiconductor device 100 and the third metal plate MP3, the problem of exhaustion of the metal plate material of the heat dissipation substrate during the IMC formation process can be prevented. Therefore, there is a special technical effect of improving the bonding strength and solving the problem of pores appearing at the bonding interface.

[0378] Refer again Fig.18 , the automatic lamination and automatic alignment of the insulating substrate and the metal plate can be achieved using the automatic alignment lamination system 800 according to the embodiment.

[0379] Based on the “automatic alignment lamination system 800 ” according to the embodiment, it is possible to perform automatic lamination and thermocompression bonding processes of several tens to more than one hundred sets.

[0380] Specifically, according to an embodiment, the bottom of the stacking unit 850 may have an inclined structure, which has a special technical effect of enabling edges of sequentially stacked spacers, metal plates, and insulating substrates to be accurately and automatically aligned.

[0381] For example, according to an embodiment, there is a special technical effect that vertical alignment accuracy can be innovatively improved by using gravity through tilted stacking.

[0382] As a result, accurate automatic alignment can be performed when performing automatic lamination of tens to more than 100 groups, and alignment can be accurately maintained even during a hot press bonding process with a pressure exceeding tens of tons. Therefore, there is a special technical effect that makes it possible to achieve no deformation of the lamination group and to achieve a high-quality heat dissipation substrate.

[0383] In addition, according to an embodiment, a predetermined unique code UC is marked on one edge of the insulating substrate, so during the lamination process of the insulating substrate, the unique code UC can be arranged to match the bottom edge of the inclined structure of the lamination unit 850 to continue the lamination process.

[0384] Therefore, a special technical effect of the unique code UC is that it can not only serve the product history of each insulating substrate, but also serve the alignment function of the stacking position of the stacking unit 850 during the stacking process.

[0385] According to an embodiment, when the unique code is opened after the hot pressing process for the inspection and history management process of the bonded heat dissipation substrate, the unique code can be opened as the hot pressing process progresses, and the unique code is placed at a specific position, so there is a special technical effect that allows the process to be carried out quickly and accurately.

[0386] According to an embodiment, a stacked group stacked by an automatic alignment stacking system device may be fastened to a predetermined carrier fixture, and by inserting a predetermined guide transfer device into the stacking carrier, the precisely aligned stacked group may be placed into a heat press while maintaining alignment.

[0387] (Hot pressing process)

[0388] Next, we will refer to Figures 21 to 22B A thermocompression bonding process of an embodiment will be described.

[0389] Reference Fig.21 The stacked group placed in a heat pressing device (not shown) may be subjected to a heat pressing process under vacuum so that Fig.22A As shown, a first heat dissipation substrate 410A and a second heat dissipation substrate 410B are manufactured.

[0390] For example, the first stacked group ST1 including the second metal plate MP2 , the second insulating substrate SS2 , and the second metal plate MP2 may be manufactured as the heat dissipation substrate 410A of the first embodiment.

[0391] In addition, the second stacked set ST2 including the first metal plate MP1 , the first insulating substrate SS1 , and the second metal plate MP2 may be manufactured as the heat dissipation substrate 410B of the second embodiment.

[0392] In addition, refer to Fig. 22B , a third stacked set ST3 including the second metal plate MP2 , the first insulating substrate SS1 , and the third metal plate MP3 may be manufactured as the heat dissipation substrate 410C of the third embodiment.

[0393] The temperature of the hot pressing process may be about 900° C. to 1100° C. Preferably, the temperature of the hot pressing process may be about 950° C. to 1000° C., but is not limited thereto.

[0394] The vacuum degree of hot pressing process can be 1.0×10 -1 torr or higher, but not limited thereto. In addition, the pressure of the hot pressing process may be about 10 MPa to about 100 MPa, but not limited thereto.

[0395] (Inspection and etching process of heat dissipation substrate)

[0396] Will refer to Fig.23To describe the inspection process and etching of the heat sink substrate.

[0397] Reference Fig.23 , a cleaning process, an inspection process, and an etching process may be performed on each heat dissipation substrate manufactured through the thermal compression bonding process.

[0398] Fig.23 The heat dissipation substrate 410B of the second embodiment shown may have a structure including a first metal plate MP1, a first insulating substrate SS1, and a second metal plate MP2, but is not limited thereto. For example, a cleaning process may be performed on the heat dissipation substrate 410B of the second embodiment manufactured by the thermocompression bonding process.

[0399] For example, brush cleaning, water washing, and drying processes may be performed on the heat dissipation substrate 410B of the second embodiment, but the processes are not limited thereto.

[0400] In addition, in an embodiment, an ultrasonic inspection of a bonding interface may be performed on a heat dissipation substrate manufactured by a thermal pressing process.

[0401] For example, according to an embodiment, the first bonding interface of each heat dissipating substrate may be inspected for interface thickness, presence of voids, and cracks using an ultrasonic inspection device.

[0402] According to an embodiment, after the thermocompression bonding process, a portion of the metal plate of each heat dissipation substrate in the dummy region may be removed to open the unique code UC formed in the dummy region.

[0403] This has a special technical effect of being able to accurately update and manage inspection information on interface thickness, void presence, and cracks on the bonding interface of a separate heat dissipation substrate after a thermal compression process. Fig.23 , an etching process for forming a circuit pattern may be performed on the heat dissipation substrate determined as a qualified product in the inspection process.

[0404] For example, the first circuit pattern CP1 may be formed on the heat dissipation substrate 410B of the second embodiment on which the heat pressing process has been performed by an etching process. For example, the first circuit pattern CP1 may be formed by partially removing the first metal plate MP1 of the heat dissipation substrate 410B of the second embodiment. The bonding metal layer 411 and the bonding layer 413 on the first insulating substrate SS1 may also be removed.

[0405] The embodiment has the following special technical effect: etching information (etchant, etching process conditions, etc.) for a separate heat dissipation substrate can be accurately updated and managed after the thermal pressing process.

[0406] In addition, refer to Fig.23The heat dissipation substrate 410B of the second embodiment may include a first metal plate MP1 having a first thickness T1 located on a first side of the first insulating substrate SS1 facing a predetermined power semiconductor device 100 and a second metal plate MP2 having a second thickness T2 stacked on a second surface of the first insulating substrate SS1.

[0407] In the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than or equal to the second thickness T2 of the second metal plate MP2. For example, in the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than the second thickness T2 of the second metal plate MP2.

[0408] On the first metal plate MP1 , a first circuit pattern CP1 including a first-first pattern p11 , a first-second pattern p12 , and a first-third pattern p13 may be formed by etching.

[0409] According to the heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor device 100 can be controlled to be thin, and thus there is a technical effect of providing a high-density power semiconductor module by ensuring a compact separation distance between the first circuit patterns CP1 of the plate MP1.

[0410] (Inspection and cutting process)

[0411] Next, we will refer to Figure 24 to Figure 26 To describe the laser scribing process, inspection process, and cutting process for heat dissipation substrates.

[0412] Reference Fig.24 , an etching inspection can be performed on the heat dissipation substrate that has completed the etching process.

[0413] For heat dissipation substrates with good etching tests, a unique code UC can be marked on the metal plate. For example, when a heat dissipation substrate includes 9 snap areas, a unique code UC can be marked on the metal plate without a circuit pattern for each snap (for example, on each snap of the second metal plate MP2).

[0414] Marking of the unique code UC on each segmented area of ​​the second metal plate MP2 may be performed after laser scribing.

[0415] Next, refer to Fig.25 , a laser scribing process and a breaking process may be performed.

[0416] In an embodiment, an inspection process may be performed after the laser scribing process and before the breaking process. The inspection process may include ultrasonic testing (SAT) which uses ultrasonic waves to assist in inspecting voids or cracks at the junction interface.

[0417] In addition, the inspection process after the laser scribing process may include a process of analyzing surface information such as surface roughness, surface pinhole inspection, protrusion inspection, and foreign matter inspection through an automatic appearance inspection process.

[0418] The embodiment has the following special technical effects: secondary bonding interface inspection information and automatic appearance inspection information for a separate heat dissipation substrate can be accurately updated and managed after an etching process.

[0419] Afterwards, if Fig.26 As shown, individual heat dissipation substrates for final qualified products can be manufactured through cutting and separation processes. Fig.26 The first metal plate MP1 of the heat dissipation substrate 410B of the second embodiment shown in FIG. Fig.24 Cases marked with a unique UC code are delivered.

[0420] Therefore, according to an embodiment, it can be confirmed that unique information related to the history of all processes starting from the initial warehousing stage of the product can be perfectly matched with the final product and delivered to the customer, and the customer can also accurately understand and use the product quality and production history through this unique information, or request after-sales service quickly and accurately when necessary.

[0421] Furthermore, simply marking product information on the heat dissipation substrate of the final product cannot perfectly match and manage film formation information such as thickness information of the insulating substrate constituting the product, thickness information of the metal plate, and bonding interface information.

[0422] According to the heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor device 100 can be controlled to be thin, and therefore, the first metal plate MP1 bonded to the power semiconductor device 100 can be controlled to be thin. There is a technical effect of providing a high-density power semiconductor module by ensuring a compact separation distance PD between the first circuit patterns CP1 of the plate MP1.

[0423] According to the third embodiment, the third thickness T3 of the third metal plate MP3 bonded to the power semiconductor device 100 can be controlled to be thick, and therefore, the third thickness of the circuit pattern can also be controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2. Therefore, during the transient liquid phase bonding of the power semiconductor device 100 and the third metal plate MP3, the problem of exhaustion of the metal plate material of the heat dissipation substrate during the IMC formation process can be prevented. Therefore, there is a special technical effect of improving the bonding strength and solving the problem of pores appearing at the bonding interface.

[0424] <Power converter including heat dissipation substrate>

[0425] Fig. 27 is a circuit diagram of a power converter 1000 to which a power semiconductor module according to an embodiment is applied.

[0426] The power converter 1000 according to the embodiment may receive DC power from a battery or a fuel cell and convert the DC power into AC power, and supply the AC power to a predetermined load. For example, the power converter 1000 according to the embodiment may include an inverter that receives DC power from a battery, converts the DC power into three-phase AC power, and supplies the three-phase AC power to the motor M. The motor M may provide power to an electric vehicle, a fuel cell vehicle, etc.

[0427] The power converter 1000 according to the embodiment may include a power semiconductor device 100. The power semiconductor device 100 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

[0428] For example, the power converter 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be embedded in each of the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and each diode may be provided separately.

[0429] The embodiment can convert DC power into AC power by on-off control of a plurality of power semiconductor devices 100a to 100f. For example, the power converter 1000 according to the embodiment turns on the first power semiconductor device 100a and turns off the second power semiconductor device 100b in the first period of one cycle to operate the motor M, so that positive polarity power can be supplied. And negative polarity power can be supplied to the motor M by turning off the first power semiconductor device 100a and turning on the second power semiconductor device 100b in the second period of one cycle.

[0430] In an embodiment, a group of power semiconductor devices arranged in series on the high voltage line and the low voltage line on the input side may be referred to as an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b include a first arm 12a, and the third power semiconductor device 100c and the fourth power semiconductor device 100d include a second arm 12b, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f may include a third arm 12c.

[0431] Fig. 27 The plurality of power semiconductor devices 100 a to 100 f shown may be packaged into one power semiconductor module, or the power semiconductor devices constituting the respective arms may be packaged into one power semiconductor module.

[0432] In the arm portion, the upper power semiconductor device and the lower power semiconductor device may be controlled not to be turned on at the same time. For example, in the first arm portion, the first power semiconductor device 100a and the second power semiconductor device 100b may not be turned on at the same time, but may be turned on and off alternately.

[0433] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, may operate in a high temperature and high voltage environment, and may have a high switching speed and low switching loss.

[0434] According to the implementation method, there is the following technical effect: when manufacturing the heat dissipation substrate, all production and quality information and historical management for each "individual heat dissipation substrate" are accurately matched and updated, including ceramic substrate thickness information, inspection information, copper plate thickness information, surface information, and bonding interface information after the bonding process.

[0435] In addition, according to an embodiment, even if the position or arrangement of the insulating substrate is changed due to an operator's mistake during the manufacturing process, through the application of the embodiment, there is a technical effect of being able to completely update and manage the history of all processes including the initial reception, cleaning steps, and hot pressing of the individual insulating substrate by confirming the unique information of the individual insulating substrate.

[0436] In addition, according to an embodiment, it can be confirmed that unique information related to the history of all processes starting from the initial warehousing stage of the product can be perfectly matched with the final product and delivered to the customer, and the customer can also accurately understand and use the product quality and production history through this unique information, or request after-sales service quickly and accurately when necessary.

[0437] In addition, according to the embodiment, there is a technical effect of minimizing thickness distribution by classifying the separate insulating substrates and metal plates by thickness and matching them by thickness grade.

[0438] Therefore, in the stacking process performed after the sputtering process, there is the following technical effect: by reading the unique IDs of the first to third substrate boxes CM1, CM2 and CM3 and matching the insulating substrate and the metal plate by thickness to perform the stacking and bonding process, the thickness and quality of the heat dissipation substrate can be optimized.

[0439] In addition, in an embodiment, the thickness of the insulating substrate and copper plate delivered in various thicknesses is carefully measured and managed to perfectly manage the thickness information so that it can be matched with each product through unique information, and based on the unique information, the thickness distribution is minimized.

[0440] In addition, the embodiment has a technical effect of providing an automatic alignment lamination device capable of automatically laminating and automatically aligning an insulating substrate and a metal plate.

[0441] Specifically, according to an embodiment, the bottom of the stacking unit 850 may have an inclined structure, which has a special technical effect of enabling the edges of the sequentially stacked spacers, metal plates, and insulating substrates to be accurately and automatically aligned. For example, according to an embodiment, there is a special technical effect of innovatively improving the vertical alignment accuracy by utilizing gravity through inclined stacking.

[0442] As a result, accurate automatic alignment can be performed when performing automatic lamination of dozens to more than 100 groups, and alignment can be accurately maintained even during a hot press bonding process with a pressure exceeding several tens of tons. Therefore, there is a special technical effect that makes it possible to achieve no deformation of the lamination group and to achieve a high-quality heat dissipation substrate.

[0443] Although the present invention has been described above with reference to the embodiments, it will be readily apparent to those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims.

Claims

1. A method for manufacturing a heat dissipation substrate for a power semiconductor module, the method comprising the following steps: preparing an insulating substrate; preparing a first metal plate and a second metal plate; stacking the first metal sheets; laminating the insulating substrate on the first metal plate; laminating a second metal plate on the insulating substrate; as well as performing a hot pressing process on the stacked first metal plate, the insulating substrate, and the second metal plate, and Wherein, a first thickness of the first metal plate is different from a second thickness of the second metal plate.

2. The method according to claim 1, wherein: The first thickness of the first metal plate is thinner than the second thickness of the second metal plate.

3. The method according to claim 1, wherein: The first metal plate includes a circuit pattern electrically connected to a predetermined power semiconductor device, Wherein, the second metal plate includes a marked first unique code.

4. The method according to claim 1, wherein: The first thickness of the first metal plate is thicker than the second thickness of the second metal plate.

5. The method according to claim 1, wherein: The steps of preparing the insulating substrate include: preparing an insulating substrate including an active area and a dummy area disposed outside the active area; and A second unique code is marked in the dummy area.

6. The method according to claim 5, wherein: The step of preparing the insulating substrate comprises: cleaning the insulating substrate; and measuring the thickness of the cleaned insulating substrate. wherein the second unique code is stored in a predetermined central server, and Wherein, the second unique code includes thickness information of the insulating substrate.

7. The method according to claim 5, wherein: The second unique code comprises a rectangular shape or a square shape, and wherein a vertex of the second unique code and a vertex of the valid area are arranged to face each other.

8. The method according to claim 5, wherein: the second unique code comprises a rectangular shape or a square shape, The minimum distance between the unique code and the effective area of ​​the insulating substrate corresponds to the distance between the vertex of the unique code and the vertex of the effective area.

9. The method according to claim 5, wherein: The second unique code comprises a rectangular shape or a square shape, and Wherein, the edge of the second unique code is arranged to face the vertex of the valid area closest to the unique code.

10. A method for manufacturing a power semiconductor module, the method comprising the following steps: Arrangement of power semiconductor devices; as well as bonding a first heat dissipation substrate and a second heat dissipation substrate to the lower side and the upper side of the power semiconductor device, respectively; Wherein, the method of manufacturing the first heat dissipation substrate or the second heat dissipation substrate includes the method according to any one of claims 1 to 9.

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