Semiconductor structure and preparation method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a preparation method of the semiconductor structure. A preparation method of a semiconductor structure comprises the steps that a substrate is provided, and the substrate comprises a substrate, a barrier layer and a dielectric layer which are arranged in sequence; the substrate is provided with a groove region; etching the trench region of the dielectric layer by using a first mixed gas, wherein the etching depth is smaller than the thickness of the dielectric layer; the etching gas in the first mixed gas is C4F8 and CH2F2. The etching gas in the first mixed gas is C4F8 and CH2F2, and the carbon content of the first mixed gas is high, so that the lateral etching degree can be reduced in the process of etching the dielectric layer, the dielectric layer can select a dielectric layer material with a lower K value, and the response speed of the device is improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and specifically to a semiconductor structure and a method for preparing the semiconductor structure. Background Art

[0002] As the size of integrated circuit nodes decreases, the RC (resistance-capacitance) coupling parasitic effect caused by metal interconnection increases rapidly, reducing the response speed of the device. Reducing RC can be achieved by reducing impedance and capacitive reactance. Among them, capacitive reactance is mainly related to the k value (dielectric constant) of the dielectric layer material. The lower the k value, the higher the response speed of the device.

[0003] However, at the 90nm process node, the dielectric layer is thicker, and the k value of the dielectric layer material used in similar products is only as low as 4. If a dielectric layer material with a lower k value is selected, lateral etching is severe during the process of etching to form the groove, and a bowl-shaped morphology is easily formed. Summary of the invention

[0004] Multiple embodiments of the present application provide a semiconductor structure and a method for preparing the semiconductor structure with reduced lateral etching.

[0005] On the one hand, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising:

[0006] Providing a substrate, the substrate comprising a substrate, a barrier layer and a dielectric layer arranged in sequence; the substrate having a groove region;

[0007] A first mixed gas is used to etch the groove region of the dielectric layer, and the etching depth is less than the thickness of the dielectric layer; the etching gas in the first mixed gas is C4F8 and CH2F2.

[0008] In some embodiments, in the first mixed gas, the gas flow rate of C4F8 falls within the range of 11 sccm to 17 sccm; the gas flow rate of CH2F2 falls within the range of 9 sccm to 15 sccm.

[0009] In some embodiments, when the first mixed gas is used to etch the groove region of the dielectric layer, the sum of the high frequency power and the low frequency power is less than 1000W, the high frequency power is in the range of 200W-400W, and the low frequency power is in the range of 600W-800W.

[0010] In some embodiments, in the step of etching the trench region of the dielectric layer using the first mixed gas, the etching depth is 60% to 70% of the thickness of the dielectric layer.

[0011] In some embodiments, the method further comprises:

[0012] After the step of etching the groove area of ​​the dielectric layer using the first mixed gas, the groove area of ​​the dielectric layer is etched using the second mixed gas until the dielectric layer is penetrated; the etching gas in the second mixed gas is C4F8.

[0013] In some embodiments, in the second mixed gas, the gas flow rate of C4F8 falls within the range of 11 sccm to 17 sccm.

[0014] In some embodiments, the substrate further comprises a dielectric isolation layer disposed on a side of the dielectric layer away from the barrier layer; and the method further comprises:

[0015] Before the step of etching the trench region of the dielectric layer using the first mixed gas, the trench region of the dielectric isolation layer is etched using a third mixed gas to expose the trench region of the dielectric layer; the etching gas in the third mixed gas is CHF3 and CF4.

[0016] In some embodiments, in the third mixed gas, the gas flow rate of CHF3 falls within the range of 180 sccm to 240 sccm, and the gas flow rate of CF4 falls within the range of 60 sccm to 100 sccm.

[0017] In some embodiments, the dielectric constant of the dielectric layer is less than 3; the thickness of the dielectric layer is within within the range.

[0018] In some embodiments, the dielectric layer is a BD layer.

[0019] On the other hand, an embodiment of the present application provides a semiconductor structure, which is prepared by the method provided by the present application, and the semiconductor structure includes:

[0020] substrate;

[0021] a barrier layer disposed on the substrate layer; and

[0022] The dielectric layer is disposed on a surface of the barrier layer away from the substrate.

[0023] In multiple implementations provided by the present application, the etching gases in the first mixed gas are C4F8 and CH2F2, which have a higher carbon content. During the etching process of the dielectric layer, the degree of lateral etching can be reduced, so that the dielectric layer material with a lower K value can be selected to improve the response speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1a A flowchart of a method for preparing a semiconductor structure is provided for one embodiment of the present application.

[0025] Figure 1b-Figure 1c for Figure 1aSchematic diagram of the cross-sectional structure of the structure obtained in each step of the method.

[0026] Figure 2a A flowchart of a method for preparing a semiconductor structure is provided for one embodiment of the present application.

[0027] Figure 2b-2d for Figure 2a Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method.

[0028] Figure 3a A flowchart of a method for preparing a semiconductor structure is provided for one embodiment of the present application.

[0029] Figure 3b-3f for Figure 3a Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method.

[0030] Figure 4a A flowchart of a method for preparing a semiconductor structure is provided for one embodiment of the present application.

[0031] Figure 4b-4d for Figure 4a Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method.

[0032] Figure 5 A schematic diagram of the cross-sectional structure of a semiconductor structure provided in one embodiment of the present application.

[0033] Description of Reference Numerals

[0034] 100. base; 110. substrate; 120. barrier layer; 130. dielectric layer; 140. dielectric isolation layer; 150. amorphous carbon layer; 160. anti-reflection layer; 101. groove region; 102. groove; 200 / 300 / 400 / 500. method for preparing semiconductor structure; 600. semiconductor structure. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0036] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0037] After research, researchers found that in the process of preparing semiconductor structures and in the process of etching grooves, the higher the carbon content, the lower the degree of lateral etching.

[0038] Based on this, the researchers proposed a method for preparing a semiconductor structure, including etching the groove area of ​​the dielectric layer using a first mixed gas; the etching gas in the first mixed gas is C4F8 and CH2F2. The higher the carbon content in the first mixed gas, the lower the degree of lateral etching. Therefore, at the 90nm process node and when the dielectric layer is thick, the dielectric layer material with a lower K value can also be selected to improve the response speed of the device.

[0039] See also Figure 1a to Figure 1c , a method 100 for preparing a semiconductor structure provided in an embodiment of the present application includes:

[0040] S01, providing a substrate 100, the substrate 100 comprising a substrate 110, a barrier layer 120 and a dielectric layer 130 arranged in sequence, see Figure 1b ;

[0041] S02, using the first mixed gas to etch the trench region 101 of the dielectric layer 130, and the etching depth is less than the thickness of the dielectric layer 130, see Figure 1c ; The etching gas in the first mixed gas is C4F8 and CH2F2.

[0042] In the method 100 for preparing the semiconductor structure, the etching gas in the first mixed gas is C4F8 and CH2F2, which has a high carbon content and can reduce the degree of lateral etching during the etching of the dielectric layer 130. Therefore, even at the 90nm process node, the dielectric layer 130 is thicker, and the dielectric layer 130 can also select a dielectric layer 130 material with a lower K value to improve the response speed of the device.

[0043] It can be understood that in step S02 , the etching depth is less than the thickness of the dielectric layer 130 , that is, the groove formed in step S02 does not penetrate the dielectric layer 130 .

[0044] The existence of the load effect in step S02 causes uneven etching rates at different locations. Specifically, the load effect refers to the phenomenon that, during the etching process, due to differences in physical properties and environmental conditions in different regions, the etching rates at different locations change under the same process conditions, resulting in different etching depths at different locations. Step S02 reduces the probability of local over-etching and the probability of local lateral etching by controlling the etching depth to be less than the thickness of the dielectric layer 130.

[0045] Specifically, in step S02, the first mixed gas selected has a higher etching rate, which improves the efficiency of semiconductor preparation. Specifically, CH2F2 in the etching gas of the first mixed gas can enhance the etching rate.

[0046] It can be understood that in step S02 , the etching position is the position of the preset etching groove in the semiconductor structure, that is, the preset groove area 101 of the substrate 100 .

[0047] It is understandable that when performing step S02, a dielectric isolation layer 140 and an amorphous carbon layer 150 are further provided on the side of the dielectric layer 130 facing away from the barrier layer 120, and the dielectric isolation layer 140 is located between the amorphous carbon layer 150 and the dielectric layer 130. Before performing step S02, through holes are provided at the positions of the groove regions 101 of the dielectric isolation layer 140 and the amorphous carbon layer 150, and the groove regions 101 of the dielectric layer 130 are exposed, so the dielectric layer 130 can be directly etched in step S02.

[0048] It is understandable that in some other embodiments, through holes may not be provided at the groove regions of the dielectric isolation layer and the amorphous carbon layer. Before step S02, the groove regions of the dielectric isolation layer and the amorphous carbon layer are removed by etching or the like.

[0049] Similarly, in some other embodiments, the side of the dielectric layer away from the barrier layer may not have a dielectric isolation layer and an amorphous carbon layer. The dielectric isolation layer and the amorphous carbon layer may be formed by deposition or the like. The formed dielectric isolation layer and the amorphous carbon layer may cover the groove area or avoid the groove area. If the groove area is covered, a step of removing the material of the corresponding layer in the groove area may be added during the preparation process.

[0050] It should be noted that the substrate 110 may be, but is not limited to, a silicon substrate 110 or a compound material such as silicon, germanium, silicon germanium, etc., such as a doped or undoped single crystal silicon substrate 110, a polycrystalline silicon substrate 110, etc., and the doping type may be N-type doping or P-type doping, etc., which is not specifically limited. Further, the substrate 110 may include a wafer and an electronic device prepared based on the wafer. The electronic device may include one or more of a transistor and a capacitor, which is also not specifically limited.

[0051] In some embodiments, the barrier layer 120 may be, but is not limited to, a silicon nitride layer.

[0052] Optionally, in the first mixed gas, the gas flow rate of C4F8 falls within the range of 11sccm to 17sccm; the gas flow rate of CH2F2 falls within the range of 9sccm to 15sccm. Specifically, in the first mixed gas, the gas flow rate of C4F8 can be any value within the range of 11sccm to 17sccm, such as 11sccm, 12sccm, 13sccm, 14sccm, 15sccm, 16sccm or 17sccm. In the first mixed gas, the gas flow rate of CH2F2 can be any value within the range of 9sccm to 15sccm, such as 9sccm, 10sccm, 11sccm, 12sccm, 13sccm, 14sccm or 15sccm.

[0053] It can be understood that the combination of C4F8 and CH2F2 can increase the etching rate while maintaining a high selectivity and optimize the effect of the etching process.

[0054] In this embodiment, the first mixed gas includes cleaning gas and inert gas in addition to etching gas. The cleaning gas is used to remove reaction residues, such as O2; the inert gas is used to dilute the etching gas to improve the uniformity of the gas and the stability of the etching process, such as N2 and Ar.

[0055] Optionally, when the first mixed gas is used to etch the groove region 101 of the dielectric layer 130, the sum of the high-frequency power and the low-frequency power is less than 1000 W, so as to reduce the energy of the plasma and reduce the risk of plasma damaging the dielectric layer 130. This helps to balance the etching rate and the protection of the underlying material, reduce the risk of plasma damaging the dielectric layer 130, and achieve the desired etching effect at the same time.

[0056] Further, optionally, when the first mixed gas is used to etch the groove area 101 of the dielectric layer 130, the high-frequency power falls within the range of 200W-400W, and the low-frequency power falls within the range of 600W-800W. The high-frequency power falls within the range of 200W-400W, which can effectively excite the etching gas and increase the reaction rate; it also helps to reduce the impact force of the plasma and reduce damage to the material of the dielectric layer 130. The low-frequency power falls within the range of 600W-800W, providing stable energy, helping to control the etching rate and ensure uniform reaction in the entire etching area; it can also provide a softer etching environment, help protect the underlying structure; it can also help control the accumulation of reaction products, reduce the risk of redeposition and contamination, and ensure the cleanliness of the etching area.

[0057] The high-frequency power is in the range of 200W-400W, and the low-frequency power is in the range of 600W-800W, which can enhance the uniformity of gas flow and plasma, ensure the uniformity of the etching process in different areas, reduce the impact of the load effect, help form a regular groove shape and consistent etching depth, and improve the performance and reliability of the device.

[0058] Optionally, in the step of etching the trench region 101 of the dielectric layer 130 using the first mixed gas, the etching depth is 60% to 70% of the thickness of the dielectric layer 130. Specifically, the etching depth can be 60%, 62%, 64%, 65%, 67%, 69% or 70% of the thickness of the dielectric layer 130.

[0059] It can be understood that, in this embodiment, the substrate 100 provided in step S01 further includes a dielectric isolation layer 140, an amorphous carbon layer 150 and an anti-reflection layer 160 which are sequentially arranged on the side of the dielectric layer 130 away from the barrier layer 120. Through holes are arranged at the trench regions of the dielectric isolation layer 140, the amorphous carbon layer 150 and the anti-reflection layer 160; the trench region 101 of the dielectric layer 130 is exposed.

[0060] It is understandable that in step S02, while etching the groove area 101 of the dielectric layer 130, the anti-reflection layer 160 and part of the amorphous carbon layer 150 outside the groove area 101 are also removed, that is, the anti-reflection layer 160 is removed and the thickness of the amorphous carbon layer 150 is reduced.

[0061] Optionally, the K value of the dielectric layer 130 is less than 3.5, for example, 3.5, 3.4, 3.3, 3.2, 3.1, 3, 2.9, 2.8, 2.7, 2.6 or 2.5. Further optionally, the K value of the dielectric layer 130 is less than 3. Specifically, the dielectric layer 130 may be, but is not limited to, a BD (black diamond) layer.

[0062] Optionally, the thickness of the dielectric layer 130 falls within Specifically, the thickness of the dielectric layer 130 may be Any value in the range, such as or

[0063] Optionally, the dielectric isolation layer 140 is a silicon oxide film layer, which has excellent electrical insulation performance and chemical stability. Further optionally, the dielectric isolation layer 140 is a SiO2 film formed by TEOS (tetraethyl orthosilicate) deposition, which has a lower dielectric constant, helps to reduce RC delay and improve device performance.

[0064] It is understandable that the amorphous carbon layer 150 and the anti-reflection layer 160 are film structures formed to cooperate with etching, and can be selected according to the etching process and the characteristics of the material to be etched in the semiconductor structure, and are not limited here.

[0065] See also Figure 2a to Figure 2d Another embodiment of the present application provides a method 300 for preparing a semiconductor structure. Different from the method 200, the method 300 further includes:

[0066] S03, using the second mixed gas to etch the trench region 101 of the dielectric layer 130 until the dielectric layer 130 is penetrated, see Figure 2d The etching gas in the second mixed gas is C4F8. Step S03 is performed after step S02.

[0067] The etching gas in the second mixed gas is C4F8, which has higher selectivity and can eliminate the loading effect in step S02; in addition, the etching of the barrier layer 120 can also be reduced.

[0068] Optionally, in the second mixed gas, the gas flow rate of C4F8 falls within the range of 11 sccm to 17 sccm. The specific gas flow rate of C4F8 can be any value within the range of 11 sccm to 17 sccm, such as 11 sccm, 12 sccm, 13 sccm, 14 sccm, 15 sccm, 16 sccm or 17 sccm.

[0069] Similarly, the second mixed gas contains cleaning gas and inert gas in addition to etching gas. The cleaning gas is used to remove reaction residues, such as O2; the inert gas is used to dilute the etching gas to improve the uniformity of the gas and the stability of the etching process, such as N2 and Ar.

[0070] It is understandable that, in step S03 , during the process of etching the dielectric layer 130 , a portion of the amorphous carbon layer 150 outside the trench region 101 is also removed, that is, the thickness of the amorphous carbon layer 150 is reduced.

[0071] It can be understood that after etching through the dielectric layer 130 in step S03 , the trench region 101 of the barrier layer 120 is exposed, which facilitates the removal of the trench region 101 of the barrier layer 120 in subsequent process steps.

[0072] For step S01 and step S02 in method 300 , refer to the relevant description in method 200 , which will not be elaborated here.

[0073] See also Figure 3a to Figure 3f Another embodiment of the present application provides a method 400 for preparing a semiconductor structure. Different from the method 300, the method 400 further includes:

[0074] S04, etching the groove region 101 of the stop layer 120, until the groove region 101 penetrates the stop layer 120, see Figure 3e ;

[0075] S05, etching to remove the amorphous carbon layer 150, see Figure 3f .

[0076] For step S01 , step S02 , and step S03 in method 400 , refer to the relevant descriptions in method 200 and method 300 , which will not be elaborated here.

[0077] In step S04 , after the trench region 101 of the barrier layer 120 is etched, a trench 102 penetrating the dielectric isolation layer 140 , the dielectric layer 130 and the barrier layer 120 is formed.

[0078] Optionally, step S04 adopts dry etching. Specifically, the operation of step S04 is to etch the groove area 101 of the barrier layer 120 using a fourth mixed gas. The etching gas in the fourth mixed gas is CF4. Optionally, in the fourth mixed gas, the gas flow rate of CF4 falls within the range of 100 sccm to 140 sccm. Specifically, the gas flow rate of CF4 can be any value within the range of 100 sccm to 140 sccm, for example, 100 sccm, 115 sccm, 120 sccm, 125 sccm, 130 sccm, 135 sccm or 140 sccm.

[0079] The fourth mixed gas includes O2, N2 and CO2 in addition to the etching gas. The gas flow rate of O2 is in the range of 4 sccm to 8 sccm, such as 4 sccm, 5 sccm, 6 sccm, 7 sccm or 8 sccm; the gas flow rate of N2 is in the range of 170 sccm to 230 sccm, such as 170 sccm, 180 sccm, 190 sccm, 200 sccm, 210 sccm, 220 sccm or 230 sccm; the gas flow rate of CO2 is in the range of 45 sccm to 65 sccm, such as 45 sccm, 50 sccm, 55 sccm, 60 sccm or 65 sccm.

[0080] It is understandable that, in step S04, during the process of etching the barrier layer 120, a portion of the amorphous carbon layer 150 outside the trench region 101 is also removed, that is, the thickness of the amorphous carbon layer 150 is reduced.

[0081] In some other embodiments, step S04 is not limited to dry etching, or even etching, and the trench region of the barrier layer may be removed.

[0082] Optionally, step S05 adopts dry etching. Specifically, the operation of step S05 is to use a fifth mixed gas to remove the amorphous carbon layer 150. The etching gas in the fifth mixed gas is CO2. The gas flow rate of CO2 falls within the range of 1000sccm to 1400sccm, such as 1000sccm, 1050sccm, 1100sccm, 1150sccm, 1200sccm, 1250sccm, 1300sccm, 1350sccm or 1400sccm.

[0083] In some other embodiments, step S05 is not limited to dry etching, or even etching, and the trench region of the barrier layer may be removed.

[0084] See also Figures 4a to 4d , a method 500 for preparing a semiconductor structure provided in another embodiment of the present application is different from the method 200 in that, in step S01, the substrate 100 further includes a dielectric isolation layer 140 disposed on a side of the dielectric layer 130 away from the barrier layer 120. In other words, the substrate 100 includes a substrate 110, a barrier layer 120, a dielectric layer 130 and a dielectric isolation layer 140 disposed in sequence, see Figure 4b The method 500 further includes:

[0085] S0a, using a third mixed gas to etch the trench region 101 of the dielectric isolation layer 140, so that the trench region 101 of the dielectric layer 130 is exposed, see Figure 4c The etching gas in the third mixed gas is CHF3 and CF4. Step S0a is performed after step S01 and before step S02.

[0086] CHF3 and CF4 have good selectivity for the dielectric isolation layer 140 and have less impact on the dielectric layer 130, which helps to reduce damage to the dielectric layer 130 during the etching process. In addition, CHF3 and CF4 have strong etching ability for the dielectric isolation layer 140, improve the etching efficiency of the dielectric isolation layer 140, and improve the preparation efficiency of the semiconductor structure.

[0087] Optionally, in this embodiment, step S0a over-etches the dielectric isolation layer 140 , that is, step S0a also etches the trench region 101 of the dielectric layer 130 to a certain extent, so that the dielectric layer 130 is fully exposed to facilitate the execution of step S02 .

[0088] Optionally, in the third mixed gas, the gas flow rate of CHF3 falls within the range of 180sccm to 240sccm, and the gas flow rate of CF4 falls within the range of 60sccm to 100sccm. Specifically, in the third mixed gas, the gas flow rate of CHF3 can be any value within the range of 180sccm to 240sccm, such as 180sccm, 185sccm, 190sccm, 195sccm, 200sccm, 205sccm, 210sccm, 215sccm, 220sccm, 225sccm, 230sccm, 235sccm or 240sccm. In the third mixed gas, the gas flow rate of CF4 can be any value within the range of 60sccm to 100sccm, such as 60sccm, 65sccm, 70sccm, 75sccm, 80sccm, 85sccm, 90sccm, 95sccm or 100sccm.

[0089] It is understood that the substrate 100 provided in step S01 further includes an amorphous carbon layer 150 and an anti-reflection layer 160 which are sequentially disposed on the side of the dielectric isolation layer 140 away from the dielectric layer 130. The groove regions of the amorphous carbon layer 150 and the anti-reflection layer 160 are removed; the groove region 101 of the dielectric isolation layer 140 is exposed.

[0090] It is understandable that in some other embodiments, through holes may not be set at the groove areas of the amorphous carbon layer and the anti-reflection layer. Before step S0a, the groove areas of the amorphous carbon layer and the anti-reflection layer are removed by etching or the like.

[0091] Similarly, in some other embodiments, the side of the dielectric isolation layer facing away from the dielectric layer may not have an amorphous carbon layer and an anti-reflection layer. The amorphous carbon layer and the anti-reflection layer may be formed by deposition or other methods.

[0092] It can be understood that during the execution of step S0a, the anti-reflection layer 160 is also partially etched, that is, the thickness of the anti-reflection layer 160 is reduced.

[0093] Of course, in some other embodiments, the method for preparing the semiconductor structure further includes the step of etching the groove region 101 of the amorphous carbon layer 150 and the groove region 101 of the anti-reflection layer 160, which can be performed in a conventional manner in the art and is not limited thereto.

[0094] An embodiment of the present application further provides a semiconductor structure 600, comprising a substrate 110, a barrier layer 120 and a dielectric layer 130. The barrier layer 120 is disposed on the substrate 110; the dielectric layer 130 is disposed on the surface of the barrier layer 120 away from the substrate 110. The semiconductor structure 600 is prepared by the method provided in the present application.

[0095] During the preparation of the above-mentioned semiconductor structure 600, the etching gases in the first mixed gas are C4F8 and CH2F2, which have a higher carbon content. During the etching process of the dielectric layer 130, the degree of lateral etching can be reduced, so that the dielectric layer 130 can select a dielectric layer 130 material with a lower K value to improve the response speed of the device.

[0096] It can be understood that the embodiments in the present application are only intended to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of protection of the present application.

[0097] It can be understood that in the various embodiments of the present application, the size of the serial number of each step does not mean the order of execution. The execution order of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0098] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0099] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. Further, the terms "upper", "lower", etc. used in this application are only used to express the relative positional relationship between features in conjunction with the accompanying drawings, and do not constitute the necessary limitation of the product form when located in the real world.

[0100] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a substrate, the substrate comprising a substrate, a barrier layer and a dielectric layer arranged in sequence; the substrate having a groove region; A first mixed gas is used to etch the groove region of the dielectric layer, and the etching depth is less than the thickness of the dielectric layer; the etching gas in the first mixed gas is C4F8 and CH2F2.

2. The method according to claim 1, characterized in that In the first mixed gas, the gas flow rate of C4F8 falls within the range of 11 sccm to 17 sccm; the gas flow rate of CH2F2 falls within the range of 9 sccm to 15 sccm.

3. The method according to claim 2, characterized in that When the first mixed gas is used to etch the groove region of the dielectric layer, the sum of the high frequency power and the low frequency power is less than 1000W, the high frequency power is in the range of 200W-400W, and the low frequency power is in the range of 600W-800W.

4. The method according to claim 2, characterized in that: In the step of etching the trench region of the dielectric layer using the first mixed gas, the etching depth is 60% to 70% of the thickness of the dielectric layer.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: After the step of etching the groove area of ​​the dielectric layer using the first mixed gas, the groove area of ​​the dielectric layer is etched using the second mixed gas until the dielectric layer is penetrated; the etching gas in the second mixed gas is C4F8.

6. The method according to claim 5, characterized in that In the second mixed gas, the gas flow rate of C4F8 falls within the range of 11 sccm to 17 sccm.

7. The method according to any one of claims 1 to 4, characterized in that: The substrate further comprises a dielectric isolation layer disposed on a side of the dielectric layer away from the barrier layer; the method further comprises: Before the step of etching the trench region of the dielectric layer using the first mixed gas, the trench region of the dielectric isolation layer is etched using a third mixed gas to expose the trench region of the dielectric layer; the etching gas in the third mixed gas is CHF3 and CF4.

8. The method according to claim 7, characterized in that In the third mixed gas, the gas flow rate of CHF3 falls within the range of 180 sccm to 240 sccm, and the gas flow rate of CF4 falls within the range of 60 sccm to 100 sccm.

9. The method according to any one of claims 1 to 4, characterized in that: The dielectric constant of the dielectric layer is less than 3; the thickness of the dielectric layer falls within within the range.

10. The method according to claim 9, characterized in that The medium layer is a BD layer.

11. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method according to any one of claims 1 to 10, and the semiconductor structure comprises: substrate; a barrier layer disposed on the substrate layer; and The dielectric layer is disposed on a surface of the barrier layer away from the substrate.

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