Heat dissipation type SIP (Session Initiation Protocol) mixed packaging piece capable of improving signal transmission speed and reliability and processing method

Abstract

The invention discloses a heat dissipation type SIP mixed packaging piece capable of improving signal transmission speed and reliability and a processing method, and belongs to the technical field of SIP packaging, a substrate and a plurality of chips are arranged on a lead frame, circuit wiring is arranged in the substrate, the substrate and the chips are arranged on the lead frame in a horizontal interval mode or in the vertical direction, and the chips are arranged on the lead frame in the horizontal interval mode or in the vertical direction. The chips are electrically connected, and the substrate is electrically connected with all the chips; and the packaging material wraps the outer sides of the substrate and the chip to form the SIP mixed packaging piece. According to the invention, the problems of signal transmission delay, power consumption increase and insufficient heat dissipation performance and reliability of the current SIP hybrid package are solved; the method is simple and efficient, a more efficient and more reliable packaging piece can be obtained, and the packaging requirements of high integration level, high performance, low cost and high reliability can be met.

Description

Technical Field

[0001] The invention belongs to the technical field of SIP packaging, and in particular relates to a heat dissipation type SIP hybrid packaging component and a processing method thereof for improving signal transmission speed and reliability. Background Art

[0002] With the continuous development of electronic products, traditional packaging technologies mainly include surface mount (SMT) technology and plug-in packaging technology. SMT technology is to directly solder components on the printed circuit board (PCB), which has the advantages of high integration and high reliability, but for electronic products with high requirements for flexibility and plasticity, SMT technology has certain limitations. Plug-in packaging technology is to insert components into slots on the PCB, which has better maintainability and flexibility, but for highly integrated and miniaturized electronic products, plug-in packaging technology is not very suitable.

[0003] As the requirements for integration and performance become higher and higher, traditional packaging technology can no longer meet these requirements. As a new packaging technology, SIP (System in Package) technology integrates multiple chips and devices in one package to improve integration and performance. Therefore, a new packaging structure and processing method are produced to obtain a package with excellent performance.

[0004] Currently, SIP hybrid packages mainly have the following two problems. First, the connection parts in this type of package sometimes cause signal transmission delays and increased power consumption. These are strongly related to chip design, and some cannot be overcome from the packaging technology. Second, the heat dissipation performance and reliability of this type of package are also insufficient. Choosing high heat dissipation and high reliability materials may not necessarily solve the problem, and may also increase costs. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a heat dissipation type SIP hybrid package and a processing method for improving signal transmission speed and reliability, so as to solve the problems of signal transmission delay, increased power consumption, and insufficient heat dissipation performance and reliability of the current SIP hybrid package; the present invention is simple and efficient, and can obtain a more efficient and reliable package, which can meet the packaging requirements of high integration, high performance, low cost and high reliability.

[0006] The present invention is achieved through the following technical solutions: A heat dissipation type SIP hybrid package for improving signal transmission speed and reliability, comprising a lead frame and a packaging material; A substrate and a plurality of chips are arranged on the lead frame, circuit wiring is arranged in the substrate, the substrate and the chips are arranged on the lead frame in a horizontally spaced manner or in a vertical direction, the chips are electrically connected, and the substrate and all the chips are electrically connected; The packaging material is wrapped around the outside of the substrate and the chip to form the SIP hybrid package.

[0007] A further improvement of the present invention is: When the substrate and the chip are arranged on the lead frame in a horizontally spaced manner, a hollow structure is provided at a portion of the lead frame in the length direction and at a corresponding position on the back side of the substrate, and a plurality of chips are fixed at intervals on another portion of the lead frame in the length direction, the substrate is electrically connected to the inner pin, and the chip is electrically connected to the inner pin and the inner pin of the lead frame.

[0008] When the substrate and the chip are arranged on the lead frame in the vertical direction, the lead frame is a hollow structure to form several interconnected carrier areas, the substrate is fixed on the carrier area, the substrate is covered with a PI film, and several chips distributed at intervals are fixed on the PI film. The substrate is electrically connected to the inner pins, and the chip is electrically connected to the inner pins.

[0009] When the substrate is an HDI board and there are three chips, the lead frame is rectangular, and hollow structures are provided on both sides and inside of the lead frame in the width direction to form a first frame and a second frame of the same shape arranged at intervals, and the first frame includes a first carrier area, a second carrier area and a third carrier area, the first carrier area is a rectangular plate, and a corner located on the upper outer side extends outward to form a first lead frame inner foot, and a first glue locking hole is provided at the junction of the first lead frame inner foot and the first carrier area, the third carrier area is a right-angled trapezoid, and the shape of the second carrier area is a rectangle with a right-angled triangle notch on one side close to the third carrier area, and the bottom extends outward on one side along the width direction. A first rectangular carrier forms an integral structure with the third carrier region, a second rectangular carrier with the same width as the first rectangular carrier extending outward from the other side, and forming an integral structure with the first carrier region, a carrier support rib extending from the outside of the first rectangular carrier close to the third carrier region, an inner foot separated from the third carrier region is arranged on the outside of the carrier support rib, an inner foot is arranged between the carrier support rib and the inner foot of the first lead frame, the fourth carrier region in the second frame corresponds to the first carrier region, the fifth carrier region corresponds to the second carrier region, the sixth carrier region corresponds to the third carrier region, the inner foot of the second lead frame corresponds to the inner foot of the first lead frame, and the second glue locking hole corresponds to the first glue locking hole; A first chip and a second chip are bonded to the first carrier region, which are spaced apart from each other. A third chip is bonded to the fourth carrier region. A substrate is bonded to the second carrier region, the third carrier region, the fifth carrier region and the sixth carrier region.

[0010] The length of the outer side of the third carrier region is 2 to 3 times the length of the inner side, and the length value of the third carrier region, the length value of the second carrier region and the width value of the first carrier region increase in sequence.

[0011] The edges of the second carrier region and the third carrier region are etched with steps to form a first carrier step and a second carrier step respectively, and the edges of the fifth carrier region and the sixth carrier region are etched with steps to form a third carrier step and a fourth carrier step respectively, and the depth of all steps is half of the thickness of the lead frame.

[0012] When the substrate is a rigid substrate and there are 4 chips, the lead frame includes a carrier region 1, a carrier region 2 and a carrier region 3, all of which have rectangular main structures. The area of ​​the rectangular plate-shaped carrier region 1 is larger than that of the carrier region 2 and the carrier region 3. The carrier region 1 is provided with a glue locking hole 1 near both sides in the length direction. The carrier region 2 and the carrier region 3 have the same shape and size, are symmetrical in the horizontal direction and are spaced apart on one side of the carrier region 1. The carrier region 2 and the carrier region 3 are respectively integrated with the carrier region 1 through the rectangular plate. The center of the gap between the carrier region 2 and the carrier region 3 coincides with the center line of the carrier region 1 in the length direction. The carrier region 2 and the carrier region 3 are provided with a glue locking hole 2 along the length direction. The other side of the carrier region 1 is provided with a first inner pin and a second inner pin. The substrate is fixed on carrier area 1, carrier area 2 and carrier area 3, the PI film covers the substrate, and chip 1 and chip 2 are bonded to the lower position of the PI film so that they are flush and relatively positioned. Parts of chip 1 and chip 2 are respectively located directly above the corresponding rectangular plates, and chip 3 and chip 4 are bonded to the upper position of the PI film so that they are flush and spaced apart.

[0013] The substrate is a glass fiber board or a ceramic substrate.

[0014] A method for processing a heat dissipation type SIP hybrid package for improving signal transmission speed and reliability as described in any one of the above, comprising the following steps: S1, bonding the back side of the substrate to the hollow part of the lead frame; S2, fixing all chips on another part of the lead frame according to their positions, electrically connecting the chips to each other, electrically connecting the substrate to all the chips, electrically connecting the substrate to the inner pins, and electrically connecting the chips to the inner pins and the inner pins of the lead frame; S3, using packaging materials to package the chip and the substrate to complete the processing of the SIP hybrid package.

[0015] A method for processing a heat dissipation type SIP hybrid package for improving signal transmission speed and reliability as described in any one of the above items, characterized by comprising the following steps: S1, fixing the substrate on the carrier area of ​​the lead frame; S2, covering the substrate with a PI film, fixing a number of spaced chips on the PI film, electrically connecting the chips to each other, the substrate to all the chips, the substrate to the inner pins, and the chips to the inner pins; S3, using packaging materials to package the chip and the substrate to complete the processing of the SIP hybrid package.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a heat dissipation type SIP hybrid package that improves signal transmission speed and reliability. By using packaging materials to fill chips and substrates, all chips and substrates are electrically connected in a horizontally spaced or vertically arranged manner through packaging technology, thereby shortening the signal transmission path, reducing signal transmission delay, and reducing power consumption. The substrate and the chip are arranged horizontally or vertically on the lead frame, which improves the heat dissipation performance; the packaging material wraps the substrate and the chip, so it is filled in the cavity of the entire package colloid part, which can protect the substrate and the chip to form an integral package. The packaging material can provide mechanical support and enhance the reliability of the SIP hybrid package. The present invention can use a SIP hybrid package obtained by simple and efficient operation, which can reduce manufacturing costs, improve production efficiency, effectively improve the electrical performance and heat dissipation performance of the SIP hybrid package, and reduce the packaging cost at the same time. The SIP hybrid package can be applied to various electronic products, especially those with high rigidity and flexibility requirements, to achieve high integration, high performance, low cost and high reliability packaging requirements.

[0017] The present invention provides a processing method for a heat dissipation type SIP hybrid package for improving signal transmission speed and reliability. When a substrate and a chip are arranged on a lead frame in a horizontally spaced manner, a space concession design for a coil on the back side of the substrate can realize overall packaging. Therefore, the back side of the substrate is bonded to a hollowed-out part of the lead frame, and then all chips are fixed on another part of the lead frame according to their positions. The chips are electrically connected to each other, the substrate is electrically connected to all the chips, the substrate is electrically connected to inner pins, the chip is electrically connected to inner pins and inner pins of the lead frame, and then the chip and the substrate are wrapped with packaging materials. The processing of the SIP hybrid package can be completed, and the integration of the package can be effectively improved, so that multiple chips can work simultaneously in one package.

[0018] The present invention provides a processing method of a heat dissipation type SIP hybrid package that improves signal transmission speed and reliability. When the substrate and the chip are arranged on the lead frame in the vertical direction, a PI film is also included. The PI film is adopted in the SIP package because of its high temperature stability, mechanical strength, low dielectric constant and low dielectric loss and good chemical stability, which can meet the requirements of the SIP package for material performance. The substrate is fixed on the carrier area of ​​the lead frame, and then the PI film is covered on the substrate, and a number of spaced chips are fixed on the PI film, and the chips are electrically connected, the substrate and all the chips are electrically connected, the substrate is electrically connected to the inner pins, and the chip is electrically connected to the inner pins. Finally, the chip and the substrate are wrapped with a packaging material, and the processing of the SIP hybrid package can be completed, which can effectively improve the integration of the package, so that multiple chips can work simultaneously in one package, and a SIP hybrid package with high integration, high performance, low cost and high reliability can be obtained. The package is suitable for electronic products with high requirements on size and weight, such as mobile devices and wireless communication equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the lead frame structure arrangement of the SIP hybrid package described in Example 1 of the present invention.

[0020] Figure 2 for Figure 1 Schematic diagram of the lead frame unit structure.

[0021] Figure 3 This is a wiring diagram of the SIP hybrid package described in Example 1 of the present invention.

[0022] Figure 4 This is a schematic diagram of the lead frame unit structure of the SIP hybrid package described in Example 2 of the present invention.

[0023] Figure 5 This is a wiring diagram of the SIP hybrid package described in Example 2 of the present invention.

[0024] In the figure: 1 is a lead frame, A1 is an inner foot, A2 is a carrier support rib, A3 is a first carrier region, A4 is a second carrier region, A5 is a third carrier region, A6 is a first carrier step, A7 is a second carrier step, A8 is a lead frame inner foot connected to the first carrier region, A9 is a first glue locking hole, A10 is a fourth carrier region, A11 is a fifth carrier region, A12 is a sixth carrier region, A13 is a third carrier step, A14 is a fourth carrier step, A15 is a lead frame inner foot connected to the second carrier region, A16 is a second glue locking hole, H1 is a first substrate, C1 is a first chip, C2 is a second chip, and C3 is a third chip; B1 is carrier area one, B2 is carrier area two, B3 is carrier area three, B4 is glue locking hole one, B5 is glue locking hole two, B6 is connecting rib, B7 is the first inner pin, B8 is the second inner pin, U1 is chip one, U2 is chip two, U3 is chip three, U3 is chip four, H2 is the second substrate, and M is PI film. DETAILED DESCRIPTION

[0025] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The present invention provides a heat dissipation type SIP hybrid package for improving signal transmission speed and reliability, comprising a lead frame, a packaging material, and a substrate and a chip bonded to the lead frame, wherein circuit wiring is arranged in the substrate. In addition to the normal structure, the lead frame needs to be designed according to the following two common situations: Case 1: When the substrate and the chip are arranged on the lead frame in a horizontally spaced manner, a hollow design is made at a corresponding position on the back of the substrate in the length direction of the lead frame according to the specific situation, and multiple chips are fixed at intervals in another part of the length direction of the lead frame. The chips are electrically connected through wires as needed, and a gap is left in the lead frame between two adjacent chips as needed. Finally, the substrate and all the chips are electrically connected as needed. The inner pins and the inner pins of the lead frame are set according to the needs of the connecting wires, the substrate is electrically connected to the inner pins, and the chip is electrically connected to the required inner pins and the inner pins connected to the lead frame (i.e., the inner pins of the lead frame).

[0027] Case 2: When the substrate and chip are arranged on the lead frame in the vertical direction, the lead frame is appropriately hollowed out as needed to form three main carrier areas interconnected, the substrate is fixed to these carrier areas, and then the PI film is covered on the substrate with an adhesive, and then a number of spaced chips are bonded as needed, the chips are electrically connected to each other through wires as needed, and the substrate is connected to all chips through wires, the substrate is connected to the required internal pins through wires, and all chips are connected to the required internal pins through wires.

[0028] The packaging material fills the cavity of the entire package colloid part to protect the substrate, chip and wire and provide mechanical support. The packaging material wraps the substrate and chip to form an integral package.

[0029] For situation 1: The present invention provides a processing method for a heat dissipation type SIP hybrid package that improves signal transmission speed and reliability. First, the back of the substrate is bonded to the hollow part of the lead frame as needed, then all chips are fixed on another part of the lead frame according to their positions, the chips are connected by wires as needed, and the substrate and all chips are electrically connected as needed. Finally, the chip and the substrate are wrapped with packaging materials.

[0030] For situation two: The present invention provides a processing method for a heat-dissipating SIP hybrid package that improves signal transmission speed and reliability. First, a substrate is fixedly glued to a carrier area of ​​a lead frame, and then a PI film is covered on the substrate. A number of spaced chips are glued on the PI film as needed. The chips are electrically connected to each other through wires as needed, and the substrate is connected to all the chips. The substrate is connected to required internal pins through wires, and all the chips are connected to required internal pins through wires. Finally, the chip and the substrate are packaged using packaging materials.

[0031] The present invention is described in detail by the following examples.

[0032] Example 1 like Figure 3 As shown, the heat dissipation type SIP hybrid package of this embodiment for improving signal transmission speed and reliability includes: Figure 2 The lead frame, substrate H1, first chip C1, second chip C2, third chip C3, and packaging materials shown in FIG. Figure 1 for Figure 2 The lead frame unit structure is shown in the figure after being arranged in four rows. Figure 2 Only 6 columns are shown. The various round holes at the upper and lower ends of the entire lead frame 1 play a role in positioning and foolproofing in the integrated circuit package. After the product is plastic-sealed, the lead frame area between adjacent row and column units will be cut off.

[0033] Figure 2The lead frame shown is rectangular, and hollowed-out designs are made on both sides and inside of the width direction as needed, forming a first frame and a second frame arranged at intervals, and the first frame includes a first carrier area A3, a second carrier area A4 and a third carrier area A5. The first carrier area A3 is a solid rectangular plate, and a corner located on the upper side of the outer side extends outward to form an inner leg A8 of the lead frame connected to the first carrier area. The first glue locking hole A9 is provided at the junction of the inner leg A8 of the lead frame connected to the first carrier area and the first carrier area A3. The shape of the third carrier area A5 is a right-angled trapezoid, and the length of the lower base (the side located on the outer side) is 2 to 3 times that of the upper base (the side located on the inner side). The shape of the second carrier area A4 is a rectangle with a right-angled triangular notch on one side close to the third carrier area A5, and a rectangular carrier (denoted as S1 but not marked in the figure for the convenience of subsequent description) extends outward from one side of its bottom along the width direction to form an integral structure with the third carrier area A5, and a rectangular carrier with the same width as the rectangular carrier S1 extends outward from the other side to form an integral structure with the first carrier area A3.

[0034] The length value of the third carrier area A5, the length value of the second carrier area A4, and the width value of the first carrier area A3 increase in sequence. A carrier support rib A2 is provided on the rectangular carrier S1 near the outer side of the third carrier area A5. Two inner pins A1 separated from the third carrier area A5 are provided on the outer side of the carrier support rib A2, and five inner pins A1 separated from the second carrier area A4 and the first carrier area A3 are provided in sequence between the carrier support rib A2 and the inner pin A8 of the lead frame connected to the first carrier area. All the inner pins A1 are T-shaped, with their narrow parts facing outwards, and do not contact each other. The second frame has the same shape as the first frame, the fourth carrier area A10 in the second frame corresponds to the first carrier area A3, the fifth carrier area 11 corresponds to the second carrier area A4, the sixth carrier area A12 corresponds to the third carrier area A5, the lead frame inner foot A15 connected to the second carrier area corresponds to the lead frame inner foot A8 connected to the first carrier area, the second glue locking hole A16 corresponds to the first glue locking hole A9, but the second frame needs to adjust the size values ​​of each carrier area as needed, wherein the outer side of the fifth carrier area 11 can also be symmetrical with a right-angled triangle notch, and the specific shape of the lead frame inner foot A15 connected to the second carrier area can also be different from the lead frame inner foot A8 connected to the first carrier area.

[0035] Specifically, steps with a width of 0.3 mm are etched at the edges of the second carrier region A4 and the third carrier region A5 to form the first carrier step A6 and the second carrier step A7, respectively, and the step depth is half the thickness of the lead frame. The same is true for the fifth carrier region A11 and the sixth carrier region A12 to form the third carrier step A13 and the fourth carrier step A14, respectively.

[0036] like Figure 3 In the lead frame structure, silver glue is used to bond the first chip C1 and the second chip C2 which are spaced apart in the first carrier area A3, silver glue is used to bond the third chip C3 in the fourth carrier area A10, and silver glue is used to bond the substrate in the second carrier area A4, the third carrier area A5, the fifth carrier area A11 and the sixth carrier area A12, which may also be an HDI board. Figure 3 The black rectangular block and the waist-round rectangular block in the figure are the circuit diagrams, and the coil is the routing on the back of the substrate. The first chip C1 and the second chip C2 are connected by wires, and the third chip C3 and the second chip C2 are connected by wires. The SIP hybrid package of this embodiment has a total of 3 chips and 1 substrate, and the spacing between the third chip C3 and the second chip C2 is not less than 0.5mm. The substrate can achieve higher line density and smaller size by using fine lines, fine spacing and complex interlayer interconnection technology, thereby providing higher performance and reliability. A coil is provided in the middle area on the back of the substrate. The coil cannot be contacted and bonded with the carrier, so it is necessary to make a hollow design for the lead frame area corresponding to the coil position of the substrate. The hollow area formed by the second carrier area A4, the third carrier area A5, the fifth carrier area A11 and the sixth carrier area A12 can meet the requirements. The gap design between the first carrier area A3 and the fourth carrier area A10 must ensure that the isolation voltage is DC 8000V and ≥0.5mm.

[0037] Silver glue is mainly bonded to the substrate in the second carrier area A4, the third carrier area A5, the fifth carrier area A11 and the sixth carrier area A12. The diffused silver glue can overflow to the first carrier step A6, the second carrier step A7, and the step surfaces of the third carrier step A13 and the fourth carrier step A14, which can effectively prevent the silver glue from being contaminated on the back of the middle area of ​​the substrate, thereby improving product reliability. At the same time, the first carrier step A6, the second carrier step A7, the third carrier step A13 and the fourth carrier step A14 can be filled with plastic packaging material. Since the plastic packaging material will melt into liquid at high temperature, it can be filled as long as there is a gap, which can increase the encapsulation strength of the product. The inner foot A1 and the first lead frame inner foot A8 and the lead frame inner foot A15 connected to the second carrier area are the areas for connecting wires. The substrate is connected to the first chip C1, the second chip C2 and the third chip C3, which can make the surface of the hybrid package smooth and will not shake.

[0038] As a further improvement, in order to ensure the stability of the substrate on the lead frame, two carrier support ribs A2 are added to the lead frame to ensure the substrate is firmly bonded to the lead frame and the stability during the transfer process after bonding. This can solve the deformation of the product during the packaging process and will not cause quality problems. The carrier support rib A2 will be led out of the package body and can be connected to the packaged product and the ribs in the external frame to support the plastic-sealed product. It will then be cut off from the outermost side to avoid shaking of the carrier and ensure the coplanarity of the product.

[0039] Example 2 like Figure 5 As shown, the heat dissipation type SIP hybrid package of this embodiment for improving signal transmission speed and reliability includes: Figure 4 The lead frame, the second substrate H2, the PI film M (polyimide film), the chip one U1, the chip two U2, the chip three U3, the chip four U4, and the packaging materials are shown.

[0040] Figure 4The lead frame structure is designed as a heterogeneous structure, including a carrier region 1 B1, a carrier region 2 B2 and a carrier region 3 B3, all of which are rectangular in main structure. The area of ​​the carrier region 1 B1 is larger than that of the carrier region 2 B2 and the carrier region 3 B3. The carrier region 1 B1 is a rectangular plate, and the upper ends on both sides in the width direction are chamfered. Two spaced-apart glue locking holes 1 B4 are respectively provided near the two sides in the length direction. The carrier region 2 B2 and the carrier region 3 B3 have the same shape and size, are symmetrical in the horizontal direction and are spaced-apart at the other end of the carrier region 1 B1 where the chamfer is provided. The carrier region 2 B2 and the carrier region 3 B3 are both provided with a The rectangular plate (for the convenience of subsequent description, it is marked as K1 and not marked in the figure) forms an integral structure with the carrier area 1 B1. The inner and outer corners of the carrier area 2 B2 and the carrier area 3 B3 are both chamfered. The gap center of the carrier area 2 B2 and the carrier area 3 B3 coincides with the center line of the length direction of the carrier area 1 B1. The corners of the carrier area 2 B2 and the carrier area 3 B3 close to each other are provided with an identical triangular notch, forming an isosceles trapezoidal structure that is narrow outside and wide inside. The carrier area 2 B2 and the carrier area 3 B3 are provided with a number of spaced and evenly distributed circular glue locking holes 2 B5 along the length direction, generally 4. A connecting rib B6 is provided on each side of the length direction of the carrier area 1 B1, which is separated from the carrier area 1 B1, and the inner side is a circular ring and the outer side is rectangular. A plurality of independent first inner pins B7 and two second inner pins B8 distributed on both sides of the first inner pin B7 are arranged on one side of the chamfer of the carrier area B1. The first inner pin B7 and the second inner pin B8 are separated from the carrier area B1. The first inner pin B7 is a cross-shaped structure with a through hole in the center (the end close to the carrier area B1 is wide, and the end away from the carrier area B1 is narrow), and the second inner pin B8 is a crank arm, the lower end of which faces the chamfer of the carrier area B1, and the upper end is provided with a waist-shaped through hole.

[0041] The first inner pin B7 is used for welding the strip wire, and the minimum spacing between the carrier area 2 B2 and the carrier area 3 B3 (ie, the width of the rectangular area outside the isosceles trapezoidal area and connected thereto) is designed to be no less than 0.5 mm. The connecting rib B6 has a supporting function.

[0042] The second substrate H2 of this embodiment is a rigid substrate, such as a glass fiber board or a ceramic substrate. The circuit wiring is connected to the second substrate H2 through a metal layer or a conductive film layer. The chip is fixed to the second substrate H2 by bonding. The packaging material is an organic polymer material. In the processing method, Figure 5As shown, first, use adhesive film to fix the second substrate H2 on the carrier area one B1, the carrier area two B2 and the carrier area three B3, then use adhesive to bond the PI film M on the second substrate H2 to completely cover the second substrate H2, and bond the flush chip one U1 and chip two U2 on the lower position of the PI film M (the positions are relative and the chip one U1 is on the rectangular plate K1 connected to the carrier area two B2, and the chip two U2 is on the rectangular plate K1 connected to the carrier area three B3), and half of the chip one U1 and chip two U2 are located above the isosceles trapezoidal area, and bond the flush and spaced chip three U3 and chip four U4 on the upper position of the PI film M. Because the PI film can withstand high temperatures of more than 400°C and has high insulation, it can meet the needs of insulating the second substrate H2 from chip one U1, chip two U2, chip three U3 and chip four U4. Chip three U3 and chip four U4 are connected by wires, chip one U1 and chip two U2 are connected by wires, the second substrate H2 is connected to chip two U2, chip three U3, and chip four U4 by wires, the second substrate H2 is connected to the second inner pin B8 and the required first inner pin B7 by wires, and chip three U3 and chip four U4 are connected to the required first inner pin B7 by wires. PI film is used in SIP packaging because of its high temperature stability, mechanical strength, low dielectric constant and low dielectric loss, and good chemical stability, which can meet the requirements of SIP packaging for material properties. After fixation, organic polymer materials are used for packaging, which can be applied by injection or coating.

[0043] Through Example 2, a SIP hybrid package with high integration, high performance, low cost and high reliability can be obtained. The package is suitable for electronic products with high requirements on size and weight, such as mobile devices and wireless communication devices. At the same time, due to the use of a rigid substrate and organic polymer materials, the package has good mechanical strength and high temperature resistance.

Claims

1. A heat dissipation type SIP hybrid package for improving signal transmission speed and reliability, characterized in that: Including lead frame and packaging materials; A substrate and a plurality of chips are arranged on the lead frame, circuit wiring is arranged in the substrate, the substrate and the chips are arranged on the lead frame in a horizontally spaced manner or in a vertical direction, the chips are electrically connected, and the substrate and all the chips are electrically connected; The packaging material is wrapped around the outside of the substrate and the chip to form the SIP hybrid package.

2. The heat dissipation type SIP hybrid package for improving signal transmission speed and reliability according to claim 1, characterized in that: When the substrate and the chip are arranged on the lead frame in a horizontally spaced manner, a hollow structure is provided at a portion of the lead frame in the length direction and at a corresponding position on the back side of the substrate, and a plurality of chips are fixed at intervals on another portion of the lead frame in the length direction, the substrate is electrically connected to the inner pin, and the chip is electrically connected to the inner pin and the inner pin of the lead frame.

3. The heat dissipation type SIP hybrid package for improving signal transmission speed and reliability according to claim 1, characterized in that: When the substrate and the chip are arranged on the lead frame in the vertical direction, the lead frame is a hollow structure to form several interconnected carrier areas, the substrate is fixed on the carrier area, the substrate is covered with a PI film, and several chips distributed at intervals are fixed on the PI film. The substrate is electrically connected to the inner pins, and the chip is electrically connected to the inner pins.

4. The heat dissipation type SIP hybrid package for improving signal transmission speed and reliability according to claim 2, characterized in that: When the substrate is an HDI board and there are three chips, the lead frame is rectangular, and hollow structures are provided on both sides and inside of the lead frame in the width direction to form a first frame and a second frame of the same shape arranged at intervals, and the first frame includes a first carrier area, a second carrier area and a third carrier area, the first carrier area is a rectangular plate, and a corner located on the upper outer side extends outward to form a first lead frame inner foot, and a first glue locking hole is provided at the junction of the first lead frame inner foot and the first carrier area, the third carrier area is a right-angled trapezoid, and the shape of the second carrier area is a rectangle with a right-angled triangle notch on one side close to the third carrier area, and the bottom extends outward on one side along the width direction. A first rectangular carrier forms an integral structure with the third carrier region, a second rectangular carrier with the same width as the first rectangular carrier extending outward from the other side, and forming an integral structure with the first carrier region, a carrier support rib extending from the outside of the first rectangular carrier close to the third carrier region, an inner foot separated from the third carrier region is arranged on the outside of the carrier support rib, an inner foot is arranged between the carrier support rib and the inner foot of the first lead frame, the fourth carrier region in the second frame corresponds to the first carrier region, the fifth carrier region corresponds to the second carrier region, the sixth carrier region corresponds to the third carrier region, the inner foot of the second lead frame corresponds to the inner foot of the first lead frame, and the second glue locking hole corresponds to the first glue locking hole; A first chip and a second chip are bonded to the first carrier region, which are spaced apart from each other. A third chip is bonded to the fourth carrier region. A substrate is bonded to the second carrier region, the third carrier region, the fifth carrier region and the sixth carrier region.

5. The heat dissipation type SIP hybrid package for improving signal transmission speed and reliability according to claim 4, characterized in that: The length of the outer side of the third carrier region is 2 to 3 times the length of the inner side, and the length value of the third carrier region, the length value of the second carrier region and the width value of the first carrier region increase in sequence.

6. The heat dissipation type SIP hybrid package for improving signal transmission speed and reliability according to claim 4, characterized in that: The edges of the second carrier region and the third carrier region are etched with steps to form a first carrier step and a second carrier step respectively, and the edges of the fifth carrier region and the sixth carrier region are etched with steps to form a third carrier step and a fourth carrier step respectively, and the depth of all steps is half of the thickness of the lead frame.

7. The heat dissipation type SIP hybrid package for improving signal transmission speed and reliability according to claim 3, characterized in that: When the substrate is a rigid substrate and there are 4 chips, the lead frame includes a carrier region 1, a carrier region 2 and a carrier region 3, all of which have rectangular main structures. The area of ​​the rectangular plate-shaped carrier region 1 is larger than that of the carrier region 2 and the carrier region 3. The carrier region 1 is provided with a glue locking hole 1 near both sides in the length direction. The carrier region 2 and the carrier region 3 have the same shape and size, are symmetrical in the horizontal direction and are spaced apart on one side of the carrier region 1. The carrier region 2 and the carrier region 3 are respectively integrated with the carrier region 1 through the rectangular plate. The center of the gap between the carrier region 2 and the carrier region 3 coincides with the center line of the carrier region 1 in the length direction. The carrier region 2 and the carrier region 3 are provided with a glue locking hole 2 along the length direction. The other side of the carrier region 1 is provided with a first inner pin and a second inner pin. The substrate is fixed on carrier area 1, carrier area 2 and carrier area 3, the PI film covers the substrate, and chip 1 and chip 2 are bonded to the lower position of the PI film so that they are flush and relatively positioned. Parts of chip 1 and chip 2 are respectively located directly above the corresponding rectangular plates, and chip 3 and chip 4 are bonded to the upper position of the PI film so that they are flush and spaced apart.

8. The heat dissipation type SIP hybrid package for improving signal transmission speed and reliability according to claim 7, characterized in that: The substrate is a glass fiber board or a ceramic substrate.

9. A method for processing a heat dissipation type SIP hybrid package for improving signal transmission speed and reliability as claimed in any one of claims 2, 4 to 6, characterized in that: The steps include: S1, bonding the back side of the substrate to the hollow part of the lead frame; S2, fixing all chips on another part of the lead frame according to their positions, electrically connecting the chips to each other, electrically connecting the substrate to all the chips, electrically connecting the substrate to the inner pins, and electrically connecting the chips to the inner pins and the inner pins of the lead frame; S3, using packaging materials to package the chip and the substrate to complete the processing of the SIP hybrid package.

10. A method for processing a heat dissipation type SIP hybrid package for improving signal transmission speed and reliability as claimed in any one of claims 3, 7 to 8, characterized in that: The steps include: S1, fixing the substrate on the carrier area of ​​the lead frame; S2, covering the substrate with a PI film, fixing a number of spaced chips on the PI film, electrically connecting the chips to each other, the substrate to all the chips, the substrate to the inner pins, and the chips to the inner pins; S3, using packaging materials to package the chip and the substrate to complete the processing of the SIP hybrid package.

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