Chip adapter plate and chip packaging structure

Abstract

The invention discloses a chip adapter plate and a chip packaging structure, and belongs to the technical field of semiconductors. The chip adapter plate comprises: a first port; a second port; the transmission signal line is connected between the first port and the second port; the transmission signal line comprises a bending section, and the bending section forms an inductor. According to the invention, impedance matching between the transmission signal line and the port can be improved, signal integrity is improved, high-speed transmission of signals is realized, and process difficulty and cost are reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip adapter board and a chip packaging structure. Background Art

[0002] Chips in a chip packaging structure can be interconnected with each other or with external devices through a chip adapter. However, due to the process limitations of the chip adapter, the distance between the transmission signal line and the transmission ground line in the chip adapter is very close, and the capacitance between the transmission signal line and the transmission ground line is strong, which makes the impedance of the transmission signal line low, resulting in an impedance mismatch problem between the transmission signal line and the port of the chip. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a chip adapter board and a chip packaging structure, which can improve the impedance matching between the transmission signal line and the port, improve the signal integrity, realize high-speed signal transmission, and reduce the process difficulty and cost.

[0004] The present application provides a chip adapter board, comprising:

[0005] First port;

[0006] Second port;

[0007] A transmission signal line is connected between the first port and the second port; the transmission signal line includes a bending section, and the bending section constitutes an inductor.

[0008] According to an embodiment of the present application, the transmission signal line further includes at least two signal routing segments, the bending segment is connected in series between two of the signal routing segments, and the bending segment is arranged on the same layer as at least one of the signal routing segments.

[0009] According to an embodiment of the present application, the chip adapter board further includes a substrate and a first wiring layer, the first wiring layer is located on one side of the substrate, and the first port is located on a side of the first wiring layer away from the substrate;

[0010] The at least two signal routing segments include a first signal routing segment, the first routing layer includes the first signal routing segment and the bending segment arranged in the same layer, and the first signal routing segment is connected between the first port and a first end of the bending segment.

[0011] According to an embodiment of the present application, the second port is located on a side of the first wiring layer away from the substrate, and the first end and the second end of the bending section are respectively located on opposite sides of the bending section;

[0012] The at least two signal routing segments further include a second signal routing segment, the first routing layer further includes the second signal routing segment disposed in the same layer as the bending segment, and the second signal routing segment is connected between the second end of the bending segment and the second port.

[0013] According to an embodiment of the present application, the chip adapter board further includes a second routing layer, the second routing layer is located between the substrate and the first routing layer; the second port is located on a side of the first routing layer away from the substrate, the second end of the bending section is located on the inner side of the bending section, and the first end of the bending section is located on the outer side of the bending section;

[0014] The at least two signal routing segments further include a third signal routing segment and a fourth signal routing segment, the second routing layer includes the third signal routing segment, and the first routing layer further includes the fourth signal routing segment disposed on the same layer as the bending segment;

[0015] The transmission signal line also includes a first connection structure and a second connection structure that respectively penetrate the first routing layer, and the first connection structure, the third signal routing segment, the second connection structure and the fourth signal routing segment are sequentially connected between the second end of the bending segment and the second port.

[0016] According to an embodiment of the present application, the second port is located on a side of the substrate away from the first wiring layer, and the first end and the second end of the bending section are respectively located on opposite sides of the bending section;

[0017] The at least two signal routing segments further include a fifth signal routing segment, and the first routing layer further includes the fifth signal routing segment disposed in the same layer as the bending segment;

[0018] The transmission signal line also includes a third connection structure penetrating the first routing layer and a first through-hole structure penetrating the substrate, and the fifth signal routing segment, the third connection structure and the first through-hole structure are sequentially connected between the second end of the bending segment and the second port.

[0019] According to an embodiment of the present application, the chip adapter board further includes a second routing layer, the second routing layer is located between the substrate and the first routing layer; the second port is located on a side of the substrate away from the first routing layer, the second end of the bending section is located on the inner side of the bending section, and the first end of the bending section is located on the outer side of the bending section;

[0020] The at least two signal routing segments further include a sixth signal routing segment, and the second routing layer includes the sixth signal routing segment;

[0021] The transmission signal line also includes a fourth connection structure running through the first routing layer, a fifth connection structure running through the second routing layer, and a second through-hole structure running through the substrate, and the fourth connection structure, the sixth signal routing segment, the fifth connection structure, and the second through-hole structure are sequentially connected between the second end of the bending segment and the second port.

[0022] According to one embodiment of the present application, the chip adapter board further includes:

[0023] The transmission ground line comprises a ground line segment arranged corresponding to the signal line segment, and the ground line segment is located between the corresponding signal line segment and the substrate.

[0024] According to one embodiment of the present application, the bending segment includes at least one of a spiral bending segment and a serpentine bending segment.

[0025] The present application provides a chip packaging structure, comprising a first chip and a chip adapter board as described in any one of the above embodiments; the first chip is connected to a first port in the chip adapter board.

[0026] According to an embodiment of the present application, the first port and the second port are located on the same side of the chip adapter board, and the chip packaging structure further includes a second chip, and the second chip is connected to the second port in the chip adapter board.

[0027] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0028] By setting a bending section in the transmission signal line between the first port and the second port, the bending section constitutes an inductor, and the inductor is connected in series on the routing path of the transmission signal line to increase the characteristic impedance of the transmission signal line, thereby improving the impedance matching between the transmission signal line and the first port and the second port, reducing reflection and loss of the signal during transmission, improving the integrity of the signal, and realizing high-speed signal transmission; moreover, the inductor is directly integrated in the transmission signal line, reducing the process difficulty and cost.

[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0031] Figure 1 This is one of the structural schematic diagrams of the chip adapter board provided in the embodiment of the present application;

[0032] Figure 2 It is one of the top views of the first routing layer provided in the embodiment of the present application;

[0033] Figure 3 This is the second structural schematic diagram of the chip adapter board provided in the embodiment of the present application;

[0034] Figure 4 This is the second top view of the first wiring layer provided in the embodiment of the present application;

[0035] Figure 5 It is one of the top views of the second routing layer provided in the embodiment of the present application;

[0036] Figure 6 This is the third structural schematic diagram of the chip adapter board provided in the embodiment of the present application;

[0037] Figure 7 This is the third top view of the first routing layer provided in the embodiment of the present application;

[0038] Figure 8 This is the fourth structural schematic diagram of the chip adapter board provided in the embodiment of the present application;

[0039] Fig. 9 This is the fourth top view of the first routing layer provided in the embodiment of the present application;

[0040] Fig.10 This is the second top view of the second routing layer provided in the embodiment of the present application;

[0041] Fig.11 It is a structural schematic diagram of the chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0043] With the continuous development of integrated circuit manufacturing technology, the marginal effect of process node refinement on system performance improvement is increasingly weakened, and Moore's Law is gradually becoming invalid. Traditional single-chip integration technology faces challenges in many aspects such as cost, power consumption and performance. Against this background, chiplet technology came into being and became an important direction for the next generation of integrated circuit technology. Chiplet technology modularizes the functions originally integrated on a single complex chip, allowing each module to be designed independently and manufactured into a chip. Subsequently, advanced 2.5D or 3D packaging technology is used to integrate these chips together to form an integrated circuit system. This technical solution not only breaks through the limitations of traditional single-chip integration, but also significantly improves the flexibility and efficiency of chip design.

[0044] At present, with the rapid development of artificial intelligence, high-performance computing and other fields, the demand for high-performance computing capabilities and big data processing capabilities has increased, which has put high demands on the bandwidth of chip-to-chip interconnection. In order to meet this demand, it is necessary to deepen and optimize the research on 2.5D packaging technology. There are two main ways for related technologies to improve the interconnection bandwidth of chips: one is to directly expand the bandwidth by increasing the number of signal channels; the other is to achieve a leap in efficiency by increasing the signal transmission speed. Therefore, in-depth research on high-speed signal transmission technology in 2.5D packaging is of vital importance to meet the stringent requirements of artificial intelligence and high-performance computing applications.

[0045] 2.5D packaging technology realizes the interconnection between chips or chips and external devices through chip adapters. However, due to the manufacturing process of chip adapters, the stacking thickness of chip adapters is usually maintained at 1 micron, resulting in extremely small spacing between the transmission signal line and the transmission ground line in the chip adapter, and a strong capacitance effect between the transmission signal line and the transmission ground line. This capacitance effect reduces the characteristic impedance of the transmission signal line, and it is difficult to achieve a transmission signal line with a standard characteristic impedance of 50Ω on the chip adapter. The characteristic impedance of the transmission signal line can usually only reach about 30Ω. Therefore, there is an impedance mismatch problem between the transmission signal line on the chip adapter and the chip port. Realizing impedance matching between the transmission signal line and the chip port is of great practical significance for reducing reflection and loss of signals during transmission, improving signal integrity, and realizing high-speed transmission of signals.

[0046] From the perspective of chip design, the relevant technology can compensate for the signal loss during transmission by increasing the port voltage of the chip and using a higher voltage to drive the signal. However, this method will inevitably increase the power consumption of the chip, which may cause energy efficiency problems.

[0047] From the perspective of processing technology, related technologies increase the thickness of the dielectric layer between the transmission signal line and the transmission ground line, or use a dielectric layer with a low dielectric constant to achieve impedance matching. However, this approach will bring problems such as the research and development costs of new processes and new materials.

[0048] In addition, related technologies also achieve impedance matching by adding passive components, such as surface-mounted inductors on the transmission signal lines of the chip adapter. However, this method not only increases the cost of passive components, but also occupies the area resources of the chip adapter. In addition, surface-mounted inductors are difficult to implement in the chip adapter process and have high process risks.

[0049] Based on this, an embodiment of the present application provides a chip adapter board and a chip packaging structure.

[0050] The chip transfer board and chip packaging structure provided in the embodiments of the present application are described below with reference to the accompanying drawings.

[0051] Figure 1 A schematic diagram of the structure of a chip adapter board provided in an embodiment of the present application, wherein the chip adapter board can be applied to a chip packaging structure.

[0052] like Figure 1 As shown, the chip adapter provided in the embodiment of the present application includes a first port 1. The first port 1 is used to connect the first chip in the chip packaging structure. For example, the first chip includes a high-speed communication port, and the first port 1 can be connected to the high-speed communication port of the first chip.

[0053] The chip adapter board may further include a second port 2. The second port 2 is used to connect the second chip in the chip package structure or an external device. For example, the second chip includes a high-speed communication port, and the second port 2 can be connected to the high-speed communication port of the second chip. For another example, the external device includes a high-speed communication port, and the second port 2 can be connected to the high-speed communication port of the external device.

[0054] The chip adapter board may further include a transmission signal line 4, which is connected between the first port 1 and the second port 2. One end of the transmission signal line 4 is connected to the first port 1, and the other end of the transmission signal line 4 is connected to the second port 2. The first chip may be connected to the second chip or an external device through the first port 1, the transmission signal line 4, and the second port 2, to achieve signal and data transmission between the first chip and the second chip or the external device.

[0055] The transmission signal line 4 includes a bending section 5, and the bending section 5 forms an inductor. Figure 2As shown, part of the routing segments (i.e., the bending segments 5) in the transmission signal line 4 are bent, and the bent routing segments have inductance characteristics, so that the bending segments 5 constitute inductance, so as to connect the inductance in series on the routing path of the transmission signal line 4, thereby effectively improving the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2.

[0056] The inductance value of the inductor is related to the position, length and bending shape of the bending section 5. By adjusting the position, length and bending shape of the bending section 5, the inductance value of the inductor can be adjusted, thereby adjusting the characteristic impedance value of the transmission signal line 4. When the characteristic impedance value of the transmission signal line 4 is adjusted to be equal to the characteristic impedance of the first port 1 and the second port 2, impedance matching between the transmission signal line 4 and the first port 1 and the second port 2 can be achieved.

[0057] In this embodiment, by setting a bending section 5 in the transmission signal line 4 between the first port 1 and the second port 2, the bending section 5 constitutes an inductor, so as to connect the inductor in series on the routing path of the transmission signal line 4, thereby improving the characteristic impedance of the transmission signal line 4, thereby improving the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2, reducing the reflection and loss of the signal during the transmission process, improving the signal integrity, and realizing high-speed transmission of the signal. In this embodiment, there is no need to compensate for the loss of the signal during the transmission process by increasing the port voltage of the chip in the chip packaging structure, thereby avoiding increasing the power consumption of the chip. At the same time, in this embodiment, there is no need to increase the thickness of the dielectric layer in the chip adapter or select a dielectric layer with a low dielectric constant to achieve impedance matching, thereby avoiding the problems of research and development costs caused by new processes and new materials. Moreover, the inductor formed by the bending section 5 is directly integrated in the transmission signal line 4, and there is no need to add additional passive devices to be mounted on the surface of the chip adapter, thereby avoiding occupying the area of ​​the chip adapter, and the process difficulty is low, the implementation difficulty is small, the process risk is low, and the cost is low.

[0058] In some embodiments, the transmission signal line 4 further includes at least two signal routing segments, the bending segment 5 is connected in series between the two signal routing segments, and the bending segment 5 is disposed on the same layer as at least one signal routing segment.

[0059] Each signal routing segment of the transmission signal line 4 may extend along the second direction Y. Figure 2 As shown, the bending section 5 can extend alternately along the first direction X and the second direction Y. The first direction X and the second direction Y are perpendicular to each other. The two ends of the bending section 5 are respectively connected to the two signal routing segments of the transmission signal line 4, that is, the bending section 5 is connected in series between the two signal routing segments, so that the bending section 5 is connected in series on the routing path of the transmission signal line 4.

[0060] The bending section 5 and part or all of the signal routing segments of the transmission signal line 4 are arranged on the same layer, and the bending section 5 and the signal routing segments arranged on the same layer can be manufactured by one process.

[0061] In this embodiment, the inductor formed by the bending segment 5 is arranged on the same layer as at least one signal routing segment of the transmission signal line 4, so that the inductor is directly integrated into the transmission signal line 4, thereby improving the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2 without adding additional passive inductors, thereby reducing costs and process difficulty.

[0062] In some embodiments, Figure 1 , Figure 3 , Figure 6 and Figure 8 As shown, the chip adapter board also includes a substrate 3 and a first routing layer 16, the first routing layer 16 is located on one side of the substrate 3, and the first port 1 is located on the side of the first routing layer 16 away from the substrate 3. The at least two signal routing segments include a first signal routing segment 41, the first routing layer 16 includes the first signal routing segment 41 and the bending segment 5 arranged on the same layer, and the first signal routing segment 41 is connected between the first port 1 and the first end 51 of the bending segment 5.

[0063] The substrate 3 is located at the bottom of the chip transfer board, and the substrate 3 provides physical support for other structures of the chip transfer board. In some embodiments, the substrate 3 includes a silicon substrate or a glass substrate.

[0064] The first routing layer 16 is located on one side of the substrate 3 along the thickness direction H, and the thickness direction H is perpendicular to the first direction X and the second direction Y. The first routing layer 16 may also include a first dielectric layer 161, that is, the first routing layer 16 may include a first signal routing segment 41, a bending segment 5 and a first dielectric layer 161. The first dielectric layer 161 is located on one side of the substrate 3 along the thickness direction H, the first signal routing segment 41 and the bending segment 5 are located on the side of the first dielectric layer 161 away from the substrate 3, and the first port 1 is located on the side of the first signal routing segment 41 away from the first dielectric layer 161.

[0065] The first signal routing segment 41 and the bending segment 5 can be arranged on the first dielectric layer 161 in the same layer, that is, the first signal routing segment 41 and the bending segment 5 can be formed by one process. The first signal routing segment 41 and the bending segment 5 can be made of the same material. For example, the first signal routing segment 41 and the bending segment 5 can respectively include metals such as copper or aluminum. The first dielectric layer 161 can include silicon carbide, etc.

[0066] The first signal routing segment 41 extends along the second direction Y, and the bending segment 5 extends alternately along the first direction X and the second direction Y. The bending segment 5 has a first end 51 and a second end 52. One end of the first signal routing segment 41 is connected to the first port 1, and the other end of the first signal routing segment 41 is connected to the first end 51 of the bending segment 5. The second end 52 of the bending segment 5 can be connected to the second port 2 through other signal routing segments of the transmission signal line 4. The first signal routing segment 41 and the bending segment 5 can be arranged in the same layer or in different layers as other signal routing segments of the transmission signal line 4.

[0067] In this embodiment, the inductor formed by the bending segment 5 is arranged and connected on the same layer as the first signal routing segment 41 of the transmission signal line 4, so that the inductor is connected in series on the routing path of the transmission signal line 4. While improving the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2, there is no need to add additional passive inductors, thereby reducing costs and process difficulty.

[0068] In some embodiments, Figure 1 and Figure 2 As shown, the second port 2 is located on the side of the first routing layer 16 facing away from the substrate 3, and the first end 51 and the second end 52 of the bending section 5 are respectively located on opposite sides of the bending section 5. The at least two signal routing segments also include a second signal routing segment 42, and the first routing layer 16 also includes a second signal routing segment 42 arranged on the same layer as the bending section 5, and the second signal routing segment 42 is connected between the second end 52 of the bending section 5 and the second port 2.

[0069] In this embodiment, the first port 1 and the second port 2 are located on the same side of the chip adapter along the thickness direction H, that is, the first port 1 and the second port 2 are both located on the side of the first wiring layer 16 away from the substrate 3. The second port 2 is used to connect the second chip in the chip packaging structure. The first end 51 and the second end 52 of the bending section 5 are respectively located on opposite sides of the bending section 5 along the second direction Y, for example, the bending section 5 is a serpentine bending section.

[0070] In the case where the first routing layer 16 also includes the first dielectric layer 161, the second signal routing segment 42 is located on the side of the first dielectric layer 161 away from the substrate 3. The first signal routing segment 41, the bending segment 5 and the second signal routing segment 42 are arranged on the first dielectric layer 161 in the same layer, that is, the first signal routing segment 41, the bending segment 5 and the second signal routing segment 42 can be formed by one process. The second signal routing segment 42 can be made of the same material as the first signal routing segment 41 and the bending segment 5. For example, the second signal routing segment 42 can include metals such as copper or aluminum.

[0071] The second signal routing segment 42 may extend along the second direction Y. One end of the second signal routing segment 42 is connected to the second end 52 of the bending segment 5 , and the other end of the second signal routing segment 42 is connected to the second port 2 .

[0072] The transmission signal line 4 in this embodiment includes a first signal routing segment 41, a bending segment 5 and a second signal routing segment 42 connected in sequence, that is, the first port 1 is connected to the second port 2 through the first signal routing segment 41, the bending segment 5 and the second signal routing segment 42, thereby realizing signal interconnection and data transmission between the first chip and the second chip.

[0073] In this embodiment, an inductor (i.e., the bending segment 5) is connected in series between the first signal routing segment 41 and the second signal routing segment 42 of the transmission signal line 4 to improve the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2. While achieving high-speed data transmission between the first chip and the second chip, there is no need to add additional passive inductors, thereby reducing costs and process difficulties. The transmission signal line 4 is located in the same film layer, reducing the thickness of the chip adapter board.

[0074] In some embodiments, Figures 3 to 5 As shown, the chip adapter board also includes a second routing layer 17, and the second routing layer 17 is located between the substrate 3 and the first routing layer 16. The second port 2 is located on the side of the first routing layer 16 away from the substrate 3, the second end 52 of the bending section 5 is located on the inner side of the bending section 5, and the first end 51 of the bending section 5 is located on the outer side of the bending section 5. The at least two signal routing segments also include a third signal routing segment 43 and a fourth signal routing segment 44, the second routing layer 17 includes the third signal routing segment 43, and the first routing layer 16 also includes a fourth signal routing segment 44 arranged on the same layer as the bending section 5. The transmission signal line 4 also includes a first connection structure 7 and a second connection structure 8 that respectively penetrate the first routing layer 16, and the first connection structure 7, the third signal routing segment 43, the second connection structure 8 and the fourth signal routing segment 44 are sequentially connected between the second end 52 of the bending section 5 and the second port 2.

[0075] In this embodiment, the first port 1 and the second port 2 are located on the same side of the chip adapter along the thickness direction H, that is, the first port 1 and the second port 2 are both located on the side of the first wiring layer 16 away from the substrate 3. The second port 2 is used to connect the second chip in the chip packaging structure. The first end 51 and the second end 52 of the bending section 5 are respectively located on the outside and the inside of the bending section 5, for example, the bending section 5 is a spiral bending section.

[0076] In the case where the first routing layer 16 further includes the first dielectric layer 161, the fourth signal routing segment 44 is located on the side of the first dielectric layer 161 away from the substrate 3. The fourth signal routing segment 44 is arranged on the first dielectric layer 161 in the same layer as the first signal routing segment 41 and the bending segment 5, that is, the first signal routing segment 41, the bending segment 5 and the fourth signal routing segment 44 can be formed by one process. The fourth signal routing segment 44 can be made of the same material as the first signal routing segment 41 and the bending segment 5. For example, the fourth signal routing segment 44 can include metals such as copper or aluminum.

[0077] The second routing layer 17 may further include a second dielectric layer 171, that is, the second routing layer 17 includes a third signal routing segment 43 and a second dielectric layer 171. The second dielectric layer 171 is located between the substrate 3 and the first dielectric layer 161, and the third signal routing segment 43 is located between the second dielectric layer 171 and the first dielectric layer 161, that is, the third signal routing segment 43 and the first signal routing segment 41, the bending segment 5 and the fourth signal routing segment 44 are located in different film layers. The material of the third signal routing segment 43 may be the same as that of the first signal routing segment 41, the bending segment 5 and the fourth signal routing segment 44. For example, the third signal routing segment 43 may include metals such as copper or aluminum. The second dielectric layer 171 may include silicon carbide or the like.

[0078] The third signal routing segment 43 and the fourth signal routing segment 44 may extend along the second direction Y, respectively. The first connection structure 7 penetrates the first dielectric layer 161, and is respectively connected to the second end 52 of the bending segment 5 and one end of the third signal routing segment 43. The second connection structure 8 penetrates the first dielectric layer 161, and is respectively connected to the other end of the third signal routing segment 43 and one end of the fourth signal routing segment 44, and the other end of the fourth signal routing segment 44 is connected to the second port 2. The first connection structure 7 may include metals such as copper or aluminum, and the second connection structure 8 may include metals such as copper or aluminum.

[0079] The transmission signal line 4 in this embodiment includes a first signal routing segment 41, a bending segment 5, a first connection structure 7, a third signal routing segment 43, a second connection structure 8 and a fourth signal routing segment 44 which are connected in sequence, that is, the first port 1 is connected to the second port 2 via the first signal routing segment 41, the bending segment 5, the first connection structure 7, the third signal routing segment 43, the second connection structure 8 and the fourth signal routing segment 44, thereby realizing signal interconnection and data transmission between the first chip and the second chip.

[0080] In this embodiment, an inductor (i.e., the bending segment 5) is connected in series between the first signal routing segment 41 and the third signal routing segment 43 of the transmission signal line 4 to improve the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2. While achieving high-speed data transmission between the first chip and the second chip, there is no need to add additional passive inductors, thereby reducing costs and process difficulty.

[0081] In some embodiments, Figure 6 and Figure 7 As shown, the second port 2 is located on the side of the substrate 3 away from the first routing layer 16, and the first end 51 and the second end 52 of the bending section 5 are respectively located on opposite sides of the bending section 5. The at least two signal routing segments also include a fifth signal routing segment 45, and the first routing layer 16 also includes a fifth signal routing segment 45 arranged on the same layer as the bending section 5. The transmission signal line 4 also includes a third connection structure 9 penetrating the first routing layer 16 and a first through-hole structure 10 penetrating the substrate 3, and the fifth signal routing segment 45, the third connection structure 9 and the first through-hole structure 10 are sequentially connected between the second end 52 of the bending section 5 and the second port 2.

[0082] In this embodiment, the first port 1 and the second port 2 are located on opposite sides of the thickness direction H of the chip adapter, that is, the first port 1 is located on the side of the first wiring layer 16 away from the substrate 3, and the second port 2 is located on the side of the substrate 3 away from the first wiring layer 16. The second port 2 is used to connect an external device. The first end 51 and the second end 52 of the bending section 5 are respectively located on opposite sides of the bending section 5 along the second direction Y, for example, the bending section 5 is a serpentine bending section.

[0083] In the case where the first routing layer 16 further includes the first dielectric layer 161, the fifth signal routing segment 45 is located on the side of the first dielectric layer 161 away from the substrate 3. The first signal routing segment 41, the bending segment 5 and the fifth signal routing segment 45 are arranged on the first dielectric layer 161 in the same layer, that is, the first signal routing segment 41, the bending segment 5 and the fifth signal routing segment 45 can be formed by one process. The fifth signal routing segment 45 can be made of the same material as the first signal routing segment 41 and the bending segment 5. For example, the fifth signal routing segment 45 can include metals such as copper or aluminum.

[0084] The fifth signal routing segment 45 extends along the second direction Y. One end of the fifth signal routing segment 45 is connected to the second end 52 of the bending segment 5. The third connection structure 9 passes through the first dielectric layer 161 and is connected to the other end of the fifth signal routing segment 45. The first through-hole structure 10 passes through the substrate 3 and is respectively connected to the third connection structure 9 and the second port 2. Among them, the third connection structure 9 may include metals such as copper or aluminum. The first through-hole structure 10 may include metals such as copper or aluminum. When the substrate 3 is a silicon substrate, the first through-hole structure 10 is a TSV (Through silicon via).

[0085] The transmission signal line 4 in this embodiment includes a first signal routing segment 41, a bending segment 5, a fifth signal routing segment 45, a third connection structure 9 and a first through-hole structure 10 connected in sequence, that is, the first port 1 is connected to the second port 2 through the first signal routing segment 41, the bending segment 5, the fifth signal routing segment 45, the third connection structure 9 and the first through-hole structure 10, thereby realizing signal interconnection and data transmission between the first chip and the external device.

[0086] In this embodiment, an inductor (i.e., the bending segment 5) is connected in series between the first signal routing segment 41 and the fifth signal routing segment 45 of the transmission signal line 4 to improve the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2. While achieving high-speed data transmission between the first chip and the external device, there is no need to add additional passive inductors, thereby reducing costs and process difficulties.

[0087] In some embodiments, Figures 8 to 10 As shown, the chip adapter board also includes a second routing layer 17, and the second routing layer 17 is located between the substrate 3 and the first routing layer 16. The second port 2 is located on the side of the substrate 3 away from the first routing layer 16, the second end 52 of the bending section 5 is located on the inner side of the bending section 5, and the first end 51 of the bending section 5 is located on the outer side of the bending section 5. The at least two signal routing segments also include a sixth signal routing segment 46, and the second routing layer 17 includes the sixth signal routing segment 46. The transmission signal line 4 also includes a fourth connection structure 11 that passes through the first routing layer 16, a fifth connection structure 12 that passes through the second routing layer 17, and a second through-hole structure 13 that passes through the substrate 3. The fourth connection structure 11, the sixth signal routing segment 46, the fifth connection structure 12, and the second through-hole structure 13 are sequentially connected between the second end 52 of the bending section 5 and the second port 2.

[0088] In this embodiment, the first port 1 and the second port 2 are located on opposite sides of the thickness direction H of the chip adapter, that is, the first port 1 is located on the side of the first wiring layer 16 away from the substrate 3, and the second port 2 is located on the side of the substrate 3 away from the first wiring layer 16. The second port 2 is used to connect an external device. The first end 51 and the second end 52 of the bending section 5 are respectively located on the outside and the inside of the bending section 5, for example, the bending section 5 is a spiral bending section.

[0089] The second routing layer 17 may also include a second dielectric layer 171, that is, the second routing layer 17 includes a sixth signal routing segment 46 and a second dielectric layer 171. The second dielectric layer 171 is located between the substrate 3 and the first dielectric layer 161, and the sixth signal routing segment 46 is located between the second dielectric layer 171 and the first dielectric layer 161, that is, the sixth signal routing segment 46 and the first signal routing segment 41 and the bending segment 5 are located in different film layers. The material of the sixth signal routing segment 46 can be the same as that of the first signal routing segment 41 and the bending segment 5. For example, the sixth signal routing segment 46 can include metals such as copper or aluminum. The second dielectric layer 171 may include silicon carbide, etc.

[0090] The sixth signal routing segment 46 may extend along the second direction Y. The fourth connection structure 11 penetrates the first dielectric layer 161 and is respectively connected to the second end 52 of the bending segment 5 and one end of the sixth signal routing segment 46. The fifth connection structure 12 penetrates the second dielectric layer 171 and is connected to the other end of the sixth signal routing segment 46. The second through-hole structure 13 penetrates the substrate 3 and is respectively connected to the fifth connection structure 12 and the second port 2. Among them, the fourth connection structure 11 may include metals such as copper or aluminum, the fifth connection structure 12 may include metals such as copper or aluminum, and the second through-hole structure 13 may include metals such as copper or aluminum. When the substrate 3 is a silicon substrate, the second through-hole structure 13 is a TSV.

[0091] The transmission signal line 4 in this embodiment includes a first signal routing segment 41, a bending segment 5, a fourth connection structure 11, a sixth signal routing segment 46, a fifth connection structure 12 and a second through-hole structure 13 connected in sequence, that is, the first port 1 is connected to the second port 2 through the first signal routing segment 41, the bending segment 5, the fourth connection structure 11, the sixth signal routing segment 46, the fifth connection structure 12 and the second through-hole structure 13, so as to realize signal interconnection and data transmission between the first chip and the external device.

[0092] In this embodiment, an inductor (i.e., the bending segment 5) is connected in series between the first signal routing segment 41 and the sixth signal routing segment 46 of the transmission signal line 4 to improve the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2. While achieving high-speed data transmission between the first chip and the external device, there is no need to add additional passive inductors, thereby reducing costs and process difficulties.

[0093] In some embodiments, Figure 1 , Figure 3 , Figure 6 and Figure 8 As shown, the chip adapter board also includes a transmission ground line 15 , and the transmission ground line 15 includes a ground line segment arranged corresponding to the signal routing segment, and the ground line segment is located between the corresponding signal routing segment and the substrate 3 .

[0094] The transmission ground line 15 may include a plurality of ground line segments, and the number of ground line segments in the transmission ground line 15 may be the same as the number of signal routing segments in the transmission signal line 4. The plurality of ground line segments may be arranged in a one-to-one correspondence with the plurality of signal routing segments. Each ground line segment may be located between the corresponding signal routing segment and the substrate 3, and the orthographic projection of each signal routing segment on the substrate 3 may coincide with the orthographic projection of the corresponding ground line segment on the substrate 3. The transmission ground line 15 is used to form a return path for signal transmission in the transmission signal line 4.

[0095] The multiple ground line segments in the transmission ground line 15 can be arranged in the same layer or in different layers, and the ground line segments in the transmission ground line 15 can be arranged in the same layer or in different layers as the signal routing segments in the transmission signal line 4 that are not arranged corresponding to the ground line segments.

[0096] In some embodiments, when the transmission signal line 4 includes a first signal routing segment 41, a bending segment 5, and a second signal routing segment 42 connected in sequence, as shown in FIG. Figure 1 As shown, the transmission ground line 15 may include a first ground line segment 151 and a second ground line segment 152. The first ground line segment 151 is arranged corresponding to the first signal routing segment 41, and the first ground line segment 151 is located between the first signal routing segment 41 and the substrate 3. The second ground line segment 152 is arranged corresponding to the second signal routing segment 42, and the second ground line segment 152 is located between the second signal routing segment 42 and the substrate 3.

[0097] The chip adapter board may also include a third routing layer 18, and the third routing layer 18 is located between the substrate 3 and the first routing layer 16. The third routing layer 18 may include a third dielectric layer 181, a first ground segment 151 and a second ground segment 152, and the third dielectric layer 181 is located between the substrate 3 and the first dielectric layer 161, and the first ground segment 151 and the second ground segment 152 are arranged in the third dielectric layer 181 in the same layer. The first ground segment 151 and the second ground segment 152 can be formed by the same process. The material of the first ground segment 151 and the second ground segment 152 can be the same as that of the first signal routing segment 41, the bending segment 5 and the second signal routing segment 42. For example, the first ground segment 151 and the second ground segment 152 may respectively include metals such as copper or aluminum.

[0098] In this embodiment, the dielectric layer between the first signal routing segment 41 and the first ground segment 151 is the first dielectric layer 161, and the dielectric layer between the second signal routing segment 42 and the second ground segment 152 is also the first dielectric layer 161. The first dielectric layer 161 can be the same in thickness and material as the dielectric layer in conventional technology, without increasing the thickness of the first dielectric layer 161 or selecting a dielectric material with a low dielectric constant, thereby avoiding the problems of research and development costs caused by new processes and new materials.

[0099] In some embodiments, when the transmission signal line 4 includes a first signal routing segment 41, a bending segment 5, a first connection structure 7, a third signal routing segment 43, a second connection structure 8, and a fourth signal routing segment 44 connected in sequence, as shown in FIG. Figure 3 As shown, the transmission ground line 15 may include a first ground line segment 151, a third ground line segment 153 and a fourth ground line segment 154. The first ground line segment 151 is arranged corresponding to the first signal routing segment 41, and the first ground line segment 151 is located between the first signal routing segment 41 and the substrate 3. The third ground line segment 153 is arranged corresponding to the third signal routing segment 43, and the third ground line segment 153 is located between the third signal routing segment 43 and the substrate 3. The fourth ground line segment 154 is arranged corresponding to the fourth signal routing segment 44, and the fourth ground line segment 154 is located between the fourth signal routing segment 44 and the substrate 3.

[0100] The first ground segment 151 and the fourth ground segment 154 are arranged in the same layer. The first ground segment 151 and the fourth ground segment 154 can be located in the second routing layer 17, that is, the second routing layer 17 can include the second dielectric layer 171, the first ground segment 151, the third signal routing segment 43 and the fourth ground segment 154, and the first ground segment 151, the third signal routing segment 43 and the fourth ground segment 154 are arranged in the same layer between the second dielectric layer 171 and the first dielectric layer 161. The first ground segment 151, the third signal routing segment 43 and the fourth ground segment 154 can be made by the same process. The materials of the first ground segment 151 and the fourth ground segment 154 can be the same as the materials of the first signal routing segment 41, the bending segment 5, the third signal routing segment 43 and the fourth signal routing segment 44. For example, the first ground segment 151 and the fourth ground segment 154 can respectively include metals such as copper or aluminum.

[0101] The chip adapter board may further include a third routing layer 18, and the third routing layer 18 is located between the substrate 3 and the second routing layer 17. The third routing layer 18 may include a third dielectric layer 181 and a third ground segment 153, and the third dielectric layer 181 is located between the substrate 3 and the second dielectric layer 171, and the third ground segment 153 is arranged in the third dielectric layer 181. The third ground segment 153 is arranged in a different layer from the first ground segment 151 and the fourth ground segment 154. The material of the third ground segment 153 may be the same as the material of the first signal routing segment 41, the bending segment 5, the third signal routing segment 43 and the fourth signal routing segment 44. For example, the third ground segment 153 may include a metal such as copper or aluminum.

[0102] In this embodiment, the dielectric layer between the first signal routing segment 41 and the first ground segment 151 is the first dielectric layer 161, the dielectric layer between the third signal routing segment 43 and the third ground segment 153 is the second dielectric layer 171, and the dielectric layer between the fourth signal routing segment 44 and the fourth ground segment 154 is the first dielectric layer 161. The first dielectric layer 161 and the second dielectric layer 171 can be the same in thickness and material as the dielectric layer in the conventional technology, respectively, without increasing the thickness of the first dielectric layer 161 and the second dielectric layer 171 or selecting a dielectric material with a low dielectric constant, thereby avoiding the problems of research and development costs caused by new processes and new materials.

[0103] In some embodiments, when the transmission signal line 4 includes the first signal routing segment 41, the bending segment 5, the fifth signal routing segment 45, the third connection structure 9 and the first through-hole structure 10, as shown in FIG. Figure 6 As shown, the transmission ground line 15 may include a first ground line segment 151 and a fifth ground line segment 155. The first ground line segment 151 is arranged corresponding to the first signal routing segment 41, and the first ground line segment 151 is located between the first signal routing segment 41 and the substrate 3. The fifth ground line segment 155 is arranged corresponding to the fifth signal routing segment 45, and the fifth ground line segment 155 is located between the fifth signal routing segment 45 and the substrate 3.

[0104] The chip adapter board may also include a third routing layer 18, and the third routing layer 18 is located between the substrate 3 and the first routing layer 16. The third routing layer 18 may include a third dielectric layer 181, a first ground segment 151 and a fifth ground segment 155, and the third dielectric layer 181 is located between the substrate 3 and the first dielectric layer 161, and the first ground segment 151 and the fifth ground segment 155 are arranged in the third dielectric layer 181 in the same layer. The first through-hole structure 10 also penetrates the third dielectric layer 181, that is, the first through-hole structure 10 penetrates the substrate 3 and the third dielectric layer 181, and is respectively connected to the third connection structure 9 and the second port 2. The first ground segment 151 and the fifth ground segment 155 can be made and formed by the same process. The materials of the first ground segment 151 and the fifth ground segment 155 can be the same as those of the first signal routing segment 41, the bending segment 5 and the fifth signal routing segment 45. For example, the first ground segment 151 and the fifth ground segment 155 can respectively include metals such as copper or aluminum.

[0105] In this embodiment, the dielectric layer between the first signal routing segment 41 and the first ground segment 151 is the first dielectric layer 161, and the dielectric layer between the fifth signal routing segment 45 and the fifth ground segment 155 is also the first dielectric layer 161. The first dielectric layer 161 can be the same in thickness and material as the dielectric layer in conventional technology, without increasing the thickness of the first dielectric layer 161 or selecting a dielectric material with a low dielectric constant, thereby avoiding the problems of research and development costs caused by new processes and new materials.

[0106] In some embodiments, when the transmission signal line 4 includes the first signal routing segment 41, the bending segment 5, the fourth connection structure 11, the sixth signal routing segment 46, the fifth connection structure 12 and the second through-hole structure 13, as shown in FIG. Figure 8 As shown, the transmission ground line 15 includes a first ground line segment 151 and a sixth ground line segment 156. The first ground line segment 151 is arranged corresponding to the first signal routing segment 41, and the first ground line segment 151 is located between the first signal routing segment 41 and the substrate 3. The sixth ground line segment 156 is arranged corresponding to the sixth signal routing segment 46, and the sixth ground line segment 156 is located between the sixth signal routing segment 46 and the substrate 3.

[0107] The first ground segment 151 and the sixth ground segment 156 are arranged in different layers. The first ground segment 151 can be located in the second routing layer 17, that is, the second routing layer 17 can include the second dielectric layer 171, the first ground segment 151 and the sixth signal routing segment 46, and the first ground segment 151 and the sixth signal routing segment 46 are arranged in the same layer between the second dielectric layer 171 and the first dielectric layer 161. The first ground segment 151 and the sixth signal routing segment 46 can be manufactured and formed by the same process. The material of the first ground segment 151 can be the same as that of the first signal routing segment 41, the bending segment 5 and the sixth signal routing segment 46. For example, the first ground segment 151 can include metals such as copper or aluminum.

[0108] The chip adapter board may also include a third routing layer 18, which is located between the substrate 3 and the second routing layer 17. The third routing layer 18 may include a third dielectric layer 181 and a sixth ground segment 156, the third dielectric layer 181 is located between the substrate 3 and the second dielectric layer 171, and the sixth ground segment 156 is arranged in the third dielectric layer 181. The second through-hole structure 13 also penetrates the third dielectric layer 181, that is, the second through-hole structure 13 penetrates the substrate 3 and the third dielectric layer 181, and is respectively connected to the fifth connection structure 12 and the second port 2. The material of the sixth ground segment 156 may be the same as that of the first signal routing segment 41, the bending segment 5 and the sixth signal routing segment 46. For example, the sixth ground segment 156 may include a metal such as copper or aluminum.

[0109] In this embodiment, the dielectric layer between the first signal routing segment 41 and the first ground segment 151 is the first dielectric layer 161, and the dielectric layer between the sixth signal routing segment 46 and the sixth ground segment 156 is the second dielectric layer 171. The first dielectric layer 161 and the second dielectric layer 171 can be the same in thickness and material as the dielectric layer in the conventional technology, respectively, without increasing the thickness of the first dielectric layer 161 and the second dielectric layer 171 or selecting a dielectric material with a low dielectric constant, thereby avoiding the problems of research and development costs caused by new processes and new materials.

[0110] In some embodiments, the bending segment 5 includes at least one of a spiral bending segment and a serpentine bending segment. The bending segment 5 extends alternately along the first direction X and the second direction Y. Figure 2 , Figure 4 , Figure 7 and Fig. 9 As shown, the first direction X may include an up-down direction, and the second direction Y may include a left-right direction. The first direction X and / or the second direction Y in which the bending section 5 extends are different, so that the bending shapes of the bending section 5 are different.

[0111] like Figure 4 and Fig. 9 As shown, the bending section 5 can be a spiral bending section. For example, the bending section 5 first extends upward from the first end 51, and then extends to the right, downward, left, upward, right, and downward to the second end 52 in sequence, forming a spiral bending section. The second end 52 of the bending section 5 is surrounded by the inner side of the bending section 5, and the first end 51 of the bending section 5 is located on the outer side of the bending section 5.

[0112] like Figure 2 and Figure 7 As shown, the bending section 5 can be a serpentine bending section. For example, the bending section 5 first extends upward from the first end 51, and then extends to the right, downward, right, upward, right, downward, right, upward, right, and downward to the second end 52 in sequence, forming a serpentine bending section. The first end 51 and the second end 52 of the bending section 5 are respectively located on opposite sides of the second direction Y of the bending section 5.

[0113] It should be noted that the bending section 5 may also be in other bending shapes, as long as the bending section 5 can constitute an inductor and meet the actual requirements of impedance matching between the transmission signal line 4 and the first port 1 and the second port 2, and no specific limitation is made here.

[0114] To summarize, according to the chip adapter board provided in the embodiment of the present application, a bending section 5 is set in the transmission signal line 4 between the first port 1 and the second port 2, and the inductor formed by the bending section 5 is connected in series on the routing path of the transmission signal line 4, so as to improve the characteristic impedance of the transmission signal line 4, thereby improving the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2, reducing the reflection and loss of the signal during the transmission process, improving the integrity of the signal, realizing high-speed transmission of the signal, and integrating the inductor with the transmission signal line 4 to reduce the process difficulty and cost.

[0115] Correspondingly, an embodiment of the present application also provides a chip packaging structure.

[0116] like Fig.11As shown, the chip packaging structure provided in the embodiment of the present application includes a first chip 200 and a chip adapter 100, and the first chip 200 is connected to the first port 1 in the chip adapter 100. The chip adapter 100 may be the chip adapter in the above embodiment, and will not be described in detail here.

[0117] The first port 1 may be located at one side of the chip adapter 100 along the thickness direction H, and the first chip 200 may be located at one side of the chip adapter 100 close to the first port 1 and connected to the first port 1. The first chip 200 may include a high-speed communication port, which is a port for realizing high-speed data transmission. The high-speed communication port of the first chip 200 may be connected to the first port 1 to transmit data and signals with other chips and / or external devices through the transmission signal line 4 of the chip adapter 100.

[0118] In some embodiments, the chip packaging structure may further include a first soldering portion, and the first port 1 may be connected to the first chip 200 via the first soldering portion. The first soldering portion may include a BGA (Ball Grid Array).

[0119] The chip adapter board 100 in this embodiment is provided with a bending section 5 in the transmission signal line 4. The inductor formed by the bending section 5 is connected in series on the routing path of the transmission signal line 4, thereby improving the characteristic impedance of the transmission signal line 4, thereby improving the impedance matching between the transmission signal line 4 and the high-speed communication port of the first chip 200, reducing reflection and loss of the signal during transmission, improving the integrity of the signal, and realizing high-speed signal transmission between the first chip 200 and other chips and / or external devices.

[0120] In some embodiments, the first port 1 and the second port 2 are located on the same side of the chip interposer 100 , and the chip package structure further includes a second chip 300 , which is connected to the second port 2 in the chip interposer 100 .

[0121] The second chip 300 may be located on a side of the chip adapter 100 close to the second port 2 and connected to the second port 2. The first chip 1 and the second chip 2 may be located on the same side of the chip adapter 100. The second chip 300 may include a high-speed communication port, which is a port for realizing high-speed data transmission. The high-speed communication port of the second chip 300 may be connected to the second port 2 to perform data and signal transmission with the first chip 200 through the transmission signal line 4 of the chip adapter 100.

[0122] In some embodiments, the chip packaging structure may further include a second soldering portion, and the second port 2 may be connected to the second chip 300 via the second soldering portion. The second soldering portion may include a BGA.

[0123] The chip adapter board 100 in this embodiment is provided with a bending section 5 in the transmission signal line 4. The inductor formed by the bending section 5 is connected in series on the routing path of the transmission signal line 4 to improve the characteristic impedance of the transmission signal line 4, thereby improving the impedance matching between the transmission signal line 4 and the high-speed communication ports of the first chip 200 and the second chip 300, reducing reflection and loss of the signal during transmission, improving the integrity of the signal, and realizing high-speed signal transmission between the first chip 200 and the second chip 300.

[0124] In some embodiments, the first port 1 and the second port 2 are located on opposite sides of the chip adapter 100 in the thickness direction H, the first chip 200 is connected to the first port 1 in the chip adapter 100 , and the second port 2 is connected to an external device.

[0125] The first port 1 may be located at one side of the chip adapter 100 along the thickness direction H. The second port 2 may be located at a side of the chip adapter 100 away from the first port 1. The external device may be located at a side of the chip adapter 100 close to the second port 2 and connected to the second port 2. The external device and the first chip 200 may be located at opposite sides of the chip adapter 100 along the thickness direction H. The first chip 200 transmits data and signals with the external device through the transmission signal line 4 of the chip adapter 100.

[0126] In some embodiments, the chip packaging structure may further include a third welding portion, a substrate 14, and a fourth welding portion. The substrate 14 is located on the side of the chip adapter 100 away from the first port 1, the third welding portion is located between the chip adapter 100 and the substrate 14, and the fourth welding portion is located on the side of the substrate 14 away from the chip adapter 100. An external device may be located on the side of the fourth welding portion away from the substrate 14. The second port 2 of the chip adapter 100 may be connected to an external device through the third welding portion, the connection structure in the substrate 14, and the fourth welding portion. The third welding portion and the fourth welding portion may include BGA, respectively.

[0127] The chip adapter board 100 in this embodiment is provided with a bending section 5 in the transmission signal line 4. The inductor formed by the bending section 5 is connected in series on the routing path of the transmission signal line 4 to improve the characteristic impedance of the transmission signal line 4, thereby improving the impedance matching between the transmission signal line 4 and the high-speed communication port of the first chip 200 and the external device, reducing the reflection and loss of the signal during the transmission process, improving the integrity of the signal, and realizing high-speed signal transmission between the first chip 200 and the external device.

[0128] It should be noted that the chip adapter board 100 may also include multiple ports, not limited to the first port 1 and the second port 2 mentioned above, and the chip package structure may also include multiple chips, not limited to the first chip 200 and the second chip 300 mentioned above. Different ports on the chip adapter board 100 can be connected to different chips in the chip package structure and / or different external devices.

[0129] In summary, according to the chip packaging structure provided by the embodiment of the present application, by setting a bending section 5 in the transmission signal line 4 between the first port 1 and the second port 2 of the chip adapter board 100, the inductor formed by the bending section 5 is connected in series on the routing path of the transmission signal line 4, thereby improving the characteristic impedance of the transmission signal line 4, thereby improving the impedance matching between the transmission signal line 4 and the first port 1 and the second port 2, reducing the reflection and loss of the signal transmitted in the routing of the chip packaging structure, improving the signal integrity, and realizing high-speed transmission of signals between chips and / or between chips and external devices. The inductor is integrated with the transmission signal line 4, reducing the process difficulty and cost of the chip packaging structure.

[0130] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0131] In the description of the present application, “plurality” means two or more.

[0132] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0133] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip adapter board, characterized in that: include: First port; Second port; A transmission signal line connected between the first port and the second port; The transmission signal line includes a bending section, and the bending section constitutes an inductor.

2. The chip transfer board according to claim 1, characterized in that: The transmission signal line further includes at least two signal routing segments, the bending segment is connected in series between two of the signal routing segments, and the bending segment is arranged on the same layer as at least one of the signal routing segments.

3. The chip transfer board according to claim 2, characterized in that: The chip adapter board further includes a substrate and a first wiring layer, wherein the first wiring layer is located on one side of the substrate, and the first port is located on a side of the first wiring layer away from the substrate; The at least two signal routing segments include a first signal routing segment, the first routing layer includes the first signal routing segment and the bending segment arranged in the same layer, and the first signal routing segment is connected between the first port and a first end of the bending segment.

4. The chip transfer board according to claim 3, characterized in that: The second port is located on a side of the first wiring layer away from the substrate, and the first end and the second end of the bending section are respectively located on two opposite sides of the bending section; The at least two signal routing segments further include a second signal routing segment, the first routing layer further includes the second signal routing segment disposed in the same layer as the bending segment, and the second signal routing segment is connected between the second end of the bending segment and the second port.

5. The chip transfer board according to claim 3, characterized in that: The chip adapter board further includes a second routing layer, which is located between the substrate and the first routing layer; the second port is located on a side of the first routing layer away from the substrate, the second end of the bending section is located on the inner side of the bending section, and the first end of the bending section is located on the outer side of the bending section; The at least two signal routing segments further include a third signal routing segment and a fourth signal routing segment, the second routing layer includes the third signal routing segment, and the first routing layer further includes the fourth signal routing segment disposed on the same layer as the bending segment; The transmission signal line also includes a first connection structure and a second connection structure that respectively penetrate the first routing layer, and the first connection structure, the third signal routing segment, the second connection structure and the fourth signal routing segment are sequentially connected between the second end of the bending segment and the second port.

6. The chip transfer board according to claim 3, characterized in that: The second port is located at a side of the substrate away from the first wiring layer, and the first end and the second end of the bending section are respectively located at two opposite sides of the bending section; The at least two signal routing segments further include a fifth signal routing segment, and the first routing layer further includes the fifth signal routing segment disposed in the same layer as the bending segment; The transmission signal line also includes a third connection structure penetrating the first routing layer and a first through-hole structure penetrating the substrate, and the fifth signal routing segment, the third connection structure and the first through-hole structure are sequentially connected between the second end of the bending segment and the second port.

7. The chip transfer board according to claim 3, characterized in that: The chip adapter board further includes a second routing layer, which is located between the substrate and the first routing layer; the second port is located on a side of the substrate away from the first routing layer, the second end of the bending section is located on the inner side of the bending section, and the first end of the bending section is located on the outer side of the bending section; The at least two signal routing segments further include a sixth signal routing segment, and the second routing layer includes the sixth signal routing segment; The transmission signal line also includes a fourth connection structure running through the first routing layer, a fifth connection structure running through the second routing layer, and a second through-hole structure running through the substrate, and the fourth connection structure, the sixth signal routing segment, the fifth connection structure, and the second through-hole structure are sequentially connected between the second end of the bending segment and the second port.

8. The chip transfer board according to claim 3, characterized in that: The chip adapter board also includes: The transmission ground line comprises a ground line segment arranged corresponding to the signal line segment, and the ground line segment is located between the corresponding signal line segment and the substrate.

9. The chip transfer board according to any one of claims 1, characterized in that: The bending section includes at least one of a spiral bending section and a serpentine bending section.

10. A chip packaging structure, characterized in that: comprising a first chip and a chip adapter board as claimed in any one of claims 1 to 9; The first chip is connected to a first port in the chip adapter board.

11. The chip packaging structure according to claim 10, characterized in that: The first port and the second port are located on the same side of the chip adapter board. The chip packaging structure further includes a second chip connected to the second port in the chip adapter board.

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