A Type-C interface power surge protection design method

Abstract

The present invention relates to the field of anti-electromagnetic interference technology, and provides a method for designing surge protection for a Type-C interface power supply. The method comprises a Type-C interface power supply, which comprises a Type-C interface, a transient voltage suppressor diode D4, and a chip end; the method comprises: obtaining an initial circuit schematic diagram and surge protection requirements of the Type-C interface, and determining the rated voltage, rated power, and response time of the Type-C interface; determining a first electrical characteristic of the Type-C interface generating low-voltage surge interference based on the rated voltage and rated power, and configuring multiple TVS transient voltage suppressor diodes at the output end of the Type-C interface to generate a first circuit schematic diagram; obtaining a second electrical characteristic after configuring the multiple TVS transient voltage suppressor diodes, and configuring multiple common-mode inductor filters at the output end of the multiple TVS transient voltage suppressor diodes to generate a second circuit schematic diagram; generating a Type-C interface to be verified based on the second circuit schematic diagram, and performing a low-voltage surge test.

Description

Technical Field

[0001] The present invention relates to the technical field of Type-C interface technology, and in particular to a method for designing power surge protection for a Type-C interface. Background Art

[0002] With the continuous development of electronic devices, the Type-C interface has been widely used in various electronic devices due to its advantages such as high-speed data transmission and fast charging. However, electronic devices may be affected by power surges during use, especially in the field of fast charging applications. As fast charging power increases (currently reaching up to 240W), the surge generated by the corresponding Type-C interface when plugging and unplugging is even greater, which can easily cause device damage.

[0003] Currently, the most common method for Type-C interface power surge protection is to add protective devices to the power network and signal network at the interface. Although this method can provide surge protection to a certain extent, its protection capability for low-voltage surges is limited. It can usually only provide surge voltage protection of around 30V for the power network and 20V for the signal network, and cannot effectively protect against higher surge voltages. Summary of the Invention

[0004] The present invention proposes a Type-C interface power surge protection design method to solve the problem that the existing Type-C interface power surge protection method is to add protection devices to the power network and signal network at the interface. Although this method can provide surge protection to a certain extent, its protection capability for low-voltage surges is limited. It can usually only provide surge voltage protection of about 30V for the power network and 20V for the signal network, and cannot effectively protect against higher surge voltages.

[0005] The present invention proposes a method for designing surge protection for a Type-C interface power supply, including a Type-C interface power supply, wherein the Type-C interface power supply comprises a Type-C interface, a transient suppression diode D4, and a chip end; wherein the input end of the Type-C interface is connected to the transient suppression diode D4, and the output end of the Type-C interface is connected to the chip end. The design method includes:

[0006] Obtain the initial circuit schematic and surge protection requirements for the Type-C interface, and determine the rated voltage, rated power, and response time of the Type-C interface;

[0007] Determine a first electrical characteristic of low-voltage surge interference generated by the Type-C interface based on the rated voltage and rated power, configure multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, and generate a first circuit schematic.

[0008] Obtaining a second electrical characteristic after configuring multiple TVS transient voltage suppression diodes, and configuring multiple common-mode inductor filters at output ends of the multiple TVS transient voltage suppression diodes to generate a second circuit schematic;

[0009] According to the second circuit schematic, generate a Type-C interface to be verified and perform a low-voltage surge test;

[0010] When the test results meet the surge protection requirements, the Type-C interface corresponding to the second circuit schematic is used as the target Type-C interface.

[0011] Furthermore, when configuring multiple TVS transient voltage suppressor diodes at the output end of the Type-C interface, the method further includes:

[0012] Configure multiple linear resistors before the TVS transient voltage suppression diode.

[0013] Furthermore, when configuring multiple TVS transient voltage suppressor diodes at the output end of the Type-C interface, the method further includes:

[0014] An inductive filter L6 is arranged before the TVS diode D4, and a target TVS diode D5 is arranged before the inductive filter L6.

[0015] Furthermore, the first electrical characteristic is the original electrical characteristic of the Type-C interface before any surge protection design is performed;

[0016] The first electrical characteristic includes:

[0017] Voltage level when the Type-C interface is working normally;

[0018] The maximum power that the Type-C port can handle under normal operating conditions;

[0019] The response speed of the Type-C interface to voltage changes;

[0020] Abnormal behavior of the Type-C interface under low-voltage surge interference, including voltage spikes and current changes.

[0021] Furthermore, the second electrical characteristic refers to the electrical characteristic after multiple TVS transient voltage suppression diodes are configured at the output end of the Type-C interface;

[0022] The second electrical characteristics include: breakdown voltage characteristics of the TVS diode, power characteristics of the TVS diode, response time of the TVS diode, impedance characteristics of the circuit, and filtering strength of the circuit.

[0023] Furthermore, obtaining the initial circuit schematic and surge protection requirements of the Type-C interface also includes:

[0024] Analyze the initial circuit schematic of the Type-C interface circuit, divide it into multiple circuit functional groups, and determine the electrical utility characteristics of each circuit functional group; the electrical utility characteristics include the connection type defined by the interface electrical characteristics;

[0025] Determine the electrical similarity of multiple circuit functional groups based on electrical utility characteristics;

[0026] Based on electrical similarity, electrical function groups with electrical similarity higher than a preset threshold are divided into electrical collection groups;

[0027] Determining electrical correlation information of each electrical combination group based on electrical utility characteristics and electrical similarity;

[0028] Technically associate the electrical correlation information with the corresponding circuit function group to determine the Type-C interface electrical correlation data;

[0029] Based on the electrical data and surge protection requirements of the Type-C interface, low-voltage surge interference is introduced to determine the circuit components of the original circuit schematic of the Type-C interface to be modified.

[0030] Furthermore, the circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined, further comprising:

[0031] Create an analog auxiliary cell library containing TVS diodes, common-mode inductors, and filter capacitors;

[0032] In the RTL design phase, the digital standard cell library and analog auxiliary cell library are used to design the mixed digital-analog circuit of the Type-C interface;

[0033] Based on the mixed digital-analog circuit, the surge protection status of the Type-C interface is determined by the TVS diodes on the power input and signal lines of the Type-C interface, and the interference intensity under different component configurations is determined. The interference intensity includes differential mode interference intensity and common mode interference intensity.

[0034] Based on the interference intensity, digital backend tools are used to automatically generate the initial layout of the Type-C interface circuit based on the RTL design;

[0035] Perform physical verification and simulation on the generated initial layout to simulate surge voltage events and ensure the protection strength of the TVS diode.

[0036] Furthermore, generating a Type-C interface to be verified according to the second circuit schematic and performing a low-voltage surge test includes:

[0037] Set the surge generator so that it outputs a surge waveform that meets the actual application conditions;

[0038] Connect the Type-C port to be verified to the surge generator;

[0039] Start the surge generator and apply a surge signal to the Type-C interface to be verified in blocking mode and conducting mode.

[0040] Use an oscilloscope and voltage and current probes to monitor the operating data of the device under test during the surge process;

[0041] Based on the operating data, the voltage and current stress waveforms in blocking mode and conducting mode are compared to analyze the response characteristics of the Type-C interface to be verified in different states.

[0042] Furthermore, in the blocking mode:

[0043] Setting a controllable power supply system so that it outputs a first voltage stress waveform that meets actual application conditions;

[0044] Put the Type-C interface to be verified into a blocked state;

[0045] Starting the controllable power supply system and applying a first voltage stress to the Type-C interface to be verified;

[0046] Use an oscilloscope and a voltage probe to monitor the voltage waves at both ends of the Type-C interface to be verified and obtain blocking operation data.

[0047] Furthermore, in the conduction mode:

[0048] Setting a controllable power supply system so that it outputs a second current stress waveform that meets actual application conditions;

[0049] Put the Type-C interface to be verified into the conductive state;

[0050] Start the controllable power system and apply a second current stress to the Type-C interface to be verified;

[0051] Use an oscilloscope and current probe to monitor the current waveform at both ends of the Type-C interface to be verified and obtain conduction operation data.

[0052] The beneficial effects of the present invention are:

[0053] This application uses only TVS as the core protection device, which simplifies the traditional three-level protection structure and reduces costs. By connecting multiple TVS in parallel to improve the current flow capacity, combined with common-mode inductors to suppress high-frequency noise, the defects of MOV / GDT are avoided in low-voltage, high-power Type-C scenarios. Reliable parallel connection is achieved through TVS selection (low dynamic resistance), layout-optimized symmetrical routing, and active current sharing control, which can break through the current limitation of traditional single TVS and replace some functions of MOV. In addition, the common-mode inductor can play a decoupling role in the surge path, delaying the surge rise time, reducing the transient pressure of the TVS, and forming a "inductor buffer + TVS clamp" collaborative protection mechanism. Therefore, the TYPE-C interface obtained under the design method of this application can not only suppress noise, but also assist in surge energy distribution, which may reduce the number or specification requirements of TVS, reduce costs, and realize current sharing control of TVS parallel connection on the chip side.

[0054] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0055] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0057] In the attached figure:

[0058] Figure 1 This is a flow chart of a method for designing a Type-C interface power surge protection method according to an embodiment of the present invention;

[0059] Figure 2 This is a schematic diagram of a first surge protection design circuit for a Type-C interface power supply according to an embodiment of the present invention;

[0060] Figure 3 This is a schematic diagram of the second surge protection design circuit for the Type-C interface power supply in an embodiment of the present invention. DETAILED DESCRIPTION

[0061] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0062] Through theoretical analysis, experimental comparison, and combined with actual design and rectification experience, this paper determines the low-voltage surge voltage level (100V) directly injected into the Type-C port to ensure the normal use of the conventional fast charging mode (≤100W). At the same time, the protection circuit of the Type-C port is optimized to improve the protection capability of the Type-C port.

[0063] Based on the mechanism of surge interference, while utilizing the discharge and clamping functions of the universal protection device TVS transient voltage suppression diode, an inductive filter's de-energizing mechanism and secondary clamping discharge measures are additionally added to the power supply end. Due to the need to take signal integrity into account on the signal end, only a small resistor is connected in series as an additional transient suppression measure, thereby improving the protection capability of the Type-C port at a low cost. The power supply end has low anti-interference performance, which causes abnormal charging function when initially injected with a 30V surge, but can still charge normally when increased to a 100V surge. The signal end may cause data link disconnection when initially injected with a 20V surge, but can still communicate normally when increased to a 50V surge.

[0064] The purpose of the present invention is to provide a Type-C interface power supply surge protection design method proposed by the present invention, including a Type-C interface power supply, the Type-C interface power supply consisting of a Type-C interface, a transient suppression diode D4 and a chip end; wherein the input end of the Type-C interface is connected to the transient suppression diode D4, and the output end of the Type-C interface is connected to the chip end. The design method includes:

[0065] Obtain the initial circuit schematic and surge protection requirements for the Type-C interface, and determine the rated voltage, rated power, and response time of the Type-C interface;

[0066] Determine a first electrical characteristic of low-voltage surge interference generated by the Type-C interface based on the rated voltage and rated power, configure multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, and generate a first circuit schematic.

[0067] Obtaining a second electrical characteristic after configuring multiple TVS transient voltage suppression diodes, and configuring multiple common-mode inductor filters at output ends of the multiple TVS transient voltage suppression diodes to generate a second circuit schematic;

[0068] Based on the second circuit schematic, a Type-C interface to be verified is generated, and a low-voltage surge test is performed. The PCB layout of the Type-C interface to be verified is generated through an EDA tool, and then converted and simulated into the Type-C interface to be verified.

[0069] When the test results meet the surge protection requirements, the Type-C interface corresponding to the second circuit schematic is used as the target Type-C interface.

[0070] like Figure 1 and Figure 2 As shown, Figure 2 This figure shows the result of the design of the present invention. Based on the characteristics of surge interference—a transient pulse interference signal—during testing, it was directly injected into the Type-C port through a CDN (coupling / decoupling network). C1 and C2 are filter capacitors for the power port. TVS transient voltage suppressor diodes D1-D3 are connected to the ground of the signal trace at the port (for ease of installation, two-way and four-way TVS devices are used, each containing two or four independent TVS diodes). These devices can be used to bypass transient interference and clamp the voltage on the signal line to a low level.

[0071] The back-end common-mode inductor filters L1-L5 also further suppress residual common-mode interference. A junction capacitor and high-power transient suppression diode D4 are added to the power supply for surge protection. This design ensures 50V surge protection (low-voltage surge direct injection) for the Type-C power port and 30V surge protection for the signal port.

[0072] TVS is typically used as the last level of protection, in conjunction with MOVs and gas discharge tubes (GDTs). This solution uses only TVS as the core protection component, simplifying the traditional three-stage protection structure and reducing costs. An MOV is a voltage-sensitive resistor. When the voltage exceeds its threshold (varistor voltage), its impedance drops sharply, allowing it to discharge large currents. A GDT conducts through internal gas ionization, allowing it to withstand surge currents of tens of kiloamperes and presents an extremely low impedance (close to a short circuit) when conducting. In this application, multiple TVS resistors are connected in parallel to increase current capacity, while common-mode inductors are used to suppress high-frequency noise, mitigating the shortcomings of MOVs and GDTs in low-voltage, high-power Type-C scenarios. Reliable parallel connection is achieved through TVS selection (low dynamic resistance), optimized symmetrical routing, and active current sharing control. This overcomes the current limitations of a traditional single TVS and replaces some of the functions of an MOV. Furthermore, the common-mode inductor provides decoupling in the surge path, slowing the surge rise time and reducing the transient stress of the TVS, creating a synergistic protection mechanism of "inductor buffering + TVS clamping." Therefore, the TYPE-C interface obtained by the design method of this application can not only suppress noise but also assist in surge energy distribution, which may reduce the number or specification requirements of TVS and reduce costs. In this application, the chip side implements current sharing control of TVS parallel connection.

[0073] As an embodiment of the present invention, when configuring multiple TVS transient voltage suppressor diodes at the output end of the Type-C interface, the method further includes:

[0074] Configure multiple linear resistors before the TVS transient voltage suppression diode (such as Figure 3 (in Chinese: R1, R2, R3).

[0075] In practical implementation, MOVs / GDTs, as the front-end circuitry, absorb the majority of surge energy. This embodiment uses a resistor + TVS combination to achieve similar hierarchical protection: the resistor absorbs primary energy through coarse current limiting, while the TVS acts as a fine clamp to protect downstream circuitry. In practical implementation, the resistor's value and power rating must be customized based on the Type-C current (e.g., 5A / 20V) to avoid excessive voltage drop or temperature rise during normal operation. Alternatively, a potentiometer or digitally controlled resistor can be used for automatic resistance adjustment to adapt to dynamic current flow.

[0076] As an embodiment of the present invention, when configuring multiple TVS transient voltage suppressor diodes at the output end of the Type-C interface, the method further includes:

[0077] An inductive filter L6 is arranged before the TVS diode D4, and a target TVS diode D5 is arranged before the inductive filter L6.

[0078] like Figure 3 First, add linear resistors R1-R3 to the signal line at the port (for ease of installation, a resistor array is used, with 2-4 resistors in each array). The resistance of R1-R3 is 2.2Ω. The current limiting effect of the resistors can effectively reduce transient large current surge interference. Then, the transient suppression diodes D1-D3 at the next stage at the port can further bypass and discharge transient interference and clamp the voltage on the signal line to a low level. The common-mode inductor filters L1-L5 at the final end can also further suppress residual common-mode interference, thereby increasing the surge protection of the signal network end from 30V to 50V.

[0079] As for the power signal network, on the basis of the original D4, an inductive filter L6 is first added to play a decoupling role. At the same time, due to its high-frequency and high-impedance characteristics, it also has a certain inhibitory effect on transient surges. Then a protective device D5 is added at the back of this device to further clamp and discharge the surge, thereby increasing the surge protection capability of the power port from 50V to 100V.

[0080] As an embodiment of the present invention: the first electrical characteristic is the original electrical characteristic of the Type-C interface before any surge protection design is performed;

[0081] The first electrical characteristic includes:

[0082] Voltage level when the Type-C interface is working normally;

[0083] The maximum power that the Type-C port can handle under normal operating conditions;

[0084] The response speed of the Type-C interface to voltage changes;

[0085] Abnormal behavior of the Type-C interface under low-voltage surge interference, including voltage spikes and current changes.

[0086] Existing surge protection solutions (such as MOV+TVS combinations) typically select components based on standard surge models (e.g., 8 / 20μs waveform, 2Ω coupling impedance), without considering the differences in electrical characteristics of specific interfaces. For example, the high power (100W PD) and high-frequency signal transmission of the Type-C interface result in parasitic parameters (such as inductance and capacitance) in the surge path that differ from those of traditional power interfaces, yet traditional solutions haven't optimized these parameters.

[0087] This application uses the first electrical characteristics (original electrical characteristics) to provide a customized basis for design. Traditional solutions directly reference standard surge parameters simply to comply with the standard. This application dynamically adjusts based on the actual dynamic characteristics of the interface, making it more suitable for Type-C high-power, high-frequency scenarios (i.e., high-power scenarios). A second improvement is then implemented based on the actual first electrical characteristics to determine the specific structure of the target Type-C interface. This enables dynamic iterative characteristic comparison and updates, reducing design costs.

[0088] As an embodiment of the present invention: the second electrical characteristic refers to the electrical characteristic after multiple TVS transient voltage suppression diodes are configured at the output end of the Type-C interface;

[0089] The second electrical characteristics include: breakdown voltage characteristics of the TVS diode, power characteristics of the TVS diode, response time of the TVS diode, impedance characteristics of the circuit, and filtering strength of the circuit.

[0090] In practical implementation, existing solutions typically focus solely on individual TVS parameters (such as breakdown voltage and peak power), ignoring the dynamic synergistic effects of multiple TVS devices connected in parallel (such as impedance stacking and response time variations). The response time of a single TVS is 1ns, but parasitic parameters can cause an overall response delay of up to 5ns when multiple TVS devices are connected in parallel. Uneven power distribution within the TVS can also lead to localized overheating, but traditional designs fail to quantify these risks.

[0091] This application considers the comprehensive electrical characteristics of parallel connection. By utilizing various electrical characteristic parameters, a gradient breakdown voltage design (e.g., 24V, 24.5V, and 25V) is implemented for multiple TVS resistors. This achieves graded discharge of surge energy and avoids current concentration caused by simultaneous conduction. For example, when the surge voltage reaches 24V, the first TVS resistor conducts first; when the voltage continues to rise to 24.5V, the second TVS resistor joins the current flow, and so on. This reduces the transient stress on a single TVS resistor and extends device life. Distributed optimization of power characteristics: Based on the power distribution data in the second electrical characteristic (e.g., each TVS resistor carries 30% of the total energy), the TVS resistor layout is dynamically adjusted (e.g., placing high-power branches closer to interface pins) to reduce the risk of thermal concentration. The junction capacitance of multiple TVS resistors (e.g., 50pF per resistor) and the PCB trace inductance (e.g., 2nH) form a controllable LC filtering network, providing impedance matching within the surge frequency band (1MHz-100MHz). To address latency, this application utilizes the timing of multiple TVS resistors on the chip, taking advantage of small differences in TVS response time (e.g., a 0.5ns step difference), to design a stepped response mechanism. The first TVS resistor (the fastest responding) handles the initial surge spike, while subsequent TVS resistors respond sequentially to cover the long tail of the surge waveform. While this increases response time, it improves the Type-C interface's surge tolerance.

[0092] As an embodiment of the present invention, the obtaining of the initial circuit schematic diagram and surge protection requirements of the Type-C interface further includes:

[0093] Analyze the initial circuit schematic of the Type-C interface circuit, divide it into multiple circuit functional groups, and determine the electrical utility characteristics of each circuit functional group; the electrical utility characteristics include the connection type defined by the interface electrical characteristics;

[0094] Determine the electrical similarity of multiple circuit functional groups based on electrical utility characteristics;

[0095] Based on electrical similarity, electrical function groups with electrical similarity higher than a preset threshold are divided into electrical collection groups;

[0096] Determining electrical correlation information of each electrical combination group based on electrical utility characteristics and electrical similarity;

[0097] Technically associate the electrical correlation information with the corresponding circuit function group to determine the Type-C interface electrical correlation data;

[0098] Based on the electrical data and surge protection requirements of the Type-C interface, low-voltage surge interference is introduced to determine the circuit components of the original circuit schematic of the Type-C interface to be modified.

[0099] In the above technical solution:

[0100] In existing technologies, surge protection design often relies on engineers' experience, manually adding TVS or MOV at key nodes (such as VBUS and CC lines), lacking systematic circuit analysis and protection planning. This can lead to over-design and protection vulnerabilities. For example, redundantly configuring protection components in low-risk areas increases cost and volume, while ignoring surge risks in atypical paths (such as ESD coupling to data lines). Furthermore, traditional technologies often design circuits based on requirements, optimizing protection designs based on circuit functional group division and electrical similarity, resulting in an inadequate match between device layout and interface characteristics. For example, the electrical characteristics of the Type-C interface's power supply group (VBUS) and signal group (CC / SBU) differ significantly, but traditional solutions do not specifically design differentiated protection strategies.

[0101] This application aims to decompose the Type-C interface circuit into multiple functional groups (such as power supply, signal, and grounding groups) and cluster them based on similarity of electrical utility characteristics (such as voltage level, impedance, and noise sensitivity). This approach allows for uniformly configured protection components only for highly similar functional groups (such as multiple VBUS power supply branches), avoiding duplication of design. Based on electrical correlation information (such as the common ground loop coupling path), common-mode inductors or TVSs are inserted at key nodes to block surge propagation. This electrical correlation data is combined with surge protection requirements to dynamically generate protection solutions. For example, if a functional group has high electrical similarity and a high surge coupling risk, a parallel multi-channel TVS solution is automatically assigned. If there is strong electromagnetic coupling between functional groups (such as high-frequency signal lines adjacent to power lines), a shielding layer or common-mode filter is inserted. Electrical similarity is calculated using Euclidean distance or cosine similarity to measure the differences in the electrical characteristics of functional components. A preset similarity threshold (such as 0.8) is set, and functional groups above this threshold are classified as the same electrical cluster. In actual implementation, electrical related information such as the coupling of the power supply group and the ground group through the PCB layer, the impedance difference between functional groups and the layout distance calculation are required.

[0102] As an embodiment of the present invention, the circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are further included:

[0103] Create an analog auxiliary cell library containing TVS diodes, common-mode inductors, and filter capacitors;

[0104] In the RTL design phase, the digital standard cell library and analog auxiliary cell library are used to design the mixed digital-analog circuit of the Type-C interface;

[0105] Based on the mixed digital-analog circuit, the surge protection status of the Type-C interface is determined by the TVS diodes at the power input and signal lines of the Type-C interface, and the differential-mode interference strength under different component configurations is determined. The interference strength includes differential-mode interference strength and common-mode interference strength.

[0106] Based on the interference intensity, digital backend tools are used to automatically generate the initial layout of the Type-C interface circuit based on the RTL design;

[0107] Perform physical verification and simulation on the generated initial layout to simulate surge voltage events and ensure the protection strength of the TVS diode.

[0108] The technical effects of the above technical solution are:

[0109] In existing solutions, analog protection components (TVS, common-mode chokes) and digital circuit design are typically completed in separate stages (e.g., digital logic design completed first, protection components manually added later). This makes it difficult to optimize protection component layout (for example, the distance between the TVS and high-speed signal lines affects impedance matching). Each modification to the protection scheme requires redrawing the layout, making automated verification impossible. Traditional methods rely on late-stage experimental testing (such as surge gun injection) to verify protection effectiveness, failing to predict performance through simulation early in the design process. This results in long development cycles and high costs.

[0110] This invention builds an analog auxiliary cell library containing specific circuit components (such as TVS diodes, common-mode inductors, and filter capacitors). These components are key components for power surge protection. During the register transfer level (RTL) design phase, the digital standard cell library and the analog auxiliary cell library are combined to design a mixed-analog circuit for the Type-C interface. This ensures that the circuit includes both digital logic and analog components for surge protection. Based on the designed mixed-analog circuit, the surge protection effect of TVS diodes on the power input and signal lines of the Type-C interface is analyzed, as well as the interface's protection status under differential-mode interference. By analyzing the circuit performance under different component configurations, the intensity of differential-mode interference is determined, which is crucial for evaluating the effectiveness of surge protection.

[0111] A digital backend tool automatically generates an initial layout for the Type-C interface circuit based on the RTL design. This is crucial for converting the circuit design into a physical layout. Physical and simulation verification of the generated initial layout ensures that the circuit layout complies with design rules. The protection strength of the TVS diode is tested by simulating surge voltage events. During this process, a multi-objective optimization function is introduced using the digital backend tool. During the layout generation phase, optimization objectives such as electrical, physical, and thermal targets are defined. A machine learning-based neural network model is then trained, taking as input the circuit functional grouping results, electrical similarity data, and interference strength. The output is the optimal layout constraints (such as the spacing between the TVS and data lines). Finally, an adaptive genetic algorithm is used to encode the location coordinates and connection relationships of the TVS and common-mode inductor into a genetic sequence. During simulation testing, specifically simulating surge voltage, a surge source is superimposed between VBUS and GND, or between the data lines (D+ / D-) and the metal casing. Hybrid simulation is then performed, including building nonlinear models of the TVS and common-mode inductor, extracting S-parameter models of the layout's parasitic parameters (tracing inductance and capacitance), calculating the TVS clamping response through time-domain simulation (SPICE), and verifying high-frequency resonance points through frequency-domain simulation (EM) to prevent self-oscillation. Finally, dynamic corrections are performed. If the simulation results indicate that the residual voltage exceeds the specified limit, the number of TVS resistors or the common-mode inductor value is automatically adjusted, and the layout is regenerated. If the resonant frequency is detected to fall within the surge frequency band, damping is inserted.

[0112] By using the analog auxiliary cell library and the digital standard cell library, you can quickly design and implement mixed-analog circuits, improving design efficiency. By accurately determining the surge protection status of components such as TVS diodes, you can optimize circuit design and improve protection effectiveness.

[0113] In actual implementation, analog auxiliary cell libraries (TVS, common-mode inductors, etc.) are called upon during the RTL design phase, making the protection components an integral part of the circuit design rather than a post-installation plugin. Calling them is done through hardware description language instructions or pre-defined APIs. For example, a TVS module is instantiated in Verilog code, and its electrical parameters (such as clamping voltage and junction capacitance) are defined. A mixed layout of digital standard cell libraries (such as logic gates and I / O cells) and analog cells optimizes the physical distance between signal paths and protection components. Component configuration is dynamically adjusted based on differential-mode and common-mode interference strength, forming a closed-loop design process. Surge models are injected into the mixed digital-analog circuit to calculate the interference strength. If differential-mode interference exceeds the specified value, the number of TVSs is increased or their dynamic resistance is reduced. If common-mode interference exceeds the specified value, a common-mode inductor is inserted or the grounding strategy is adjusted. Based on the optimization results, a physical layout including the protection components is automatically generated using digital backend tools (such as Cadence Innovus). During the physical verification phase, surge events (such as 8 / 20μs waveforms) are simulated to directly evaluate the TVS clamping effectiveness through simulation, replacing traditional laboratory testing and shortening the development cycle.

[0114] As an embodiment of the present invention, generating a Type-C interface to be verified according to the second circuit schematic and performing a low-voltage surge test includes:

[0115] Set the surge generator so that it outputs a surge waveform that meets the actual application conditions;

[0116] Connect the Type-C port to be verified to the surge generator;

[0117] Start the surge generator and apply a surge signal to the Type-C interface to be verified in blocking mode and conducting mode.

[0118] Use an oscilloscope and voltage and current probes to monitor the operating data of the device under test during the surge process;

[0119] Based on the operating data, the voltage and current stress waveforms in blocking mode and conducting mode are compared to analyze the response characteristics of the Type-C interface to be verified in different states.

[0120] In this application, a surge generator is configured to output conditions that simulate the actual application of a Type-C interface. This involves using a high-speed oscilloscope to capture surge events in real-world scenarios (hot plugging, protocol switching, and sudden load changes), monitoring the instantaneous current, determining characteristic parameters, and then superimposing multiple pulses to create a dynamic waveform. This determines the potential surge waveform. This waveform is determined by integrating the frequency, amplitude, and number of pulses of the Type-C interface to be verified on a timeline to ensure that the test conditions align with actual operating conditions. The Type-C interface to be tested is connected to the surge generator in preparation for the surge test. The surge generator was activated in blocking mode (when the PD protocol is not completed, power supply is not activated, the device is in a high-impedance state, and surge events occur during device plugging and unplugging, protocol negotiation failure, or standby mode) and conducting mode (when the handshake protocol is completed, power supply is activated, the device is in a low-impedance state, and surge events occur during full-load device operation, data transmission, or dynamic power adjustment (such as 20V to 5V switching)). Surge signals were applied to the Type-C interface to simulate actual surge events. An oscilloscope and voltage and current probes were used to monitor the voltage and current changes of the Type-C interface in real time during the surge process. Operational data was recorded and compared with the voltage and current stress waveforms in blocking mode and conducting mode. Through joint spectral and time domain analysis, the response characteristics of the Type-C interface in different states were determined and its protection effectiveness was evaluated.

[0121] Existing surge tests are typically based on standard waveforms. However, in real-world Type-C interface operating conditions (such as hot plugging and fast charging), surge waveforms can contain high-frequency oscillations or multiple pulses, resulting in test results that are out of sync with real-world scenarios. Traditional methods test only in a single operating mode (e.g., the on-state), ignoring differences in surge response in blocking modes (e.g., standby mode, protocol handshake), resulting in incomplete protection design coverage. This application captures real-world Type-C interface operating scenarios (e.g., voltage transients during PD protocol switching and VBUS hot plug jitter) to construct a multi-dimensional surge waveform library (e.g., composite waveforms superimposed with high-frequency noise), replacing the single standard waveform and improving test realism. For example, a surge generator is pre-configured with a surge model triggered by the USB PD protocol (e.g., a voltage drop superimposed with a 1MHz oscillation during a 20V→5V switch). Surges are injected in both blocking mode (e.g., CC line handshake not occurring) and conducting mode (e.g., full power supply). By comparing the voltage stress waveforms (e.g., peak value, rise time) and current path distribution in the two modes, protection blind spots are identified. For example, in blocking mode, surge energy may be coupled to the data line through parasitic capacitance. In conducting mode, the low impedance of the VBUS path causes surge current to concentrate. Based on the comparative analysis results, the protection strategy can be dynamically adjusted. For example, if the residual voltage on the data line exceeds the standard in blocking mode, the number of TVS resistors on the data line can be increased; if common-mode noise is significant in conducting mode, the common-mode inductor layout can be optimized.

[0122] As an embodiment of the present invention: in the blocking mode:

[0123] Setting a controllable power supply system so that it outputs a first voltage stress waveform that meets actual application conditions;

[0124] Put the Type-C interface to be verified into a blocked state;

[0125] Starting the controllable power supply system and applying a first voltage stress to the Type-C interface to be verified;

[0126] Use an oscilloscope and a voltage probe to monitor the voltage waves at both ends of the Type-C interface to be verified and obtain blocking operation data.

[0127] In actual implementation, the controllable power supply must output a first voltage stress waveform to simulate complex voltage variations in real-world scenarios (such as plug-in surges, power transients, and EFT bursts). The Type-C interface is then placed into blocking mode through logical control (e.g., CC pin configuration) or physical disconnection. The controllable power supply is then connected to the VBUS (or CC / SBU) pin of the interface under test, and a dynamic voltage waveform is applied. Finally, an oscilloscope is used to capture the real-time voltage waveform across the interface and analyze characteristics such as overshoot, oscillation, and clamping response. Peak voltage withstand, voltage dropout time, waveform distortion, and leakage current (requires a current probe) are determined. Traditional tests often use static voltage (such as withstand voltage tests), while this solution uses programmable voltage waveforms to simulate dynamic stresses in real-world scenarios, more closely resembling actual failure modes (such as cumulative damage caused by repeated plugging and unplugging). By focusing on the reliability of the Type-C interface in its non-operating state, this approach overcomes the shortcomings of traditional testing that focuses solely on the conducting mode (for example, preventing damage from unexpected voltage inrush during device standby). By capturing transient responses, voltage waveform characteristics can be correlated with physical damage (such as insulation breakdown and FET breakdown), providing a direct basis for failure analysis.

[0128] As an embodiment of the present invention: in the conduction mode:

[0129] Setting a controllable power supply system so that it outputs a second current stress waveform that meets actual application conditions;

[0130] Put the Type-C interface to be verified into the conductive state;

[0131] Start the controllable power system and apply a second current stress to the Type-C interface to be verified;

[0132] Use an oscilloscope and current probe to monitor the current waveform at both ends of the Type-C interface to be verified and obtain conduction operation data.

[0133] In actual implementation, the controllable power supply system is configured to output a second current stress waveform (e.g., waveform shape, amplitude range, and time characteristics). This second current stress waveform is not a standard pulse, but rather a complex waveform designed based on real-world application scenarios (e.g., current jumps and load steps in the PD protocol). Waveform generation is triggered by the PD protocol state machine. Conventional current measurement and monitoring are difficult because current measurement may involve factors such as rapid switching of large currents and impedance matching between the current source and the load. Voltage monitoring is typically used. However, this application simulates operating conditions, enabling current monitoring. The Type-C interface is placed in the on-state. Current waveform details (e.g., overshoot, oscillation, and recovery time) are captured in real time based on the interface's on-state (e.g., VBUS active power supply, CC pin negotiation completed) in preparation for the current stress test. The controllable power supply system is activated, and the second current stress is applied to the Type-C interface to be tested. An oscilloscope and current probe are used to monitor the current waveform across the Type-C interface to obtain operational data in the on-state mode. Traditional current testing methods cannot reflect the effects of dynamic current stress in real-world operating conditions (e.g., sudden current changes caused by PD protocol negotiation and load competition when multiple devices are connected in parallel). This solution provides more realistic failure mode coverage (such as current overshoot causing MOSFET burnout and inductor saturation). It also enables data-driven optimization, guiding the selection of protective devices through waveform analysis, such as matching fuse blowing characteristics with the current rise rate.

[0134] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A Type-C interface power surge protection design method, characterized in that: The device comprises a Type-C interface power supply, which comprises a Type-C interface, a transient suppression diode D4, and a chip end; wherein the input end of the Type-C interface is connected to the transient suppression diode D4, and the output end of the Type-C interface is connected to the chip end. The design method comprises: Obtain the initial circuit schematic and surge protection requirements of the Type-C interface, and determine the rated voltage, rated power, and response time of the Type-C interface; The obtaining of the initial circuit schematic diagram and surge protection requirements of the Type-C interface further includes: Analyze the initial circuit schematic of the Type-C interface circuit, divide it into multiple circuit functional groups, and determine the electrical utility characteristics of each circuit functional group; the electrical utility characteristics include the connection type defined by the interface electrical characteristics; Determine the electrical similarity of multiple circuit functional groups based on electrical utility characteristics; Based on electrical similarity, electrical function groups with electrical similarity higher than a preset threshold are divided into electrical collection groups; Determining electrical correlation information of each electrical combination group based on electrical utility characteristics and electrical similarity; Technically associate the electrical correlation information with the corresponding circuit function group to determine the Type-C interface electrical correlation data; Based on the electrical data and surge protection requirements of the Type-C interface, low-voltage surge interference is introduced to determine the circuit components of the original circuit schematic of the Type-C interface to be modified. The circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined, further comprising: Create an analog auxiliary cell library containing TVS diodes, common-mode inductors, and filter capacitors; In the RTL design phase, the digital standard cell library and analog auxiliary cell library are used to design the mixed digital-analog circuit of the Type-C interface; Based on the mixed digital-analog circuit, the surge protection status of the Type-C interface is determined by the TVS diodes on the power input and signal lines of the Type-C interface, and the interference intensity under different component configurations is determined. The interference intensity includes differential mode interference intensity and common mode interference intensity. Based on the interference intensity, digital backend tools are used to automatically generate the initial layout of the Type-C interface circuit based on the RTL design; Perform physical verification and simulation on the generated initial layout to simulate surge voltage events and ensure the protection strength of the TVS diode; Determine a first electrical characteristic of low-voltage surge interference generated by the Type-C interface based on the rated voltage and rated power, and configure multiple TVS transient voltage suppressor diodes at the output end of the Type-C interface to generate a first circuit schematic. The method further includes: Configure multiple linear resistors before multiple TVS transient voltage suppression diodes; An inductive filter L6 is placed before the transient suppression diode D4, and a target transient suppression diode D5 is placed before the inductive filter L6. Obtaining a second electrical characteristic after configuring multiple TVS transient voltage suppression diodes, and configuring multiple common-mode inductor filters at output ends of the multiple TVS transient voltage suppression diodes to generate a second circuit schematic; Based on the second circuit schematic, generate a Type-C interface to be verified and perform a low-voltage surge test. The low-voltage surge test includes: Set the surge generator to output a surge waveform that meets the actual application conditions Connect the Type-C port to be verified to the surge generator; Start the surge generator and apply a surge signal to the Type-C interface to be verified in blocking mode and conducting mode. Use an oscilloscope and voltage and current probes to monitor the operating data of the device under test during the surge process; Based on the operating data, compare the voltage and current stress waveforms in blocking mode and conducting mode, and analyze the response characteristics of the Type-C interface to be verified in different states; When the test results meet the surge protection requirements, the Type-C interface corresponding to the second circuit schematic is used as the target Type-C interface.

2. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: The first electrical characteristic is the original electrical characteristic of the Type-C interface before any surge protection design is performed; The first electrical characteristic includes: Voltage level when the Type-C interface is working normally; The maximum power that the Type-C port can handle under normal operating conditions; The response speed of the Type-C interface to voltage changes; Abnormal behavior of the Type-C interface under low-voltage surge interference, including voltage spikes and current changes.

3. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: The second electrical characteristics refer to the electrical characteristics after multiple TVS transient voltage suppression diodes are configured at the output end of the Type-C interface; The second electrical characteristics include: breakdown voltage characteristics of the TVS diode, power characteristics of the TVS diode, response time of the TVS diode, impedance characteristics of the circuit, and filtering strength of the circuit.

4. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: In the blocking mode: Setting a controllable power supply system so that it outputs a first voltage stress waveform that meets actual application conditions; Put the Type-C interface to be verified into a blocked state; Starting the controllable power supply system and applying a first voltage stress to the Type-C interface to be verified; Use an oscilloscope and a voltage probe to monitor the voltage waves at both ends of the Type-C interface to be verified and obtain blocking operation data.

5. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: In the conduction mode: Set up a controllable power supply system to output a second current stress waveform that meets the actual application conditions Put the Type-C interface to be verified into the conductive state; Start the controllable power system and apply a second current stress to the Type-C interface to be verified; Use an oscilloscope and current probe to monitor the current waveform at both ends of the Type-C interface to be verified and obtain conduction operation data.

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