Radiation-proof FPGA (Field Programmable Gate Array) embedded 28Gbps serial interface signal compensation circuit

Abstract

The invention provides an anti-radiation FPGA (Field Programmable Gate Array) embedded 28Gbps serial interface signal compensation circuit, which mainly solves the problem of high error rate of data transmission of an anti-radiation FPGA device. According to the scheme, a main path signal circuit carries out impedance matching and common-mode terminal voltage processing on a high-frequency attenuation signal according to a control signal of a first anti-radiation configuration circuit to obtain a main path output signal, and the main path output signal is input into a first signal superposition circuit and a second signal superposition circuit; the equalization signal circuit performs equalization processing on the high-frequency attenuation signal according to a control signal of the second anti-radiation configuration circuit to obtain an equalization signal, and inputs the equalization signal into the first signal superposition circuit; and the first signal superposition circuit superposes the main path output signal and the equalization signal according to the control signal of the anti-radiation auxiliary circuit to obtain a superposition signal, so that compensation processing of the data signal is realized, the problems of compensation degree limitation, power supply voltage limitation, power supply noise limitation and the like are avoided, and error codes are further reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit. Background Art

[0002] As the data transmission performance requirements for radiation-resistant FPGA devices in the field of modern satellite communications become higher and higher, the single-channel rate requirements for its embedded high-speed serial interface have reached the gigabit per second level. When the signal transmission reaches the gigabit rate, the signal integrity problem will become more and more obvious. Since the frequency characteristics of the signal transmission link are low-pass characteristics, the high-frequency components of the signal will be greatly attenuated when they pass through the transmission cable from the system transmitter to the receiver, which is manifested in the time domain as signal distortion, slow rise and fall edges, and signal amplitude reduction. If the high-frequency component compensation processing of the signal is not performed, the clock data recovery circuit at the receiving end will generate bit errors when receiving the signal due to insufficient sampling and holding time.

[0003] To this end, in the prior art, high-speed serial interfaces add pre-compensation processing at the transmitting end, including two methods: (1) increasing the amplitude of the high-frequency component of the signal, that is, increasing the signal amplitude at the rising and falling edges by a certain proportion; (2) reducing the amplitude of the low-frequency component of the signal, that is, reducing the signal amplitude outside the rising and falling edges by a certain proportion. After the high frequency is attenuated through the cable transmission, the amplitudes of the low-frequency and high-frequency components tend to be smooth, and then the low-frequency and high-frequency components of the signal are amplified together at the receiving end. The above scheme only adds a pre-compensation processing method at the transmitting end, but there are still the following problems: (1) Different materials and lengths of transmission cables lead to different signal attenuation, so the degree of compensation is difficult to determine; (2) If the method of increasing the amplitude is adopted, it will be limited by the power supply voltage; (3) If the method of reducing the amplitude is adopted, it will be limited by the power supply noise. In addition, when the signal amplitude becomes low, after attenuation through the transmission cable, it will further increase the pressure on the receiving end to identify the signal; these problems will lead to an increase in the bit error rate. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art and reduce the bit error rate of data transmission of radiation-resistant FPGA devices, the present invention provides a radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit. The present invention can superimpose and amplify the original high-frequency attenuated signal after being processed by the main signal circuit and the equalization signal circuit, thereby realizing compensation processing of the data signal, avoiding the problems of compensation degree limitation, power supply voltage limitation, and power supply noise limitation caused by the prior art of only pre-compensation at the transmitting end, so that better signal compensation effect can be achieved, and it has radiation resistance, avoids the occurrence of single particle effects, and ensures the reliability of signal transmission.

[0005] The radiation-resistant FPGA has a built-in 28Gbps serial interface signal compensation circuit, including a data receiving end, a main signal circuit, an equalization signal circuit, a first signal superposition circuit, a first radiation-resistant configuration circuit, a second radiation-resistant configuration circuit, and an radiation-resistant auxiliary circuit; the data receiving end includes a first receiving output end RX1 and a second receiving output end RX2;

[0006] The first anti-radiation configuration circuit is used to reinforce the storage and output of the control signal of the equalization signal circuit; the second anti-radiation configuration circuit is used to reinforce the storage and output of the control signal of the main signal circuit; the anti-radiation auxiliary circuit is used to reinforce the storage and output of the control signal of the signal superposition circuit; the output end of the first anti-radiation configuration circuit is the first control signal CS1; the output end of the second anti-radiation configuration circuit is the second control signal CS2; the anti-radiation auxiliary circuit includes a first control signal output end EN1, a second control signal output end EN2, a first reference current output end B1 and a second reference current output end B2;

[0007] The main signal circuit performs impedance matching and common-mode terminal voltage processing on the high-frequency attenuation signal according to the control signal of the first anti-radiation configuration circuit to obtain a main output signal, and inputs the main output signal into the first signal superposition circuit;

[0008] The equalization signal circuit performs equalization processing on the high-frequency attenuation signal according to the control signal of the second anti-radiation configuration circuit to obtain an equalization signal, and inputs the equalization signal into the first signal superposition circuit;

[0009] The first signal superposition circuit superimposes the main output signal and the equalization signal according to the control signal of the anti-radiation auxiliary circuit to obtain a superimposed signal; and then connects the superimposed signal to the data recognition terminal and the edge recognition terminal respectively.

[0010] Furthermore, the radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit includes a second signal superposition circuit; the second signal superposition circuit superimposes the main output signal and the equalization signal according to the control signal of the radiation-resistant auxiliary circuit to obtain a superimposed signal; the first signal superposition circuit has the same structure as the second signal superposition circuit; the input of the second signal superposition circuit 107 includes a ninth input terminal VI9, a tenth input terminal VI10, an eleventh input terminal VI11, a twelfth input terminal VI12, a second reference current input terminal I2 and a second superimposed control signal input terminal S2; the ninth input terminal VI9 is ​​connected to the first output terminal VO1; the tenth input terminal VI10 is connected to the second output terminal VO2; the eleventh input terminal VI11 is connected to the third output terminal VO3; the twelfth input terminal VI12 is connected to the fourth output terminal VO4; the second superimposed control signal input terminal S2 is connected to the second control signal output terminal EN2; the second reference current input terminal I2 is connected to the second reference current output terminal B2; the second superimposed control The signal input terminal S2 is a 12-bit control signal, and the second superposition control signal input terminal S2 includes 12 input terminals and 12 output terminals, and the input terminals and the output terminals correspond to each other one by one; the output of the second signal superposition circuit 107 is the seventh output terminal VO7 and the eighth output terminal VO8; the fifth output terminal VO5, the sixth output terminal VO6, the seventh output terminal VO7 and the eighth output terminal VO8 are connected to the input terminal of the data delay processing circuit in sequence; the data delay processing circuit delays the superposition signals output by the first signal superposition circuit and the second signal superposition circuit, and inputs the superposition signals after delay processing into the data identification terminal and the edge identification terminal respectively; the input of the data delay processing circuit includes the thirteenth input terminal VI13, the fourteenth input terminal VI14, the fifteenth input terminal VI15 and the sixteenth input terminal VI16; the output of the data delay processing circuit is the ninth output terminal VO9 and the tenth output terminal VO10; the ninth output terminal VO9 is connected to the data identification terminal; the tenth output terminal VO10 is connected to the edge identification terminal.

[0011] Furthermore, the input end of the main signal circuit 104 includes a third input end VI3, a fourth input end VI4 and a main control input end SC; the main control input end SC is a digital switch; the main control input end SC includes seven input ends and seven output ends, and the input ends correspond to the output ends one by one; the main control input end SC is connected to the second control signal CS2; the output end of the main signal circuit 104 includes a third output end VO3 and a fourth output end VO4; the first receiving output end RX1 is connected to the third input end VI3; the second receiving output end RX2 is connected to the fourth input end VI4; the third output end VO3 is connected to the seventh input end VI7; the fourth output end VO4 is connected to the eighth input end VI8;

[0012] The main signal circuit 104 includes a first impedance matching resistor array, a second impedance matching resistor array, a first coupling capacitor 204, a second coupling capacitor 205 and a common mode voltage circuit;

[0013] The first coupling capacitor 204 includes a first capacitor C1 and a sixth terminal SC of the main control input terminal SC. <5> ; The sixth terminal SC of the first capacitor C1 and the main control input terminal SC <5> in parallel;

[0014] The second coupling capacitor 205 includes a second capacitor C2 and a sixth terminal SC of the main control input terminal SC. <6> ; The sixth terminal SC of the second capacitor C2 and the main control input terminal SC <6> in parallel;

[0015] The first impedance matching resistor array R1 includes five resistors connected in parallel; each resistor is connected in series with a pair of input terminals and an output terminal of the main control input terminal SC; the five resistors are connected in series with the first terminal to the fifth terminal of the main control input terminal SC in sequence; the second impedance matching resistor array R2 is the same as the first impedance matching resistor array R1;

[0016] The third input terminal VI3 of the main signal circuit 104 is connected to the input terminal of the first impedance matching resistor array; the third input terminal VI3 of the main signal circuit 104 is connected to one end of the first coupling capacitor 204; the other end of the first coupling capacitor 204 is connected to the third output terminal VO3;

[0017] The fourth input terminal VI4 of the main signal circuit 104 is connected to the input terminal of the second impedance matching resistor array; the fourth input terminal VI4 of the main signal circuit 104 is connected to one end of the second coupling capacitor 205; the other end of the second coupling capacitor 205 is connected to the fourth output terminal VO4;

[0018] The output end of the first impedance matching resistor array and the output end of the second impedance matching resistor array are connected to the input end of the common mode voltage circuit 203; the output end of the common mode voltage circuit 203 is grounded;

[0019] Furthermore, the common mode voltage circuit 203 is used to adjust the common mode terminal voltage of the main signal circuit signal;

[0020] The common-mode voltage circuit includes a first common-mode digital switch, a second common-mode digital switch and a third common-mode digital switch; the input end of the common-mode voltage circuit is respectively connected to the input end of the first common-mode digital switch, the input end of the second common-mode digital switch and the input end of the third common-mode digital switch; the output end of the first common-mode digital switch is connected to a 1.2V voltage; the output end of the second common-mode digital switch is connected to a 0.8V voltage; the output end of the third common-mode digital switch is connected to ground; in a DC coupling scenario, the common-mode voltage circuit output selects a 1.2V voltage mode or a grounding mode; in an AC coupling scenario, the common-mode voltage circuit output selects a 0.8V voltage mode.

[0021] Furthermore, the input end of the equalization signal circuit 105 includes a first input end VI1, a second input end VI2 and an equalization control input end EC; the equalization control input end EC is a digital switch; the equalization control input end EC includes sixteen input ends and sixteen output ends, and the input ends correspond to the output ends one by one; the equalization control input end EC is connected to the first control signal CS1; the output end of the equalization signal circuit 105 includes a first output end VO1 and a second output end VO2;

[0022] The equalizing signal circuit 105 comprises a first resistor array 302, a second resistor array 303, a third resistor array 305 and a fourth resistor array 306, a first input capacitor C3 and a second input capacitor C4; the first input terminal VI1 of the equalizing signal circuit 105 is connected to the input terminal of the first input capacitor C3; the output terminal of the first input capacitor C3 is respectively connected to the input terminal of the first resistor array, the input terminal of the second resistor array and the first output terminal VO1; the second input terminal VI2 of the equalizing signal circuit 105 is connected to the input terminal of the second input capacitor C4; the output terminal of the second input capacitor C4 is respectively connected to the input terminal of the third resistor array, the input terminal of the fourth resistor array and the second output terminal VO2 of the equalizing signal circuit; the input terminal of the first resistor array 302 is connected to the input terminal of the seventh resistor R7 and the eighth resistor R8 connected in parallel; the output terminal of the seventh resistor R7 and the eighth resistor R8 connected in parallel is connected to the input terminal of the fifth resistor R5; the output terminal of the fifth resistor R5 is connected to the drain of the PMOS switch tube MP3; the third output terminal EC of the equalizing control input terminal EC <2> The output end of the seventh resistor R7 and the eighth resistor R8 connected in parallel is connected to the input end of the sixth resistor R6; the output end of the sixth resistor R6 is connected to the drain of the PMOS switch tube MP4; the fourth output end EC of the balance control input end EC <3> The gate of the PMOS switch tube MP4 is connected to the source of the PMOS switch tube MP3; the source of the PMOS switch tube MP4 and the source of the PMOS switch tube MP3 are connected to the drain of the PMOS switch tube MP2 respectively; the source of the PMOS switch tube MP4 and the source of the PMOS switch tube MP3 are connected to the input end of the fourth resistor R4 respectively; the gate of the PMOS switch tube MP2 is connected to the second output end EC of the balance control input end EC <1> The output end of the fourth resistor R4 is connected to the source of the PMOS switch tube MP2; the output end of the fourth resistor R4 and the source of the PMOS switch tube MP2 are respectively connected to the drain of the PMOS switch tube MP1; the output end of the fourth resistor R4 and the source of the PMOS switch tube MP2 are respectively connected to the input end of the third resistor R3; the gate of the PMOS switch tube MP1 is connected to the first output end EC of the equalization control input end EC <0> The output end of the third resistor R3 is connected to the source of the PMOS switch tube MP1; the source of the PMOS switch tube MP1 is connected to the analog power supply terminal AVDD;

[0023] The input end of the second resistor array 303 is connected to the input end of the ninth resistor R9 and the tenth resistor R10 in parallel; the output end of the ninth resistor R9 and the tenth resistor R10 in parallel is connected to the input end of the eleventh resistor R11; the output end of the eleventh resistor R11 is connected to the drain of the NMOS switch tube MN3; the output end of the ninth resistor R9 and the tenth resistor R10 in parallel is connected to the input end of the twelfth resistor R12; the output end of the twelfth resistor R12 is connected to the drain of the NMOS switch tube MN4; the source of the NMOS switch tube MN3 is connected to the source of the NMOS switch tube MN4; the gate of the NMOS switch tube MN3 is connected to the fifth output end EC of the equalization control input end EC <4> Connect the gate of the NMOS switch tube MN4 to the eighth output terminal EC of the balanced control input terminal EC <7> The source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the drain of the NMOS switch tube MN2; the source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the input end of the thirteenth resistor R13; the source of the NMOS switch tube MN2 is connected to the output end of the thirteenth resistor R13; the gate of the NMOS switch tube MN2 is connected to the sixth output end EC of the balance control input end EC <5> The source of the NMOS switch tube MN2 and the output end of the thirteenth resistor R13 are respectively connected to the drain of the NMOS switch tube MN1; the source of the NMOS switch tube MN2 and the output end of the thirteenth resistor R13 are respectively connected to the input end of the fourteenth resistor R14; the source of the NMOS switch tube MN1 is connected to the output end of the fourteenth resistor R14 and is grounded at the same time; the gate of the NMOS switch tube MN1 is connected to the seventh output end EC of the balance control input end EC <6> The input end of the third resistor array 305 is connected to the input end of the nineteenth resistor R19 and the twentieth resistor R20 in parallel; the output end of the nineteenth resistor R19 and the twentieth resistor R20 in parallel is connected to the input end of the seventeenth resistor R17; the output end of the seventeenth resistor R17 is connected to the drain of the PMOS switch tube MP7; the eleventh output end EC of the balance control input end EC <10> The output end of the nineteenth resistor R19 and the twentieth resistor R20 connected in parallel are connected to the input end of the eighteenth resistor R18; the output end of the eighteenth resistor R18 is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC of the balance control input end EC is connected to the gate of the PMOS tube MP7; the output end of the nineteenth resistor R19 and the twentieth resistor R20 connected in parallel are connected to the input end of the eighteenth resistor R18; the output end of the eighteenth resistor R18 is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC of the balance control input end EC <11> The gate of the PMOS switch tube MP8 is connected; the source of the PMOS switch tube MP7 is connected to the source of the PMOS switch tube MP8; the source of the PMOS switch tube MP7 and the source of the PMOS switch tube MP8 are respectively connected to the drain of the PMOS switch tube MP6; the source of the PMOS switch tube MP7 and the source of the PMOS switch tube MP8 are respectively connected to the input end of the sixteenth resistor R16; the gate of the PMOS switch tube MP6 is connected to the tenth output end EC of the balance control input end EC <9> connect;The output end of the sixteenth resistor R16 is connected to the source of the PMOS switch tube MP6; the output end of the sixteenth resistor R16 and the source of the PMOS switch tube MP6 are respectively connected to the drain of the PMOS switch tube MP5; the output end of the sixteenth resistor R16 and the source of the PMOS switch tube MP6 are respectively connected to the input end of the fifteenth resistor R15; the gate of the PMOS switch tube MP5 is connected to the ninth output end EC of the equalization control input end EC <8> The output end of the fifteenth resistor R15 is connected to the source of the PMOS switch tube MP5; the source of the PMOS switch tube MP5 is connected to the analog power supply terminal AVDD; the input end of the fourth resistor array 306 is connected to the input end of the twenty-first resistor R21 and the twenty-second resistor R22 in parallel; the output end of the twenty-first resistor R21 and the twenty-second resistor R22 in parallel is connected to the input end of the twenty-third resistor R23; the output end of the twenty-third resistor R23 is connected to the drain of the NMOS switch tube MN7; the output ends of the twenty-first resistor R21 and the twenty-second resistor R22 in parallel are respectively connected to the input end of the twenty-fourth resistor R24; the output end of the twenty-fourth resistor R24 ​​is connected to the drain of the NMOS switch tube MN8; the source of the NMOS switch tube MN7 is connected to the source of the NMOS switch tube MN8; the gate of the NMOS switch tube MN7 is connected to the thirteenth output terminal EC of the equalization control input terminal EC <12> Connect the gate of the NMOS switch tube MN8 to the sixteenth output terminal EC of the balanced control input terminal EC <15> The source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the drain of the NMOS switch tube MN6; the source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the input end of the twenty-fifth resistor R25; the source of the NMOS switch tube MN6 is connected to the output end of the twenty-fifth resistor R25; the gate of the NMOS switch tube MN6 is connected to the fourteenth output end EC of the balance control input end EC <13> The source of the NMOS switch tube MN6 and the output end of the 25th resistor R25 are respectively connected to the drain of the NMOS switch tube MN5; the source of the NMOS switch tube MN6 and the output end of the 25th resistor R25 are respectively connected to the input end of the 26th resistor R26; the source of the NMOS switch tube MN5 is connected to the output end of the 26th resistor R26 and is grounded at the same time; the gate of the NMOS switch tube MN5 is connected to the fifteenth output end EC of the equalization control input end EC <14> connect.;

[0024] Furthermore, the input end of the first signal superposition circuit includes a fifth input end VI5, a sixth input end VI6, a seventh input end VI7, an eighth input end VI8, a first reference current input end I1 and a first superposition control signal input end S1; the first superposition control signal input end S1 is connected to the first control signal output end EN1; the first reference current input end I1 is connected to the first reference current output end B1; the first superposition control signal input end S1 is a 12-bit control signal, and the first superposition control signal input end S1 includes 12 input ends and 12 output ends, and the input ends and the output ends correspond one to one; the output end of the first signal superposition circuit 106 includes a fifth output end VO5 and a sixth output end VO6; the fifth output end VO5 is connected to the data identification end; the sixth output end VO6 is connected to the edge identification end;

[0025] The first signal superposition circuit 106 includes an enable control circuit 401, a first input pair of transistors 404, a second input pair of transistors 405, a first current source array 402, a second current source array 403, a first load resistor array 406 and a second load resistor array 407;

[0026] The first input pair of transistors 404 includes an NMOS transistor MN11 and an NMOS transistor MN12; the fifth input terminal VI5 of the first signal superposition circuit 106 is connected to the gate of MN11; the sixth input terminal VI6 of the first signal superposition circuit 106 is connected to the gate of MN12; the source of the NMOS transistor MN11 is connected to the source of the NMOS transistor MN12; the drain of MN11 is connected to the input terminal of the first load resistor array 406; the drain of MN12 is connected to the input terminal of the second load resistor array 407;

[0027] The second input pair of transistors 405 includes an NMOS transistor MN13 and an NMOS transistor MN14; the seventh input terminal VI7 of the first signal superposition circuit 106 is connected to the gate of MN13; the eighth input terminal VI8 of the first signal superposition circuit 106 is connected to the gate of MN14; the source of the NMOS transistor MN13 is connected to the source of the NMOS transistor MN14; the drain of MN13 is connected to the input terminal of the first load resistor array 406; the drain of MN14 is connected to the input terminal of the second load resistor array 407;

[0028] The first load resistor array 406 includes a twenty-eighth resistor R28, a PMOS switch tube MP9, a PMOS switch tube MP10 and a twenty-seventh resistor R27; the input end of the first load resistor array 406 is simultaneously connected to the input end of the twenty-eighth resistor R28, the input end of the twenty-seventh resistor R27 and the fifth output end VO5; the output end of the twenty-eighth resistor R28 is connected to the drain of the PMOS switch tube MP10; the source of the PMOS switch tube MP10 is connected to the analog power supply end AVDD; the gate of the PMOS switch tube MP10 is connected to the second output end S1 of the first superimposed control signal input end S1 <1> The output end of the twenty-seventh resistor R27 is connected to the drain of the PMOS switch tube MP9; the source of the PMOS switch tube MP9 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP9 is connected to the first output terminal S1 of the first superimposed control signal input terminal S1 <0> connect;

[0029] The second load resistor array 407 includes a twenty-ninth resistor R29, a PMOS switch tube MP11, a PMOS switch tube MP12 and a thirtieth resistor R30; the input end of the second load resistor array 407 is simultaneously connected to the input end of the twenty-ninth resistor R29, the input end of the thirtieth resistor R30 and the sixth output end VO6; the output end of the twenty-ninth resistor R29 is connected to the drain of the PMOS switch tube MP11; the source of the PMOS switch tube MP11 is connected to the analog power supply end AVDD; the gate of the PMOS switch tube MP11 is connected to the second output end S1 of the first superimposed control signal input end S1 <1> The output end of the 30th resistor R30 is connected to the drain of the PMOS switch tube MP12; the source of the PMOS switch tube MP12 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP12 is connected to the first output terminal S1 of the first superimposed control signal input terminal S1 <0> connect;

[0030] The first current source array includes four NMOS tubes; the sources of the four NMOS tubes are grounded respectively; the gate of each NMOS tube is connected in series with an output terminal of the first superposition control signal input terminal S1; the gates of the four NMOS tubes are connected in series with the fifth to eighth output terminals of the first superposition control signal input terminal S1 in sequence; the drains of the four NMOS tubes are connected in parallel and are connected to the source of the NMOS tube MN11 and the source of the NMOS tube MN12 respectively;

[0031] The second current source array includes four NMOS tubes; the sources of the four NMOS tubes are grounded respectively; the gate of each NMOS tube is connected in series with an output terminal of the first superposition control signal input terminal S1; the gates of the four NMOS tubes are connected in series with the ninth to twelfth output terminals of the first superposition control signal input terminal S1 in sequence; the drains of the four NMOS tubes are connected in parallel and are connected to the source of the NMOS tube MN13 and the source of the NMOS tube MN14 respectively;

[0032] The enabling control circuit includes an NMOS transistor MN9, an NMOS transistor MN10 and a PMOS switch transistor MP13; the first reference current input terminal I1 is connected to the drain of the NMOS transistor MN9 and the source of the PMOS switch transistor MP13 respectively; the source of the NMOS transistor MN9 is connected to the drain of the PMOS switch transistor MP13; the gate of the NMOS transistor MN9 is connected to the fourth input output terminal S1 of the first superimposed control signal input terminal S1 <3> The gate of the PMOS switch MP13 is connected to the third input terminal S1 of the first superimposed control signal input terminal S1. <2> The source of the NMOS tube MN9 is connected to the drain of the NMOS tube MN10; the source of the NMOS tube MN10 is grounded; the gate of the NMOS tube MN10 is connected to the third input and output terminal S1 of the first superimposed control signal input terminal S1 <2> The source of the NMOS tube MN9 is respectively connected to the gates of the four NMOS tubes of the first current source array; the source of the NMOS tube MN9 is respectively connected to the gates of the four NMOS tubes of the second current source array.

[0033] The beneficial effect of the present invention is that the signal compensation circuit proposed in the present invention can superimpose and amplify the original high-frequency attenuated signal after being processed by the main signal circuit and the equalization signal circuit at the receiving end, thereby realizing the compensation processing of the data signal, avoiding the problems such as the limitation of the compensation degree, power supply voltage limitation and power supply noise limitation brought by the prior art that only pre-compensation is performed at the transmitting end, so that better signal compensation effect can be achieved and bit errors can be reduced. When the superimposed signal output by the signal superposition circuit proposed in the present invention is divided into two or more transmission paths, the compensated processed signal is respectively transmitted to the data identification end and the edge identification end after delay processing, so as to perform clock and data recovery processing, which is helpful to achieve better signal fidelity and reduce bit errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of a 28Gbps serial interface signal compensation circuit embedded in a radiation-resistant FPGA provided by an embodiment of the present invention;

[0035] Figure 2 It is a schematic diagram of another radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit provided by an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of a main signal circuit provided by an embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of a balanced signal circuit provided by an embodiment of the present invention;

[0038] Figure 5 is a schematic diagram of a signal superposition circuit provided by an embodiment of the present invention;

[0039] In the figure, 101-receiving end data path; 102-first anti-radiation configuration circuit; 103-second anti-radiation configuration circuit; 104-main signal circuit; 105-balanced signal circuit; 106-first signal superposition circuit; 107-second signal superposition circuit; 108-anti-radiation auxiliary circuit; 109-data delay processing circuit;

[0040] 203 - common mode voltage circuit; 204 - first coupling capacitor; 205 - second coupling capacitor;

[0041] 302 - first resistor array; 303 - second resistor array; 305 - third resistor array; 306 - fourth resistor array;

[0042] 401 -enable control circuit; 402 -first current source array; 403 -second current source array; 404 -first input pair of tubes; 405 -second input pair of tubes; 406 -first load resistor array; 407 -second irradiation resistor array;

[0043] RX1-first receiving output terminal; RX2-second receiving output terminal;

[0044] VI1-first input terminal; VI2-second input terminal; VI3-third input terminal; VI4-fourth input terminal; VI5-fifth input terminal; VI6-sixth input terminal; VI7-seventh input terminal; VI8-eighth input terminal; VI9-ninth input terminal; VI10-tenth input terminal; VI11-eleventh input terminal; VI12-twelfth input terminal; VI13-thirteenth input terminal; VI14-fourteenth input terminal; VI15-fifteenth input terminal; VI16-sixteenth input terminal;

[0045] VO1-first output terminal; VO2-second output terminal; VO3-third output terminal; VO4-fourth output terminal; VO5-fifth output terminal; VO6-sixth output terminal; VO7-seventh output terminal; VO8-eighth output terminal; VO9-ninth output terminal; VO10-tenth output terminal;

[0046] CS1-first control signal; CS2-second control signal; EC-balance control input terminal; SC-main control input terminal; S1-first superposition control signal input terminal; S2-second superposition control signal input terminal; I1-first reference current input terminal; I2-second reference current input terminal; EN1-first control signal output terminal; EN2-second control signal output terminal EN; B1-first reference current output terminal; B2-second reference current output terminal;

[0047] C1-first capacitor; C2-second capacitor; C3-first input capacitor; C4-second input capacitor;

[0048] R1-first impedance matching resistor array; R2-second impedance matching resistor array;

[0049] R3-the third resistor; R4-the fourth resistor; R5-the fifth resistor; R6-the sixth resistor; R7-the seventh resistor; R8-the eighth resistor; R9-the ninth resistor; R10-the tenth resistor; R11-the eleventh resistor; R12-the twelfth resistor; R13-the thirteenth resistor; R14-the fourteenth resistor; R15-the fifteenth resistor; R16-the sixteenth resistor; R17-the seventeenth resistor; R18-the eighteenth resistor; R19-the nineteenth resistor; R20-the twentieth resistor; R21-the twenty-first resistor; R22-the twenty-second resistor; R23-the twenty-third resistor; R24-the twenty-fourth resistor; R25-the twenty-fifth resistor; R26-the twenty-sixth resistor; R27-the twenty-seventh resistor; R28-the twenty-eighth resistor; R29-the twenty-ninth resistor; R30-the thirtieth resistor. DETAILED DESCRIPTION

[0050] The radiation-resistant FPGA has a built-in 28Gbps serial interface signal compensation circuit, including a data receiving end, a main signal circuit, an equalization signal circuit, a first signal superposition circuit, a second signal superposition circuit, a first radiation-resistant configuration circuit, a second radiation-resistant configuration circuit, and an radiation-resistant auxiliary circuit;

[0051] The data receiving end includes a first receiving output end RX1 and a second receiving output end RX2; the input end of the equalizing signal circuit 105 includes a first input end VI1, a second input end VI2 and an equalizing control input end EC; the equalizing control input end EC is a digital switch; the equalizing control input end EC includes sixteen input ends and sixteen output ends, and the input ends correspond to the output ends one by one; the output end of the equalizing signal circuit 105 includes a first output end VO1 and a second output end VO2; the input end of the main signal circuit 104 includes a third input end VI3, a fourth input end VI4 and a main control input end SC; the main control input end SC is a digital switch; the main control input end SC includes seven input ends and seven output ends. output terminals, and the input terminals correspond to the output terminals one by one; the output terminals of the main signal circuit 104 include a third output terminal VO3 and a fourth output terminal VO4; the first anti-radiation configuration circuit and the second anti-radiation configuration circuit both include a digital buffer unit and a radiation hardening storage unit, and have the ability to resist the influence of single particle effects; the output terminal of the first anti-radiation configuration circuit is a first control signal CS1; the output terminal of the second anti-radiation configuration circuit is a second control signal CS2; the anti-radiation auxiliary circuit includes a first control signal output terminal EN1, a second control signal output terminal EN2, a first reference current output terminal B1 and a second reference current output terminal B2; the anti-radiation auxiliary circuit is used for the current source array in the signal superposition circuit Provide a reference current, and reinforce the storage and output of the control signal of the main signal circuit / balanced signal circuit / signal superposition circuit; the input end of the first signal superposition circuit 106 includes a fifth input end VI5, a sixth input end VI6, a seventh input end VI7, an eighth input end VI8, a first reference current input end I1 and a first superposition control signal input end S1; the first superposition control signal input end S1 is a 12-bit control signal, and the first superposition control signal input end S1 includes 12 input ends and 12 output ends, and the input end and the output end correspond one to one; the output end of the first signal superposition circuit 106 includes a fifth output end VO5 and a sixth output end VO6; the first signal superposition circuit 106 and the second signal superposition circuit 1 07; the input of the second signal superposition circuit 107 includes a ninth input terminal VI9, a tenth input terminal VI10, an eleventh input terminal VI11, a twelfth input terminal VI12, a second reference current input terminal I2 and a second superposition control signal input terminal S2; the second superposition control signal input terminal S2 is a 12-bit control signal, and the second superposition control signal input terminal S2 includes 12 input terminals and 12 output terminals, and the input terminals and the output terminals correspond one to one; the output of the second signal superposition circuit 107 is a seventh output terminal VO7 and an eighth output terminal VO8; the first receiving output terminal RX1 is respectively connected to the third input terminal VI3 of the main signal circuit 104 and the first input terminal VI1 of the equalization signal circuit 105;The second receiving output terminal RX2 is respectively connected to the fourth input terminal VI4 of the main signal circuit 104 and the second input terminal VI2 of the equalized signal circuit 105; the first control signal CS1 is connected to the equalized control input terminal EC of the equalized signal circuit 105; the second control signal CS2 is connected to the main control input terminal SC of the main signal circuit 104; the output terminal VO1 of the equalized signal circuit 105 is respectively connected to the fifth input terminal VI5 of the first signal superposition circuit 106 and the ninth input terminal VI9 of the second signal superposition circuit 107; The output terminal VO2 of the equalizing signal circuit 105 is respectively connected to the sixth input terminal VI6 of the first signal superposition circuit 106 and the tenth input terminal VI10 of the second signal superposition circuit 107; the output terminal VO3 of the main signal circuit 104 is respectively connected to the seventh input terminal VI7 of the first signal superposition circuit 106 and the eleventh input terminal VI11 of the second signal superposition circuit 107; the output terminal VO4 of the main signal circuit 104 is respectively connected to the eighth input terminal VI8 of the first signal superposition circuit 106 and the twelfth input terminal VI12 of the second signal superposition circuit 107; the first control signal output terminal EN1 of the anti-radiation auxiliary circuit is connected to the first superposition control signal input terminal S1 of the first signal superposition circuit 106; The first reference current output terminal B1 of the auxiliary circuit is connected to the first reference current input terminal I1 of the first signal superposition circuit 106; the second control signal output terminal EN2 of the anti-radiation auxiliary circuit is connected to the second superposition control signal input terminal S2 of the second signal superposition circuit; the second reference current output terminal B2 of the anti-radiation auxiliary circuit is connected to the second reference current input terminal I2 of the second signal superposition circuit; the output terminal B1 is connected to the first reference current input terminal I1 of the first signal superposition circuit 106, and the output terminal of 106 includes the fifth output terminal VO5 and the sixth output terminal VO6, which are respectively connected to the data identification terminal; the output of the second signal superposition circuit 107 is the seventh output terminal VO7 and the eighth output terminal VO8, which are respectively connected to the edge identification terminal. ;

[0052] When the transmission path of the superimposed signal includes at least two, a data delay processing circuit is added; the data delay processing circuit is used to perform delay processing on the superimposed signal, and input the superimposed signal after delay processing into the data identification terminal and the edge identification terminal of the clock data recovery circuit respectively; the input of the data delay processing circuit includes the thirteenth input terminal VI13, the fourteenth input terminal VI14, the fifteenth input terminal VI15 and the sixteenth input terminal VI16; the output of the data delay processing circuit includes the ninth output terminal VO9 and the tenth output terminal VO10; the fifth output terminal VO5 of the first signal superimposed circuit 106 is connected to the thirteenth input terminal VI13; the sixth output terminal VO6 of the first signal superimposed circuit 106 is connected to VI14; the seventh output terminal VO7 of the second signal superimposed circuit 106 is connected to VI15; the eighth output terminal VO8 of the second signal superimposed circuit 106 is connected to VI16; the ninth output terminal VO9 of the data delay processing circuit is connected to the data identification terminal; the tenth output terminal VO10 of the data delay processing circuit is connected to the edge identification terminal.

[0053] The data receiving end receives the high-frequency attenuated signal, and transmits the signal to the equalization signal circuit and the main signal circuit respectively through the first receiving output end RX1 and the second receiving output end RX2;

[0054] The equalizing signal circuit 105 comprises a first resistor array 302, a second resistor array 303, a third resistor array 305 and a fourth resistor array 306, a first input capacitor C3 and a second input capacitor C4; the first input terminal VI1 of the equalizing signal circuit 105 is connected to the input terminal of the first input capacitor C3; the output terminal of the first input capacitor C3 is respectively connected to the input terminal of the first resistor array, the input terminal of the second resistor array and the first output terminal VO1; the second input terminal VI2 of the equalizing signal circuit 105 is connected to the input terminal of the second input capacitor C4; the output terminal of the second input capacitor C4 is respectively connected to the input terminal of the third resistor array, the input terminal of the fourth resistor array and the second output terminal VO2 of the equalizing signal circuit; the input terminal of the first resistor array 302 is connected to the input terminal of the seventh resistor R7 and the eighth resistor R8 connected in parallel; the output terminal of the seventh resistor R7 and the eighth resistor R8 connected in parallel is connected to the input terminal of the fifth resistor R5; the output terminal of the fifth resistor R5 is connected to the drain of the PMOS switch tube MP3; the third output terminal EC of the equalizing control input terminal EC <2> The output end of the seventh resistor R7 and the eighth resistor R8 connected in parallel is connected to the input end of the sixth resistor R6; the output end of the sixth resistor R6 is connected to the drain of the PMOS switch tube MP4; the fourth output end EC of the balance control input end EC <3> The gate of the PMOS switch tube MP4 is connected to the source of the PMOS switch tube MP3; the source of the PMOS switch tube MP4 and the source of the PMOS switch tube MP3 are connected to the drain of the PMOS switch tube MP2 respectively; the source of the PMOS switch tube MP4 and the source of the PMOS switch tube MP3 are connected to the input end of the fourth resistor R4 respectively; the gate of the PMOS switch tube MP2 is connected to the second output end EC of the balance control input end EC <1> The output end of the fourth resistor R4 is connected to the source of the PMOS switch tube MP2; the output end of the fourth resistor R4 and the source of the PMOS switch tube MP2 are respectively connected to the drain of the PMOS switch tube MP1; the output end of the fourth resistor R4 and the source of the PMOS switch tube MP2 are respectively connected to the input end of the third resistor R3; the gate of the PMOS switch tube MP1 is connected to the first output end EC of the equalization control input end EC <0> The output end of the third resistor R3 is connected to the source of the PMOS switch tube MP1; the source of the PMOS switch tube MP1 is connected to the analog power supply terminal AVDD;

[0055] The input end of the second resistor array 303 is connected to the input end of the ninth resistor R9 and the tenth resistor R10 in parallel; the output end of the ninth resistor R9 and the tenth resistor R10 in parallel is connected to the input end of the eleventh resistor R11; the output end of the eleventh resistor R11 is connected to the drain of the NMOS switch tube MN3; the output end of the ninth resistor R9 and the tenth resistor R10 in parallel is connected to the input end of the twelfth resistor R12; the output end of the twelfth resistor R12 is connected to the drain of the NMOS switch tube MN4; the source of the NMOS switch tube MN3 is connected to the source of the NMOS switch tube MN4; the gate of the NMOS switch tube MN3 is connected to the fifth output end EC of the equalization control input end EC <4> Connect the gate of the NMOS switch tube MN4 to the eighth output terminal EC of the balanced control input terminal EC <7> The source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the drain of the NMOS switch tube MN2; the source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the input end of the thirteenth resistor R13; the source of the NMOS switch tube MN2 is connected to the output end of the thirteenth resistor R13; the gate of the NMOS switch tube MN2 is connected to the sixth output end EC of the balance control input end EC <5> The source of the NMOS switch tube MN2 and the output end of the thirteenth resistor R13 are respectively connected to the drain of the NMOS switch tube MN1; the source of the NMOS switch tube MN2 and the output end of the thirteenth resistor R13 are respectively connected to the input end of the fourteenth resistor R14; the source of the NMOS switch tube MN1 is connected to the output end of the fourteenth resistor R14 and is grounded at the same time; the gate of the NMOS switch tube MN1 is connected to the seventh output end EC of the balance control input end EC <6> The input end of the third resistor array 305 is connected to the input end of the nineteenth resistor R19 and the twentieth resistor R20 in parallel; the output end of the nineteenth resistor R19 and the twentieth resistor R20 in parallel is connected to the input end of the seventeenth resistor R17; the output end of the seventeenth resistor R17 is connected to the drain of the PMOS switch tube MP7; the eleventh output end EC of the balance control input end EC <10> The output end of the nineteenth resistor R19 and the twentieth resistor R20 connected in parallel are connected to the input end of the eighteenth resistor R18; the output end of the eighteenth resistor R18 is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC of the balance control input end EC is connected to the gate of the PMOS tube MP7; the output end of the nineteenth resistor R19 and the twentieth resistor R20 connected in parallel are connected to the input end of the eighteenth resistor R18; the output end of the eighteenth resistor R18 is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC of the balance control input end EC <11> The gate of the PMOS switch tube MP8 is connected; the source of the PMOS switch tube MP7 is connected to the source of the PMOS switch tube MP8; the source of the PMOS switch tube MP7 and the source of the PMOS switch tube MP8 are respectively connected to the drain of the PMOS switch tube MP6; the source of the PMOS switch tube MP7 and the source of the PMOS switch tube MP8 are respectively connected to the input end of the sixteenth resistor R16; the gate of the PMOS switch tube MP6 is connected to the tenth output end EC of the balance control input end EC <9> connect;The output end of the sixteenth resistor R16 is connected to the source of the PMOS switch tube MP6; the output end of the sixteenth resistor R16 and the source of the PMOS switch tube MP6 are respectively connected to the drain of the PMOS switch tube MP5; the output end of the sixteenth resistor R16 and the source of the PMOS switch tube MP6 are respectively connected to the input end of the fifteenth resistor R15; the gate of the PMOS switch tube MP5 is connected to the ninth output end EC of the equalization control input end EC <8> The output end of the fifteenth resistor R15 is connected to the source of the PMOS switch tube MP5; the source of the PMOS switch tube MP5 is connected to the analog power supply terminal AVDD; the input end of the fourth resistor array 306 is connected to the input end of the twenty-first resistor R21 and the twenty-second resistor R22 in parallel; the output end of the twenty-first resistor R21 and the twenty-second resistor R22 in parallel is connected to the input end of the twenty-third resistor R23; the output end of the twenty-third resistor R23 is connected to the drain of the NMOS switch tube MN7; the output ends of the twenty-first resistor R21 and the twenty-second resistor R22 in parallel are respectively connected to the input end of the twenty-fourth resistor R24; the output end of the twenty-fourth resistor R24 ​​is connected to the drain of the NMOS switch tube MN8; the source of the NMOS switch tube MN7 is connected to the source of the NMOS switch tube MN8; the gate of the NMOS switch tube MN7 is connected to the thirteenth output terminal EC of the equalization control input terminal EC <12> Connect the gate of the NMOS switch tube MN8 to the sixteenth output terminal EC of the balanced control input terminal EC <15> The source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the drain of the NMOS switch tube MN6; the source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the input end of the twenty-fifth resistor R25; the source of the NMOS switch tube MN6 is connected to the output end of the twenty-fifth resistor R25; the gate of the NMOS switch tube MN6 is connected to the fourteenth output end EC of the balance control input end EC <13> The source of the NMOS switch tube MN6 and the output end of the 25th resistor R25 are respectively connected to the drain of the NMOS switch tube MN5; the source of the NMOS switch tube MN6 and the output end of the 25th resistor R25 are respectively connected to the input end of the 26th resistor R26; the source of the NMOS switch tube MN5 is connected to the output end of the 26th resistor R26 and is grounded at the same time; the gate of the NMOS switch tube MN5 is connected to the fifteenth output end EC of the equalization control input end EC <14> connect;

[0056] The input end of the main signal circuit 104 includes a third input end VI3, a fourth input end VI4 and a main control input end SC; the main control input end SC is a digital switch; the main control input end SC includes seven input ends and seven output ends, and the input ends correspond to the output ends one by one; the output end of the main signal circuit 104 includes a third output end VO3 and a fourth output end VO4;

[0057] The main signal circuit 104 includes a first impedance matching resistor array, a second impedance matching resistor array, a first coupling capacitor 204, a second coupling capacitor 205 and a common mode voltage circuit;

[0058] The first coupling capacitor 204 includes a first capacitor C1 and a sixth terminal SC of the main control input terminal SC. <5> ; The sixth terminal SC of the first capacitor C1 and the main control input terminal SC <5> in parallel;

[0059] The second coupling capacitor 205 includes a second capacitor C2 and a sixth terminal SC of the main control input terminal SC. <6> ; The sixth terminal SC of the second capacitor C2 and the main control input terminal SC <6> in parallel;

[0060] The first impedance matching resistor array R1 includes five resistors connected in parallel; each resistor is connected in series with a pair of input terminals and an output terminal of the main control input terminal SC; the five resistors are connected in series with the first terminal to the fifth terminal of the main control input terminal SC in sequence; the second impedance matching resistor array R2 is the same as the first impedance matching resistor array R1;

[0061] The third input terminal VI3 of the main signal circuit 104 is connected to the input terminal of the first impedance matching resistor array; the third input terminal VI3 of the main signal circuit 104 is connected to one end of the first coupling capacitor 204; the other end of the first coupling capacitor 204 is connected to the third output terminal VO3;

[0062] The fourth input terminal VI4 of the main signal circuit 104 is connected to the input terminal of the second impedance matching resistor array; the fourth input terminal VI4 of the main signal circuit 104 is connected to one end of the second coupling capacitor 205; the other end of the second coupling capacitor 205 is connected to the fourth output terminal VO4;

[0063] The output end of the first impedance matching resistor array and the output end of the second impedance matching resistor array are connected to the input end of the common mode voltage circuit 203; the output end of the common mode voltage circuit 203 is grounded;

[0064] The first impedance matching resistor array and the second impedance matching resistor array are used to receive data signals from the receiving end data path 101, and are also used to adjust the output impedance of the main signal circuit 104 to achieve impedance matching with the transmission line impedance, so as to reduce the signal reflection problem caused by impedance discontinuity;

[0065] The common-mode voltage circuit 203 is used to adjust the common-mode terminal voltage of the main signal circuit signal; the common-mode voltage circuit includes a first common-mode digital switch, a second common-mode digital switch and a third common-mode digital switch; the input end of the common-mode voltage circuit is respectively connected to the input end of the first common-mode digital switch, the input end of the second common-mode digital switch and the input end of the third common-mode digital switch; the output end of the first common-mode digital switch is connected to a 1.2V voltage; the output end of the second common-mode digital switch is connected to a 0.8V voltage; the output end of the third common-mode digital switch is connected to ground; in a DC coupling scenario, the common-mode voltage circuit output selects a 1.2V voltage mode or a grounding mode; in an AC coupling scenario, the common-mode voltage circuit output selects a 0.8V voltage mode.

[0066] The first signal superposition circuit 106 and the second signal superposition circuit 107 have the same structure;

[0067] The first signal superposition circuit 106 includes an enable control circuit 401, a first input pair of transistors 404, a second input pair of transistors 405, a first current source array 402, a second current source array 403, a first load resistor array 406 and a second load resistor array 407;

[0068] The first input pair of transistors 404 includes an NMOS transistor MN11 and an NMOS transistor MN12; the fifth input terminal VI5 of the first signal superposition circuit 106 is connected to the gate of MN11; the sixth input terminal VI6 of the first signal superposition circuit 106 is connected to the gate of MN12; the source of the NMOS transistor MN11 is connected to the source of the NMOS transistor MN12; the drain of MN11 is connected to the input terminal of the first load resistor array 406; the drain of MN12 is connected to the input terminal of the second load resistor array 407;

[0069] The first input pair of transistors 405 includes an NMOS transistor MN13 and an NMOS transistor MN14; the seventh input terminal VI7 of the first signal superposition circuit 106 is connected to the gate of MN13; the eighth input terminal VI8 of the first signal superposition circuit 106 is connected to the gate of MN14; the source of the NMOS transistor MN13 is connected to the source of the NMOS transistor MN14; the drain of MN13 is connected to the input terminal of the first load resistor array 406; the drain of MN14 is connected to the input terminal of the second load resistor array 407;

[0070] The first load resistor array 406 includes a twenty-eighth resistor R28, a PMOS switch tube MP9, a PMOS switch tube MP10 and a twenty-seventh resistor R27; the input end of the first load resistor array 406 is simultaneously connected to the input end of the twenty-eighth resistor R28, the input end of the twenty-seventh resistor R27 and the fifth output end VO5; the output end of the twenty-eighth resistor R28 is connected to the drain of the PMOS switch tube MP10; the source of the PMOS switch tube MP10 is connected to the analog power supply end AVDD; the gate of the PMOS switch tube MP10 is connected to the second output end S1 of the first superimposed control signal input end S1 <1> The output end of the twenty-seventh resistor R27 is connected to the drain of the PMOS switch tube MP9; the source of the PMOS switch tube MP9 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP9 is connected to the first output terminal S1 of the first superimposed control signal input terminal S1 <0> connect;

[0071] The second load resistor array 407 includes a twenty-ninth resistor R29, a PMOS switch tube MP11, a PMOS switch tube MP12 and a thirtieth resistor R30; the input end of the second load resistor array 407 is simultaneously connected to the input end of the twenty-ninth resistor R29, the input end of the thirtieth resistor R30 and the sixth output end VO6; the output end of the twenty-ninth resistor R29 is connected to the drain of the PMOS switch tube MP11; the source of the PMOS switch tube MP11 is connected to the analog power supply end AVDD; the gate of the PMOS switch tube MP11 is connected to the second output end S1 of the first superimposed control signal input end S1 <1> The output end of the 30th resistor R30 is connected to the drain of the PMOS switch tube MP12; the source of the PMOS switch tube MP12 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP12 is connected to the first output terminal S1 of the first superimposed control signal input terminal S1 <0> connect;

[0072] The first current source array includes four NMOS tubes; the sources of the four NMOS tubes are grounded respectively; the gate of each NMOS tube is connected in series with an output terminal of the first superposition control signal input terminal S1; the gates of the four NMOS tubes are connected in series with the fifth to eighth output terminals of the first superposition control signal input terminal S1 in sequence; the drains of the four NMOS tubes are connected in parallel and are connected to the source of the NMOS tube MN11 and the source of the NMOS tube MN12 respectively;

[0073] The second current source array includes four NMOS tubes; the sources of the four NMOS tubes are grounded respectively; the gate of each NMOS tube is connected in series with an output terminal of the first superposition control signal input terminal S1; the gates of the four NMOS tubes are connected in series with the ninth to twelfth output terminals of the first superposition control signal input terminal S1 in sequence; the drains of the four NMOS tubes are connected in parallel and are connected to the source of the NMOS tube MN13 and the source of the NMOS tube MN14 respectively;

[0074] The enabling control circuit includes an NMOS transistor MN9, an NMOS transistor MN10 and a PMOS switch transistor MP13; the first reference current input terminal I1 is connected to the drain of the NMOS transistor MN9 and the source of the PMOS switch transistor MP13 respectively; the source of the NMOS transistor MN9 is connected to the drain of the PMOS switch transistor MP13; the gate of the NMOS transistor MN9 is connected to the fourth input output terminal S1 of the first superimposed control signal input terminal S1 <3> The gate of the PMOS switch MP13 is connected to the third input terminal S1 of the first superimposed control signal input terminal S1. <2> The source of the NMOS tube MN9 is connected to the drain of the NMOS tube MN10; the source of the NMOS tube MN10 is grounded; the gate of the NMOS tube MN10 is connected to the third input and output terminal S1 of the first superimposed control signal input terminal S1 <2> The source of the NMOS tube MN9 is respectively connected to the gates of the four NMOS tubes of the first current source array; the source of the NMOS tube MN9 is respectively connected to the gates of the four NMOS tubes of the second current source array;

[0075] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0076] The present invention provides a radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit, which can superimpose and amplify the original high-frequency attenuated signal after being processed by the main signal circuit and the equalization signal circuit, thereby realizing the compensation processing of the data signal, avoiding the problems of the compensation degree limitation, power supply voltage limitation and power supply noise limitation caused by the prior art that only pre-compensation is performed at the transmitting end, so that a better signal compensation effect can be achieved, and the radiation resistance is possessed, the single particle effect is avoided, and the reliability of signal transmission is guaranteed. Among them, the single particle effect refers to the phenomenon that a single high-energy charged particle in space hits the sensitive part of the microelectronic device, and the device generates additional charge or causes the material atoms to shift due to the ionization effect, and its logical state changes, and the function is disturbed or fails.

[0077] like Figure 1As shown, the above-mentioned radiation-resistant FPGA has an embedded 28Gbps serial interface signal compensation circuit, including a main signal circuit, a balanced signal circuit, a signal superposition circuit and an anti-radiation circuit; the main signal circuit and the balanced signal circuit are respectively used to receive high-frequency attenuation signals, and the high-frequency attenuation signals come from the serial interface receiving end; the main signal circuit is also used to perform impedance matching and common-mode terminal voltage processing on the high-frequency attenuation signal according to the control signal of the main signal circuit, to obtain a main output signal, and input the main output signal into the signal superposition circuit; the balanced signal circuit is also used to perform balanced processing on the high-frequency attenuation signal according to the control signal of the balanced signal circuit, to obtain a balanced signal, and input the balanced signal into the signal superposition circuit; the signal superposition circuit is used to superimpose the main output signal and the balanced signal according to the control signal of the signal superposition circuit, to obtain a superposition signal; the anti-radiation circuit is used to reinforce the storage and output the control signals of the main signal circuit / balanced signal circuit / signal superposition circuit.

[0078] For example, Figure 2 As shown, in some optional embodiments, the receiving end data path 101 is a data signal path for receiving data from the system transmitting end and the transmission cable, and this data is a data signal after high-frequency attenuation. The first receiving output terminal RX1 of the receiving end data path 101 is respectively connected to the first input terminal VI3 of the main signal circuit 104 and the first input terminal VI1 of the equalizing signal circuit 105; the second receiving output terminal RX2 of the receiving end data path 101 is respectively connected to the second input terminal VI4 of the main signal circuit 104 and the second input terminal VI2 of the equalizing signal circuit 105; the receiving end data path 101 transmits the high-frequency attenuated signal to the equalizing signal circuit 105 for equalizing processing, and the receiving end data path 101 transmits the high-frequency attenuated signal to the main signal circuit 104 for impedance matching and common-mode terminal voltage processing.

[0079] Based on the same inventive concept, the radiation-resistant FPGA embedded serial interface signal compensation circuit provided in the embodiment of the present invention, the signal compensation set at the receiving end is not limited to the 28Gbps transmission rate, and can also be used in signal transmission at other transmission rates. Preferably, the signal compensation scheme provided in the embodiment of the present invention is suitable for signal transmission of a 28Gbps serial interface embedded in an FPGA.

[0080] like Figure 2As shown, in some optional embodiments, the anti-radiation circuit includes a first anti-radiation configuration circuit 102, a second anti-radiation configuration circuit 103 and an anti-radiation auxiliary circuit 108. The control signal output terminal CS1 of the first anti-radiation configuration circuit 102 is connected to the control signal input terminal EC of the equalization signal circuit 105, and is used to provide a control signal for the equalization signal circuit 105. The control signal output terminal CS2 of the second anti-radiation configuration circuit 103 is connected to the control signal input terminal SC of the main signal circuit 104, and is used to provide a control signal for the main signal circuit 104. The control signal output terminal CS1 of the first anti-radiation configuration circuit 102 is a digital switch signal, including 16 output terminals; the control signal output terminal CS2 of the second anti-radiation configuration circuit 103 is a digital switch signal, including 5 output terminals. The output terminals EN1 and EN2 of the anti-radiation auxiliary circuit 108 are both digital switch signals, each including 12 output terminals.

[0081] In the above-mentioned embodiment, the anti-radiation circuit as shown in the anti-radiation auxiliary circuit 108 includes a voltage and current bias circuit and an anti-radiation reinforcement storage circuit; the voltage and current bias circuit is used to provide a reference current for the current source array in the signal superposition circuit; the anti-radiation reinforcement storage circuit is used to reinforce the storage and output the control signal of the main signal circuit / balanced signal circuit / signal superposition circuit.

[0082] In the above-mentioned embodiments, the anti-radiation circuit as shown in the first anti-radiation configuration circuit 102 or the second anti-radiation configuration circuit 103 is composed of a digital logic circuit, specifically including a digital buffer unit, a radiation hardened storage unit, etc., and has the ability to resist the influence of single particle effects, that is, it has radiation resistance, and is used to provide a control signal for the main signal circuit 104 or the balanced signal circuit 105.

[0083] In some specific embodiments, when the transmission path of the superimposed signal includes at least two, the radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit also includes: a data delay processing circuit and a clock data recovery circuit; the data delay processing circuit is used to perform delay processing on the superimposed signal, and input the delayed superimposed signal into the data identification end and edge identification end of the clock data recovery circuit respectively; the clock data recovery circuit is used to perform data recovery and clock recovery on the superimposed signal after delay processing.

[0084] For example, Figure 2As shown, in some optional embodiments, the signal superposition circuit includes a first signal superposition circuit 106 and a second signal superposition circuit 107. At this time, when the transmission path of the superimposed signal includes four paths, they are: the first output terminal VO5 of the first signal superposition circuit 106 to the first input terminal VI13 of the data delay processing circuit 109, the second output terminal VO6 of the first signal superposition circuit 106 to the second input terminal VI14 of the data delay processing circuit 109, the first output terminal VO7 of the second signal superposition circuit 107 to the third input terminal VI15 of the data delay processing circuit 109, and the second output terminal VO8 of the second signal superposition circuit 107 to the fourth input terminal VI16 of the data delay processing circuit 109.

[0085] In some specific embodiments, the signal connection of the 28Gbps serial interface signal compensation circuit embedded in the radiation-resistant FPGA is as follows: the main signal circuit includes two signal input terminals, two signal output terminals and one control signal input terminal; the balanced signal circuit includes two signal input terminals, two signal output terminals and one control signal input terminal; the signal superposition circuit includes a first signal superposition circuit and a second signal superposition circuit with the same structure, and the first signal superposition circuit includes four signal input terminals, two signal output terminals, a control signal input terminal and a reference current input terminal; the anti-radiation circuit includes a first anti-radiation configuration circuit, a second anti-radiation configuration circuit and an anti-radiation auxiliary circuit, the control signal output terminal of the first anti-radiation configuration circuit is connected to the control signal input terminal of the balanced signal circuit, the control signal output terminal of the second anti-radiation configuration circuit is connected to the control signal input terminal of the main signal circuit, and the anti-radiation auxiliary circuit includes two control signal output terminals and two reference current output terminals. , a control signal output end of the anti-radiation auxiliary circuit is connected to the control signal input end of the first signal superposition circuit, a reference current output end of the anti-radiation auxiliary circuit is connected to the reference current input end of the first signal superposition circuit, another control signal output end of the anti-radiation auxiliary circuit is connected to the control signal input end of the second signal superposition circuit, and another reference current output end of the anti-radiation auxiliary circuit is connected to the reference current input end of the second signal superposition circuit; the two signal output ends of the main signal circuit are respectively connected to the two signal input ends of the first signal superposition circuit and the second signal superposition circuit, and the two signal output ends of the equalization signal circuit are respectively connected to the other two signal input ends of the first signal superposition circuit and the second signal superposition circuit; the anti-radiation FPGA embedded 28Gbps serial interface signal compensation circuit also includes a data delay processing circuit, and the data delay processing circuit includes four signal input ends, which are respectively connected to the signal output ends of the first signal superposition circuit and the second signal superposition circuit.

[0086] by Figure 2 Taking the connection shown in FIG. 1 as an example, the signal connection in the above implementation includes:

[0087] The first output terminal VO3 of the main signal circuit 104 is respectively connected to the third input terminal VI7 of the first signal superposition circuit 106 and the third input terminal VI11 of the second signal superposition circuit 107, and the second output terminal VO4 of the main signal circuit 104 is respectively connected to the fourth input terminal VI8 of the first signal superposition circuit 106 and the fourth input terminal VI12 of the second signal superposition circuit 107, for transmitting the high-frequency attenuated signal after impedance matching and setting the common-mode terminal voltage to the first signal superposition circuit 106 and the second signal superposition circuit 107 for superposition processing. The first output terminal VO1 of the equalized signal circuit 105 is respectively connected to the first input terminal VI5 of the first signal superposition circuit 106 and the first input terminal VI9 of the second signal superposition circuit 107, and the second output terminal VO2 of the equalized signal circuit 105 is respectively connected to the second input terminal VI6 of the first signal superposition circuit 106 and the second input terminal VI10 of the second signal superposition circuit 107, for transmitting the equalized signal after equalization processing to the first signal superposition circuit 106 and the second signal superposition circuit 107 for superposition processing.

[0088] Figure 2 In the embodiment, the first output terminal VO5 of the first signal superposition circuit 106 is connected to the first input terminal VI13 of the data delay processing circuit 109, and the second output terminal VO6 thereof is connected to the second input terminal VI14 of the data delay processing circuit 109; the first signal superposition circuit 106 superimposes the high-frequency attenuated signal processed by the main signal circuit 104 and the equalized signal processed by the equalized signal circuit 105 to achieve the signal compensation effect, and outputs the compensated signal to the data identification terminal of the clock data recovery circuit after delay processing. The first output terminal VO7 of the second signal superposition circuit 107 is connected to the third input terminal VI15 of the data delay processing circuit 109, and the second output terminal VO8 thereof is connected to the fourth input terminal VI16 of the data delay processing circuit 109; the second signal superposition circuit 106 superimposes the high-frequency attenuated signal processed by the main signal circuit 104 and the equalized signal processed by the equalized signal circuit 105 to achieve the signal compensation effect, and outputs the compensated signal to the edge identification terminal of the clock data recovery circuit after delay processing.

[0089] Figure 2In the embodiment, the control signal output terminal EN1 and the reference current output terminal B1 of the anti-radiation auxiliary circuit 108 are respectively connected to the control signal input terminal S1 and the reference current input terminal I1 of the first signal superposition circuit 106, and the control signal output terminal EN2 and the reference current output terminal B2 of the anti-radiation auxiliary circuit 108 are respectively connected to the control signal input terminal S2 and the reference current input terminal I2 of the second signal superposition circuit 107, so as to respectively provide control signals and bias voltages to the first signal superposition circuit 106 and the second signal superposition circuit 107. The first signal output terminal VO9 and the second signal output terminal VO10 of the data delay processing circuit 109 are respectively connected to the data identification terminal and the edge identification terminal of the clock and data recovery circuit CDR (Clock and Data Recovery) at the receiving end for data recovery and clock recovery.

[0090] In some specific embodiments, the main signal circuit includes an impedance matching resistor array, a common mode voltage circuit and an output signal control code switch; the impedance matching resistor array includes a switch with a multi-bit control code and a variable resistor array, which is used to receive a high-frequency attenuation signal and adjust the output impedance of the main signal circuit to match the transmission line impedance; the common mode voltage circuit is respectively connected to the variable resistor array and the ground terminal, and is used to adjust the common mode terminal voltage of the main signal circuit signal; the output signal control code switch is respectively connected to the impedance matching resistor array and the signal output terminal of the main signal circuit; the switch with a multi-bit control code and the output signal control code switch are used to receive the control signal of the main signal circuit output by the anti-radiation circuit.

[0091] For example, Figure 3 As shown, the main signal circuit 104 includes a first impedance matching resistor array, a second impedance matching resistor array, a common mode voltage circuit 203, a first coupling capacitor 204 and a second coupling capacitor 205. The first impedance matching resistor array and the second impedance matching resistor array are variable resistors composed of switches and resistor arrays R1 and R2 controlled by a five-bit control code, respectively, and are used to receive data signals from the receiving end data path 101, and are also used to adjust the output impedance of the main signal circuit 104 to achieve impedance matching with the transmission line impedance, so as to reduce the signal reflection problem caused by impedance discontinuity.

[0092] In some specific implementations, the common-mode voltage circuit includes a power supply mode, a grounding mode, and a two-thirds power supply mode. Different common-mode voltages are used for different application scenarios. Specifically, in a DC coupling scenario, the common-mode voltage circuit selects a power supply mode or a grounding mode; in an AC coupling scenario, the common-mode voltage circuit selects a two-thirds power supply mode.

[0093] For example, Figure 3As shown, the common mode voltage circuit 203 is used to adjust the common mode terminal voltage of the main signal circuit signal, and has three selection modes: connected to power supply, ground, and two-thirds of the power supply value. One of the three modes can be selected according to system application requirements.

[0094] There are two ways to use the coupling capacitor in the common mode voltage circuit 203. One is to use the coupling capacitor on the external board level; the other is to use the internal coupling capacitor when there is no external soldered coupling capacitor. When the internal coupling capacitor is selected, in some specific implementations, the main signal circuit further includes coupling capacitors, and each coupling capacitor is connected in parallel to both ends of the output signal control code switch. Figure 3 As shown, the first coupling capacitor 204 is controlled by the control code SC <5> The switch and capacitor C1 controlled by the control code SC are composed of the second coupling capacitor 205. <6> The controlled switch and capacitor C2 are used to select whether to transmit the signal from the receiving end data path 101 in the internal / external capacitor coupling mode. Figure 3 In the example, SC<6:0> indicates that the input terminal SC is a 7-bit control signal, including 7 input terminals and 7 output terminals, and the input terminals and output terminals correspond one to one. <0> Indicates the first bit of the SC signal, SC <6> Indicates the 7th bit of the control signal SC.

[0095] In some specific embodiments, the equalizing signal circuit includes a high-pass filter circuit; the high-pass filter circuit includes an input capacitor, a PMOS switch tube resistor array and an NMOS switch tube resistor array; the input capacitor is used to receive a high-frequency attenuation signal and transmit the signal to the PMOS switch tube resistor array and the NMOS switch tube resistor array; the PMOS switch tube resistor array includes multiple PMOS switch tubes and resistors, and the PMOS switch tube resistor array is respectively connected to the analog power supply end and the high-pass filter circuit signal output end; the NMOS switch tube resistor array includes multiple NMOS switch tubes and resistors, and the NMOS switch tube resistor array is respectively connected to the ground end and the high-pass filter circuit signal output end; the PMOS switch tubes of the PMOS switch tube resistor array and the NMOS switch tubes of the NMOS switch tube resistor array are used to receive the control signal of the equalizing signal circuit output by the anti-radiation circuit to turn on or off the high-pass filter circuit.

[0096] In some specific implementations, the equalization signal circuit further includes a redundant high-pass filter circuit; the redundant high-pass filter circuit has the same structure as the high-pass filter circuit.

[0097] For example, Figure 4As shown, the equalization signal circuit 105 includes a first input capacitor, a second input capacitor, a first resistor array 302, a second resistor array 303, a third resistor array 305, and a fourth resistor array 306. The first input capacitor, the first resistor array 302, and the second resistor array 303 respectively form a high-pass filter circuit; the second input capacitor, the third resistor array 305, and the fourth resistor array 306 respectively form a redundant high-pass filter circuit. The first resistor array 302 and the third resistor array 305 are respectively connected to the analog power supply terminal (AVDD), the first resistor array 302 is also connected to the high-pass filter circuit signal output terminal VO1, and the third resistor array 305 is also connected to the redundant high-pass filter circuit signal output terminal VO2. The second resistor array 303 and the fourth resistor array 306 are respectively connected to the ground terminal, the second resistor array 303 is also connected to the high-pass filter circuit signal output terminal VO1, and the fourth resistor array 306 is also connected to the redundant high-pass filter circuit signal output terminal VO2.

[0098] Figure 4 In the embodiment, the first input capacitor C3 is connected between the first input terminal VI1 of the balanced signal circuit 105 and the first output terminal VO1 of the balanced signal circuit 105, and the second input capacitor C4 is connected between the second input terminal VI2 of the balanced signal circuit 105 and the second output terminal VO2 of the balanced signal circuit 105.

[0099] Figure 4 In the embodiment, the first resistor array 302 is composed of PMOS switch tubes MP1, MP2, MP3, MP4 and resistors R3, R4, R5, R6, R7, R8; the second resistor array 303 is composed of NMOS switch tubes MN1, MN2, MN3, MN4 and resistors R9, R10, R11, R12, R13, R14; the third resistor array 305 is composed of PMOS switch tubes MP5, MP6, MP7, MP8 and resistors R15, R16, R17, R18, R19, R20; the fourth resistor array 306 is composed of NMOS switch tubes MN5, MN6, MN7, MN8 and resistors R21, R22, R23, R24, R25, R26. Taking the first resistor array 302 as an example, the internal connection of the resistor array is explained. After resistors R7 and R8 are connected in parallel, one end is connected to the first output terminal VO1 of the balanced signal circuit 105, and the other end of resistors R7 and R8 are connected in parallel to one end of resistors R5 and R6. The other end of resistor R5 is connected to the drain of MP3, and the other end of resistor R6 is connected to the drain of MP4. The sources of MP3 and MP4 are connected to each other. The drain of MP2 is connected to the source of MP3, and the resistor R4 is connected in parallel between the source and drain of MP2. The drain of MP1 is connected to the source of MP2, and the resistor R3 is connected in parallel between the source and drain of MP1. The source of MP1 is connected to the analog power supply terminal (AVDD).

[0100] Figure 4In the , EC<15:0> indicates that the input terminal EC is a 16-bit control signal, including 16 input terminals and 16 output terminals, and the input terminals and output terminals correspond one to one. <0> ,EC <1> ,EC <2> ,EC <3> The gate input terminals of the PMOS switch tubes MP1, MP2, MP3, and MP4 of the first resistor array 302 are connected to the 5th to 8th bits EC of the signal EC. <4> ,EC <5> ,EC <6> ,EC <7> The gate input terminals of the NMOS switch tubes MN3, MN2, MN1, and MN4 of the second resistor array 303 are connected to the 9th to 12th bits of the signal EC. <8> ,EC <9> ,EC <10> ,EC <11> The gate input terminals of the PMOS switch tubes MP5, MP6, MP7, and MP8 of the third resistor array 305 are connected to the 13th to 16th bits of the signal EC. <12> ,EC <13> ,EC <14> ,EC <15> They are respectively connected to the gate input terminals of the NMOS switch tubes MN7 , MN6 , MN5 , and MN8 of the fourth resistor array 306 .

[0101] In some specific embodiments, the balanced signal circuit includes a first working mode, a second working mode and a third working mode. In the first working mode, the high-pass filter circuit and the redundant high-pass filter circuit are both in an off state, and the high-frequency attenuation signal is output to the signal superposition circuit after passing through the input capacitor without passing through the PMOS switch tube resistor array and the NMOS switch tube resistor array; in the second working mode, the PMOS switch tube resistor array is in an on state, and the NMOS switch tube resistor array is in an off state. By controlling the PMOS switch tube and changing the resistance value of the PMOS switch tube resistor array, the high-frequency bandwidth of the high-pass filter circuit is controlled, and the high-frequency signal amplitude is processed without loss and the low-frequency signal amplitude is reduced to obtain a balanced signal; in the third working mode, the NMOS switch tube resistor array is in an on state, and the PMOS switch tube resistor array is in an off state. By controlling the NMOS switch tube and changing the resistance value of the NMOS switch tube resistor array, the high-frequency bandwidth of the redundant high-pass filter circuit is controlled, and the high-frequency signal amplitude is processed without loss and the low-frequency signal amplitude is reduced to obtain a balanced signal.

[0102] For example, Figure 4 In the balanced signal circuit shown, the PMOS switch tube and the NMOS switch tube are used to turn on and off the path resistance. When working normally, there are three selection modes:

[0103] The first working mode is that the first, second, third and fourth input resistor arrays are all in the off state. At this time, the high-pass filter circuit is not formed, the signal does not enter the compensation state, and the input signal is directly output to the first signal superposition circuit 106 and the second signal superposition circuit 107 of the next stage after passing through capacitors C3 and C4.

[0104] The second working mode is that the first and third resistor arrays are in the on state, and the second and fourth resistor arrays are in the off state. At this time, a high-pass filter circuit is formed and the signal is in a balanced state. The resistance values ​​of the first resistor array 302 and the third resistor array 305 are changed by the PMOS tube switch, thereby changing the high-frequency bandwidth of the high-pass filter to achieve different degrees of balanced effects. In the signal balanced state, after the high-frequency signal amplitude is processed without loss and the low-frequency signal amplitude is reduced, the balanced signal is output to the input end of the first signal superposition circuit 106 and the second signal superposition circuit 107.

[0105] The third working mode is that the first and third resistor arrays are in the off state, and the second and fourth resistor arrays are in the on state, at which time a high-pass filter circuit is formed and the signal is in a balanced state. The resistance values ​​of the second resistor array 303 and the third resistor array 306 are changed by the NMOS tube switch, thereby changing the high-frequency bandwidth of the high-pass filter to achieve different degrees of balanced effects. In the signal balanced state, after the high-frequency signal amplitude is processed without loss and the low-frequency signal amplitude is reduced, the balanced signal is output to the input end of the first signal superposition circuit 106 and the second signal superposition circuit 107.

[0106] In some specific embodiments, the signal superposition circuit includes an enable control circuit, an input pair of tubes, a current source array and a load resistor array; wherein the enable control circuit, the current source array and the load resistor array are used to receive the control signal of the signal superposition circuit output by the anti-radiation circuit; the enable control circuit includes a PMOS switch tube and an NMOS switch tube, which are used to control the bias voltage output by the anti-radiation circuit to be transmitted to the current source array, and control the on / off of the current source array; the input pair of tubes includes a pair of NMOS switch tubes, which are used to receive the main output signal and the balanced signal; the current source array is an NMOS switch tube current source array, and according to the control signal of the signal superposition circuit output by the anti-radiation circuit, the amplitude and gain multiple of the superposition signal are controlled by adjusting the current of the current source array; the load resistor array includes a PMOS switch tube and a resistor, which is used to control the amplitude and common mode terminal voltage of the superposition signal by adjusting the output resistance. The common mode terminal voltage control performed by the load resistor array can be adapted to the common mode of the previous stage to achieve better signal transmission. The common mode terminal voltage will affect the response speed of the next stage circuit. A more suitable common mode value will make the response speed of the next stage circuit faster.

[0107] For example, Figure 5 The signal superposition circuit shown in the figure, the first signal superposition circuit 106 includes an enable control circuit 401, a first input pair of transistors 404, a second input pair of transistors 405, a first current source array 402, a second current source array 403, a first load resistor array 406, and a second load resistor array 407. The first signal superposition circuit 106 includes signal input terminals VIN5, VIN6, VIN7, and VIN8 (corresponding to Figure 2 VI5, VI6, VI7 and VI8 in the figure), signal output terminals VO5 and VO6, reference current input terminal I1, and control signal input terminal S1<11:0>, where S1<11:0> indicates that input terminal S1 is a 12-bit control signal, including 12 input terminals and 12 output terminals, and the input terminals and output terminals correspond to each other. The enabling control circuit 401 is composed of a PMOS switch tube MP13 and NMOS switch tubes MN9 and MN10, the source of MN10 is grounded, the source of MP13 is connected to the drain of MN9, and the drain of MP13 is connected to the source of MN9. The reference current input terminal I1 of the first signal superposition circuit 106 is connected to the source of MP13 and the drain of MN9, and the gate of MN9 is connected to the 4th output terminal S1 of S1. <3> MN10 and MP13 gates are connected to the 3rd output terminal S1 of S1 <2> The enabling control circuit 401 is used to control the bias voltage output by the anti-radiation auxiliary circuit 108 to be transmitted to the first current source array 402 and the second current source array 403, and is also used to turn off the first and second current source arrays in a non-working state and enter a low power consumption mode. The bias voltage provides a reference current to the current source array in the signal superposition circuit.

[0108] Figure 5 In the embodiment, the first input pair of transistors 404 is composed of NMOS transistors MN11 and MN12, the sources of MN11 and MN12 are connected to each other, the drains of MN11 and MN12 are connected to the first load resistor array 406 and the second load resistor array 407 respectively, and the gates of MN11 and MN12 are connected to the signal input terminals VIN5 and VIN6 of the first signal superposition circuit 106 respectively, for receiving the output signal of the balanced signal circuit 105. The second input pair of transistors 405 is composed of NMOS transistors MN13 and MN14, the sources of MN13 and MN14 are connected to each other, the drains of MN13 and MN14 are connected to the first load resistor array 406 and the second load resistor array 407 respectively, and the gates of MN13 and MN14 are connected to the signal input terminals VIN7 and VIN8 of the first signal superposition circuit 106 respectively, for receiving the output signal of the main signal circuit 104.

[0109] Figure 5In the embodiment, the first current source array 402 and the second current source array 403 are respectively composed of NMOS transistor current source arrays MN15 and MN16, whose current magnitudes are respectively adjusted by the 5th to 8th bit output terminals S1<7:4> and the 9th to 12th bit output terminals S1<11:8> of the control signal S1, and the amplitude and gain multiple of the output signal of the first signal superposition circuit 106 are adjusted by changing the magnitude of the current, and the source electrodes of the NMOS transistor current source arrays MN15 and MN16 are grounded. The first load resistor array 406 is composed of PMOS switch tubes MP9, MP10 and resistors R27, R28, and the second load resistor array 407 is respectively composed of PMOS switch tubes MP11, MP12 and resistors R29, R30, and is used to adjust the output resistance value, thereby changing the amplitude and common mode terminal voltage of the output signal of the first signal superposition circuit 106. The gates of MP9 and MP12 are connected to the 1st bit output terminal S1 of S1. <0> The gates of MP10 and MP11 are connected to the second output terminal S1 of S1. <1> . The sources of MP9, MP10, MP11, and MP12 are connected to the analog power supply terminal (AVDD). One end of the resistor R27 is connected to the drain of the PMOS switch tube MP9, and the other end is connected to the signal output terminal VO5. One end of the resistor R28 is connected to the drain of the PMOS switch tube MP10, and the other end is connected to the drain of the NMOS tube MN11, the drain of the NMOS tube MN13, and the signal output terminal VO5. One end of the resistor R30 is connected to the drain of the PMOS switch tube MP12, and the other end is connected to the signal output terminal VO6. One end of the resistor R29 is connected to the drain of the PMOS switch tube MP11, and the other end is connected to the drain of the NMOS tube MN12, the drain of the NMOS tube MN14, and the signal output terminal VO6.

[0110] The first signal superposition circuit 106 and the second signal superposition circuit 107 superimpose and amplify the high-frequency attenuated signal of the main signal circuit 104 and the low-frequency attenuated signal of the equalization signal circuit 105 to achieve compensation processing of the data signal. The second signal superposition circuit 107 has the same structure as the first signal superposition circuit 106.

[0111] The signal compensation circuit proposed in the present invention can superimpose and amplify the original high-frequency attenuated signal after being processed by the main signal circuit and the equalization signal circuit at the receiving end, thereby realizing compensation processing of the data signal, avoiding the problems of compensation degree limitation, power supply voltage limitation and power supply noise limitation brought about by the prior art of only performing pre-compensation at the sending end, thereby achieving better signal compensation effect and reducing bit errors.

[0112] In some embodiments of the present invention, when the superimposed signal output by the signal superposition circuit proposed in the present invention is divided into two or more transmission paths, the compensated signal is respectively transmitted to the data identification end and edge identification end of the clock data recovery circuit after delay processing, so as to perform clock and data recovery processing, which helps to achieve better signal fidelity and reduce bit errors.

Claims

1. The radiation-resistant FPGA has an embedded 28Gbps serial interface signal compensation circuit, which is characterized by: It includes a data receiving end, a main signal circuit, an equalization signal circuit, a first signal superposition circuit, a first anti-radiation configuration circuit, a second anti-radiation configuration circuit and an anti-radiation auxiliary circuit; the data receiving end includes a first receiving output end (RX1) and a second receiving output end (RX2); The first anti-radiation configuration circuit is used to reinforce the storage and output of the control signal of the equalization signal circuit; the second anti-radiation configuration circuit is used to reinforce the storage and output of the control signal of the main signal circuit; the anti-radiation auxiliary circuit is used to reinforce the storage and output of the control signal of the signal superposition circuit; the output end of the first anti-radiation configuration circuit is the first control signal (CS1); the output end of the second anti-radiation configuration circuit is the second control signal (CS2); the anti-radiation auxiliary circuit includes a first control signal output end (EN1), a second control signal output end (EN2), a first reference current output end (B1) and a second reference current output end (B2); The main signal circuit performs impedance matching and common-mode terminal voltage processing on the high-frequency attenuation signal according to the control signal of the first anti-radiation configuration circuit to obtain a main output signal, and inputs the main output signal into the first signal superposition circuit; The equalization signal circuit performs equalization processing on the high-frequency attenuation signal according to the control signal of the second anti-radiation configuration circuit to obtain an equalization signal, and inputs the equalization signal into the first signal superposition circuit; The first signal superposition circuit superimposes the main output signal and the equalization signal according to the control signal of the anti-radiation auxiliary circuit to obtain a superimposed signal; and then connects the superimposed signal to the data identification terminal and the edge identification terminal respectively; the input terminal of the first signal superposition circuit includes a fifth input terminal (VI5), a sixth input terminal (VI6), a seventh input terminal (VI7), an eighth input terminal (VI8), a first reference current input terminal (I1) and a first superimposed control signal input terminal (S1); the first superimposed control signal input terminal (S1) is connected to the first control signal output terminal (EN1); the first reference current input terminal (I1) is connected to the first reference current output terminal (B1); the first superimposed control signal input terminal (S1) is a 12-bit control signal, and the first superimposed control signal input terminal (S1) includes 12 input terminals and 12 output terminals, and the input terminals and the output terminals correspond to each other one by one; the output terminal of the first signal superposition circuit (106) includes a fifth output terminal (VO5) and a sixth output terminal (VO6); the fifth output terminal (VO5) is connected to the data identification terminal; and the sixth output terminal (VO6) is connected to the edge identification terminal.

2. The radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 1, characterized in that: The input end of the main signal circuit (104) includes a third input end (VI3), a fourth input end (VI4) and a main control input end (SC); the main control input end (SC) is a digital switch; the main control input end (SC) includes seven input ends and seven output ends, and the input ends correspond to the output ends one by one; the main control input end (SC) is connected to the second control signal (CS2); the output end of the main signal circuit (104) includes a third output end (VO3) and a fourth output end (VO4); the first receiving output end (RX1) is connected to the third input end (VI3); the second receiving output end (RX2) is connected to the fourth input end (VI4); the third output end (VO3) is connected to the seventh input end (VI7); the fourth output end (VO4) is connected to the eighth input end (VI8); The main signal circuit (104) comprises a first impedance matching resistor array, a second impedance matching resistor array, a first coupling capacitor (204), a second coupling capacitor (205) and a common mode voltage circuit; The first coupling capacitor (204) comprises a first capacitor (C1) and a sixth terminal SC of the main control input terminal (SC). <5> ; The sixth terminal SC of the first capacitor (C1) and the main control input terminal (SC) <5> in parallel; The second coupling capacitor (205) comprises a second capacitor (C2) and a sixth terminal SC of the main control input terminal (SC). <6> ; The sixth terminal SC of the second capacitor (C2) and the main control input terminal (SC) <6> in parallel; The first impedance matching resistor array (R1) comprises five resistors connected in parallel; each resistor is connected in series with a pair of input terminals and an output terminal of a main control input terminal (SC); the five resistors are connected in series with the first terminal to the fifth terminal of the main control input terminal (SC) in sequence; the second impedance matching resistor array (R2) is the same as the first impedance matching resistor array (R1); The third input end (VI3) of the main signal circuit (104) is connected to the input end of the first impedance matching resistor array; the third input end (VI3) of the main signal circuit (104) is connected to one end of the first coupling capacitor (204); the other end of the first coupling capacitor (204) is connected to the third output end (VO3); The fourth input terminal (VI4) of the main signal circuit (104) is connected to the input terminal of the second impedance matching resistor array; the fourth input terminal (VI4) of the main signal circuit (104) is connected to one end of the second coupling capacitor (205); the other end of the second coupling capacitor (205) is connected to the fourth output terminal (VO4); The output end of the first impedance matching resistor array and the output end of the second impedance matching resistor array are connected to the input end of a common mode voltage circuit (203); the common mode voltage circuit (203) is used to adjust the common mode terminal voltage of the main signal circuit signal.

3. The radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 1, characterized in that: The input end of the equalizing signal circuit (105) comprises a first input end (VI1), a second input end (VI2) and an equalizing control input end (EC); the equalizing control input end (EC) is a digital switch; the equalizing control input end (EC) comprises sixteen input ends and sixteen output ends, and the input ends correspond to the output ends one by one; the equalizing control input end (EC) is connected to a first control signal (CS1); the output end of the equalizing signal circuit (105) comprises a first output end (VO1) and a second output end (VO2); the first input end (VI1) is connected to a first receiving output end (RX1); The second input terminal (VI2) is connected to the second receiving output terminal (RX2); the first output terminal (VO1) is connected to the fifth input terminal (VI5); the second output terminal (VO2) is connected to the sixth input terminal (VI6); The balanced signal circuit (105) comprises a first resistor array (302), a second resistor array (303), a third resistor array (305), a fourth resistor array (306), a first input capacitor (C3), and a second input capacitor (C4); a first input terminal (VI1) of the balanced signal circuit (105) is connected to an input terminal of the first input capacitor (C3); an output terminal of the first input capacitor (C3) is respectively connected to an input terminal of the first resistor array, an input terminal of the second resistor array, and a first output terminal (VO1); a second input terminal (VI2) of the balanced signal circuit (105) is connected to a second input terminal (VI3) of the balanced signal circuit (105); The input end of the input capacitor (C4) is connected; the output end of the second input capacitor (C4) is respectively connected to the input end of the third resistor array, the input end of the fourth resistor array and the second output end (VO2) of the equalization signal circuit; the input end of the first resistor array (302) is connected to the input end of the seventh resistor (R7) and the eighth resistor (R8) connected in parallel; the output end of the seventh resistor (R7) and the eighth resistor (R8) connected in parallel is connected to the input end of the fifth resistor (R5); the output end of the fifth resistor (R5) is connected to the drain of the PMOS switch tube MP3; the third output end EC of the equalization control input end (EC) is connected to the third output end EC of the equalization control input end (EC). <2> The output end of the seventh resistor (R7) and the eighth resistor (R8) connected in parallel is connected to the input end of the sixth resistor (R6); the output end of the sixth resistor (R6) is connected to the drain of the PMOS switch tube MP4; the fourth output end EC of the balance control input end (EC) <3> The gate of the PMOS switch tube MP4 is connected; the source of the PMOS switch tube MP4 is connected to the source of the PMOS switch tube MP3; the source of the PMOS switch tube MP4 and the source of the PMOS switch tube MP3 are respectively connected to the drain of the PMOS switch tube MP2; the source of the PMOS switch tube MP4 and the source of the PMOS switch tube MP3 are respectively connected to the input end of the fourth resistor (R4); the gate of the PMOS switch tube MP2 is connected to the second output end EC of the equalization control input end (EC) <1> The output end of the fourth resistor (R4) is connected to the source of the PMOS switch tube MP2; the output end of the fourth resistor (R4) and the source of the PMOS switch tube MP2 are respectively connected to the drain of the PMOS switch tube MP1; the output end of the fourth resistor (R4) and the source of the PMOS switch tube MP2 are respectively connected to the input end of the third resistor (R3); the gate of the PMOS switch tube MP1 is connected to the first output end EC of the equalization control input end (EC) <0> connection; the output end of the third resistor (R3) is connected to the source of the PMOS switch tube MP1; The source of the PMOS switch tube MP1 is connected to the analog power supply terminal AVDD; The input end of the second resistor array (303) is connected to the input end of the ninth resistor (R9) and the tenth resistor (R10) connected in parallel; the output end of the ninth resistor (R9) and the tenth resistor (R10) connected in parallel is connected to the input end of the eleventh resistor (R11); the output end of the eleventh resistor (R11) is connected to the drain of the NMOS switch tube MN3; the output end of the ninth resistor (R9) and the tenth resistor (R10) connected in parallel is connected to the input end of the twelfth resistor (R12); the output end of the twelfth resistor (R12) is connected to the drain of the NMOS switch tube MN4; the source of the NMOS switch tube MN3 is connected to the source of the NMOS switch tube MN4; the gate of the NMOS switch tube MN3 is connected to the fifth output end EC of the equalization control input end (EC) <4> Connect the gate of the NMOS switch tube MN4 to the eighth output terminal EC of the balanced control input terminal (EC) <7> The source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the drain of the NMOS switch tube MN2; the source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the input end of the thirteenth resistor (R13); the source of the NMOS switch tube MN2 is connected to the output end of the thirteenth resistor (R13); the gate of the NMOS switch tube MN2 is connected to the sixth output end EC of the balance control input end (EC) <5> The source of the NMOS switch tube MN2 and the output end of the thirteenth resistor (R13) are respectively connected to the drain of the NMOS switch tube MN1; the source of the NMOS switch tube MN2 and the output end of the thirteenth resistor (R13) are respectively connected to the input end of the fourteenth resistor (R14); the source of the NMOS switch tube MN1 is connected to the output end of the fourteenth resistor (R14) and is grounded at the same time; the gate of the NMOS switch tube MN1 is connected to the seventh output end EC of the equalization control input end (EC) <6> The input end of the third resistor array (305) is connected to the input end of the nineteenth resistor (R19) and the twentieth resistor (R20) connected in parallel; the output end of the nineteenth resistor (R19) and the twentieth resistor (R20) connected in parallel is connected to the input end of the seventeenth resistor (R17); the output end of the seventeenth resistor (R17) is connected to the drain of the PMOS switch tube MP7; the eleventh output end EC of the balance control input end (EC) is connected to the input end of the eleventh resistor (R17); <10> The output end of the nineteenth resistor (R19) and the twentieth resistor (R20) connected in parallel is connected to the input end of the eighteenth resistor (R18); the output end of the eighteenth resistor (R18) is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC of the balance control input end (EC) is connected to the gate of the PMOS tube MP7; the output end of the nineteenth resistor (R19) and the twentieth resistor (R20) connected in parallel is connected to the input end of the eighteenth resistor (R18); the output end of the eighteenth resistor (R18) is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC of the balance control input end (EC) <11> The gate electrode of the PMOS tube MP8 is connected; the source electrode of the PMOS switch tube MP7 is connected to the source electrode of the PMOS tube MP8; the source electrode of the PMOS switch tube MP7 and the source electrode of the PMOS tube MP8 are connected to the drain electrode of the PMOS switch tube MP6 respectively;The source of the PMOS switch tube MP7 and the source of the PMOS tube MP8 are respectively connected to the input end of the sixteenth resistor (R16); the gate of the PMOS switch tube MP6 is connected to the tenth output end EC of the equalization control input end (EC). <9> The output end of the sixteenth resistor (R16) is connected to the source of the PMOS switch tube MP6; the output end of the sixteenth resistor (R16) and the source of the PMOS switch tube MP6 are respectively connected to the drain of the PMOS switch tube MP5; the output end of the sixteenth resistor (R16) and the source of the PMOS switch tube MP6 are respectively connected to the input end of the fifteenth resistor (R15); the gate of the PMOS switch tube MP5 is connected to the ninth output end EC of the equalization control input end (EC) <8> The output end of the fifteenth resistor (R15) is connected to the source of the PMOS switch tube MP5; the source of the PMOS switch tube MP5 is connected to the analog power supply terminal AVDD; the input end of the fourth resistor array (306) is connected to the input end of the twenty-first resistor (R21) and the twenty-second resistor (R22) connected in parallel; the output end of the twenty-first resistor (R21) and the twenty-second resistor (R22) connected in parallel is connected to the input end of the twenty-third resistor (R23); the output end of the twenty-third resistor (R23) is connected to the drain of the NMOS switch tube MN7; the output end of the twenty-first resistor (R21) and the twenty-second resistor (R22) connected in parallel are respectively connected to the input end of the twenty-fourth resistor (R24); the output end of the twenty-fourth resistor (R24) is connected to the drain of the NMOS switch tube MN8; the source of the NMOS switch tube MN7 is connected to the source of the NMOS switch tube MN8; the gate of the NMOS switch tube MN7 is connected to the thirteenth output end EC of the equalization control input end (EC) <12> Connect the gate of the NMOS switch tube MN8 to the sixteenth output terminal EC of the balanced control input terminal (EC) <15> The source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the drain of the NMOS switch tube MN6; the source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the input end of the twenty-fifth resistor (R25); the source of the NMOS switch tube MN6 is connected to the output end of the twenty-fifth resistor (R25); the gate of the NMOS switch tube MN6 is connected to the fourteenth output end EC of the equalization control input end (EC) <13> The source of the NMOS switch tube MN6 and the output end of the 25th resistor (R25) are respectively connected to the drain of the NMOS switch tube MN5; the source of the NMOS switch tube MN6 and the output end of the 25th resistor (R25) are respectively connected to the input end of the 26th resistor (R26); the source of the NMOS switch tube MN5 is connected to the output end of the 26th resistor (R26) and is grounded at the same time; the gate of the NMOS switch tube MN5 is connected to the 15th output end EC of the equalization control input end (EC) <14> connect.; 4. The radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 1, characterized in that: The first signal superposition circuit (106) comprises an enable control circuit (401), a first input pair of transistors (404), a second input pair of transistors (405), a first current source array (402), a second current source array (403), a first load resistor array (406) and a second load resistor array (407); The first input pair of transistors (404) comprises an NMOS transistor MN11 and an NMOS transistor MN12; the fifth input terminal (VI5) of the first signal superposition circuit (106) is connected to the gate of MN11; the sixth input terminal (VI6) of the first signal superposition circuit (106) is connected to the gate of MN12; the source of the NMOS transistor MN11 is connected to the source of the NMOS transistor MN12; the drain of MN11 is connected to the input terminal of the first load resistor array (406); and the drain of MN12 is connected to the input terminal of the second load resistor array (407); The second input pair of transistors (405) comprises an NMOS transistor MN13 and an NMOS transistor MN14; the seventh input terminal (VI7) of the first signal superposition circuit (106) is connected to the gate of MN13; the eighth input terminal (VI8) of the first signal superposition circuit (106) is connected to the gate of MN14; the source of the NMOS transistor MN13 is connected to the source of the NMOS transistor MN14; the drain of MN13 is connected to the input terminal of the first load resistor array (406); and the drain of MN14 is connected to the input terminal of the second load resistor array (407); The first load resistor array (406) comprises a twenty-eighth resistor (R28), a PMOS switch tube MP9, a PMOS switch tube MP10 and a twenty-seventh resistor (R27); an input end of the first load resistor array (406) is simultaneously connected to an input end of the twenty-eighth resistor (R28), an input end of the twenty-seventh resistor (R27) and a fifth output end (VO5); an output end of the twenty-eighth resistor (R28) is connected to a drain of the PMOS switch tube MP10; a source of the PMOS switch tube MP10 is connected to an analog power supply end AVDD; a gate of the PMOS switch tube MP10 is connected to a second output end S1 of the first superimposed control signal input end (S1). <1> The output end of the twenty-seventh resistor (R27) is connected to the drain of the PMOS switch tube MP9; the source of the PMOS switch tube MP9 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP9 is connected to the first output terminal S1 of the first superimposed control signal input terminal (S1) <0> connect; The second load resistor array (407) comprises a twenty-ninth resistor (R29), a PMOS switch tube MP11, a PMOS switch tube MP12 and a thirtieth resistor (R30); the input end of the second load resistor array (407) is simultaneously connected to the input end of the twenty-ninth resistor (R29), the input end of the thirtieth resistor (R30) and the sixth output end (VO6); the output end of the twenty-ninth resistor (R29) is connected to the drain of the PMOS switch tube MP11; the source of the PMOS switch tube MP11 is connected to the analog power supply end AVDD; the gate of the PMOS switch tube MP11 is connected to the second output end S1 of the first superimposed control signal input end (S1) <1> The output end of the 30th resistor (R30) is connected to the drain of the PMOS switch tube MP12; the source of the PMOS switch tube MP12 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP12 is connected to the first output terminal S1 of the first superimposed control signal input terminal (S1) <0> connect; The first current source array comprises four NMOS tubes; the sources of the four NMOS tubes are respectively grounded; the gate of each NMOS tube is connected in series with an output terminal of the first superposition control signal input terminal (S1); the gates of the four NMOS tubes are connected in series with the fifth to eighth output terminals of the first superposition control signal input terminal (S1) in sequence; the drains of the four NMOS tubes are connected in parallel and are respectively connected to the source of the NMOS tube MN11 and the source of the NMOS tube MN12; The second current source array comprises four NMOS tubes; the sources of the four NMOS tubes are respectively grounded; the gate of each NMOS tube is connected in series with an output terminal of the first superposition control signal input terminal (S1); the gates of the four NMOS tubes are connected in series with the ninth to twelfth output terminals of the first superposition control signal input terminal (S1) in sequence; the drains of the four NMOS tubes are connected in parallel and are respectively connected to the source of the NMOS tube MN13 and the source of the NMOS tube MN14; The enabling control circuit comprises an NMOS transistor MN9, an NMOS transistor MN10 and a PMOS switch transistor MP13; the first reference current input terminal (I1) is respectively connected to the drain of the NMOS transistor MN9 and the source of the PMOS switch transistor MP13; the source of the NMOS transistor MN9 is connected to the drain of the PMOS switch transistor MP13; the gate of the NMOS transistor MN9 is connected to the fourth input output terminal S1 of the first superposition control signal input terminal (S1); <3> Connect the gate of the PMOS switch tube MP13 to the third input output terminal S1 of the first superimposed control signal input terminal (S1) <2> The source of the NMOS tube MN9 is connected to the drain of the NMOS tube MN10; the source of the NMOS tube MN10 is grounded; the gate of the NMOS tube MN10 is connected to the third input-output terminal S1 of the first superimposed control signal input terminal (S1) <2> The source of the NMOS tube MN9 is respectively connected to the gates of the four NMOS tubes of the first current source array; the source of the NMOS tube MN9 is respectively connected to the gates of the four NMOS tubes of the second current source array.

5. The radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 4, characterized in that: The radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit comprises a second signal superposition circuit; the second signal superposition circuit superimposes the main output signal and the equalization signal according to the control signal of the radiation-resistant auxiliary circuit to obtain a superposition signal; the first signal superposition circuit has the same structure as the second signal superposition circuit; the input of the second signal superposition circuit (107) comprises a ninth input terminal (VI9), a tenth input terminal (VI10), an eleventh input terminal (VI11), a twelfth input terminal (VI12), a second reference current input terminal (I2) and a second superposition control signal input terminal (S2); the ninth input terminal (VI9) is connected to the first output terminal (VO1); the tenth input terminal (VI10) is connected to the second output terminal (VO2); the eleventh input terminal (VI11) is connected to the third output terminal (VO3); the twelfth input terminal (VI12) is connected to the fourth output terminal (VO4); the second superposition control signal input terminal (S2) is connected to the second control signal output terminal (EN2); the second reference current input terminal (I2) is connected to the second reference current output terminal (B2); the second superposition control signal The first signal superposition circuit (107) is connected to the data delay processing circuit, wherein the first signal superposition circuit (107) and the second signal superposition circuit (107) are connected to each other via a 12-bit control signal input terminal (S2); the second superposition control signal input terminal (S2) includes 12 input terminals and 12 output terminals, and the input terminals and the output terminals correspond to each other one by one; the output of the second signal superposition circuit (107) is the seventh output terminal (VO7) and the eighth output terminal (VO8); the fifth output terminal (VO5), the sixth output terminal (VO6), the seventh output terminal (VO7) and the eighth output terminal (VO8) are connected to the input terminal of the data delay processing circuit in sequence; the data delay processing circuit connects the first signal superposition circuit and the second signal superposition circuit to the data delay processing circuit. The superimposed signal output by the adding circuit is delayed, and the superimposed signal after the delay processing is respectively input into the data identification terminal and the edge identification terminal; the input of the data delay processing circuit includes a thirteenth input terminal (VI13), a fourteenth input terminal (VI14), a fifteenth input terminal (VI15) and a sixteenth input terminal (VI16); the output of the data delay processing circuit is a ninth output terminal (VO9) and a tenth output terminal (VO10); the ninth output terminal (VO9) is connected to the data identification terminal; and the tenth output terminal (VO10) is connected to the edge identification terminal.

6. The radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 2, characterized in that: The common-mode voltage circuit includes a first common-mode digital switch, a second common-mode digital switch and a third common-mode digital switch; the input end of the common-mode voltage circuit is respectively connected to the input end of the first common-mode digital switch, the input end of the second common-mode digital switch and the input end of the third common-mode digital switch; the output end of the first common-mode digital switch is connected to a 1.2V voltage; the output end of the second common-mode digital switch is connected to a 0.8V voltage; the output end of the third common-mode digital switch is connected to ground; in a DC coupling scenario, the common-mode voltage circuit output selects a 1.2V voltage mode or a grounding mode; in an AC coupling scenario, the common-mode voltage circuit output selects a 0.8V voltage mode.

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