Interstage reference voltage calibration circuit and calibration method for pipelined analog-to-digital converter

Abstract

The invention relates to the technical field of analog-to-digital conversion, and discloses an inter-stage reference voltage calibration circuit for a pipelined analog-to-digital converter, which comprises a comparator connected with a pre-stage reference voltage buffer and a post-stage reference voltage buffer and used for comparing the magnitude of a benchmark reference voltage and the magnitude of a post-stage reference voltage; wherein the benchmark reference voltage is constructed by a pre-stage reference voltage buffer; and the state machine is connected with the comparator and is used for controlling the adjustable resistor array of the post-stage reference voltage buffer according to the comparison result of the comparator so as to adjust the post-stage reference voltage. According to the calibration circuit, only one comparator is added on hardware, the post-stage reference voltage is adjusted according to the comparison result of the comparator so as to resist disappearance, and the energy consumption of the comparator is low. The invention further discloses an inter-stage reference voltage calibration method for the pipelined analog-to-digital converter.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital conversion, for example, to an inter-stage reference voltage calibration circuit and calibration method for a pipeline analog-to-digital converter. Background Art

[0002] Pipeline ADC (Pipeline Analog-to-Digital Converter) is a type of analog-to-digital converter, which consists of multiple sub-pipeline stages, each of which has a similar circuit architecture. Each sub-pipeline stage contains a low-resolution sub-ADC (commonly Flash ADC or SAR ADC), a DAC, and an inter-stage residual amplifier. The residual amplifier amplifies the remaining signal after the current stage is quantized, and then the next stage performs fine quantization.

[0003] In order to prevent the linearity of the operational amplifier from decreasing as the differential value of the input signal increases, the pipeline ADC uses interstage gain attenuation technology. That is, by reducing the quantization range of the second-stage sub-ADC to half of the first-stage, the interstage gain is halved, thereby reducing the design difficulty. The common implementation of interstage gain attenuation technology is to set the second-stage reference voltage to half of the first-stage reference voltage, and the reference voltage is usually provided by an on-chip reference buffer. However, when the DC value ratio of the two-stage reference voltage deviates from the designed value, an interstage gain error will occur. The interstage gain error will seriously affect the dynamic performance of the pipeline linear analog-to-digital converter, causing errors in the quantization results.

[0004] For inter-stage gain errors, off-chip digital domain calibration is generally used. However, the power consumption of off-chip digital domain calibration is relatively high and it cannot be applied on a large scale.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide an inter-stage reference voltage calibration circuit and a calibration method for a pipeline analog-to-digital converter, so as to provide a calibration circuit with low power consumption.

[0008] In some embodiments, the circuit includes: a comparator, connected to a front-stage reference voltage buffer and a rear-stage reference voltage buffer, for comparing the magnitude of a reference reference voltage and a rear-stage reference voltage; wherein the reference reference voltage is constructed by the front-stage reference voltage buffer; a state machine, connected to the comparator, for controlling an adjustable resistor array of the rear-stage reference voltage buffer according to the comparison result of the comparator to adjust the rear-stage reference voltage.

[0009] In some embodiments, the method includes: when a calibration control clock is received, controlling a comparator to compare a baseline reference voltage and a subsequent-stage reference voltage; determining whether the subsequent-stage reference voltage needs to be calibrated based on the comparison result; and when it is determined that the subsequent-stage reference voltage needs to be calibrated, adjusting an adjustable resistor array of a subsequent-stage reference voltage buffer based on the comparison result.

[0010] The inter-stage reference voltage calibration circuit and calibration method for a pipeline analog-to-digital converter provided in the embodiments of the present disclosure can achieve the following technical effects:

[0011] Comparators and state machines are introduced on the basis of the original circuit. A reference voltage is constructed and compared with the subsequent reference voltage. When the two are mismatched, the mismatch is offset by adjusting the size of the subsequent reference voltage. The calibration circuit only adds a comparator to the hardware, and the comparator consumes less energy. In addition, the calibration circuit does not affect other modules of the analog-to-digital converter, which is easy to transplant.

[0012] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0014] Figure 1 is a schematic diagram of an inter-stage reference voltage calibration circuit of a pipeline analog-to-digital converter provided by an embodiment of the present disclosure;

[0015] Figure 2 is a circuit diagram of a front-stage reference voltage buffer provided by an embodiment of the present disclosure;

[0016] Figure 3 is a schematic diagram of a calibration circuit provided by an embodiment of the present disclosure;

[0017] Figure 4 is a circuit diagram of a comparison module provided by an embodiment of the present disclosure;

[0018] Figure 5is a circuit diagram of a post-stage reference voltage buffer provided by an embodiment of the present disclosure;

[0019] Figure 6 is a circuit diagram of an adjustable resistor array provided by an embodiment of the present disclosure;

[0020] Figure 7 is a schematic diagram of an inter-stage reference voltage calibration method for a pipeline analog-to-digital converter provided by an embodiment of the present disclosure;

[0021] Figure 8 is a schematic diagram of another inter-stage reference voltage calibration method for a pipeline analog-to-digital converter provided by an embodiment of the present disclosure;

[0022] Fig. 9 is a schematic diagram of another inter-stage reference voltage calibration method for a pipeline analog-to-digital converter provided by an embodiment of the present disclosure;

[0023] Fig.10 It is a schematic diagram of an inter-stage reference voltage calibration device for a pipeline analog-to-digital converter provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0025] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0026] Unless otherwise stated, the term "plurality" means two or more.

[0027] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0028] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0029] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0030] For adjacent sub-pipeline stages, in the absence of inter-stage redundant bits, the large signal gain G1 of the inter-stage residual amplifier is determined by the following formula:

[0031]

[0032] In the above formula, N is the resolution of the previous stage, Vref2 and Vref1 are the reference voltage values ​​of the next stage and the previous stage respectively. In actual design, the gain linearity of the commonly used inter-stage residual amplifier will decrease with the increase of the differential value of the input signal, thereby reducing the linearity of the ADC quantization. Therefore, in order to reduce the difficulty of amplifier design, Vref2 is often set to half of Vref1 during design, and the gain of the inter-stage residual amplifier is reduced by reducing the quantization range of the second-stage ADC.

[0033] Since the reference voltage buffer often uses an open-loop structure with low output impedance, its output voltage is greatly affected by factors such as temperature, and it is impossible to ensure that the output voltage ratio of the two-stage reference voltage buffer meets the design requirements (that is, Vref2 is half of Vref1). This will cause code jumping in the ADC output, seriously affecting the ADC's DNL (Differential Non-Linearity) and INL (Integral Non-Linearity), significantly reducing the linearity of the ADC quantization process. The circuit structure of the reference voltage buffer can be found in Figure 2 .

[0034] To solve the above problems, combined with Figure 1 As shown, the embodiment of the present disclosure provides an inter-stage reference voltage calibration circuit of a pipeline analog-to-digital converter, including a comparator 100 and a state machine 200. The comparator 100′ is connected to a front-stage reference voltage buffer 300 and a rear-stage reference voltage buffer 400, and is used to compare the magnitude of a reference reference voltage Vref1 / 2 and a rear-stage reference voltage Vref2. The reference reference voltage Vref1 / 2 is constructed by the front-stage reference voltage buffer 300. The state machine 200′ is connected to the comparator 100, and controls an adjustable resistor array 401 of the rear-stage reference voltage buffer 400 according to the comparison result of the comparator 100 to adjust the rear-stage reference voltage.

[0035] Here, the front-stage reference voltage buffer 300 is mainly used to construct a reference reference voltage Vref1 / 2 in the embodiment of the present disclosure, wherein the reference reference voltage Vref1 / 2 is half of the front-stage reference voltage Vref1. In this way, the comparator 100 connects the front-stage reference voltage buffer and the rear-stage reference voltage buffer to compare the reference reference voltage Vref1 / 2 and the rear-stage reference voltage Vref2. The state machine 200 is connected to the output end of the comparator 100 to determine whether the reference reference voltage and the rear-stage reference voltage are mismatched. If mismatched, the adjustable resistor array of the rear-stage reference voltage is adjusted to adjust the size of the rear-stage reference voltage. Thereby, the ratio of the reference voltage of the inter-stage reference buffer meets the design requirements.

[0036] In addition, the state machine 200 is fully called an on-chip digital logic state machine, which refers to a state machine implemented inside an integrated circuit for controlling device behavior.

[0037] The inter-stage reference voltage calibration circuit of the pipeline analog-to-digital converter provided by the embodiment of the present disclosure is adopted, and a comparator and a state machine are introduced on the basis of the original circuit. A reference reference voltage is constructed and compared with a subsequent reference voltage; when the two are mismatched, the mismatch is offset by adjusting the magnitude of the subsequent reference voltage. The calibration circuit only adds a comparator to the hardware, and the comparator consumes less energy. In addition, the calibration circuit does not affect other modules of the analog-to-digital converter, and is easy to transplant.

[0038] Combination Figure 2 , optionally, the pre-stage reference voltage buffer includes an amplifier AMP1, an NMOS tube and two resistors R. Among them, the non-inverting input terminal of the amplifier is connected to the first input voltage Vin1, and the inverting input terminal is connected to the source of the NMOS tube. The drain of the NMOS tube is connected to the power supply, the gate is connected to the output terminal of the amplifier, and the source is also connected to two resistors R connected in series. Among them, the voltage of the two resistors is used as the pre-stage reference voltage Vref1, and the voltage of the grounding resistor is used as the reference reference voltage Vref1 / 2. The resistance values ​​of the two resistors are the same, so the pre-stage reference voltage Vref1 is twice the reference reference voltage Vref1 / 2. In this way, by connecting two resistors with the same resistance value in series at the NMOS source terminal of the pre-stage reference voltage buffer, a reference reference voltage Vref1 / 2 with half the value of the pre-stage reference voltage is constructed.

[0039] Combination Figure 3Optionally, the comparator 100 includes an input signal switching selection module 101, a comparison module 102, and an output signal switching selection module 103. The input signal switching selection module 101 has two input terminals connected to the reference reference voltage Vref1 / 2 and the subsequent reference voltage Vref2 respectively; it is used to invert and switch the reference reference voltage and the subsequent reference voltage. The comparison module 102 is connected to the input signal switching selection module 102, and is used to compare the magnitudes of the reference reference voltage Vref1 / 2 and the subsequent reference voltage Vref2 to output a voltage signal. The output signal switching selection module 103 is used to invert and switch the output voltage.

[0040] It is understandable that although the calibration circuit can compare the base reference voltage and the subsequent reference voltage and calibrate the subsequent reference voltage, there will be an offset in the calibration circuit, which reduces the calibration accuracy. In order to improve the accuracy of the calibration, the comparator in the disclosed embodiment is provided with a switching selection function. During calibration, the input voltage and output voltage can be reversed and calibrated twice, and the average of the two calibration results can be taken to eliminate the offset in the calibration circuit.

[0041] Furthermore, combined with Figure 4 , the comparison module includes a pre-stage preamplifier 121, a pre-stage latch 122 and a storage latch. The pre-stage preamplifier 121 is used to amplify the input differential signal and suppress noise. The pre-stage latch 122 uses the principle of positive feedback to enhance the amplification of the difference between the two input signals. The storage latch is used to save the current result when the latch is set (this component is not shown in the figure). Among them, the step response of the pre-stage preamplifier is fast at first and then full, while the pre-stage latch is the opposite. The pre-stage preamplifier is used to amplify the differential signal input to a slow change interval beyond the latch, thereby reducing the delay of the comparator.

[0042] Specifically, the differential mode signal includes Vip and Vim, which are respectively used as the positive input signal and the negative input signal of the front stage pre-amplifier; after being amplified by the front stage pre-amplifier, the differential mode voltages Vp and Vm are output. The differential mode voltages Vp and Vm are used as two input signals of the front stage latch, and the differential mode voltages are compared and the comparison results are output. Among them, the front stage latch includes input pair tubes M1 and M4, MOS tubes M2, M3, M5, and M6 constituting inverters, and MOS tube M7 of the current source. The gates of the input pair tubes M1 and M4 are respectively connected to the differential mode signals Vp and Vm; the drain voltages of the MOS tubes M5 and M6 are respectively used as the output voltages Vop and Vom. The gate of the MOS tube M7 is connected to the clock signal clk_b for resetting.

[0043] The working principle of the comparison module is as follows: When the clock signal clk_b is a high-level signal, the comparator is in the setting stage. The output of the pre-amplifier is set to high, so that the gate input signal of the pre-latch input to the tubes M1 and M4 is a high-level signal, and the two differential outputs of the pre-latch are pulled down, that is, the output voltages Vop and Vom are low-level signals. When the clock signal clk_b is a low-level signal, the comparator is in the comparison stage. The differential mode voltages Vp and Vm output by the pre-amplifier begin to discharge. Due to the different differential mode voltages of the comparator input, the discharge speeds of Vp and Vm are different. When the voltage Vm is greater than the threshold voltage of the input tube M1, the input tube M1 is turned on, the drain of the input tube M1 begins to discharge, and the gate of M5 also begins to discharge (similarly, when the voltage Vp is greater than the threshold voltage of the input tube M4, the gate of M6 also begins to discharge). When Vm is greater than Vp, the gate voltage of M5 is pulled down to ground before the gate voltage of M6, and M2 is turned off first, thereby outputting two comparison results, a high level and a low level.

[0044] Combination Figure 5 The post-stage reference voltage buffer includes an amplifier AMP2, an adjustable resistor array RX, a MOS tube and a capacitor C. The amplifier AMP2 has a positive input connected to a voltage reference source Vin2, a negative input connected to an output, and an output connected to a second resistor R2. The voltage value of the second resistor R2 is used as the output post-stage reference voltage Vref2. The adjustable resistor array RX has one end connected to the negative input and output of the amplifier AMP2 through a first resistor R1 connected in series, and the other end is grounded. The post-stage reference voltage is adjusted by adjusting the resistance of the adjustable resistor array RX.

[0045] Here, two MOS tubes are connected in parallel to improve the output capacity of the amplifier. The source of one MOS tube x1 is connected in series with the adjustable resistor array through the first resistor, and the source is also connected to the inverting input terminal of the amplifier. The other MOS tube x10 is connected in series with the second resistor to output the subsequent reference voltage. In this way, during calibration, the size of the subsequent reference voltage can be adjusted by adjusting the resistance value of the adjustable resistor array connected to the circuit.

[0046] Optionally, in the initial state, the resistance values ​​of the adjustable resistor array RX, the first resistor R1 and the second resistor R2 satisfy the following relationship: R1+RX=10*R2.

[0047] Here, in the initial state, some resistors in the adjustable resistor array are connected to the circuit. In this way, the number of resistors connected to the circuit can be reduced or increased based on the magnitude of the base reference voltage and the subsequent reference voltage, thereby adjusting the magnitude of the output reference voltage. As an example, the number of resistors in the adjustable resistor array is 14, then in the initial state, about half of the resistors in the circuit can be connected to satisfy the above relationship.

[0048] Combination Figure 6 As shown, optionally, each resistor in the adjustable resistor array corresponds to a switch, and the total resistance of the adjustable resistor array is controlled by controlling the number of switches that are closed or disconnected. In addition, the resistance values ​​of the resistors in the adjustable resistor array are the same. In this way, the adjustable resistor array can be easily regulated during the calibration process.

[0049] Optionally, the control word of the adjustable resistor array is encoded in a thermometer code.

[0050] Here, the thermometer code is a special binary encoding method. As the value increases, the "1" in the code gradually increases from the lowest bit to represent different values. This encoding method can reduce differential nonlinear noise, ensure monotonicity, and reduce burr noise.

[0051] Combination Figure 7 As shown, the embodiment of the present disclosure provides an inter-stage reference voltage calibration circuit method for a pipeline analog-to-digital converter, comprising:

[0052] S101 , when a calibration control clock is received, the state machine controls the comparator to compare a base reference voltage with a subsequent reference voltage.

[0053] S102: The state machine determines whether the subsequent reference voltage needs to be calibrated according to the comparison result.

[0054] S103, when it is determined that the subsequent reference voltage needs to be calibrated, the state machine adjusts the adjustable resistor array of the subsequent reference voltage buffer according to the comparison result.

[0055] Here, when the inter-stage reference voltage needs to be calibrated, the state machine receives the signal of the calibration control clock and controls the comparator to compare the magnitude of the reference reference voltage and the subsequent reference voltage input at the two input terminals. According to the comparison result, it is determined whether the subsequent reference voltage needs to be calibrated. As an example, if the comparison result shows that the subsequent reference voltage is less than the reference reference voltage, and the difference between the two is large; or, the subsequent reference voltage is greater than the reference reference voltage, and the difference between the two is large; then it is determined that the subsequent reference voltage needs to be calibrated. Then, based on the comparison result, the adjustable resistor array of the subsequent reference voltage buffer is adjusted. Specifically, when the subsequent reference voltage is small, the number of resistors in the adjustable resistor array in the access circuit is reduced, so that the adjusted subsequent reference voltage increases to approach the reference reference voltage. Alternatively, when the subsequent reference voltage is large, the number of resistors in the adjustable resistor group array in the access circuit is increased, so that the adjusted subsequent reference voltage is reduced to approach the reference reference voltage.

[0056] In addition, it is preferred to perform calibration when the power is turned on. That is, when the power is turned on, the state machine will receive the calibration control clock. In this way, only one foreground calibration needs to be performed in the chip after the power is turned on.

[0057] The inter-stage reference voltage calibration circuit method for pipeline analog-to-digital converters according to the disclosed embodiment is used to compare the base reference voltage and the subsequent reference voltage after receiving the calibration control clock signal. Based on the comparison result, it is determined whether the inter-stage voltage is mismatched. In the case of mismatch, the adjustable resistor array of the subsequent reference voltage buffer is adjusted to adjust the size of the subsequent reference voltage so that the ratio of the previous reference voltage to the subsequent reference voltage meets the design requirements.

[0058] Optionally, S102, the state machine determines whether the subsequent reference voltage needs to be calibrated according to the comparison result.

[0059] In a plurality of consecutive sampling cycles, when the absolute difference between the number of high voltage signals and the number of low voltage signals outputted is greater than a preset threshold and the positive and negative values ​​of the difference are consistent, the state machine determines that the subsequent reference voltage needs to be calibrated.

[0060] The comparison result includes the output high voltage signal and the output low voltage signal.

[0061] Here, in order to ensure the accuracy of the comparison, the output results of the comparator are collected in multiple consecutive sampling cycles. The output results of the comparator include a high voltage signal or a low voltage signal. When the input signal at the in-phase input terminal is greater than the input signal at the inverting input terminal, the comparator outputs a high voltage signal. When the input signal at the in-phase input terminal is less than the input signal at the inverting input terminal, the comparator outputs a low level signal. Based on the multiple output results of the collected comparator, the absolute difference between the number of high level signals num_h and the number of low level signals num_l in the output results can be compared. If the absolute difference is greater than the preset threshold, it indicates that the ratio of the inter-stage reference voltage is mismatched, that is, it is determined that the post-stage reference voltage needs to be calibrated.

[0062] In addition, the positive and negative cases of the difference are the same, which means that the difference ΔV=num_h-num_l is greater than zero in a plurality of consecutive calibration cycles, or ΔV is less than zero; the absolute difference is |ΔV|.

[0063] Optionally, in S103, the state machine adjusts the adjustable resistor array of the subsequent reference voltage buffer according to the comparison result, including:

[0064] The state machine determines the calibration direction based on the comparison result.

[0065] The state machine adjusts the switch state of the adjustable resistor array of the subsequent reference voltage buffer based on the calibration direction.

[0066] Here, when the input signal and the output signal end of the input signal end of the comparator are determined, the calibration direction can be determined based on the comparison result. Specifically, when the back-stage reference voltage is connected to the in-phase input end of the comparator, the reference reference voltage is connected to the inverting input end of the comparator, and the positive end of the comparator outputs the result, if the back-stage reference voltage is greater than the reference reference voltage, the comparator outputs a high-level signal; otherwise, a low-level signal is output. In this way, the magnitude relationship of the two input reference signals can be determined based on the output result. It can be understood that the reference reference voltage is the desired target voltage, so when the back-stage reference voltage is greater than the reference reference voltage, the calibration direction is to reduce the back-stage reference voltage. The switch state of the adjustable resistor array is adjusted in the direction of reducing the back-stage reference voltage. When the back-stage reference voltage is less than the reference reference voltage, the calibration direction is to increase the back-stage reference voltage. The switch state of the adjustable resistor array is adjusted in the direction of increasing the back-stage reference voltage. In this way, the change trend of the switch state of the adjustable resistor array can be adjusted in a targeted manner based on the comparison result.

[0067] Optionally, the state machine determines the calibration direction according to the comparison result, including:

[0068] When the output result indicates that the subsequent reference voltage is greater than the base reference voltage, the state machine determines that the calibration direction is to increase the number of resistors in the adjustable resistor array connected to the subsequent reference voltage buffer.

[0069] When the output result indicates that the subsequent reference voltage is less than the base reference voltage, the state machine determines that the calibration direction is to reduce the number of resistors in the adjustable resistor array connected to the subsequent reference voltage buffer.

[0070] Here, based on the above-mentioned setting of the input and output signals, when the number of high-level signals in the output result is large, the output result indicates that the subsequent reference voltage is greater than the reference reference voltage. At this time, it is determined to reduce the subsequent reference voltage, that is, to increase the number of resistors in the circuit connected to the adjustable resistor array. When the number of low-level signals in the output result is large, the output result indicates that the subsequent reference voltage is less than the reference reference voltage. At this time, it is determined to increase the subsequent reference voltage, that is, to reduce the number of resistors in the circuit connected to the adjustable resistor array.

[0071] Combination Figure 8 As shown, the embodiment of the present disclosure provides another inter-stage reference voltage calibration circuit method for a pipeline analog-to-digital converter, comprising:

[0072] S101 , when a calibration control clock is received, the state machine controls the comparator to compare a base reference voltage with a subsequent reference voltage.

[0073] S102: The state machine determines whether the subsequent reference voltage needs to be calibrated according to the comparison result.

[0074] S103, when it is determined that the subsequent reference voltage needs to be calibrated, the state machine adjusts the adjustable resistor array of the subsequent reference voltage buffer according to the comparison result.

[0075] S204: When the absolute difference between the number of high voltage signals and the number of low voltage signals in the latest comparison result is less than or equal to a preset threshold, the state machine determines that the calibration is finished.

[0076] Here, when adjusting the adjustable resistor array, the comparison result of the comparator is sampled. If the absolute difference in the number of high voltage signals in the latest comparison result is less than or equal to the preset threshold, it indicates that the equivalent offset of the two reference voltages input to the current comparator is less than the equivalent noise at the comparator input. At this time, the adjustable resistor array will no longer continue to adjust and the calibration is terminated. Among them, the sampled comparison result is as mentioned above, and multiple comparison results within a continuous sampling cycle are obtained. In addition, when the calibration is terminated, the control word of the adjustable resistor array is saved. In this way, the offset of the subsequent reference voltage is compensated so that the offset voltage is compensated below the noise voltage.

[0077] Combination Fig. 9 As shown, the embodiment of the present disclosure provides another inter-stage reference voltage calibration method for a pipeline analog-to-digital converter, comprising:

[0078] S101 , when a calibration control clock is received, the state machine controls the comparator to compare a base reference voltage with a subsequent reference voltage.

[0079] S102: The state machine determines whether the subsequent reference voltage needs to be calibrated according to the comparison result.

[0080] S103, when it is determined that the subsequent reference voltage needs to be calibrated, the state machine adjusts the adjustable resistor array of the subsequent reference voltage buffer according to the comparison result.

[0081] S204: When the absolute difference between the number of high voltage signals and the number of low voltage signals in the latest comparison result is less than or equal to a preset threshold, the state machine determines that the calibration is finished.

[0082] S305, the state machine controls the comparator to invert and switch the input signal and the output signal, and obtains the comparison result again.

[0083] S306 , when the comparison result obtained again meets the calibration condition, the state machine adjusts the adjustable resistor array of the subsequent reference voltage buffer again according to the comparison result obtained again.

[0084] As mentioned above, there is also an offset voltage in the calibration circuit. In order to improve the calibration accuracy. After the first calibration result, the comparator is controlled to flip and switch the input signal and output signal for the second calibration. After obtaining the second calibration result, the final calibration result is obtained by combining the first calibration result. That is, a complete calibration cycle includes the first calibration and the second calibration. In this way, the offset voltage in the calibration circuit can be offset and the influence of the offset voltage on the calibration accuracy can be reduced.

[0085] Among them, controlling the comparator to reverse and switch the input signal and output signal includes: setting the current comparator input signal and output signal as follows, the reference voltage is the inverting input signal, the subsequent reference voltage is the inverting input signal, and the signal at the positive output end is the output signal. Then, after the switching signal is flipped, the input signal and output signal of the comparator are as follows: the reference voltage is the inverting input signal, the subsequent reference voltage is the inverting input signal, and the signal at the negative output end is the output signal. In this way, the value of the output signal after the comparator is reversed and switched remains consistent.

[0086] In addition, the judgment logic and calibration logic of the second calibration are the same as those of the first calibration, and will not be described in detail here.

[0087] Optionally, after step S306, the method further includes:

[0088] The state machine uses the average value of the second control word corresponding to the adjustable resistor array after the adjustment again and the first control word corresponding to the adjustable resistor array after the last adjustment as the final calibration control word.

[0089] Here, in order to improve the accuracy of the calibration result, the average value of the control word of the adjustable resistor array after two calibrations before and after the comparator is reversed is used as the final calibration control word. This offsets the offset voltage in the calibration circuit and ensures the accuracy of the calibration. As mentioned above, the control word encoding method of the adjustable resistor array is a thermometer code. When calculating the average value, if the value of a certain bit is not an integer, it is rounded up. Thus, the final calibration control word is calculated, and the adjustable resistor array is connected to the circuit according to the final calibration control word.

[0090] Combination Fig.10As shown, an embodiment of the present disclosure provides an inter-stage reference voltage calibration device 500 for a pipeline analog-to-digital converter, including a processor 501 and a memory 502. Optionally, the device may also include a communication interface 503 and a bus 504. The processor 501, the communication interface 503, and the memory 502 may communicate with each other through the bus 504. The communication interface 503 may be used for information transmission. The processor 501 may call the logic instructions in the memory 502 to execute the inter-stage reference voltage calibration method for the pipeline analog-to-digital converter of the above embodiment.

[0091] In addition, the logic instructions in the memory 502 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0092] The memory 502 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 501 executes the function application and data processing by running the program instructions / modules stored in the memory 502, that is, the inter-stage reference voltage calibration method for the pipeline analog-to-digital converter in the above embodiment is implemented.

[0093] The memory 502 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 502 may include a high-speed random access memory and may also include a non-volatile memory.

[0094] The embodiment of the present disclosure provides an inter-stage reference voltage calibration circuit for a pipeline analog-to-digital converter, including: a comparator 100, a state machine 200, and the above-mentioned inter-stage reference voltage calibration device 500 for a pipeline analog-to-digital converter. The inter-stage reference voltage calibration device 500 for a pipeline analog-to-digital converter is installed in the state machine body. The installation relationship described here is not limited to placement inside the state machine body, but also includes installation connections with other components of the state machine, including but not limited to physical connections, electrical connections, or signal transmission connections. It can be understood by those skilled in the art that the inter-stage reference voltage calibration device 500 for a pipeline analog-to-digital converter can be adapted to a feasible state machine, thereby realizing other feasible embodiments.

[0095] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned inter-stage reference voltage calibration method for a pipeline analog-to-digital converter.

[0096] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0097] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0098] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0099] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0100] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. An inter-stage reference voltage calibration circuit for a pipeline analog-to-digital converter, characterized in that: include: A comparator is connected to the front-stage reference voltage buffer and the rear-stage reference voltage buffer, and is used to compare the base reference voltage and the rear-stage reference voltage; wherein the base reference voltage is constructed by the front-stage reference voltage buffer; The state machine is connected to the comparator and controls the adjustable resistor array of the post-stage reference voltage buffer according to the comparison result of the comparator to adjust the post-stage reference voltage.

2. The circuit according to claim 1, characterized in that The comparator comprises: An input signal switching selection module, wherein two input terminals are respectively connected to a reference voltage and a subsequent reference voltage; and is used for inverse switching between the reference voltage and the subsequent reference voltage; A comparison module, connected to the input signal switching selection module, for comparing the base reference voltage and the subsequent reference voltage to output a voltage; The output signal switching selection module is used to reversely switch the output voltage.

3. The circuit according to claim 1, characterized in that The post-stage reference voltage buffer comprises: An amplifier, wherein the positive input terminal is connected to a voltage reference source, the negative input terminal is connected to an output terminal, the output terminal is connected to a second resistor, and the voltage value of the second resistor is used as a subsequent reference voltage of the output; An adjustable resistor array, one end of which is connected to the negative input terminal and the output terminal of the amplifier through a first resistor connected in series, and the other end of which is grounded; The subsequent reference voltage is adjusted by adjusting the resistance of the adjustable resistor array.

4. A method for calibrating an inter-stage reference voltage of a pipeline analog-to-digital converter, based on the circuit according to any one of claims 1 to 3, characterized in that: The method comprises: In case of receiving the calibration control clock, controlling the comparator to compare the base reference voltage with the subsequent reference voltage; According to the comparison result, determine whether the subsequent reference voltage needs to be calibrated; When it is determined that the subsequent reference voltage needs to be calibrated, the adjustable resistor array of the subsequent reference voltage buffer is adjusted according to the comparison result.

5. The method according to claim 4, characterized in that According to the comparison result, determine whether the subsequent reference voltage needs to be calibrated, including: In a plurality of consecutive sampling periods, when the absolute difference between the number of high voltage signals and the number of low voltage signals outputted is greater than a preset threshold and the positive and negative values ​​of the difference are consistent, it is determined that the subsequent reference voltage needs to be calibrated; The comparison result includes the output high voltage signal and the output low voltage signal.

6. The method according to claim 4, characterized in that According to the comparison result, the adjustable resistor array of the subsequent reference voltage buffer is adjusted, including: According to the comparison result, the calibration direction is determined; Based on the calibration direction, the switch state of the adjustable resistor array of the subsequent reference voltage buffer is adjusted.

7. The method according to claim 6, characterized in that Based on the comparison results, determine the calibration direction, including: When the output result indicates that the subsequent reference voltage is greater than the reference voltage, the calibration direction is determined to be to increase the number of resistors in the adjustable resistor array connected to the subsequent reference voltage buffer; When the output result indicates that the post-stage reference voltage is less than the base reference voltage, the calibration direction is determined to be to reduce the number of resistors connected to the post-stage reference voltage buffer in the adjustable resistor array.

8. The method according to any one of claims 4 to 7, characterized in that: After adjusting the adjustable resistor array of the subsequent reference voltage buffer according to the comparison result, the method further includes: When the absolute difference between the number of high voltage signals and the number of low voltage signals in the latest comparison result is less than or equal to the preset threshold, it is determined that the current calibration is finished.

9. The method according to claim 7, characterized in that: After the calibration is completed, it also includes: Control the comparator to invert the switching of input signal and output signal, and obtain the comparison result again; When the comparison result obtained again satisfies the calibration condition, the adjustable resistor array of the subsequent reference voltage buffer is adjusted again according to the comparison result obtained again.

10. The method according to claim 9, characterized in that After adjusting the adjustable resistor array of the subsequent reference voltage buffer again, it also includes: The average value of the second control word corresponding to the adjustable resistor array after the second adjustment and the first control word corresponding to the adjustable resistor array after the last adjustment is used as the final calibration control word.

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