Single-level C-ADC circuit structure based on comparison of double-voltage scaling signal and single reference voltage and sampling method of single-level C-ADC circuit structure

Abstract

The invention discloses a single-level C-ADC circuit structure based on comparison of a double-voltage scaling signal and a single reference voltage and a double-scaling voltage sampling method of the single-level C-ADC circuit structure. The converter comprises an adaptive resolution module, a double voltage scaling module, a three-input comparator module and a control logic module. The sampling method comprises the following steps: according to an analog signal to be converted, generating two signals which synchronize the change of the analog signal; comparing the two generated synchronous signals with a single reference voltage signal respectively; when any synchronizing signal passes through the reference voltage from a high level or a low level, triggering sampling; when sampling is triggered, an output pulse signal is generated to indicate the direction of crossing the reference voltage, the two signals used for synchronously inputting changes are reset, and the process is repeated. According to the event-driven analog-to-digital converter and the sampling method thereof, the precision requirement on the reference voltage is reduced, the precision of the analog-to-digital converter is improved, and the power consumption of the analog-to-digital converter is saved.

Description

Technical Field

[0001] The present invention relates to the field of analog / digital converters, and in particular to a single-level C-ADC circuit structure based on comparison of a dual voltage scaling signal with a single reference voltage and a sampling method thereof. Background Art

[0002] Analog-to-Digital Converter (ADC) is an important component in electronic systems that converts analog signals into digital signals. It is widely used in medical devices, smart sensors, wearable devices and other scenarios. Traditional ADC technology is based on the Nyquist sampling theorem, and the sampling frequency must be at least twice the highest frequency of the signal. Many real signals, such as human electrocardiogram signals and brain electroencephalogram signals, have sparse characteristics, that is, the signal is in a stable state for a long time and only changes dramatically at a few time points.

[0003] Traditional ADC designs all use a uniform sampling method based on time signals, such as Figure 1 As shown in Figure 1, this method is inefficient in acquisition when processing sparse signals, which not only increases unnecessary dynamic power consumption, but also generates a large amount of redundant data, resulting in increased complexity in subsequent processing. Therefore, an event-driven analog-to-digital converter (LC-ADC) has been proposed in recent years. It performs non-uniform sampling by detecting important changes in the signal (such as crossing a preset level). Figure 2 . Since this type of analog-to-digital converter does not require a sampling clock, the power consumption increase caused by the clock circuit can be avoided; and since the action is only generated when the signal changes significantly, when processing sparse signals, it is possible to generate fewer samples, thereby reducing the dynamic power consumption of the circuit; and the number of samples, that is, the amount of data, is greatly reduced, which can reduce the pressure of subsequent data processing and data transmission. Therefore, in principle, the event-driven analog-to-digital converter is very suitable for low-power acquisition of sparse signals. In addition to low power consumption, the event-driven analog-to-digital converter also has the advantages of relatively simple circuit structure and no aliasing (Al ias-Free).

[0004] Although the mainstream architectures of existing LC-ADCs, such as the "Clockless Flash" architecture, dual floating level architecture, and dual fixed level architecture, have achieved power consumption reduction to a certain extent, they still have the following shortcomings:

[0005] 1. Conflict between dynamic power consumption and resolution: Dynamic power consumption increases dramatically with the increase of resolution, and it is difficult to optimize both at the same time.

[0006] 2. Limited static power consumption: As a source of static power consumption, the existing architecture requires at least two comparators, which limits the space for power consumption optimization.

[0007] 3. Level error affects resolution: In the dual fixed level architecture, the quantization step size is directly affected by the level error, resulting in the effective resolution being limited by the level accuracy.

[0008] In summary, it is still difficult for existing technologies to strike a balance between low power consumption and high resolution, and a new architecture is urgently needed to break through the bottleneck of existing technologies. This architecture needs to include a new event-driven analog-to-digital converter circuit design and a new event-driven sampling method design. Summary of the invention

[0009] In order to solve the above problems, the present invention provides a single-level LC-ADC sampling method and circuit structure based on the comparison of dual-scaled signals and single reference voltage. Through the innovation of sampling method, the optimization design of key modules and the introduction of adaptive control strategy, efficient and low-power sparse signal acquisition is achieved, while the effective resolution is improved.

[0010] According to one aspect of the present invention, a single-level C-ADC circuit structure based on comparison of a dual voltage scaling signal with a single reference voltage is proposed, comprising:

[0011] A dual voltage scaler module is used to receive an input signal from an analog / digital converter and generate two scaled signals V that scale the input signal synchronously. P1 and V P2 , and make them have the same scaling ratio and a constant common-mode voltage V CM1 and V CM2 At the same time, it also receives the output pulse waveform finally output by the control module, which is used to scale the signal V P1 and V P2 Perform a reset.

[0012] A three-input comparator module is used to scale the signal V P1 and V P2 At the same time, with the single-level reference voltage V REF comparison, used to detect whether any scaled signal crosses the single-level reference voltage V from below or above REF If it crosses, the corresponding output pulse signal will be output.

[0013] The control logic module is used to receive the output signal of the comparator module, and output the reset signal RESET and the outputs CH and CL of the analog / digital converter respectively through the XNOR logic gate and the buffer circuit.

[0014] The adaptive quantization resolution logic module controls the quantization step size of the analog-to-digital converter by monitoring the interval time between adjacent pulses of the reset signal RESET.

[0015] On-chip single voltage reference circuit for generating a stable reference voltage V REF, ensuring that the quantization step size is independent of the level error.

[0016] Preferably, the adaptive quantization resolution logic module uses a time-to-voltage converter to convert the interval time between adjacent pulses in the reset signal RESET into a corresponding voltage.

[0017] Preferably, a gain code generator is used to generate a gain code according to an output voltage value of the time-to-voltage converter to control the dual voltage scaler to adjust the quantization step size.

[0018] Preferably, the common mode voltage difference of the scaled signal is calculated according to the following formula:

[0019] V CM1 =V REF +r·V STEP , V CM2 =V REF -r·V STEP

[0020] Where r is the scaling factor, V STEP is the quantization step size.

[0021] Preferably, the switched capacitor array of the dual voltage scaler is composed of a plurality of parallel basic unit capacitors, each unit capacitor having a capacitance value of C0. By controlling the number of unit capacitors, fine scaling adjustment can be achieved, further optimizing the dynamic range of the quantization step.

[0022] Preferably, the capacitor material of the dual voltage scaler adopts a low temperature drift medium, and a temperature compensation network is introduced into the circuit design to ensure the stability of the scaled signal in a wide temperature range.

[0023] Preferably, the three-input comparator adopts a rail-to-rail input structure to support a wider input signal range while ensuring normal operation at an extremely low supply voltage (0.6V).

[0024] Preferably, the input end of the three-input comparator adopts a self-bias circuit design, without the need for an external bias circuit, thereby further simplifying the design and reducing static power consumption.

[0025] According to another aspect of the present invention, a sampling method based on the above circuit structure is provided, comprising the following steps:

[0026] The dual voltage scaler generates a synchronously scaled signal V P1 and V P2 .

[0027] Detection scaling signal V P1 and V P2 Whether to cross the reference voltage VREF and generate an output pulse signal when crossing.

[0028] When generating the output pulse signal, the reset signal is generated synchronously and V P1 and V P2 Reset to the common mode signal V CM1 With V CM2 .

[0029] The quantization step size is dynamically adjusted to match the rate of change of the signal.

[0030] Preferably, the adaptive resolution control logic adjusts the quantization step size by:

[0031] Increase or decrease the common-mode voltage of the scaled signal;

[0032] Dynamically changing the number of unit capacitors enabled in the capacitor array;

[0033] Adjusts the output voltage of the on-chip reference circuit.

[0034] Preferably, the sampling method supports processing multiple crossing events of the input signal simultaneously, generating multiple pulse signals, which are used for adjusting the scaling signal and recording the timestamp respectively.

[0035] Preferably, when the sparse signal is stable for a long time, the control logic module enters a low-power sleep mode and is reactivated only when a rapid change in the signal is detected, thereby further saving energy.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] 1) Traditional ADC designs usually use a single input signal to compare with a fixed reference voltage. However, the present invention introduces a dual voltage scaler module to generate two scaled signals (VP1 and VP2) with the same scaling ratio but different common mode voltages, and compares them with a single reference voltage VREF, which not only improves the flexibility of signal processing, but also helps to improve the effective resolution and sampling efficiency of the ADC. An effective resolution of more than 8.5 bits is achieved.

[0038] 2) By monitoring the interval time between adjacent pulses of the reset signal RESET, the adaptive quantization resolution logic module can dynamically adjust the quantization step size of the ADC, so that the ADC can adjust its performance in real time according to the change rate of the input signal, thereby reducing power consumption while ensuring accuracy.

[0039] 3) The sampling method supports the simultaneous processing of multiple crossing events of the input signal and generates multiple pulse signals, which are used to adjust the scaling signal and record the timestamp. This design not only improves the parallel processing capability of the ADC, but also helps to achieve more accurate time synchronization and signal analysis.

[0040] 4) The present invention not only improves the performance and flexibility of ADC, but also achieves low power consumption and efficient signal processing.

[0041] The total power consumption is reduced to nanowatt level, supporting long-term low-power operation. The single-level comparator and on-chip reference circuit reduce the number of circuit modules. It is particularly suitable for efficient acquisition of sparse signals such as ECG signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0043] Figure 1 A sampling method diagram of an existing clock-driven analog / digital converter;

[0044] Figure 2 A sampling method diagram of an existing event-driven analog / digital converter;

[0045] Figure 3 A circuit block diagram of an embodiment of the present invention;

[0046] Figure 4 is a sampling diagram of a signal in an example of the present invention;

[0047] Figure 5 This is a circuit design diagram of a dual voltage scaling module in a preferred embodiment of the present invention;

[0048] Figure 6 A circuit diagram of a three-input comparator design in a preferred embodiment of the present invention;

[0049] Figure 7 A circuit diagram of an adaptive quantization resolution module in a preferred embodiment of the present invention;

[0050] Figure 8 This is a circuit diagram of a control logic module in a preferred example of the present invention.

[0051] Fig. 9 The flowchart of a sampling method according to an embodiment of the present invention is shown in FIG. DETAILED DESCRIPTION

[0052] The following is a detailed description of the embodiments of the present invention: This embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation method and a specific operation process are given. It should be pointed out that for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

[0053] Embodiment 1:

[0054] This embodiment describes in detail the ultra-low power consumption event-driven analog / digital converter of the present invention, and its structural diagram is shown in FIG. Figure 3As shown, it includes: a dual voltage scaling circuit, a three-input comparator circuit, an adaptive edge rate control circuit, a control logic circuit and an on-chip single voltage reference circuit.

[0055] The signal sampling diagram in this example is as follows Figure 4 As shown. The dual voltage scaling circuit generates corresponding scaling signals VP1 and VP2 according to the input signal VIN. These two signals are used by the three-input comparator circuit to compare with the reference voltage VREF generated by the on-chip single voltage reference circuit. When VP1 crosses VREF from above or VP2 crosses VREF from below, the three-input comparator is triggered, and an output pulse signal is generated on CL or CH respectively through the output control logic, and a reset RESET signal is generated through the XOR logic gate to reset VP1 and VP2 to the common mode voltage VCM1 and VCM2 respectively. The resolution of the entire analog / digital converter is adaptively controlled by the adaptive resolution control circuit according to the pulse interval of the RESET signal.

[0056] In the embodiment, the dual voltage scaler generates synchronous scaling signals VP1 and VP2 through two sets of switch capacitor arrays, and its core circuit is as follows: Figure 5 As shown. Each group of switched capacitor arrays contains three types of capacitors C1, C2, and C3, which are dynamically adjusted through a multiplexer. The charge is redistributed through the switched capacitor array, and the final quantization step of the analog / digital converter is C3 / C1·VDD, where VDD is the power supply voltage. The value of the capacitor in the capacitor array C3 can be controlled through the adaptive resolution control module, thereby realizing the control of the quantization step.

[0057] In a preferred embodiment, the three-input comparator compares the scaled signals VP1 and VP2 with the single reference voltage VREF at the same time and outputs a crossing event detection signal. The core circuit thereof is as follows Figure 6 As shown in the figure. This circuit adopts a rail-to-rail input structure to support a wider input signal range. At the same time, the input end adopts a self-bias circuit, which does not require an additional bias module, further reducing static power consumption.

[0058] In a preferred embodiment, the circuit diagram of the adaptive quantization resolution logic module is as follows: Figure 7 As shown. The frequency of the RESET signal is converted into voltage through two current sources and capacitors, and the gain coding is adjusted through a counter. Due to the difference in the size of the two current sources and capacitors, they can be used to detect the upper and lower limits of the RESET signal frequency respectively.

[0059] Embodiment 2:

[0060] This embodiment describes in detail the ultra-low power consumption event-driven analog / digital converter sampling method of the present invention, and its operation flow chart is as follows: Figure 8 As shown, it includes the following steps:

[0061] S11: Generate scaling signals VP1 and VP2 according to the signal input to the analog / digital converter and the quantization step size.

[0062] S12: Wait for VP1 or VP2 to cross the single-level reference voltage VREF.

[0063] S13: When VP1 or VP2 crosses the single-level reference voltage VREF, a sampling signal is output and a reset signal RESET is generated, otherwise, the process returns to step S12.

[0064] S14: Adjust the quantization step size according to the frequency of the reset signal RESET, and return to step S11.

[0065] The above specific implementation methods further illustrate the technical solutions and evaluation effects of the present invention in detail. Those skilled in the art should understand that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. The technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention, and the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A single-level C-ADC circuit structure based on comparing a dual voltage scaling signal with a single reference voltage, characterized in that: include: A dual voltage scaler circuit module is used to receive an input signal of an analog / digital converter, generate two scaled signals VP1 and VP2 that synchronously track the input signal, wherein the scaled signals VP1 and VP2 have the same scale ratio and have constant common mode voltages VCM1 and VCM2, respectively, to achieve a quantization step size that is independent of a quantization level VREF, and also receive an output pulse waveform finally output by a control module, and is used to reset the scaled signals VP1 and VP2; A three-input comparator module, for comparing the scaled signals VP1 and VP2 with the single-level reference voltage VREF simultaneously, to detect whether any scaled signal crosses the single-level reference voltage VREF from below or above, and outputting a corresponding output pulse signal when the crossing is detected; A control logic module, used for receiving the output signal of the three-input comparator module, and outputting a reset signal RESET and the outputs CH and CL of the analog / digital converter respectively through an XNOR logic gate and a buffer circuit to control the reset of the scaling signal; An adaptive quantization resolution logic module, used to control the quantization step size of the analog / digital converter by monitoring the interval time between adjacent pulses of the reset signal RESET, so as to achieve an adaptive quantization resolution; On-chip single voltage reference circuit to generate a stable reference voltage VREF to ensure that the quantization step size is independent of level errors.

2. The single-level C-ADC circuit structure according to claim 1, characterized in that: The dual voltage scaler circuit module includes two fully symmetrical switch capacitor arrays and a set of switch control logic blocks.

3. The single-level C-ADC circuit structure according to claim 2, characterized in that: The switch capacitor array is composed of a plurality of basic unit capacitors connected in parallel, each unit capacitor has a value of C0, and the scaling rate is adjusted by controlling the number of unit capacitors to ensure that a predetermined difference exists between the common mode voltages of VP1 and VP2 to generate a specified quantization step.

4. The single-level C-ADC circuit structure according to claim 1, characterized in that: The adaptive quantization resolution logic module comprises: A time-to-voltage converter, used for converting the interval time between adjacent pulses in the reset signal RESET into a corresponding voltage; The gain code generator is used to generate a gain code according to the output voltage value of the time-to-voltage converter to control the dual voltage scaler to adjust the quantization step size.

5. The single-level C-ADC circuit structure according to claim 1, characterized in that: The common-mode voltage difference of the scaled signal is calculated according to the following formula: V CM1 =V REF -r·V STEP , V CM2 =V REF -r·V STEP , where r is the scaling factor, V STEP is the quantization step size.

6. The single-level C-ADC circuit structure according to claim 1, characterized in that: The capacitor material of the dual voltage scaler adopts a low temperature drift medium.

7. The single-level C-ADC circuit structure according to claim 1, characterized in that: The control logic module is composed of a buffer and an XNOR gate to generate a corresponding output pulse signal when it is detected that the input signal crosses VREF.

8. A sampling method based on the single-level C-ADC circuit structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: A dual voltage scaler module generates two scaled signals VP1 and VP2 that synchronously track the input signal, and the scaled signals VP1 and VP2 have the same scale ratio and maintain a constant common mode voltage; Comparing the scaled signals using a single reference voltage VREF, detecting whether the scaled signal VP1 or VP2 crosses the reference voltage VREF, and generating an output pulse signal when the crossing is detected; When generating the output pulse signal, a reset signal is synchronously generated, and the scaling signals VP1 and VP2 are reset to the common mode signals VCM1 and VCM2 respectively; According to the input signal change rate, the quantization step size of the scaled signal is dynamically adjusted to achieve adaptive quantization resolution.

9. The method according to claim 8, characterized in that: The adjustment of the quantization step size is achieved by the following steps: The pulse interval time of the reset signal is used to estimate the change rate of the input signal; generating a gain coded signal according to the rate of change; A quantization step size of the dual-scaled signal is adjusted based on the gain encoding signal.

10. The method according to any one of claims 8 to 9, wherein the comparison and reset cycle of the scaled signal with the single reference voltage is automatically repeated after each change of the input signal by one quantization step, thereby achieving continuous sampling.

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