Three-dimensional memory structure and integration method thereof

Abstract

The invention provides a three-dimensional memory structure and an integration method thereof, and belongs to the technical field of semiconductors. The memory structure is formed by stacking a plurality of unit structures from bottom to top, each unit structure comprises a ring gate low-power-consumption bidirectional conduction device serving as a write-in tube of the memory and a ring channel high-performance device serving as a read-out tube of the memory, and the source end of the write-in tube serves as the gate end of the read-out tube at the same time. The write-in tube and the read-out tube are connected in the horizontal direction; according to the memory structure, the advantages of long retention time, high reading speed, low power consumption and the like are realized at the same time, stacking of multiple layers of memory units is realized in a limited area, and the memory density is increased; according to the method provided by the invention, a plurality of repetitive unit structures in the storage structure share the process steps of photoetching, etching, ion implantation, annealing and the like, so that the process cost of each bit of storage information in the storage structure is remarkably reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional memory structure and an integration method thereof. Background Art

[0002] With the development of artificial intelligence and Internet of Things technologies, the demand for high-speed, high-density, and low-power memory has increased dramatically. Existing memories need to compromise between operating speed, storage density, and operating power consumption, and cannot have the advantages of all three at the same time. Therefore, it is necessary to invent a new type of high-speed, high-density, and low-power memory. Summary of the invention

[0003] The purpose of the present invention is to design a three-dimensional memory structure and its integration method, wherein the memory structure includes a ring-gate low-power bidirectional conductive device as a write tube of the memory and a ring-channel high-performance device as a read tube of the memory, thereby achieving high-speed reading and writing while extending the retention time of the memory and reducing the power consumption of the memory.

[0004] The technical solution of the present invention is as follows:

[0005] A three-dimensional memory structure is composed of multiple unit structures stacked from bottom to top, each unit structure includes a write tube and a read tube, and the source end of the write tube also serves as the gate end of the read tube, so as to realize the connection between the write tube and the read tube in the horizontal direction. The gate ends of the write tubes of the unit structure in the same row are connected together through the gate conductive layer to form a write word line WWL, the drain ends of the write tubes of the unit structure in the same column are connected together through the contact metal to form a write bit line WBL, the source end of the write tube also serves as the gate end of the read tube and the storage node SN of the unit structure, the source ends of the read tubes of the unit structure in the same row are connected together through the source-drain metal to form a read word line RWL, and the drain ends of the read tubes of the unit structure in the same column are connected together through the contact metal to form a read bit line RBL. The write tube is a low-power bidirectional conductive device with a ring gate structure, and the specific characteristics are that the two sides of the channel of the write tube are its source end and drain end respectively, the gate end surrounds the channel in the direction perpendicular to the channel, the source end is close to the gate end in the horizontal direction, and the drain end is separated from the gate end in the horizontal direction. The write tube channel is composed of a write channel layer, and the gate end is composed of a gate dielectric layer and a gate conductive layer. The drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, that is, the doping types of the source and drain semiconductor parts are opposite. The readout tube is a high-performance device with a ring channel structure, and the specific feature is that the gate end of the readout tube is composed of the contact metal of the write tube source end and the readout tube gate dielectric, and the readout tube gate dielectric wraps the contact metal of the write tube source end. The channel of the readout tube is composed of a readout channel layer, and the readout channel layer wraps the readout tube gate dielectric layer. The source and drain ends of the readout tube are both composed of a contact metal and a readout channel layer close to the contact metal, and the source and drain ends are both in contact with the readout tube channel.

[0006] The present invention also provides a method for integrating the above three-dimensional memory structure, the specific steps of which include:

[0007] Step 1: depositing multiple layers of sacrificial layer material and write channel layer material on a substrate, wherein the specific method is to deposit a layer of sacrificial layer material, then deposit a layer of write channel layer material, and then repeatedly deposit sacrificial layer material and write channel layer material, and the last deposited material is the sacrificial layer material, and the number of layers of the write channel layer is the number of repetitions of the unit structure in the above memory structure;

[0008] Step 2: define the active area, the specific method is to pattern the active area by photolithography, and then etch the sacrificial layer material outside the active area and the write channel layer material to form the active area;

[0009] Step 3: forming active area isolation, the specific method is to deposit isolation layer material, then pattern the memory array area by photolithography, then etch the excess isolation layer material outside the memory array, and then planarize it by chemical mechanical polishing (CMP);

[0010] Step 4: forming a sidewall isolation, the specific method is to pattern the sidewall area by photolithography, then etch the sacrificial layer material and the isolation layer material in the sidewall area, then deposit the sidewall layer material, then planarize it by CMP, then pattern the storage array area by photolithography, and then etch the excess sidewall layer material outside the storage array;

[0011] Step 5: forming a write-in tube gate terminal, specifically, patterning the area between the write-in tube gate and the gate by photolithography, then etching the isolation layer between the write-in tube gates, then depositing the sidewall layer material, then planarizing by CMP, then patterning the area between the write-in tube gates by photolithography, then etching the redundant sidewall layer material between the write-in tube gates, then preparing the gate stack by a standard polySi-SiO2 process or HKMG process, and then removing the photoresist and redundant materials;

[0012] Step 6: forming a source-drain semiconductor layer, specifically, patterning the drain region of the write tube by photolithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by ion implantation, then patterning the source region of the write tube by photolithography, then etching the sacrificial layer material in the source region of the write tube, and then forming an N-type semiconductor layer by ion implantation;

[0013] Step 7: forming source-drain contacts, specifically, patterning the source and drain of the write tube by photolithography, then etching the isolation layer material in the region between the write tube sources and the region between the write tube drains, then depositing the sidewall layer material, then flattening by CMP, then patterning the source and drain of the write tube by photolithography, then etching the redundant sidewall layer material in the region between the write tube sources and the region between the drains, then depositing the pre-contact metal, then using annealing to allow the pre-contact metal to react with the semiconductor to generate metal silicide as the contact metal, then removing the unreacted pre-contact metal, and then using annealing to activate the impurities;

[0014] Step 8: forming a readout tube region, the specific method is to pattern the readout tube region by photolithography, and then etch the excess contact metal on the write tube source and outside the readout tube region to form the readout tube region;

[0015] Step 9: forming a readout tube gate dielectric, the specific method is to pattern the readout tube region by photolithography, then deposit the gate dielectric layer material, and then remove the photoresist and excess material;

[0016] Step 10: forming a readout pipe channel layer, the specific method is to pattern the readout pipe region by photolithography, then form the readout pipe channel layer material, and then remove the photoresist and excess material;

[0017] Step 11: forming an independent channel region of the readout tube, the specific method is to pattern the readout tube channel region by photolithography, and then etch the readout tube channel layer material outside the readout tube channel region to remove the interconnection region of multiple readout tubes;

[0018] Step 12: forming a readout tube sidewall, specifically by depositing a sidewall layer material, then patterning the readout tube sidewall region by photolithography, and then etching the sidewall layer material outside the sidewall region to form the readout tube sidewall;

[0019] Step 13: forming a readout tube source-drain metal contact, the specific method is to pattern the readout tube channel region by photolithography, then form a contact metal, then remove the photoresist and excess materials, and then anneal;

[0020] Step 14: forming the RWL, the specific method is to pattern the RWL area by photolithography, then deposit the source and drain metal, and then remove the photoresist and excess metal;

[0021] Step 15: forming the WBL and RBL regions, specifically by depositing the sidewall layer material, then planarizing it by CMP, then patterning the WBL and RBL regions by photolithography, and then etching the sacrificial layer material in the WBL and RBL regions;

[0022] Step 16: Form RBL and WBL metal contacts. The specific method is to deposit pre-contact metal, then use annealing to allow the pre-contact metal to react with the semiconductor, then remove the unreacted pre-contact metal, and then anneal. The metal silicide formed in the RBL area and the WBL area can serve as the RBL and WBL metal contacts.

[0023] Specifically, the substrate in step 1 can be a bare silicon wafer or a silicon wafer on which front-end devices and circuits have been prepared. The sacrificial layer material can be a dielectric material such as fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, etc., whose dielectric constant is not greater than that of silicon dioxide, or a semiconductor material such as germanium silicon. The thickness of the deposited single-layer sacrificial layer material is between 10nm and 500nm, and the method of depositing the sacrificial layer material can be PVD, CVD, epitaxy, etc. The write channel layer material can be a semiconductor material such as amorphous silicon or single crystal silicon, and the thickness of the deposited single-layer write channel layer material is between 10nm and 500nm, and the method of depositing the write channel layer material can be PVD, CVD, epitaxy, etc.

[0024] The isolation material in step 3 may be a dielectric material such as silicon dioxide, and the method of depositing the isolation material may be PVD, CVD, ALD, etc. The thickness of the isolation layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material;

[0025] The sidewall material in step 4 may be a dielectric material such as silicon nitride, and the sidewall material may be deposited by PVD, CVD, ALD, etc. The thickness of the sidewall layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material;

[0026] The P-type impurities implanted in step 6 may be boron or boron fluoride, and the N-type impurities may be phosphorus or arsenic. The energy of the ion implantation is between 1keV and 100keV, and the dose of the ion implantation is between 1E13cm -2 To 1E17cm -2 The angle of ion implantation is between 0° and 90°;

[0027] In step 7, the pre-contact metal material may be a metal such as titanium, nickel or cobalt, and the contact metal material may be a metal silicide material such as titanium silicon, nickel silicon or cobalt silicon. The method of depositing the pre-contact metal material may be PVD, etc., and the thickness of the pre-contact metal material is between 10nm and 1000nm;

[0028] The width of the etched contact metal in step 8 is no greater than twice the thickness of the readout channel layer material in step 10;

[0029] In step 9, the gate dielectric layer material may be a dielectric layer such as silicon dioxide, hafnium oxide, zirconium oxide, or a stacked material of two of them. The gate dielectric layer material may be deposited by ALD or CVD, and the gate dielectric layer material thickness is between 1 nm and 10 nm.

[0030] In step 10, the readout pipe channel layer material can be a semiconductor material such as N-type impurity doped amorphous silicon, N-type impurity doped single crystal silicon or oxide semiconductor. The readout pipe channel layer material can be formed by material deposition processes such as PVD, CVD, ALD, epitaxy, and auxiliary doping methods such as ion implantation. The thickness of the readout pipe channel layer material is between 1nm and 100nm;

[0031] The contact metal in step 13 may be a metal material such as titanium, tantalum, titanium nitride, tantalum nitride, platinum, or a metal material such as titanium silicon, nickel silicon, cobalt silicon, etc.;

[0032] The source and drain metal in step 14 can be a metal material such as tungsten, copper, titanium nitride, tantalum nitride, or a laminated material of several metals. The specific technical effects of the three-dimensional memory structure and its integration method of the present invention are as follows:

[0033] 1. The write tube of the proposed memory structure is a low-power bidirectional conduction device with a ring gate, and the read tube is a high-performance ring channel device, which can simultaneously achieve the advantages of long retention time, fast read speed, and low power consumption;

[0034] 2. The proposed memory structure is a three-dimensional structure, which can realize the stacking of multiple layers of memory cells in a limited area and increase the storage density;

[0035] 3. The proposed integration method enables multiple repetitive unit structures in the storage structure to share the process steps of lithography, etching, ion implantation, annealing, etc., which significantly reduces the process cost of storing information per bit in the storage structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Yes Description Figures 2 to 18 Schematic diagram of viewing angles;

[0037] Figure 2 is a schematic diagram of the display effect obtained by using the memory structure and the integration method proposed by the present invention, showing a cross-sectional view along the channel direction, wherein Figure 2 (a) is a schematic diagram of a single storage unit structure. Figure 2 (b) is a memory structure diagram after multiple unit structures are stacked up and down;

[0038] Figure 3-Figure 18 This is a schematic diagram of the steps for preparing the memory structure proposed by the present invention by using the integration method proposed by the present invention, wherein:

[0039] Figure 3 is a front view of depositing multiple layers of sacrificial layer materials and writing channel layers;

[0040] Figure 4 It is a top view after defining the active area;

[0041] Figure 5 is a top view after forming an active area isolation layer;

[0042] Figure 6 It is a front view after forming the side wall isolation layer;

[0043] Figure 7 (a) is a cross-sectional view along the channel direction after the write gate end is formed. Figure 7 (b) is a top view after the write-in tube gate end is formed;

[0044] Figure 8 It is a cross-sectional view along the channel direction after the source and drain semiconductor layers are formed;

[0045] Fig. 9 It is a cross-sectional view along the channel direction after the source-drain contact is formed;

[0046] Fig.10 It is a cross-sectional view along the channel direction after the readout tube region is formed;

[0047] Fig.11 It is a cross-sectional view along the channel direction after the readout tube gate dielectric is formed;

[0048] Fig.12 It is a cross-sectional view along the channel direction after the readout pipe channel layer is formed;

[0049] Fig.13 It is a cross-sectional view along the channel direction after the independent channel region of the readout tube is formed;

[0050] Fig.14 It is a cross-sectional view along the channel direction after the readout tube side wall is formed;

[0051] Fig.15 It is a cross-sectional view along the channel direction after the readout tube source-drain metal contact is formed;

[0052] Fig.16 It is a cross-sectional view along the channel direction after the RWL is formed;

[0053] Fig.17 It is a cross-sectional view along the channel direction after the WBL and RBL regions are formed;

[0054] Fig.18 It is a cross-sectional view along the channel direction after the metal contacts between RBL and WBL are formed;

[0055] In the figure:

[0056] 1——Write channel layer 2——Sacrificial layer

[0057] 3——Isolation layer 4——Side wall layer

[0058] 5——Gate dielectric layer 6——Gate conductive layer

[0059] 7——P-type semiconductor layer 8——N-type semiconductor layer

[0060] 9——Contact metal 10——Readout channel layer

[0061] 11——Source and drain metal 12——WWL

[0062] 13——WBL 14——RWL

[0063] 15——RBL DETAILED DESCRIPTION

[0064] The present invention is further described below by examples. It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

[0065] Figure 2 is a schematic diagram of one of the presentation effects obtained by using the memory structure and integration method proposed by the present invention, wherein Figure 2 (b) is a schematic diagram of a single storage unit structure. Figure 2 (a) is a diagram of the memory structure after multiple unit structures are stacked up and down. Figure 1 Yes Description Figures 2 to 18 Schematic diagram of viewing angles, with the directions of the three viewing angles along the channel direction, top view and front view marked. Figure 2 The memory structure shown in (a) consists of multiple Figure 2 The unit structure shown in (b) is stacked from bottom to top. Figure 2 (b), the write tube is located on the left and the read tube is located on the right. Each unit structure consists of a write tube and a read tube. The source end of the write tube also serves as the gate end of the read tube to achieve the connection between the write tube and the read tube in the horizontal direction. In each unit structure, the write tube is a low-power bidirectional conductive device with a ring-gate structure. The specific features are as follows: the channel of the write tube is composed of a write tube channel layer 1 composed of lightly doped single crystal silicon, and the right and left sides of the write tube channel are its source and drain ends respectively. The gate end is composed of a stacked gate dielectric layer 5 composed of silicon dioxide and hafnium oxide and a gate conductive layer 6 composed of titanium nitride, with a length of 60nm. The gate end is in a direction perpendicular to the channel and surrounds the channel on all sides. Figure 2 The cross-sectional view along the channel direction shows that the gate end is located at the upper and lower sides of the channel. The source end is composed of a contact metal 9 composed of metal silicide and an N-type semiconductor layer 8 composed of arsenic-doped single crystal silicon. The source end is located on the right side of the channel, and the source end is close to the gate end in the horizontal direction. The drain end is composed of a contact metal 9 composed of metal silicide and a P-type semiconductor layer 7 composed of boron fluoride-doped single crystal silicon. The drain end is located on the left side of the channel, and the drain end is 40nm away from the gate end in the horizontal direction. The readout tube is a high-performance device with a ring channel structure, and the specific features are as follows: the gate end of the readout tube is composed of a contact metal 9 composed of a metal silicide at the source end of the write tube and a gate dielectric layer 5 composed of a silicon dioxide-hafnium oxide stack, and the readout tube gate dielectric layer 5 wraps the contact metal 9 at the source end of the write tube. The readout tube channel is a readout tube channel layer 10 composed of arsenic-doped single crystal silicon, and the readout tube channel 10 wraps the readout tube gate dielectric layer 5. The source and drain ends of the readout tube are respectively composed of a contact metal 9 composed of metal silicide and its adjacent readout tube channel layer 10. The contact metal at the source end and the contact metal at the drain end are separated by 60nm. The contact metal at the source end is connected to multiple unit structures through the source-drain metal 11.

[0066] Figure 2 The memory structure shown in (a) can be achieved by placing multiple Figure 2 (b) is obtained by stacking the unit structure shown in FIG. 1 up and down. The specific features are as follows: the gate ends of the write tubes of the unit structure in the same row are connected together through the gate conductive layer 6 to form the write word line WWL12, the drain ends of the write tubes of the unit structure in the same column are connected together through the contact metal 9 to form the write bit line WBL13, the source ends of the read tubes of the unit structure in the same row are connected together through the source-drain metal to form the read word line RWL14, and the drain ends of the read tubes of the unit structure in the same column are connected together through the contact metal to form the read bit line RBL15. In each unit structure, the source end of the write tube serves as the gate end of the read tube, and the source end of the write tube and the gate end of the read tube are the storage node SN of the unit structure.

[0067] Figure 2 The memory shown can be prepared by the integration method proposed in this patent. The specific method is shown in FIG. Figures 3 to 18 , the steps are as follows:

[0068] First, a plurality of sacrificial layer materials composed of fluorine-doped silicon dioxide and a write channel layer material composed of amorphous silicon are deposited on the substrate, such as Figure 3 As shown, the specific method is to deposit a 200nm layer of fluorine-doped silicon dioxide by PVD, then deposit a 100nm layer of amorphous silicon, and then repeatedly deposit fluorine-doped silicon dioxide and amorphous silicon layers, a total of four layers of fluorine-doped silicon dioxide and three layers of amorphous silicon;

[0069] Next, define the active region, such as Figure 4As shown, the specific method is to pattern the active area by photolithography, and then etch the fluorine-doped silicon dioxide and amorphous silicon outside the active area to form the active area;

[0070] Next, an active region isolation layer is formed, such as Figure 5 As shown, the specific method is to deposit an isolation layer material composed of 1300nm silicon dioxide, then pattern the storage array area by photolithography, then etch the excess silicon dioxide outside the storage array, and then planarize it by chemical mechanical polishing (CMP);

[0071] Next, a sidewall isolation layer is formed, such as Figure 6 As shown, the specific method is to pattern the sidewall area by photolithography, then etch the fluorine-doped silicon dioxide and silicon dioxide in the sidewall area, then deposit a sidewall layer material composed of 1300nm silicon nitride, then planarize it by CMP, then pattern the storage array area by photolithography, and then etch the excess silicon nitride outside the storage array;

[0072] Next, the gate end of the write tube is formed, such as Figure 7 As shown, the specific method is to pattern the area between the gate and the pipe by photolithography, then etch the silicon dioxide isolation layer between the gate and the pipe, then deposit the silicon nitride sidewall, then planarize it by CMP, then pattern the area between the gate and the pipe by photolithography, then etch the excess silicon nitride between the gate and the pipe, then use the standard HKMG process to prepare the gate dielectric layer and the gate conductive layer, then remove the photoresist and excess materials, and the gate conductive layer formed in this step connects the gate ends of multiple unit structures together to form a WWL.

[0073] Next, source and drain semiconductor layers are formed, such as Figure 8 As shown, the specific method is to pattern the drain area of ​​the write tube by photolithography, then etch the fluorine-doped silicon dioxide in the drain area, and then ion-implant boron fluoride at a condition of 5keV5E15cm -2 The injection angle is 10°, and then the source region of the write tube is patterned by photolithography, and then the fluorine-doped silicon dioxide in the source region of the write tube is etched, and then arsenic is ion-implanted. The injection conditions are 12keV5E15cm -2 , the injection angle is 10°;

[0074] Next, source-drain contacts are formed, such as Fig. 9As shown, the specific method is to pattern the source and drain of the write tube by photolithography, then etch the silicon dioxide isolation layer in the area between the write tube sources and the silicon dioxide isolation layer in the area between the write tube drains, then deposit silicon nitride sidewalls, then flatten by CMP, then pattern the source and drain of the write tube by photolithography, then etch the excess silicon nitride material in the area between the write tube sources and the area between the drains, then deposit 90nm nickel, then anneal at 500℃ for 15min to generate nickel-silicon alloy, then remove unreacted nickel, then anneal at 600℃ for 30min to activate impurities and convert the amorphous silicon in the write tube area into single crystal silicon;

[0075] Next, the readout tube region is formed, such as Fig.10 As shown, the specific method is to pattern the readout tube region by photolithography, and then etch the excess nickel-silicon alloy written on the tube source and located outside the readout tube region to form the readout tube region;

[0076] Next, the readout gate dielectric is formed, such as Fig.11 As shown, the specific method is to pattern the readout tube area by photolithography, then deposit a 3nm hafnium oxide dielectric layer, then deposit a 1nm silicon dioxide dielectric layer, and then remove the photoresist and excess materials;

[0077] Next, a readout channel layer is formed, such as Fig.12 As shown, the specific method is to pattern the readout tube area by photolithography, then deposit 60nm amorphous silicon material, and then ion implant arsenic under the conditions of 12keV5E15cm -2 , the implantation angle is 10°, and then the photoresist and excess materials are removed;

[0078] Next, the readout tube independent channel region is formed, such as Fig.13 As shown, the specific method is to pattern the readout tube channel region by photolithography, and then etch the amorphous silicon outside the readout tube channel region to remove the interconnection region of multiple readout tubes;

[0079] Next, the readout tube side walls are formed, such as Fig.14 As shown, the specific method is to deposit 1300nm silicon nitride, then pattern the readout tube side wall region by photolithography, and then etch the silicon nitride outside the side wall region to form the readout tube side wall;

[0080] Next, the contact metal of the source and drain regions of the readout tube is formed, such as Fig.15As shown, the specific method is to pattern the channel region of the readout tube by photolithography, then deposit 30nm nickel, then anneal at 650℃ for 12min, then remove the unreacted nickel, then anneal at 650℃ for 30min again, form a nickel-silicon alloy in the source and drain region of the readout tube, and at the same time make the amorphous silicon in the readout tube region become single crystal silicon, and then remove the photoresist and excess materials;

[0081] Next, form the RWL, such as Fig.16 As shown, the specific method is to pattern the RWL region by photolithography, and then deposit source and drain metal composed of metal tungsten, the metal tungsten connects the readout tube source regions of multiple unit structures together to form RWL, and then remove the photoresist and excess metal;

[0082] Next, the WBL and RBL regions are formed, as Fig.17 As shown, the specific method is to deposit 1300nm silicon nitride, then planarize it by CMP, then pattern the WBL and RBL regions by photolithography, and then etch the fluorine-doped silicon dioxide in the WBL and RBL regions;

[0083] Next, the contact metals of RBL and WBL regions are formed, such as Fig.18 As shown, the specific method is to deposit 50nm nickel, then anneal at 550℃ for 12min, then remove the unreacted nickel, and then anneal at 550℃ for 30min again, to form a contact metal composed of nickel-silicon alloy in the RBL and WBL regions, and the contact metal connects the write tube drain regions of multiple unit structures together to form WBL, and connects the read tube drain regions of multiple unit structures together to form RBL.

[0084] Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A three-dimensional memory structure, characterized in that: The invention is composed of a plurality of unit structures stacked from bottom to top, each unit structure includes a write tube and a read tube, the source end of the write tube is also used as the gate end of the read tube, so as to realize the connection between the write tube and the read tube in the horizontal direction; the gate ends of the write tubes of the unit structures in the same row are connected together through a gate conductive layer to form a write word line WWL, the drain ends of the write tubes of the unit structures in the same column are connected together through a contact metal to form a write bit line WBL, the source end of the write tube is also used as the gate end of the read tube and the storage node SN of the unit structure, the source ends of the read tubes of the unit structures in the same row are connected together through a source-drain metal to form a read word line RWL, and the drain ends of the read tubes of the unit structures in the same column are connected together through a contact metal to form a read bit line RBL; the write tube is a low-power bidirectional conductive device with a ring gate structure, and the read tube is a high-performance device with a ring channel structure.

2. The three-dimensional memory structure according to claim 1, characterized in that: The write tube has a source end and a drain end on both sides of its channel, a gate end in a direction perpendicular to the channel and surrounding the channel, a source end close to the gate end in a horizontal direction, and a drain end separated from the gate end by a distance in the horizontal direction; the write tube channel is composed of a write channel layer, the gate end is composed of a gate dielectric layer and a gate conductive layer, the drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, that is, the doping types of the semiconductor parts of the source end and the drain end are opposite.

3. The three-dimensional memory structure according to claim 1, wherein: The gate end of the readout tube is composed of the contact metal of the source end of the write tube and the readout tube gate dielectric, the readout tube gate dielectric wraps the contact metal of the source end of the write tube, the channel of the readout tube is composed of the readout channel layer, the readout channel layer wraps the readout tube gate dielectric layer, the source end and the drain end of the readout tube are both composed of the contact metal and the readout channel layer close to the contact metal, and the source end and the drain end are both in contact with the readout tube channel.

4. A method for integrating a three-dimensional memory structure, characterized in that: The specific steps include: Step 1: depositing multiple layers of sacrificial layer material and write channel layer material on a substrate, wherein the specific method is to deposit a layer of sacrificial layer material, then deposit a layer of write channel layer material, and then repeatedly deposit sacrificial layer material and write channel layer material, and the last deposited material is the sacrificial layer material, and the number of layers of the write channel layer is the number of repetitions of the unit structure in the above memory structure; Step 2: define the active area, the specific method is to pattern the active area by photolithography, and then etch the sacrificial layer material outside the active area and the write channel layer material to form the active area; Step 3: forming active area isolation, the specific method is to deposit isolation layer material, then pattern the memory array area by photolithography, then etch the excess isolation layer material outside the memory array, and then planarize it by chemical mechanical polishing (CMP); Step 4: forming a sidewall isolation, the specific method is to pattern the sidewall area by photolithography, then etch the sacrificial layer material and the isolation layer material in the sidewall area, then deposit the sidewall layer material, then planarize it by CMP, then pattern the storage array area by photolithography, and then etch the excess sidewall layer material outside the storage array; Step 5: forming a write-in tube gate terminal, specifically, patterning the area between the write-in tube gate and the gate by photolithography, then etching the isolation layer between the write-in tube gates, then depositing the sidewall layer material, then planarizing by CMP, then patterning the area between the write-in tube gates by photolithography, then etching the redundant sidewall layer material between the write-in tube gates, then preparing the gate stack by a standard polySi-SiO2 process or HKMG process, and then removing the photoresist and redundant materials; Step 6: forming a source-drain semiconductor layer, specifically, patterning the drain region of the write tube by photolithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by ion implantation, then patterning the source region of the write tube by photolithography, then etching the sacrificial layer material in the source region of the write tube, and then forming an N-type semiconductor layer by ion implantation; Step 7: forming source-drain contacts, specifically, patterning the source and drain of the write tube by photolithography, then etching the isolation layer material in the region between the write tube sources and the region between the write tube drains, then depositing the sidewall layer material, then flattening by CMP, then patterning the source and drain of the write tube by photolithography, then etching the redundant sidewall layer material in the region between the write tube sources and the region between the drains, then depositing the pre-contact metal, then using annealing to allow the pre-contact metal to react with the semiconductor to generate metal silicide as the contact metal, then removing the unreacted pre-contact metal, and then using annealing to activate the impurities; Step 8: forming a readout tube region, the specific method is to pattern the readout tube region by photolithography, and then etch the excess contact metal on the write tube source and outside the readout tube region to form the readout tube region; Step 9: forming a readout tube gate dielectric, the specific method is to pattern the readout tube region by photolithography, then deposit the gate dielectric layer material, and then remove the photoresist and excess material; Step 10: forming a readout pipe channel layer, the specific method is to pattern the readout pipe region by photolithography, then form the readout pipe channel layer material, and then remove the photoresist and excess material; Step 11: forming an independent channel region of the readout tube, the specific method is to pattern the readout tube channel region by photolithography, and then etch the readout tube channel layer material outside the readout tube channel region to remove the interconnection region of multiple readout tubes; Step 12: forming a readout tube sidewall, specifically by depositing a sidewall layer material, then patterning the readout tube sidewall region by photolithography, and then etching the sidewall layer material outside the sidewall region to form the readout tube sidewall; Step 13: forming a readout tube source-drain metal contact, the specific method is to pattern the readout tube channel region by photolithography, then form a contact metal, then remove the photoresist and excess materials, and then anneal; Step 14: forming the RWL, the specific method is to pattern the RWL area by photolithography, then deposit the source and drain metal, and then remove the photoresist and excess metal; Step 15: forming the WBL and RBL regions, specifically by depositing the sidewall layer material, then planarizing it by CMP, then patterning the WBL and RBL regions by photolithography, and then etching the sacrificial layer material in the WBL and RBL regions; Step 16: Form RBL and WBL metal contacts. The specific method is to deposit pre-contact metal, then use annealing to allow the pre-contact metal to react with the semiconductor, then remove the unreacted pre-contact metal, and then anneal. The metal silicide formed in the RBL area and the WBL area can serve as the RBL and WBL metal contacts.

5. The method for integrating a three-dimensional memory structure according to claim 4, wherein: The substrate in step 1 is a bare silicon wafer, or a silicon wafer on which front-end devices and circuits have been prepared; the sacrificial layer material is a dielectric material with a dielectric constant not greater than that of silicon dioxide: fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or a semiconductor material: germanium silicon; the thickness of the deposited single-layer sacrificial layer material is between 10nm and 500nm, and the method of depositing the sacrificial layer material is: PVD, CVD or epitaxy; the write channel layer material is amorphous silicon or single crystal silicon, the thickness of the deposited single-layer write channel layer material is between 10nm and 500nm, and the method of depositing the write channel layer material is PVD, CVD or epitaxy.

6. The method for integrating a three-dimensional memory structure according to claim 4, wherein: The isolation material in step 3 is a dielectric material silicon dioxide, and the isolation material is deposited by PVD, CVD or ALD. The thickness of the isolation layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material.

7. The method for integrating a three-dimensional memory structure according to claim 4, wherein: The sidewall material in step 4 is a dielectric material silicon nitride, and the sidewall material is deposited by PVD, CVD or ALD. The thickness of the sidewall layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material.

8. The method for integrating a three-dimensional memory structure according to claim 4, wherein: In step 6, the P-type impurity ion implanted is boron or boron fluoride, the N-type impurity is phosphorus or arsenic, the energy of the ion implantation is between 1keV and 100keV, and the dose of the ion implantation is 1E13cm -2 To 1E17cm -2 The angle of ion implantation is between 0° and 90°.

9. The method for integrating a three-dimensional memory structure according to claim 4, wherein: In step 7, the pre-contact metal material is a metal: titanium, nickel or cobalt, and the contact metal material is a metal silicide material: titanium silicon, nickel silicon or cobalt silicon; the method of depositing the pre-contact metal material is PVD, and the thickness of the pre-contact metal material is between 10nm and 1000nm.

10. The method for integrating a three-dimensional memory structure according to claim 4, wherein: The width of the etched contact metal in step 8 is no greater than twice the thickness of the readout channel layer material in step 10; In step 9, the gate dielectric layer material is silicon dioxide, hafnium oxide, zirconium oxide, or a stacked material of two of them, the gate dielectric layer material is deposited by ALD or CVD, and the gate dielectric layer material has a thickness between 1 nm and 10 nm; In the step 10, the readout pipe channel layer material is: N-type impurity-doped amorphous silicon, N-type impurity-doped single crystal silicon or oxide semiconductor; the readout pipe channel layer material is formed by material deposition process: PVD, CVD, ALD, epitaxy, and auxiliary doping method: ion implantation; The thickness of the readout channel layer material is between 1 nm and 100 nm; In step 13, the contact metal is titanium, tantalum, titanium nitride, tantalum nitride, platinum, titanium silicon, nickel silicon or cobalt silicon; In step 14, the source and drain metals are tungsten, copper, titanium nitride, tantalum nitride, or a stacked material of several metals.

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