Planar silicon carbide MOSFET structure and preparation method thereof

Abstract

According to the planar silicon carbide MOSFET structure and the preparation method thereof provided by the invention, the SiC source region starts to be etched above the SiC source region through an inductive coupling plasma etching process, so that the source contact hole can be formed in the SiC source region, and the source contact hole can extend into the silicon carbide substrate, so that after a source metal layer is formed subsequently, the source metal layer can be formed in the silicon carbide substrate. According to the invention, the contact area between the source region and the source region metal layer can be increased, and the source contact resistance of the silicon carbide MOSFET structure is reduced, so that the on resistance of the silicon carbide MOSFET structure is reduced, and finally the loss of the device can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a planar silicon carbide MOSFET structure and a preparation method thereof. Background Art

[0002] Wide bandgap semiconductor material silicon carbide is a group IV-IV compound semiconductor with advantages such as 2.3-3.3eV bandgap width, high thermal conductivity (at least 3 times that of silicon) and high critical breakdown electric field (at least 10 times that of silicon). Based on the above superior properties of silicon carbide material, it has become an ideal material for preparing high-power, high-voltage, high-temperature resistant MOSFET devices.

[0003] MOSFET is the most widely used device structure in power devices. Due to the lack of charge storage effect, silicon carbide MOSFET has better switching characteristics and lower switching losses than bipolar devices. For MOSFET, there are two main directions for future devices. One is trench gate silicon carbide MOSFET, which has better forward conduction capability than planar gate silicon carbide MOSFET, but the technical difficulties in trench etching process and trench gate oxide protection design method are relatively large.

[0004] like Figure 1 As shown, it shows a unit structure of a power MOSFET based on silicon carbide material, which includes from bottom to top: drain, heavily doped N-type substrate, lightly doped N-type drift region, P-well region, heavily doped N-type source region, planar gate and source. It can be seen from the figure that the resistance of each part on the equivalent current path between the source and the drain is connected in series, so the total on-resistance of the unit structure is equal to the sum of the resistances of each part. Among them, the source contact resistance RCS mainly depends on the contact area between the source metal layer and the heavily doped N-type source region and the contact resistivity of the source region. The larger the contact area of ​​the source region and the smaller the contact resistivity of the source region, the smaller the source contact resistance RCS. Although the contact resistivity can be optimized by optimizing the ohmic contact process, for example, by selecting appropriate metallization materials, adjusting the thickness of the metal layer and the annealing process, the performance of the ohmic contact can be optimized, thereby reducing the contact resistivity; however, when designing MOSFET, it is necessary to consider the compactness and integration of the structure while ensuring performance, and the contact area cannot be increased indefinitely. Since the unit structure size of the MOSFET is fixed, the contact area between the source metal layer and the heavily doped N-type source region is limited by the size of the unit structure of the MOSFET, thereby affecting the source contact resistance RCS, and thus seriously affecting the total on-resistance of the unit structure. Therefore, how to increase the contact area between the source metal layer and the heavily doped N-type source region has become a problem that needs to be solved urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a planar silicon carbide MOSFET structure and a preparation method thereof, so as to solve the problem in the prior art that the contact area between the source metal layer and the heavily doped N-type source region is limited due to the size limitation of the unit structure of the MOSFET, thereby affecting the on-resistance of the MOSFET.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a planar silicon carbide MOSFET structure, the preparation method comprising the following steps:

[0008] S1: providing a substrate, and forming a drift region on the front side of the substrate by an epitaxial process;

[0009] S2: performing ion implantation at the top of the drift region to form a P-type base region, wherein the depth of the P-type base region is less than the height of the drift region;

[0010] S3: performing ion implantation on the top of the P-type base region to form a source region, wherein the depth of the source region is less than the height of the P-type base region;

[0011] S4: forming a gate structure above the source region, wherein the gate structure comprises a gate oxide layer located on the drift region and a polysilicon gate located on the gate oxide layer;

[0012] S5: etching the source region to form a source contact hole in the source region;

[0013] S6: depositing an ohmic metal layer and a source metal layer in the source contact hole in sequence, wherein the ohmic metal layer forms an ohmic contact with the source region, and the source metal layer fills the source contact hole and covers the gate structure and is connected to the ohmic metal layer;

[0014] S7: thinning the back side of the substrate and depositing metal on the back side of the substrate to form a drain metal layer.

[0015] Optionally, the doping concentration of the P-type base region includes 1×10 17 cm -3 ~1×10 18 cm -3 , the implantation depth of the P-type base region is 900 to 1200 nm.

[0016] Optionally, the doping concentration of the source region includes 1×10 19 cm -3 ~1×10 20 cm -3 , the injection depth of the source region includes 400 to 600 nm.

[0017] Optionally, a lateral dimension of the source contact hole is in the range of 900-1200 nm, and a depth of the source contact hole extending in the source region is in the range of 150-250 nm.

[0018] Optionally, after forming the polysilicon gate, a step of forming an interlayer dielectric layer is further included, wherein the interlayer dielectric layer covers the polysilicon gate.

[0019] Optionally, the ion types implanted when forming the P-type base region include one or more of aluminum ions and boron ions.

[0020] Optionally, the process for etching the polysilicon gate, the gate oxide layer and the source region is an inductively coupled plasma etching process.

[0021] The present invention also provides a planar silicon carbide MOSFET structure, the planar silicon carbide MOSFET structure at least comprising:

[0022] substrate;

[0023] A drift region, wherein the drift region is disposed on the front surface of the substrate and covers the substrate;

[0024] A P-type base region, wherein the P-type base region is located in the drift region and has a depth less than a depth of the substrate;

[0025] A source region, wherein the source region is located in the P-type base region and the depth of the source region is less than the depth of the P-type base region;

[0026] a source contact hole, wherein the source contact hole is located in the source region, and the depth of the source contact hole extending in the source region is less than the depth of the source region;

[0027] A gate structure, the gate structure comprising a polysilicon gate, a gate oxide layer and an interlayer dielectric layer, the interlayer dielectric layer being located above the drift region and covering the gate oxide layer and the polysilicon gate;

[0028] an ohmic metal layer, the ohmic metal layer being located at the bottom of the source contact hole and contacting the source region to form an ohmic contact;

[0029] a source metal layer, covering the gate structure, filling the source contact hole and contacting the ohmic metal layer;

[0030] A drain metal layer is located on the back of the substrate.

[0031] Optionally, the ohmic metal layer is made of one or a combination of titanium, nickel or platinum, and the source metal layer is made of one or a combination of titanium, nickel or platinum.

[0032] Optionally, the doping concentration of the drift region includes 5×10 15 cm -3 ~1×10 16 cm -3 .

[0033] As described above, the planar silicon carbide MOSFET structure and preparation method thereof of the present invention have the following beneficial effects: a source contact hole is formed above the source region using an inductively coupled plasma etching process, so that the source contact hole extends toward the interior of the silicon carbide substrate, thereby increasing the contact area between the source region and the source region metal layer, reducing the source contact resistance of the silicon carbide MOSFET structure, thereby reducing the on-resistance of the silicon carbide MOSFET structure, and ultimately reducing device losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The figure shows a unit structure of a power MOSFET based on silicon carbide material in the prior art.

[0035] Figure 2 It is a schematic flow chart of the method for preparing the planar silicon carbide MOSFET structure of the present invention.

[0036] Figure 3 It is a schematic cross-sectional structure diagram of forming an N-type drift region in the silicon carbide MOSFET structure of the present invention.

[0037] Figure 4 It is a schematic cross-sectional structure diagram of a P-type base region formed in the silicon carbide MOSFET structure of the present invention.

[0038] Figure 5 It is a schematic diagram showing the cross-sectional structure of a source region formed in the silicon carbide MOSFET structure of the present invention.

[0039] Figure 6 It is a schematic cross-sectional structure diagram of a gate structure formed in the silicon carbide MOSFET structure of the present invention.

[0040] Figure 7 It is a schematic cross-sectional structure diagram of an interlayer dielectric layer formed in the silicon carbide MOSFET structure of the present invention.

[0041] Figure 8 It is a schematic cross-sectional structure diagram of forming a source contact hole in the silicon carbide MOSFET structure of the present invention.

[0042] Fig. 9 It is a schematic cross-sectional structure diagram of the silicon carbide MOSFET structure of the present invention forming an ohmic metal layer.

[0043] Fig.10 It is a schematic cross-sectional structure diagram of forming a source metal layer in the silicon carbide MOSFET structure of the present invention.

[0044] Fig.11 It is a schematic cross-sectional structure diagram of forming a drain metal layer in the silicon carbide MOSFET structure of the present invention.

[0045] Component number description

[0046] 10. Substrate; 11. Drift region; 12. P-type base region; 13. Source region; 14. Gate oxide layer; 15. Polysilicon gate; 16. Interlayer dielectric layer; 17. Source contact hole; 18. Ohmic metal layer; 19. Source metal layer; 20. Drain metal layer; S1~S7, steps. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0049] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0050] See also Figures 1 to 11It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0051] Embodiment 1

[0052] like Figure 2 As shown, an embodiment of the present invention provides a method for preparing a planar silicon carbide MOSFET structure, the method comprising the following steps:

[0053] S1: providing a substrate 10, and forming a drift region 11 on the front side of the substrate 10 by an epitaxial process;

[0054] S2: performing ion implantation at the top of the drift region 11 to form a P-type base region 12, wherein the depth of the P-type base region 12 is smaller than the height of the drift region 11;

[0055] S3: performing ion implantation on the top of the P-type base region 12 to form a source region 13, wherein the depth of the source region 13 is less than the height of the P-type base region 12;

[0056] S4: forming a gate structure above the source region 13 , wherein the gate structure includes a gate oxide layer 14 located on the drift region 11 and a polysilicon gate 15 located on the gate oxide layer 14 ;

[0057] S5: etching the source region 13 to form a source contact hole 17 in the source region 13;

[0058] S6: depositing an ohmic metal layer 18 and a source metal layer 19 in sequence in the source contact hole 17, wherein the ohmic metal layer 18 forms an ohmic contact with the source region 13, and the source metal layer 19 fills the source contact hole 17 and covers the gate structure, and is connected to the ohmic metal layer 18;

[0059] S7: thinning the back side of the substrate 10 and depositing metal on the back side of the substrate 10 to form a drain metal layer 20 .

[0060] The following is a further introduction to the preparation method of the planar silicon carbide MOSFET structure in conjunction with the accompanying drawings, as follows:

[0061] For details, please refer to Figure 3 , perform step S1, provide a substrate 10, and form a drift region 11 on the front side of the substrate 10 through an epitaxial process.

[0062] As an example, the substrate 10 may be a silicon substrate, or other types, such as germanium, silicon carbide (SiC), or silicon germanium (SiGe). The substrate 10 may also include compound semiconductors and / or alloy semiconductors, such as gallium nitride, gallium arsenide, etc. The substrate 10 proposed in the present invention may be an N-type substrate or a P-type substrate. In the present embodiment, the substrate 10 uses an N-type heavily doped silicon carbide substrate 10 and forms an N-type drift region 11 on the N-type heavily doped silicon carbide substrate 10. It should be noted that heavy doping and subsequent light doping are relative concepts, and the specific doping dose can be adjusted as needed.

[0063] In this embodiment, an N-type drift region 11 is formed on the front surface of the substrate 10 by a multi-layer epitaxial growth process, and the doping concentration type of the N-type drift region 11 is lightly doped.

[0064] For details, please refer to Figure 4 , executing step S2, performing ion implantation at the top of the drift region 11 to form a P-type base region 12, wherein the depth of the P-type base region 12 is less than the height of the drift region 11.

[0065] like Figure 4 As shown, ion implantation is performed on the front side of the N-type drift region 11 to form a P-type base region 12. Specifically, a photoresist masking layer is made on the front side of the N-type drift region 11, and P+ ion implantation is performed by ion implantation, which is pushed and diffused to form the P-type base region 12. The impurity ion types implanted into the P-type base region 12 include one or more of aluminum ions and boron ions, that is, it can be one of them or a combination of two. In this embodiment, aluminum ions are selected as the impurity ion types implanted. The depth of the P-type base region 12 finally formed is less than the height of the drift region 11. After the P-type base region 12 is formed, the photoresist masking layer can be removed by ashing.

[0066] Optionally, the doping concentration of the P-type base region 12 includes 1×10 17 cm -3 ~1×10 18 cm -3 , for example, it can be 1×10 17 cm -3 , 1×10 17.5 cm -3 or 1×10 18 cm -3 .

[0067] Optionally, the implantation depth of the P-type base region 12 is 900-1200 nm, for example, 900 nm, 1000 nm, 1100 nm or 1200 nm. In this embodiment, the implantation depth of the P-type base region 12 can be controlled by controlling parameters such as implantation energy, implantation time and temperature in the ion implantation process, which is well known to those skilled in the art and will not be described in detail herein.

[0068] For details, please refer to Figure 5 , executing step S3, performing ion implantation on the top of the P-type base region 12 to form a source region 13, and the depth of the source region 13 is less than the height of the P-type base region 12.

[0069] like Figure 5 As shown, ion implantation is performed again on the top of the P-type base region 12 to form a source region 13. Specifically, a photoresist masking layer is formed again on the top surface of the P-type base region 12, and an implantation area for the source region 13 is reserved for N+ ion implantation. The implanted impurity ions of the N+ source region 13 are generally arsenic ions. After the implantation is completed, the photoresist masking layer is removed and diffusion is promoted to form the N+ source region 13. Among them, the N+ source region 13 is located in the P-type base region 12, and a certain distance needs to be reserved between the side of the N+ source region 13 and the side of the P-type base region 12, and the depth of the N+ source region 13 is less than the depth of the P-type base region 12.

[0070] Optionally, the doping concentration of the source region 13 includes 1×10 19 cm -3 ~1×10 20 cm -3 , for example, it can be 1×10 19 cm -3 , 1×10 19.5 cm -3 or 1×10 20 cm -3 .

[0071] Optionally, the implantation depth of the source region 13 includes 400-600nm, for example, 400nm, 500nm or 600nm. In this embodiment, the implantation depth of the N+ source region 13 can be controlled by controlling parameters such as implantation energy, implantation time and temperature in the ion implantation process, which is well known to those skilled in the art and will not be described in detail here.

[0072] For details, please refer to Figure 6 , executing step S4 to form a gate structure above the source region 13 , the gate structure comprising a gate oxide layer 14 located on the drift region 11 and a polysilicon gate 15 located on the gate oxide layer 14 .

[0073] Specifically, Figure 6As shown, a gate oxide layer 14 and a polysilicon gate 15 are formed on the top of the N-type drift region 11, the bottom of the gate oxide layer 14 is in contact with the top of the N-type drift region 11, the top of the P-type base region 12, and the top of the N+ source region 13, the polysilicon gate 15 is located above the gate oxide layer 14 and covers the gate oxide layer 14, and the gate oxide layer 14 and the polysilicon gate 15 constitute the gate structure. In addition, after the gate structure is formed, a planarization operation needs to be performed through a CMP process to obtain a better flatness of the upper surface of the obtained polysilicon gate 15, so as to provide a good process platform for the subsequent formation of an interlayer dielectric layer 16, so as to improve the quality of the interlayer dielectric layer 16 formed subsequently.

[0074] As an example, after forming the gate structure, a step of forming an interlayer dielectric layer 16 is further included, wherein the interlayer dielectric layer 16 covers the polysilicon gate 15 .

[0075] like Figure 7 As shown, in this embodiment, after the gate structure is formed, the center position of the gate structure is etched using an inductively coupled plasma etching process to serve as a working platform for the subsequent formation of the source contact hole 17. Specifically, a photoresist masking layer is formed on the top of the polysilicon gate 15, and an etching area for the source contact hole 17 is reserved. After the etching of the gate structure is completed, the photoresist masking layer is removed. Then, an interlayer dielectric layer 16 is formed on the top and sidewalls of the polysilicon gate 15. The interlayer dielectric layer 16 completely covers the polysilicon gate 15 and is attached to the gate oxide layer 14. The interlayer dielectric layer 16 can protect the polysilicon gate 15 from contacting the source metal layer 19, and can further protect the source region 13.

[0076] For details, please refer to Figure 8 , executing step S5 , etching the source region 13 to form a source contact hole 17 in the source region 13 .

[0077] like Figure 8 As shown, in this embodiment, after forming the gate structure and the interlayer dielectric layer 16, the center of the source region 13 is etched to form a source contact hole 17 as a subsequent source metal filling hole. Specifically, the source region 13 is etched using the photoresist masking layer for etching the gate structure as a mask, and the inductively coupled plasma etching process is continued to be used to etch the source region 13 to form a source contact hole 17 in the source region 13. The depth of the source contact hole 17 is less than the depth of the source region 13.

[0078] During the etching process, since the thickness of the polysilicon gate 15 is different from that of the source region 13, the etching rates of the polysilicon gate 15 and the source region 13 are also different, and ultimately the etching length of the polysilicon gate 15 in the lateral direction is greater than the etching length of the source region 13, thereby avoiding the generation of leakage current.

[0079] After the etching is completed, the photoresist masking layer is removed by an ashing process, and the top of the source region 13 is cleaned by dilute HCl and RCA, so as to remove the organic matter and oxide remaining on the top surface of the source region 13 .

[0080] Optionally, the lateral dimension of the source contact hole 17 is in the range of 900-1200 nm, for example, 900 nm, 1000 nm or 1200 nm.

[0081] Optionally, the source contact hole 17 extends in the source region 13 to a depth ranging from 150 to 250 nm, for example, 150 nm, 200 nm or 250 nm.

[0082] For details, please refer to Fig. 9 and Fig.10 , execute step S6, deposit an ohmic metal layer 18 and a source metal layer 19 in the source contact hole 17 in sequence, the ohmic metal layer 18 forms an ohmic contact with the source region 13, the source metal layer 19 fills the source contact hole 17 and covers the gate structure, and is connected to the ohmic metal layer 18.

[0083] As an example, the ohmic metal layer 18 can be made of titanium, nickel, platinum or other metals with good conductivity, which is not limited here, and the source metal layer 19 can be made of titanium, nickel, platinum or other metals with good conductivity, which is not limited here.

[0084] Specifically, Fig. 9 As shown, in this embodiment, after forming the interlayer dielectric layer 16, metal is deposited at the bottom of the source contact hole 17, and annealing is performed in a high-temperature inert gas atmosphere to form an ohmic metal layer 18, wherein the ohmic metal layer 18 covers the bottom of the source contact hole 17 and covers the sidewalls of the source contact hole 17. After forming the ohmic metal layer 18, a planarization operation is required to be performed through a CMP process so that the upper surface of the ohmic metal layer 18 is flush with the upper surface of the source, thereby providing a good process platform for the subsequent formation of the source metal layer 19. Since the doping concentration of the source region 13 is high, an ohmic contact is formed between the ohmic metal layer 18 and the source region 13.

[0085] Optionally, the method of forming the ohmic metal layer 18 includes magnetron sputtering or other suitable methods.

[0086] Specifically, Fig.10 As shown, in this embodiment, metal is continuously deposited on the gate structure to form a source metal layer 19 , wherein the source metal layer 19 fills the source contact hole 17 and covers the ohmic metal layer 18 and the interlayer dielectric layer 16 .

[0087] For details, please refer to Fig.11 , perform step S7 to thin the back side of the substrate 10 and deposit metal on the back side of the substrate 10 to form a drain metal layer 20 .

[0088] Specifically, Fig.11 As shown, in this embodiment, after forming the ohmic contact and the source metal layer 19, the back side of the substrate 10 is thinned to reduce the device's specific on-resistance, and then metal is deposited on the back side of the N-type drift region 11 to form a drain metal layer 20, and the drain metal layer 20 is thickened to form the drain of the device.

[0089] As an example, the drain metal layer 20 may be made of titanium, nickel, platinum or other metals with good conductivity, which is not limited here.

[0090] The embodiment of the present invention forms a source contact hole 17 above the source region 13 through an inductively coupled plasma etching process, so that the source contact hole 17 extends into the interior of the silicon carbide substrate 10, which can increase the contact area between the source region 13 and the source region metal layer 19, reduce the source contact resistance of the silicon carbide MOSFET structure, thereby reducing the on-resistance of the silicon carbide MOSFET structure, and ultimately reduce device losses.

[0091] Embodiment 2

[0092] like Fig.11 As shown, this embodiment provides a planar silicon carbide MOSFET structure, and the planar silicon carbide MOSFET structure at least includes: a substrate 10; a drift region 11, wherein the drift region 11 is arranged on the front side of the substrate 10 and covers the substrate 10; a P-type base region 12, wherein the P-type base region 12 is located in the drift region 11 and the depth of the P-type base region 12 is less than the depth of the substrate 10; a source region 13, wherein the source region 13 is located in the P-type base region 12 and the depth of the source region 13 is less than the depth of the P-type base region 12; a source contact hole 17, wherein the source contact hole 17 is located in the source region 13 and the source contact hole 17 is located in the source region 13. The depth of the extension in the region 13 is less than the depth of the source region 13; a gate structure, the gate structure includes a polysilicon gate 15, a gate oxide layer 14 and an interlayer dielectric layer 16, the interlayer dielectric layer 16 is located above the drift region 11 and covers the gate oxide layer 14 and the polysilicon gate 15; an ohmic metal layer 18, the ohmic metal layer 18 is located at the bottom of the source contact hole 17 and contacts the source region 13 to form an ohmic contact; a source metal layer 19, covering the gate structure, filling the source contact hole 17 and contacting the ohmic metal layer 18; a drain metal layer 20, the drain metal layer 20 is located on the back of the substrate 10.

[0093] As an example, the ohmic metal layer 18 is made of one or a combination of titanium, nickel or platinum, and the source metal layer 19 is made of one or a combination of titanium, nickel or platinum.

[0094] Specifically, in this embodiment, the material of the source metal layer 19 and the ohmic metal layer 18 can be metal Ni, or other metals or alloys. The material of the source metal layer 19 and the ohmic metal layer 18 can be the same or different, and the selection is made according to the actual application.

[0095] As an example, the doping concentration of the drift region 11 includes 5×10 15 cm -3 ~1×10 16 cm -3 .

[0096] The difference between the silicon carbide MOSFET structure in this embodiment and the conventional MOSFET is that the source contact hole 17 is etched downward, so that the contact area between the formed source metal layer 19 and the source region 13 is increased, thereby reducing the contact resistance of the source region 13, thereby reducing the on-resistance of the silicon carbide MOSFET structure.

[0097] In summary, the present invention provides a planar silicon carbide MOSFET structure and a preparation method thereof, wherein a source contact hole is formed above the source region by using an inductively coupled plasma etching process, so that the source contact hole extends toward the inside of the silicon carbide substrate, thereby increasing the contact area between the source region and the source region metal layer, reducing the source contact resistance of the silicon carbide MOSFET structure, thereby reducing the on-resistance of the silicon carbide MOSFET structure, and ultimately reducing device loss. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a planar silicon carbide MOSFET structure, characterized in that: The preparation method comprises the following steps: Providing a substrate, and forming a drift region on the front side of the substrate by an epitaxial process; Performing ion implantation at the top of the drift region to form a P-type base region, wherein the depth of the P-type base region is less than the height of the drift region; Performing ion implantation on the top of the P-type base region to form a source region, wherein the depth of the source region is less than the height of the P-type base region; forming a gate structure above the source region, the gate structure comprising a gate oxide layer located on the drift region and a polysilicon gate located on the gate oxide layer; Etching the source region to form a source contact hole in the source region; An ohmic metal layer and a source metal layer are sequentially deposited in the source contact hole, the ohmic metal layer forms an ohmic contact with the source region, the source metal layer fills the source contact hole and covers the gate structure, and is connected to the ohmic metal layer; The back side of the substrate is thinned, and metal is deposited on the back side of the substrate to form a drain metal layer.

2. The method for preparing a planar silicon carbide MOSFET structure according to claim 1, characterized in that: The doping concentration of the P-type base region includes 1×10 17 cm -3 ~1×10 18 cm -3 , the implantation depth of the P-type base region is 900 to 1200 nm.

3. The method for preparing a planar silicon carbide MOSFET structure according to claim 1, characterized in that: The doping concentration of the source region includes 1×10 19 cm -3 ~1×10 20 cm -3 , the injection depth of the source region includes 400 to 600 nm.

4. The method for preparing a planar silicon carbide MOSFET structure according to claim 1, characterized in that: The lateral dimension of the source contact hole is in the range of 900-1200 nm, and the depth of the source contact hole extending in the source region is in the range of 150-250 nm.

5. The method for preparing a planar silicon carbide MOSFET structure according to claim 1, characterized in that: After forming the polysilicon gate, the method further includes forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the polysilicon gate.

6. The method for preparing a planar silicon carbide MOSFET structure according to claim 4, characterized in that: The types of ions implanted when forming the P-type base region include one or more of aluminum ions and boron ions.

7. The method for preparing a planar silicon carbide MOSFET structure according to claim 1, characterized in that: The process for etching the polysilicon gate, the gate oxide layer and the source region is an inductively coupled plasma etching process.

8. A planar silicon carbide MOSFET structure, characterized in that: The planar silicon carbide MOSFET structure at least includes: substrate; A drift region, wherein the drift region is disposed on the front surface of the substrate and covers the substrate; A P-type base region, wherein the P-type base region is located in the drift region and has a depth less than a depth of the substrate; A source region, wherein the source region is located in the P-type base region and the depth of the source region is less than the depth of the P-type base region; a source contact hole, wherein the source contact hole is located in the source region, and the depth of the source contact hole extending in the source region is less than the depth of the source region; A gate structure, the gate structure comprising a polysilicon gate, a gate oxide layer and an interlayer dielectric layer, the interlayer dielectric layer being located above the drift region and covering the gate oxide layer and the polysilicon gate; an ohmic metal layer, the ohmic metal layer being located at the bottom of the source contact hole and contacting the source region to form an ohmic contact; a source metal layer, covering the gate structure, filling the source contact hole and contacting the ohmic metal layer; A drain metal layer is located on the back of the substrate.

9. The planar silicon carbide MOSFET structure according to claim 8, characterized in that: The ohmic metal layer is made of one or a combination of titanium, nickel or platinum, and the source metal layer is made of one or a combination of titanium, nickel or platinum.

10. The planar silicon carbide MOSFET structure according to claim 8, characterized in that: The doping concentration of the drift region includes 5×10 15 cm -3 ~1×10 16 cm -3 .

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