Groove type silicon carbide device and preparation method thereof

Abstract

According to the trench type silicon carbide device and the preparation method thereof, trench type source electrode and gate electrode trench steps are introduced into the trench type silicon carbide device, and gate-drain capacitance is converted into a form that gate-source and drain-source capacitors are connected in series, so that the on-resistance of the silicon carbide device is not increased too much; the gate-drain capacitance is obviously reduced, the switching speed of the device is improved, the switching loss is reduced, meanwhile, the gate oxide protection region at the bottom of the trench can shield the electric field intensity in the gate oxide, protect the gate oxide and avoid gate oxide breakdown, so that the device is prevented from being broken down and burnt out too early, and the reliability of the device is improved. Besides, the device structure and the preparation method are simple, and the effect is remarkable, so that preparation and production of high-performance and batch groove type silicon carbide devices can be realized, and the device has huge market potential and wide application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor component production, and in particular to a trench type silicon carbide device and a preparation method thereof. Background Art

[0002] As a third-generation wide bandgap semiconductor material, silicon carbide has a high critical breakdown electric field, high thermal conductivity, high electron saturation drift rate, and strong radiation resistance, making it a mainstream power device material for high-voltage, high-temperature, high-frequency, and radiation-resistant applications. Trench-type silicon carbide devices have received extensive attention due to their low on-resistance and small parasitic capacitance, but the high electric field in the gate oxide at the bottom of the trench can easily cause gate oxide breakdown, leading to device failure. By ion implantation at the bottom of the trench gate to form a P + The gate oxide protection zone can shield the electric field, protect the gate oxide, and improve the withstand voltage. This method has been widely used in the design and optimization of trench silicon carbide devices. At present, the optimization of trench devices mainly focuses on reducing the on-resistance and gate-drain capacitance without the gate oxide bearing high electric fields, thereby reducing losses. However, there is a trade-off between on-resistance and gate-drain capacitance. The material advantages of silicon carbide make silicon carbide devices more suitable for high-frequency applications. Therefore, reducing the gate-drain capacitance to reduce the dynamic power consumption of the device in high-frequency applications without increasing the on-resistance too much is still a problem. Summary of the invention

[0003] Purpose of the invention: The present invention aims to provide a trench silicon carbide device and a method for preparing the same which can significantly reduce the gate-drain capacitance without increasing the on-resistance too much.

[0004] Technical solution: A trench-type silicon carbide device proposed in the present invention comprises a substrate, a buffer layer located on the upper surface of the substrate, a first epitaxial layer located on the upper surface of the buffer layer, a second epitaxial layer located on the upper surface of the first epitaxial layer, a source region located on the upper surface of the second epitaxial layer, a gate trench, a source trench, a gate oxide protection region, and a gate trench step;

[0005] The gate trench is located at the center of the first epitaxial layer, the second epitaxial layer and the source region, and the source trench is located outside the first epitaxial layer, the second epitaxial layer and the source region; the gate oxide protection zone is located at the bottom of the gate trench; a gate trench step is formed at the bottom of the gate trench; the outermost periphery of the inner space of the gate trench and the top of the gate oxide protection zone are covered with a dielectric layer, the polysilicon layer is filled in the gate trench, and the outer side and bottom of the polysilicon layer are surrounded by the dielectric layer; the upper surface of the polysilicon layer is covered with a passivation layer; the bottom of the source trench is provided with a buried bottom contact zone, and the inner side of the source trench is provided with a buried bottom contact zone. The wall is provided with a buried layer side wall contact area; the top of the source area, the outer surface of the buried layer side wall contact area, and the top of the buried layer bottom contact area are all covered with a source ohmic contact layer; a recessed gate window is provided at the center of the passivation layer for placing a gate electrode, and the gate electrode is in contact with the upper surface of the polysilicon layer, and recessed source windows are provided on both sides of the passivation layer for placing a source electrode, and the source electrode is in contact with the surface of the source ohmic contact layer; a drain ohmic contact layer is provided on the lower surface of the substrate, and a drain electrode is provided on the lower surface of the drain ohmic contact layer.

[0006] Preferably, the substrate, buffer layer, first epitaxial layer, source region and polysilicon layer are of the first doping type; the second epitaxial layer, gate oxide protection region, buried layer bottom contact region and buried layer sidewall contact region are of the second doping type.

[0007] Preferably, the depth of the second epitaxial layer is 0.5-0.8 μm, and the doping concentration is 1e17-5e17 cm -3 ; The source region has a depth of 0.2-0.4 μm, a width of 6.0-6.8 μm, and a doping concentration of 1e19-1e20 cm -3 The gate trench has a width of 3.5 to 4.5 μm and a depth of 1.2 to 2.2 μm; the gate trench step has a single-side width of 0.1 to 0.2 μm and a depth of 0.1 to 0.25 μm; the source trench has a width of 2.2 to 2.5 μm and a depth the same as the gate trench (106); the gate oxide protection zone has a depth of 0.5 to 0.8 μm and a doping concentration of 8e18 to 1e20 cm -3 .

[0008] Preferably, the depth of the bottom contact area of ​​the buried layer is 0.7-1.1 μm; the width of the sidewall contact area of ​​the buried layer is 0.3-0.6 μm, and the doping concentration is 1e19-1e20 cm -3 ; The thickness of the dielectric layer is 40 to 60 nm.

[0009] A method for preparing a trench-type silicon carbide device, characterized in that it comprises the following steps:

[0010] S1: forming the buffer layer on the upper surface of the substrate;

[0011] S2: forming the first epitaxial layer on the upper surface of the buffer layer;

[0012] S3: forming the second epitaxial layer on the upper surface of the first epitaxial layer;

[0013] S4: forming the source region on the upper surface of the second epitaxial layer;

[0014] S5: etching the source region, the second epitaxial layer and the first epitaxial layer to obtain the gate trench and the source trench;

[0015] S6: forming a gate oxide protection zone in the gate trench;

[0016] S7: etching the source region, the second epitaxial layer and the first epitaxial layer to obtain the gate trench step;

[0017] S8: forming the buried layer bottom contact region and the buried layer sidewall contact region in the source trench;

[0018] S9: forming the dielectric layer on the sidewalls of the gate trench, the gate trench step and the upper surface of the gate oxide protection zone;

[0019] S10: filling the polysilicon layer on the upper surface of the dielectric layer in the gate trench and the gate trench step;

[0020] S11: forming the passivation layer on the upper surface of the polysilicon layer and the source region, and forming the source window on both sides of the passivation layer;

[0021] S12: forming a source ohmic contact layer in the source window, and forming a drain ohmic contact layer on the lower surface of the substrate;

[0022] S13: etching the center of the passivation layer to obtain the gate window, exposing the polysilicon layer region;

[0023] S14: forming the gate electrode in the gate window, forming the source electrode on the upper surface of the source ohmic contact layer, and forming the drain electrode on the lower surface of the drain ohmic contact layer.

[0024] Preferably, in step 5, an etching mask layer is grown on the surface of the source region by a chemical vapor deposition process; a photoresist is coated on the surface of the etching mask layer and patterned to obtain a patterned photoresist layer; the etching mask layer is subjected to reactive ion etching according to the patterned photoresist layer to form a patterned etching mask layer; the patterned photoresist layer is removed, and the source region, the second epitaxial layer and the first epitaxial layer are subjected to inductively coupled plasma etching according to the patterned etching mask layer to form a gate trench and a source trench; the patterned etching mask layer is removed; and a high-temperature passivation treatment is performed to modify the morphology of the gate trench and the source trench.

[0025] Preferably, in step 7, an etching mask layer is grown on the surface of the source region by a chemical vapor deposition process; a photoresist is coated on the surface of the etching mask layer and patterned to obtain a patterned photoresist layer; the etching mask layer is subjected to reactive ion etching according to the patterned photoresist layer to form a patterned etching mask layer; the patterned photoresist layer is removed, and the source region, the second epitaxial layer and the first epitaxial layer are subjected to inductively coupled plasma etching according to the patterned etching mask layer to form a gate wide trench, and the etching depth of the gate wide trench becomes shallower to obtain a gate trench step; the patterned etching mask layer is removed; and a high-temperature passivation treatment is performed to modify the morphology of the gate trench step.

[0026] Preferably, step 8 specifically includes S81: forming an ion implantation mask layer on the surface of the source trench and the first epitaxial layer, coating the surface with photoresist, and performing patterning to obtain a patterned photoresist; S82: etching the ion implantation mask layer based on the patterned photoresist to form an ion implantation window; S83: removing the patterned photoresist, and vertically implanting aluminum ions into the first epitaxial layer based on the etched ion implantation mask layer to form a buried layer bottom contact area, and removing the etched ion implantation mask layer to obtain a buried layer bottom contact area; S84: forming an ion implantation mask layer on the side wall surface of the source trench; S85: similarly, obtaining a buried layer side wall contact area by obliquely implanting aluminum ions, and removing the etched ion implantation mask layer to obtain a buried layer side wall contact area.

[0027] Preferably, in step 9, a silicon dioxide layer is grown on the gate trench, the sidewalls of the gate trench step and the surface of the gate oxide protection area by a thermal oxidation process, and the silicon dioxide layer is annealed to form the dielectric layer.

[0028] Preferably, in step 10, a polysilicon layer is grown on the surface of the dielectric layer by low-pressure chemical vapor deposition, and the polysilicon layer and the dielectric layer are sequentially etched to remove excess polysilicon layer and dielectric layer outside the gate trench to expose the source region, and the remaining polysilicon layer is flush with the source region.

[0029] Beneficial effects: 1. The present invention forms a source trench by etching the source electrode, and forms a buried layer bottom contact area and a buried layer side wall contact area at the bottom and side wall of the source trench by ion implantation. The buried layer bottom contact area converts the capacitance of the gate electrode side wall and the drain electrode into a series connection of the gate-source capacitance and the drain-source capacitance through coupling, thereby greatly reducing the gate-drain capacitance; 2. The present invention introduces a gate trench step, so that the depletion area formed by the gate oxide protection area moves toward the center line of the device, and the interval with the depletion area formed by the second epitaxial layer becomes farther, thereby making the depletion area formed by the gate oxide protection area away from the path for electrons to transmit downward, and providing a wider path for electrons to pass through, thereby compensating for the increase in on-resistance caused by the buried layer bottom contact area and the buried layer side wall contact area; 3. Under the premise of maintaining a slightly increased on-resistance of the trench silicon carbide device, the gate-drain capacitance is significantly reduced, the switching speed of the device is improved, and the switching loss is reduced; 4. The sizes and doping concentrations of the second epitaxial layer and the source region selected by the present invention match each other, and the sizes of the gate / source grooves, gate groove steps, buried layer bottom contact areas, and buried layer sidewall contact areas are preferably selected, so that the present invention can be applied to a 1200V breakdown voltage level, meeting the requirement that the optimal threshold voltage is between 2-4V for system application needs, and achieving optimal device performance; 5. The device structure and preparation method of the present invention are simple, and the effect is significant, and can realize high-performance, batch-scale preparation and production of trench silicon carbide devices, and has huge market potential and broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic cross-sectional view of S2 of a trench silicon carbide device provided in an embodiment of the present invention;

[0031] Figure 2 A schematic cross-sectional view of S4 of a trench silicon carbide device provided in an embodiment of the present invention;

[0032] Figure 3 A schematic cross-sectional view of S5 of a trench silicon carbide device provided in an embodiment of the present invention;

[0033] Figure 4 A schematic cross-sectional view of S6 of a trench silicon carbide device provided in an embodiment of the present invention;

[0034] Figure 5 A schematic cross-sectional view of S7 of a trench silicon carbide device provided in an embodiment of the present invention;

[0035] Figure 6 A schematic cross-sectional view of S83 of a trench silicon carbide device provided in an embodiment of the present invention;

[0036] Figure 7 A schematic cross-sectional view of S84 of a trench silicon carbide device provided in an embodiment of the present invention;

[0037] Figure 8A schematic cross-sectional view of S85 of a trench silicon carbide device provided in an embodiment of the present invention;

[0038] Fig. 9 A schematic cross-sectional view of S9 of a trench silicon carbide device provided in an embodiment of the present invention;

[0039] Fig.10 A schematic cross-sectional view of S10 of a trench silicon carbide device provided in an embodiment of the present invention;

[0040] Fig.11 A schematic cross-sectional view of S11 of a trench silicon carbide device provided in an embodiment of the present invention;

[0041] Fig.12 A schematic cross-sectional view of S12 of a trench silicon carbide device provided in an embodiment of the present invention;

[0042] Fig.13 A schematic cross-sectional view of S13 of a trench silicon carbide device provided in an embodiment of the present invention;

[0043] Fig.14 A schematic cross-sectional view of S14 of a trench silicon carbide device provided in an embodiment of the present invention;

[0044] Fig.15 The present invention is a flow chart of a method for preparing a trench-type silicon carbide device.

[0045] Among them: 101, substrate; 102, buffer layer; 103, epitaxial layer; 104, second epitaxial layer; 105, source region; 106, gate trench; 107, source trench; 108, gate oxide protection area; 109, gate trench step; 110, buried layer bottom contact region; 111, buried layer sidewall contact region; 112, dielectric layer; 113, polysilicon layer; 114, passivation layer; 115, source window; 116, source ohmic contact layer; 117, drain ohmic contact layer; 118, gate window; 119, gate electrode; 120, source electrode; 121, drain electrode. DETAILED DESCRIPTION

[0046] like Fig.14As shown, the trench-type silicon carbide device structure of the present invention comprises: a heavily doped substrate 101 of a first doping type; a heavily doped buffer layer 102 of a first doping type, located on the upper surface of the substrate 101; a lightly doped first epitaxial layer 103 of a first doping type, located on the upper surface of the buffer layer 102; a lightly doped second epitaxial layer 104 of a second doping type, located on the upper surface of the first epitaxial layer 103; a heavily doped source region 105 of a first doping type, located on the upper surface of the second epitaxial layer 104; a gate trench 106, located in the first epitaxial layer 103, the second epitaxial layer 104 and the source region 105; a heavily doped gate oxide protection region 108 of a second doping type, located in the gate trench 106; a gate trench step 109, located in the first epitaxial layer 103, the second epitaxial layer 104 and the source region 105; a dielectric layer 112, located on the surface of the gate trench 106 and the gate trench step 109; a polysilicon layer 110 of a first doping type 13, the surface of the dielectric layer 112 filled in the gate trench 106 and the gate trench step 109; the source trench 107, located outside the first epitaxial layer 103, the second epitaxial layer 104 and the source region 105; the second doping type heavily doped buried layer bottom contact region 110 and the buried layer sidewall contact region 111, located in the source trench 107; the passivation layer 114, located between the source electrode 120 and the gate electrode 119, between the polysilicon layer 113 and the source region 106 surface; a source ohmic contact layer 116, located on the surfaces of a source region 106 of a first doping type, a buried bottom contact region 110 of a second doping type, and a sidewall contact region 111; a drain ohmic contact layer 117, located on the lower surface of the bottom of the substrate 101; a gate electrode 119, located on the upper surface of the polysilicon layer 113; a source electrode 120, located on the upper surface of the source ohmic contact layer 116; and a drain electrode, located on the lower surface of the drain ohmic contact layer 117.

[0047] The substrate 101, the buffer layer 102 and the source region 105 are heavily doped with the first doping type; the first epitaxial layer 103 is lightly doped with the first doping type; the second epitaxial layer 104 is lightly doped with the second doping type; the gate oxide protection area 108, the buried bottom contact area 110 and the buried sidewall contact area 111 are heavily doped with the second doping type; the polysilicon layer 113 is the first doping type; when the doping concentration is ≤1e17cm -3 Lightly doped, when the doping concentration is ≥1e18cm -3 Heavily doped.

[0048] The thickness of the buffer layer 102 is 0.5-1 μm, preferably 0.6-0.9 μm, and in this embodiment, 0.8 μm is selected. The first doping type is N-type, and the second doping type is P-type; in other embodiments, the first doping type may also be P-type, and the second doping type may be N-type.

[0049] The depth of the second epitaxial layer 104 of the second doping type is 0.5-0.8 μm, preferably 0.6-0.7 μm. In this embodiment, 0.6 μm is selected. The doping concentration of the second epitaxial layer 104 is 1e17-5e17 cm -3 , preferably 1e17~3e17cm -3 In this embodiment, 2e17cm -3 .

[0050] The depth of the first doping type source region 105 is 0.2-0.4 μm, preferably 0.2-0.3 μm, and in this embodiment, 0.2 μm is selected; the width of the source region 105 is 6.0-6.8 μm, preferably 6.0-6.4 μm, and in this embodiment, 6.2 μm is selected; the doping concentration of the source region 105 is 1e19-1e20 cm -3 , preferably 1e19~3e19cm -3 In this embodiment, 1e19cm -3 .

[0051] The width of the gate trench 106 is 3.5-4.5 μm, preferably 3.8-4.2 μm, and in the present embodiment, it is selected as 4.0 μm; the depth of the gate trench 106 is 1.2-2.2 μm, preferably 1.6-2.0 μm, and in the present embodiment, it is selected as 1.8 μm; the single-side width of the gate trench step 109 is 0.1-0.2 μm, preferably 0.15-0.2 μm, and in the present embodiment, it is selected as 0.2 μm; the depth of the gate trench step 109 is 0.1-0.25 μm, preferably 0.15-0.2 μm, and in the present embodiment, it is selected as 0.15 μm; the width of the source trench 107 is 2.2-2.5 μm, preferably 2.2-2.4 μm, and in the present embodiment, it is selected as 2.3 μm, and the depth is the same as that of the gate trench.

[0052] The depth of the second doping type gate oxide protection zone 108 is 0.5-0.8 μm, preferably 0.6-0.7 μm. In this embodiment, 0.7 μm is selected. The doping concentration of the gate oxide protection zone 108 is 8e18-1e20 cm -3 , preferably 8e18~2e19cm -3 In this embodiment, 1e19cm -3 .

[0053] The depth of the second doping type buried bottom contact region 110 is 0.7-1.1 μm, preferably 0.7-0.9 μm, and in this embodiment, 0.7 μm is selected; the width of the buried sidewall contact region 111 is 0.3-0.6 μm, preferably 0.3-0.4 μm, and in this embodiment, 0.3 μm is selected; the doping concentrations of the buried bottom contact region 110 and the buried sidewall contact region 111 are both 1e19-1e20 cm -3 , preferably 1e19~3e19cm -3 In this embodiment, 1e19cm -3 .

[0054] The dielectric layer 112 is located on the sidewalls and bottom of the gate trench 106 and the gate trench step 109 . The thickness of the dielectric layer is 40-60 nm, preferably 45-55 nm. In the present embodiment, 50 nm is selected.

[0055] It should be noted that the dielectric layer 112 utilizes a thermal oxidation process to grow a silicon dioxide layer on the surface of the gate trench 106, which can achieve excellent interface properties between the silicon dioxide layer and the gate trench 106, reduce the interface state density between the two, and is beneficial to improving the channel mobility of the gate trench 106, thereby reducing the on-resistance of the trench-type silicon carbide device.

[0056] like Fig.15 As shown, the method for preparing a trench-type silicon carbide device of the present invention comprises the following steps:

[0057] S1: forming a heavily doped buffer layer 102 of a first doping type on an upper surface of a heavily doped substrate 101 of a first doping type;

[0058] S2: forming a lightly doped first epitaxial layer 103 of a first doping type on the upper surface of the buffer layer 102;

[0059] S3: forming a lightly doped second epitaxial layer 104 of a second doping type on the upper surface of the first epitaxial layer 103;

[0060] S4: forming a heavily doped source region 105 of a first doping type on the upper surface of the second epitaxial layer 104;

[0061] S5: etching the source region 105, the second epitaxial layer 104 and the first epitaxial layer 103 to obtain a gate trench 106 and a source trench 107;

[0062] S6: forming a heavily doped gate oxide protection area 108 of a second doping type in the gate trench 106;

[0063] S7: etching the source region 105, the second epitaxial layer 104 and the first epitaxial layer 103 to obtain a gate trench step 109;

[0064] S8: forming a heavily doped buried layer bottom contact region 110 and a buried layer sidewall contact region 111 of a second doping type in the source trench 107;

[0065] S9: forming a dielectric layer 112 on the sidewalls of the gate trench 106 , the gate trench step 109 and the upper surface of the gate oxide protection area 108 ;

[0066] S10: filling a polysilicon layer 113 of a first doping type on the upper surface of the dielectric layer 112 in the gate trench 106 and the gate trench step 109;

[0067] S11: forming a passivation layer 114 on the upper surfaces of the polysilicon layer 113 and the source region 106, thereby forming a source window 115;

[0068] S12: forming a source ohmic contact layer 116 in the source window 115 and a drain ohmic contact layer 117 on the lower surface of the substrate 101;

[0069] S13: etching the passivation layer 114 to obtain a gate window 118 to expose the polysilicon layer region;

[0070] S14 : forming a gate electrode 119 in the gate window 118 , forming a source electrode 120 on the upper surface of the source ohmic contact layer 116 , and forming a drain electrode 121 on the lower surface of the drain ohmic contact layer 117 .

[0071] Figure 1 to Figure 14 They are schematic diagrams of the structure of the trench type silicon carbide device presented in each step of the method for preparing the trench type silicon carbide device of the present invention.

[0072] like Figure 1 As shown, it is a schematic diagram of the structure of forming a lightly doped first epitaxial layer of the first doping type on the upper surface of the substrate and the buffer layer, providing a heavily doped substrate 101 of the first doping type and a heavily doped buffer layer 102 of the first doping type, and forming a lightly doped first epitaxial layer 103 of the first doping type on the upper surface of the buffer layer 102. It should be noted that the role of the buffer layer 102 is to assist the first epitaxial layer 103 and the substrate 101 to better achieve concentration matching, which is beneficial to accurately control the doping concentration of the first epitaxial layer 103 during the growth process.

[0073] On the one hand, the material of the first epitaxial layer 103 and the material of the substrate 101 can be the same, for example, the material of the substrate 101 and the material of the first epitaxial layer 103 are both one of 4H-silicon carbide, 6H-silicon carbide or 3C-silicon carbide; in the present embodiment, the material of the substrate 101 and the material of the first epitaxial layer 103 are both 4H-silicon carbide; further, in the present embodiment, the crystal orientation of the material of the substrate 101 is biased towards the (11-20) direction with an inclination angle of (4±0.5)°.

[0074] On the other hand, the material of the first epitaxial layer 103 can be different from the material of the substrate 101. For example, the material of the substrate 101 can be one of single crystal silicon, polycrystalline silicon, sapphire and gallium arsenide; the material of the first epitaxial layer 103 can be one of 4H-silicon carbide, 6H-silicon carbide or 3C-silicon carbide.

[0075] like Figure 2 As shown, it is a structural schematic diagram of forming a second epitaxial layer 104 lightly doped with the second doping type and a source region 105 heavily doped with the first doping type in the first epitaxial layer, a second epitaxial layer 104 lightly doped with the second doping type is formed in the upper surface of the first epitaxial layer 103, and a source region 105 heavily doped with the first doping type is formed on the upper surface of the epitaxial layer 104.

[0076] like Figure 3 , which is a schematic diagram of the structure of forming gate trenches and source trenches in the epitaxial layer and the source region, the source region 105, the second epitaxial layer 104 and the first epitaxial layer 103 are etched to obtain the gate trench 106 and the source trench 107, and the specific method is as follows:

[0077] An etching mask layer is grown on the surface of the second epitaxial layer and the source region, and a dense and uniform SiO2 film is grown by a chemical vapor deposition process (CVD) with a thickness of 0.8 to 1.5 μm, preferably 0.9 to 1.1 μm, and in this embodiment, 1.0 μm is selected; a photoresist is coated on the surface of the etching mask layer, and a photolithography process such as exposure, development and hardening is used to form a patterned photoresist layer; the etching mask layer is subjected to reactive ion etching (RIE) etching according to the patterned photoresist layer to form a patterned etching mask layer; the patterned photoresist layer is removed, and the epitaxial layer and the source region are subjected to inductively coupled plasma etching according to the patterned etching mask layer. Coupled Plasma (ICP) etching, the etching gas is a mixed gas of SF6 / O2, the flow ratio is 5:1-2:1, preferably 3:1-2:1, in this embodiment, 2:1 is selected, the total gas flow is 10-25 sccm, preferably 15-20 sccm, in this embodiment, 18 sccm is selected to form the gate trench 106 and the source trench 107; remove the patterned etching mask layer; perform high temperature passivation treatment on the epitaxial layer, the treatment temperature is 1400-1 700°C, preferably 1550~1650°C, in the present embodiment, 1600°C is selected, the processing atmosphere is one gas or a mixture of several gases selected from H2, SiH4, Ar, the processing time is 10~30min, preferably 15~25min, in the present embodiment, 22min is selected, the gas pressure is 50~100Torr, preferably 65~85Torr, in the present embodiment, 75Torr is selected, so as to modify the morphology of the gate trench 106 and the source trench 107.

[0078] It should be noted that the morphology modification of the gate trench 106 and the source trench 107 is performed by utilizing the micro-etching and atomic recombination mechanism of the surface of the gate trench 106 and the source trench 107 during the high-temperature passivation process. The modification purposes are as follows: first, it can eliminate etching damage and reduce the surface roughness of the gate trench 106, so as to improve the device channel carrier mobility; second, it can modify the shape of the formed gate trench 106 and the source trench 107 to achieve smooth bottom angles of the trenches, so as to reduce the electric field concentration effect at the bottom angles.

[0079] like Figure 4 , which is a schematic structural diagram of a heavily doped gate oxide protection zone of the second doping type formed in the gate trench, wherein a heavily doped gate oxide protection zone 108 of the second doping type is formed in the gate trench 106 .

[0080] It should be noted that after the heavily doped gate oxide protection zone 108 of the second doping type is formed in the obtained gate trench 106 by aluminum ion implantation, the implanted aluminum ions need to be subjected to a high temperature activation process to activate the implanted aluminum ions to form effective acceptor doping.

[0081] like Figure 5 , which is a schematic diagram of a structure in which a gate trench step is formed in an epitaxial layer and a source region. The source region 105, the second epitaxial layer 104 and the first epitaxial layer 103 are etched to obtain a gate trench step 109. The specific method is as follows:

[0082] An etching mask layer is grown on the surface of the source region, and a dense and uniform SiO2 film is grown by a chemical vapor deposition process, with a thickness of 0.8 to 1.5 μm, preferably 0.9 to 1.1 μm, and in this embodiment, 1.0 μm is selected; a photoresist is coated on the surface of the etching mask layer, and a photolithography process such as exposure, development and hardening is used to form a patterned photoresist layer; the etching mask layer is subjected to reactive ion etching according to the patterned photoresist layer to form a patterned etching mask layer; the patterned photoresist layer is removed, and a patterned etching mask layer is formed according to the patterned etching process. The mask layer is etched to perform inductively coupled plasma etching on the source region, the second epitaxial layer and the first epitaxial layer to form a gate wide trench, and the etching depth becomes shallower at the same time. The etching gas is a mixed gas of SF6 / O2, and the flow ratio is 5:1~2:1, preferably 3:1~2:1. In the present embodiment, 2:1 is selected. The total gas flow rate is 10~25sccm, preferably 15~20sccm. In the present embodiment, 18sccm is selected to form a gate trench step. The subsequent steps are the same as the steps after the gate trench is formed.

[0083] like Figure 6 , Figure 7 , Figure 8 , which is a schematic diagram of a structure of forming a heavily doped buried layer contact region of the second doping type in the source trench, and forming a heavily doped buried layer bottom contact region 110 and a buried layer sidewall contact region 111 of the second doping type in the obtained source trench 107. The specific method is as follows:

[0084] An ion implantation mask layer is formed on the surface of the source trench 107 and the first epitaxial layer 103, and a photoresist is coated on the surface and patterned to obtain a patterned photoresist; the ion implantation mask layer is etched based on the patterned photoresist to form an ion implantation window; the patterned photoresist is removed, and aluminum ions are vertically implanted into the first epitaxial layer based on the etched ion implantation mask layer to form a buried layer bottom contact region 110; the etched ion implantation mask layer is removed to obtain a buried layer bottom contact region; an ion implantation mask layer is formed on the side wall surface of the source trench 107; similarly, a buried layer side wall contact region 111 is obtained by oblique implantation of aluminum ions.

[0085] It should be noted that the buried layer bottom contact area 110 needs to be formed by a single vertical injection of aluminum ions, and the buried layer sidewall contact area 111 needs to be formed by two single-sided oblique injections of aluminum ions. After the contact area is formed, the injected aluminum ions need to be subjected to a high-temperature activation process to activate the injected aluminum ions to form effective acceptor doping.

[0086] like Fig. 9 , which is a schematic diagram of a structure in which a dielectric layer is formed in a gate trench and a source trench, a dielectric layer 112 is formed on the sidewalls of the gate trench 106, the gate trench step 109 and the upper surface of the gate oxide protection zone 108, and the specific method is as follows:

[0087] A silicon dioxide layer is grown on the surface of the buried layer bottom contact area 110, the buried layer sidewall contact area 111, the gate trench 106, the sidewall of the gate trench step 109 and the gate oxide protection area 108 by means of a thermal oxidation process, the thermal oxidation temperature is 1100-1300°C, preferably 1150-1200°C, and in the present embodiment, 1180°C is selected, and the oxidizing gas is O2 or a H2 / O2 mixed gas; the silicon dioxide layer is annealed in a gas atmosphere of N2O or NO, the annealing temperature is 1100-1250°C, preferably 1150-1200°C, and in the present embodiment, 1180°C is selected, and the annealing time is 30-60min, preferably 40-55min, and in the present embodiment, 45min is selected.

[0088] It should be noted that, by growing a silicon dioxide layer 112 on the surface of the gate trench 106 and the gate trench step 109 using a thermal oxidation process, excellent interface properties between the silicon dioxide layer 112 and the gate trench 106 and the gate trench step 109 can be achieved, and the interface state density between the two can be reduced, which is beneficial to improving the channel mobility of the gate trench 106 and the gate trench step 109, and further reducing the on-resistance of the trench-type silicon carbide device.

[0089] like Fig.10 As shown, it is a schematic diagram of a structure in which the upper surface of the dielectric layer in the gate trench and the gate trench step is filled with polysilicon of the first doping type, and the upper surface of the dielectric layer 112 in the gate trench 106 and the gate trench step 109 is filled with polysilicon 113 of the first doping type, and the specific method is as follows:

[0090] A first doped type polysilicon layer 113 is grown on the surface of the gate dielectric layer using an LPCVD process, with a growth temperature of 600-800°C, preferably 650-750°C, and in the present embodiment, 700°C is selected; the first doped type polysilicon layer 113 and the dielectric layer 112 are sequentially etched using an ICP etching process to remove the polysilicon layer 113 and the dielectric layer 112 outside the gate trench.

[0091] like Fig.11, which is a schematic diagram of a structure in which a source window is formed in a passivation layer. A passivation layer 114 is formed on the upper surfaces of the polysilicon layer 113 and the source region 105 , and a source window 115 is formed in the passivation layer.

[0092] On the one hand, the main function of the passivation layer 114 is to form a protective film on the device surface and overcome device surface defects, thereby enhancing the stability and reliability of the device. As an example, the material of the passivation layer 114 can be a composite layer of one or both of silicon dioxide and nitride.

[0093] On the other hand, the method of forming the source window 115 in the passivation layer 114 may be RIE etching or ICP etching, and the source window 115 exposes the source region 105 and the buried layer bottom contact region 110 .

[0094] like Fig.12 , which is a schematic structural diagram of forming a source ohmic contact layer 116 in a source window 115 and forming a drain ohmic contact layer 117 on the lower surface of the substrate.

[0095] like Fig.13 , which is a schematic structural diagram of forming a gate window 118 at a position corresponding to the polysilicon region in the passivation layer 114 .

[0096] As an example, the method of forming the gate window 118 may be RIE etching or ICP etching.

[0097] like Fig.14 As shown, it is a schematic diagram of the structure of a trench silicon carbide device according to an embodiment of the present invention, wherein a gate electrode 119 is formed in a gate window 118, a source electrode 120 is formed on the upper surface of the source ohmic contact layer 116, and a drain electrode 121 is formed on the lower surface of the drain ohmic contact layer 117.

[0098] The present invention forms a source trench 107 by etching the source electrode, and forms a buried bottom contact region 110 and a buried side wall contact region 111 on the side wall and bottom of the source trench 107 by ion implantation. The coupling effect of the buried bottom contact region 110 converts the capacitance of the gate side wall and the drain electrode into a series connection of the gate-source capacitance and the drain-source capacitance, thereby greatly reducing the gate-drain capacitance. Due to the presence of the buried bottom contact region 110 and the buried side wall contact region 111, the current path of the device during forward conduction is narrower than that of the traditional trench structure, and the on-resistance is significantly increased. Therefore, by introducing the gate trench step 109, the depletion region formed by the gate oxide protection region 108 moves toward the center line of the device, and the interval with the depletion region formed by the second epitaxial layer 104 becomes farther, thereby making the depletion region formed by the gate oxide protection region 108 away from the path for electrons to transmit downward, and providing a wider path for electrons to pass through, which significantly compensates for the increase in on-resistance caused by the buried bottom contact region 110 and the buried side wall contact region 111. Finally, under the premise of maintaining a slightly increased on-resistance of the trench silicon carbide device, the gate-drain capacitance is significantly reduced, the switching speed of the device is increased, and the switching loss is reduced. In addition, the device structure and preparation method of the present invention are simple and effective, so high-performance, batch-scale trench silicon carbide device preparation and production can be achieved, which has huge market potential and broad application prospects. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

Claims

1. A trench-type silicon carbide device, characterized in that: It comprises a substrate (101), a buffer layer (102) located on the upper surface of the substrate (101), a first epitaxial layer (103) located on the upper surface of the buffer layer (102), a second epitaxial layer (104) located on the upper surface of the first epitaxial layer (103), a source region (105) located on the upper surface of the second epitaxial layer (104), a gate trench (106), a source trench (107), a gate oxide protection region (108), and a gate trench step (109); The gate trench (106) is located at the central position of the first epitaxial layer (103), the second epitaxial layer (104) and the source region (105); the source trench (107) is located outside the first epitaxial layer (103), the second epitaxial layer (104) and the source region (105); the gate oxide protection zone (108) is located at the bottom of the gate trench (106); a gate trench step (109) is formed at the bottom of the gate trench (106); the outermost periphery of the inner space of the gate trench (106) and the top of the gate oxide protection zone (108) are covered with a dielectric layer (112); a polysilicon layer (113) is filled in the gate trench (106) and the outer side and bottom of the polysilicon layer (113) are surrounded by the dielectric layer (112); the upper surface of the polysilicon layer (113) is covered with a passivation layer (114); the bottom of the source trench (107) is provided with a buried bottom contact zone (110 ), a buried layer side wall contact region (111) is provided on the inner side wall of the source trench (107); the top of the source region (105), the outer surface of the buried layer side wall contact region (111), and the top of the buried layer bottom contact region (110) are all covered with a source ohmic contact layer (116); a recessed gate window (118) is provided at the center of the passivation layer (114) for accommodating a gate electrode (119), the gate electrode (119) is in contact with the upper surface of the polysilicon layer (113), recessed source windows (115) are provided on both sides of the passivation layer (114) for accommodating a source electrode (120), the source electrode (120) is in contact with the surface of the source ohmic contact layer (116); a drain ohmic contact layer (117) is provided on the lower surface of the substrate (101), and a drain electrode (121) is provided on the lower surface of the drain ohmic contact layer (117).

2. The trench silicon carbide device according to claim 1, characterized in that: The substrate (101), the buffer layer (102), the first epitaxial layer (103), the source region (105) and the polysilicon layer (113) are of a first doping type; the second epitaxial layer (104), the gate oxide protection region (108), the buried layer bottom contact region (110) and the buried layer sidewall contact region (111) are of a second doping type.

3. The trench silicon carbide device according to claim 2, characterized in that: The second epitaxial layer (105) has a depth of 0.5 to 0.8 μm and a doping concentration of 1e17 to 5e17 cm -3 The source region (106) has a depth of 0.2 to 0.4 μm, a width of 6.0 to 6.8 μm, and a doping concentration of 1e19 to 1e20 cm -3 The gate trench (106) has a width of 3.5 to 4.5 μm and a depth of 1.2 to 2.2 μm; the gate trench step (109) has a single-side width of 0.1 to 0.2 μm and a depth of 0.1 to 0.25 μm; the source trench (107) has a width of 2.2 to 2.5 μm and a depth the same as the gate trench (106); the gate oxide protection zone (108) has a depth of 0.5 to 0.8 μm and a doping concentration of 8e18 to 1e20 cm -3 .

4. The trench silicon carbide device according to claim 2, characterized in that: The depth of the buried layer bottom contact area (110) is 0.7-1.1 μm; the width of the buried layer sidewall contact area (111) is 0.3-0.6 μm, and the doping concentration is 1e19-1e20 cm -3 ; The thickness of the dielectric layer (112) is 40 to 60 nm.

5. A method for preparing a trench silicon carbide device according to any one of claims 1 to 4, characterized in that: The steps include: S1: forming the buffer layer (102) on the upper surface of the substrate (101); S2: forming the first epitaxial layer (103) on the upper surface of the buffer layer (102); S3: forming the second epitaxial layer (104) on the upper surface of the first epitaxial layer (103); S4: forming the source region (105) on the upper surface of the second epitaxial layer (104); S5: etching the source region (105), the second epitaxial layer (104) and the first epitaxial layer (103) to obtain the gate trench (106) and the source trench (107); S6: forming a gate oxide protection area (108) in the gate trench (106); S7: etching the source region (105), the second epitaxial layer (104) and the first epitaxial layer (103) to obtain the gate trench step (109); S8: forming the buried layer bottom contact region (110) and the buried layer sidewall contact region (111) in the source trench (107); S9: forming the dielectric layer (112) on the sidewalls of the gate trench (106), the gate trench step (109) and the upper surface of the gate oxide protection area (108); S10: filling the polysilicon layer (113) on the upper surface of the dielectric layer (112) in the gate trench (106) and the gate trench step (109); S11: forming the passivation layer (114) on the upper surfaces of the polysilicon layer (113) and the source region (106), and forming the source windows (115) on both sides of the passivation layer (114); S12: forming a source ohmic contact layer (116) in the source window (115), and forming a drain ohmic contact layer (117) on the lower surface of the substrate (101); S13: etching the center of the passivation layer (114) to obtain the gate window (118) to expose the polysilicon layer (113) region; S14: forming the gate electrode (119) in the gate window (118), forming the source electrode (120) on the upper surface of the source ohmic contact layer (116), and forming the drain electrode (121) on the lower surface of the drain ohmic contact layer (117).

6. The method for preparing a trench silicon carbide device according to claim 5, characterized in that: In the step 5, an etching mask layer is grown on the surface of the source region (105) by a chemical vapor deposition process; a photoresist is coated on the surface of the etching mask layer, and a patterning process is performed to obtain a patterned photoresist layer; Reactive ion etching is performed on the etching mask layer according to the patterned photoresist layer to form a patterned etching mask layer; the patterned photoresist layer is removed, and the source region (105), the second epitaxial layer (104) and the first epitaxial layer (103) are subjected to inductively coupled plasma etching according to the patterned etching mask layer to form a gate trench (106) and a source trench (107); the patterned etching mask layer is removed; and a high-temperature passivation treatment is performed to modify the morphology of the gate trench (106) and the source trench (107).

7. The method for preparing a trench silicon carbide device according to claim 5, characterized in that: In the step 7, an etching mask layer is grown on the surface of the source region (105) by a chemical vapor deposition process; a photoresist is coated on the surface of the etching mask layer, and a patterning process is performed to obtain a patterned photoresist layer; Reactive ion etching is performed on an etching mask layer according to a patterned photoresist layer to form a patterned etching mask layer; the patterned photoresist layer is removed, and inductively coupled plasma etching is performed on the source region (105), the second epitaxial layer (104) and the first epitaxial layer (103) according to the patterned etching mask layer to form a gate wide trench, wherein the etching depth of the gate wide trench becomes shallower to obtain a gate trench step (109); the patterned etching mask layer is removed; and a high temperature passivation treatment is performed to modify the morphology of the gate trench step (109).

8. The method for preparing a trench silicon carbide device according to claim 5, characterized in that: The step 8 specifically includes S81: forming an ion implantation mask layer on the surface of the source trench (107) and the first epitaxial layer (103), coating the surface with photoresist, and performing patterning to obtain a patterned photoresist; S82: etching the ion implantation mask layer according to the patterned photoresist to form an ion implantation window; S83: removing the patterned photoresist, vertically implanting aluminum ions into the first epitaxial layer (103) based on the etched ion implantation mask layer to form a buried layer bottom contact region (110), and removing the etched ion implantation mask layer to obtain a buried layer bottom contact region (110); S84: forming an ion implantation mask layer on the side wall surface of the source trench (107); S85: Similarly, aluminum ions are injected obliquely to obtain the buried layer sidewall contact region (111), and the ion injection mask layer after etching is removed to obtain the buried layer sidewall contact region (111).

9. The method for preparing a trench silicon carbide device according to claim 5, characterized in that: In step 9, a silicon dioxide layer is grown on the gate trench (106), the sidewalls of the gate trench step (109) and the surface of the gate oxide protection area (108) by a thermal oxidation process, and the silicon dioxide layer is annealed to form the dielectric layer (112).

10. The method for preparing a trench silicon carbide device according to claim 5, characterized in that: In the step 10, a polysilicon layer (113) is grown on the surface of the dielectric layer (112) by low-pressure chemical vapor deposition, and the polysilicon layer (113) and the dielectric layer (112) are sequentially etched to remove excess polysilicon layer (113) and dielectric layer (112) outside the gate trench (106), exposing the source region (105), and the remaining polysilicon layer (113) is flush with the source region (105).

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