Planar silicon carbide JFET device and preparation method thereof

Abstract

The invention provides a planar silicon carbide JFET (Junction Field Effect Transistor) device and a preparation method thereof. The planar silicon carbide JFET device is of a bilateral symmetry structure and is sequentially provided with a drain electrode, an N-type substrate and an N-type epitaxial layer from bottom to top. An N + source region and two P-type gate regions are arranged in the N-type epitaxial layer; the P-type gate regions are symmetrically arranged on the two sides along the upper surface of the N-type epitaxial layer, and the P-type gate regions form two symmetrical arc-shaped contact surfaces in the N-type epitaxial layer; the N + source region is arranged on the upper surface of the N-type epitaxial layer and is in contact with the two arc-shaped contact surfaces; a grid electrode is arranged on the upper surface of the N + source region, a source electrode is arranged in a partial region of the upper surface of the P-type grid region, and a channel region formed by the grid electrode and the source electrode is filled with a passivation layer; and the P-type gate region is formed by performing deep ion implantation by utilizing a channel effect. Compared with an original groove type JFET device, the planar silicon carbide JFET device has the advantages that the process steps are simplified and the manufacturing cost is reduced due to the fact that a groove does not need to be etched.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon carbide power devices, and in particular to a planar silicon carbide JFET device and a preparation method thereof. Background Art

[0002] In the field of power electronics, with the increasing demand for high efficiency, miniaturization and high temperature working environment, traditional silicon-based power devices are gradually unable to meet the requirements of modern applications. Silicon carbide (SiC), as a wide bandgap semiconductor material, has become an ideal choice for manufacturing power switching devices working under high voltage, high frequency and high temperature conditions due to its excellent physical properties, such as high breakdown electric field strength, high thermal conductivity and large bandgap width. In particular, in SiC JFET (junction field effect transistor), due to its inherent unipolar conduction mechanism, there is no minority carrier storage effect, thus achieving lower switching losses and higher switching speeds. In addition, SiC JFET does not require a gate oxide layer, which not only improves the reliability of the device, but also avoids the low mobility problem in traditional MOSFET, while being able to withstand higher current gain and operating temperature. Therefore, SiC JFET is considered to be a mature solution for high voltage power conversion applications.

[0003] In the design and manufacture of SiC JFET devices, according to their structural characteristics, they are mainly divided into two categories: trench type and planar type. The trench type SiC JFET forms a trench structure through a precise etching process, which effectively shortens the channel length, thereby reducing the on-resistance of the device and improving performance. This technical route has received widespread attention in early research because it has to some extent solved the high on-resistance problem caused by the long channel of traditional planar JFET. In contrast, although the planar SiC JFET avoids complex etching processes, its horizontal channel design often leads to a narrow and long channel, which not only increases the on-resistance, but also limits the miniaturization of the device cell structure, thereby affecting the overall performance and cost-effectiveness of the device.

[0004] Although trench SiC JFETs have shown significant advantages in performance improvement, their complex etching process not only increases production costs, but may also introduce additional reliability issues, such as etching damage, interface states, etc., which may affect the long-term stability and service life of the device. On the other hand, although the existing planar SiC JFET has the advantage of simple process, its inherent structural limitations, especially the high on-resistance caused by the narrow channel and the difficult-to-shrink cellular structure, limit its application potential in the field of high-performance, miniaturized power switching devices. Therefore, how to overcome the structural deficiencies while maintaining the simplicity of the planar JFET process has become a key issue that needs to be urgently addressed in the current development of SiC JFET technology. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a planar silicon carbide JFET device and a preparation method thereof.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a planar silicon carbide JFET device, wherein the planar silicon carbide JFET device is a bilaterally symmetrical structure, comprising:

[0008] Arranged from bottom to top: drain, N-type substrate and N-type epitaxial layer;

[0009] An N+ source region and two P-type gate regions are arranged inside the N-type epitaxial layer; the P-type gate regions are symmetrically arranged on both sides along the upper surface of the N-type epitaxial layer, and the P-type gate regions form two symmetrical arc-shaped contact surfaces inside the N-type epitaxial layer;

[0010] The N+ source region is disposed on the upper surface of the N-type epitaxial layer and is in contact with the two arc-shaped contact surfaces;

[0011] A gate is disposed on the upper surface of the N+ source region, a source is disposed on a portion of the upper surface of the P-type gate region, and a channel region formed by the gate and the source is filled with a passivation layer;

[0012] The P-type gate region is formed by deep ion implantation utilizing the channel effect.

[0013] Optionally, the P-type gate region includes: a P+ region and a P- region;

[0014] The concentration of P-type ions in the P+ region is greater than that in the P- region;

[0015] The P+ region is arranged on a side close to the upper surface of the N-type epitaxial layer.

[0016] Optionally, the P-type ion concentration in the P-type gate region is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the P-type gate region is 1.0 to 6.0 μm, and the junction depth of the P-type gate region is 2 μm to 3 μm;

[0017] The P-type ions are boron ions or aluminum ions.

[0018] Optionally, the N-type ion concentration in the N+ source region is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the N+ source region is 0.5 to 2.0 μm, and the junction depth of the N+ source region is 0.1 μm to 0.5 μm;

[0019] The N-type ions are nitrogen ions or phosphorus ions.

[0020] Optionally, the gate is a Ti / Ni / Al metal alloy.

[0021] Optionally, the passivation layer is SiO2 or SiN x。

[0022] In a second aspect, the present invention provides a method for preparing a planar silicon carbide JFET device, comprising:

[0023] S101, polishing and cleaning the N-type substrate;

[0024] S102, growing an N-type epitaxial layer on an N-type substrate;

[0025] S103, forming an N+ source region inside the N-type epitaxial layer by ion implantation, and forming a P-type gate region inside the N-type epitaxial layer by deep ion implantation using a channel effect;

[0026] S104, performing sacrificial oxidation on the surface of the N-type epitaxial layer using wet oxygen to form a sacrificial layer;

[0027] S105, removing the sacrificial layer and depositing a passivation layer;

[0028] S106, opening a window in the passivation layer to form a gate ohmic contact window and a source ohmic contact window;

[0029] S107, depositing metal in the gate ohmic contact window and the source ohmic contact window, and annealing to form a gate and a source;

[0030] S108, flipping the current planar silicon carbide JFET device, performing back metal processing, and forming a drain.

[0031] Optionally, the P-type ion concentration in the P-type gate region is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the P-type gate region is 1.0 to 6.0 μm, and the junction depth of the P-type gate region is 2 μm to 3 μm;

[0032] The P-type ions are boron ions or aluminum ions.

[0033] Optionally, the N-type ion concentration in the N+ source region is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the N+ source region is 0.5 to 2.0 μm, and the junction depth of the N+ source region is 0.1 μm to 0.5 μm;

[0034] The N-type ions are nitrogen ions or phosphorus ions.

[0035] The present invention provides a planar silicon carbide JFET device and a preparation method thereof. The planar silicon carbide JFET device is a bilaterally symmetrical structure, comprising: a drain, an N-type substrate and an N-type epitaxial layer arranged in sequence from bottom to top; an N+ source region and two P-type gate regions are arranged inside the N-type epitaxial layer; the P-type gate region is symmetrically arranged on both sides along the upper surface of the N-type epitaxial layer, and the P-type gate region forms two symmetrical arc-shaped contact surfaces inside the N-type epitaxial layer; the N+ source region is arranged on the upper surface of the N-type epitaxial layer and contacts the two arc-shaped contact surfaces; a gate is arranged on the upper surface of the N+ source region, a source is arranged on a part of the upper surface of the P-type gate region, and a passivation layer is filled in the channel region formed by the gate and the source; the P-type gate region is formed by deep ion implantation using the channel effect. The planar silicon carbide JFET device of the present invention does not require trench etching, so compared with the existing trench JFET device, the process steps are simplified and the manufacturing cost is reduced; compared with the existing planar JFET device, the present invention does not require secondary epitaxial growth, reducing the process complexity; secondly, since the planar silicon carbide JFET device of the present invention does not have a narrow and long channel, the on-resistance is reduced, and the gate-drain overlap capacitance is also reduced accordingly, thereby improving the performance of the planar silicon carbide JFET device; finally, since the present invention utilizes the channel effect to perform deep ion implantation to form a P-type gate region, it helps to alleviate electric field concentration and improves the reverse characteristics of the planar silicon carbide JFET device.

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic structural diagram of a planar silicon carbide JFET device provided in an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a process for preparing a planar silicon carbide JFET device provided in an embodiment of the present invention;

[0039] Figure 3 The schematic diagram of the structure of the planar silicon carbide JFET device corresponding to the S102 treatment is shown by way of example;

[0040] Figure 4 The schematic diagram of the structure of the planar silicon carbide JFET device corresponding to the S103 treatment is shown by way of example;

[0041] Figure 5 The schematic diagram of the structure of the planar silicon carbide JFET device corresponding to the S105 treatment is shown by way of example;

[0042] Figure 6The schematic diagram of the structure of the planar silicon carbide JFET device corresponding to the S107 treatment is shown by way of example;

[0043] Figure 7 The schematic structural diagram of the corresponding planar silicon carbide JFET device after S108 treatment is exemplarily shown. DETAILED DESCRIPTION

[0044] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0045] In order to simplify the process steps, reduce the manufacturing cost of a planar silicon carbide JFET device, and improve the performance of the planar silicon carbide JFET device, an embodiment of the present invention provides a planar silicon carbide JFET device. Figure 1 A schematic diagram of the structure of a planar silicon carbide JFET device provided in an embodiment of the present invention. Specifically, Figure 1 FIG. (a) is a cross-sectional view of a planar silicon carbide JFET device provided by an embodiment of the present invention, Figure 1 FIG. (b) is a three-dimensional diagram of a planar silicon carbide JFET device provided by an embodiment of the present invention. Figure 1 As shown, it includes: arranged in sequence from bottom to top: a drain 8, an N-type substrate 1 and an N-type epitaxial layer 2;

[0046] An N+ source region 4 and two P-type gate regions 3 are arranged inside the N-type epitaxial layer 2; the P-type gate regions 3 are symmetrically arranged on both sides along the upper surface of the N-type epitaxial layer 2, and the P-type gate regions 3 form two symmetrical arc-shaped contact surfaces inside the N-type epitaxial layer 2;

[0047] The N+ source region 4 is disposed on the upper surface of the N-type epitaxial layer 2 and is in contact with the two arc-shaped contact surfaces;

[0048] A gate electrode 6 is disposed on the upper surface of the N+ source region 4, a source electrode 7 is disposed on a portion of the upper surface of the P-type gate region 3, and a channel region formed by the gate electrode 6 and the source electrode 7 is filled with a passivation layer 5;

[0049] The P-type gate region 3 is formed by deep ion implantation utilizing the channel effect.

[0050] It should be noted that the channeling effect, also known as channeling, refers to the phenomenon that in crystalline materials, when injected ions or charged particles are incident along a direction in which the crystal atoms are arranged more sparsely or regularly (such as the direction of the main crystal axis of the crystal), they may collide less with the lattice atoms and thus be able to penetrate to a deeper position than expected.

[0051] Furthermore, the narrow channel structure of the planar SiC JFET is a major reason for its high on-resistance. The on-resistance is related to the length and width of the channel. The narrow channel increases the resistance when electrons pass through, thereby increasing the resistance. In the embodiment of the present invention, deep ion implantation is performed through the channel effect to form a P-type gate region. Without increasing the channel length, the conductivity of the material below the P-type gate region (from N-type to P-type) can be changed, effectively "shortening" the equivalent channel length on the electron flow path, thereby reducing the on-resistance. In addition, the cell structure of the existing planar SiC JFET is limited by the channel length and width, and it is difficult to further reduce it to achieve higher integration and smaller device size. The deep ion implantation technology used in the embodiment of the present invention does not rely on the physical size of the channel, but forms the gate region by changing the conductivity inside the material, which makes the design of the cell structure more flexible and can achieve a smaller size without sacrificing device performance.

[0052] The embodiment of the present invention proposes a planar silicon carbide JFET device, which eliminates the need for trench etching compared to the original trench JFET, and only requires deep ion implantation using the channel effect to form a channel. Compared to the original horizontal channel planar JFET, the device eliminates the need for secondary epitaxy, reduces the number of process steps, and reduces the cell size of the device due to the absence of a narrow channel. In addition, the planar silicon carbide JFET device in the embodiment of the present invention is a planar vertical device that combines the advantages of trench devices and planar devices, improves electron mobility, and reduces forward resistance compared to the original horizontal channel JFET.

[0053] Optionally, the P-type gate region 3 includes: a P+ region and a P- region;

[0054] The concentration of P-type ions in the P+ region is greater than that in the P- region;

[0055] The P+ region is arranged on a side close to the upper surface of the N-type epitaxial layer 2 .

[0056] Optionally, the P-type ion concentration in the P-type gate region 3 is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the P-type gate region 3 is 1.0 to 6.0 μm, and the junction depth of the P-type gate region 3 is 2 μm to 3 μm;

[0057] The P-type ions are boron ions or aluminum ions.

[0058] Optionally, the N-type ion concentration of the N+ source region 4 is 1×10 18 cm -3 ~1×10 20 cm -3, the width of the N+ source region 4 is 0.5 to 2.0 μm, and the junction depth of the N+ source region 4 is 0.1 μm to 0.5 μm;

[0059] The N-type ions are nitrogen ions or phosphorus ions.

[0060] Optionally, the gate 6 is a Ti / Ni / Al metal alloy.

[0061] The interface between the gate 6 and the P-type gate region 3 is a gate ohmic contact, the interface between the source 7 and the N+ source region 4 is a source ohmic contact; and the interface between the drain 8 and the N-type substrate 1 is a drain ohmic contact.

[0062] Optionally, the passivation layer 5 is made of SiO2 or SiN x。

[0063] It should be noted that, in the implementation of the present invention, the passivation layer 5 can be specifically used for metal masking.

[0064] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a planar silicon carbide JFET device. Figure 2 A schematic diagram of a process for preparing a planar silicon carbide JFET device provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, including:

[0065] S101 , polishing and cleaning the N-type substrate 1 .

[0066] S102 , growing an N-type epitaxial layer 2 on the N-type substrate 1 .

[0067] In this step, a 1-100 μm thick layer with a doping concentration of 1×10 14 cm -3 ~1×10 17 cm -3 The N-type epitaxial layer 2 is used as the drift region and channel region of the device. The thickness and doping concentration of the N-type epitaxial layer 2 are determined by the withstand voltage level of the device. The doping concentration and thickness of the N-type epitaxial layer 2 of a general 1200V planar SiC JFET device are 8×15 cm -3 , 9μm.

[0068] The doping ions of the N-type epitaxial layer 2 may be N (nitrogen), P (phosphorus) or other impurity ions that can form an N-type semiconductor. Figure 3 The schematic structural diagram of the corresponding planar silicon carbide JFET device after S102 treatment is exemplarily shown.

[0069] S103 , forming an N+ source region 4 inside the N-type epitaxial layer 2 by ion implantation, and forming a P-type gate region 3 inside the N-type epitaxial layer 2 by deep ion implantation using a channel effect.

[0070] On the basis of S102, a mask layer is grown on the N-type epitaxial layer 2 by CVD, and then the P-type gate region 3 is formed by coating, exposing, developing, etching the mask layer, stripping, and P-type ion implantation; then the N+ source region 4 is formed by N-type ion implantation. In particular, since the P-type gate region 3 requires deeper doping to form a channel, it is necessary to utilize deep ion implantation using the channel effect, and the implanted ion energy is between 100keV and 1MeV, with a typical value of 500keV. Since the deep ion implantation is from shallow to deep, the side of the P-type gate region 3 close to the device surface is a high-concentration P+ region, and the side close to the substrate is a low-concentration P- region. The cross-sectional contact morphology of the P- region of the P-type gate region 3 and the N-type epitaxial layer 2 will form an arc surface, which is the same as the general morphology formed by ion implantation in the direction of the main crystal axis using the channel effect. Correspondingly, Figure 4 The schematic structural diagram of the corresponding planar silicon carbide JFET device after S103 treatment is exemplarily shown.

[0071] It should be noted that the P-type ion concentration in the P-type gate region 3 is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the P-type gate region 3 is 1.0 to 6.0 μm, and the junction depth of the P-type gate region 3 is 2 μm to 3 μm;

[0072] The P-type ions are boron ions or aluminum ions.

[0073] The N-type ion concentration of the N+ source region 4 is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the N+ source region 4 is 0.5 to 2.0 μm, and the junction depth of the N+ source region 4 is 0.1 μm to 0.5 μm;

[0074] The N-type ions are nitrogen ions or phosphorus ions.

[0075] S104 , performing sacrificial oxidation on the surface of the N-type epitaxial layer 2 using wet oxygen to form a sacrificial layer.

[0076] S105 , removing the sacrificial layer and depositing a passivation layer 5 .

[0077] Correspondingly, Figure 5 The schematic structural diagram of the corresponding planar silicon carbide JFET device after S105 treatment is exemplarily shown.

[0078] S106 , opening windows in the passivation layer 5 to form a gate ohmic contact window and a source ohmic contact window.

[0079] S107 , depositing metal in the gate ohmic contact window and the source ohmic contact window, and annealing to form the gate 6 and the source 7 .

[0080] It should be noted that the source electrode 7 may be made of Ni metal.

[0081] Correspondingly, Figure 6 The schematic structural diagram of the corresponding planar silicon carbide JFET device after S107 treatment is exemplarily shown.

[0082] S108 , flipping the current planar silicon carbide JFET device over, performing back metal processing, and forming a drain 8 .

[0083] Correspondingly, Figure 7 The schematic structural diagram of the corresponding planar silicon carbide JFET device after S108 treatment is exemplarily shown.

[0084] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0085] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes of the above disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0086] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A planar silicon carbide JFET device, characterized in that: The planar silicon carbide JFET device has a bilaterally symmetrical structure, comprising: Arranged in order from bottom to top: a drain (8), an N-type substrate (1) and an N-type epitaxial layer (2); An N+ source region (4) and two P-type gate regions (3) are arranged inside the N-type epitaxial layer (2); the P-type gate regions (3) are symmetrically arranged on both sides along the upper surface of the N-type epitaxial layer (2), and the P-type gate regions (3) form two symmetrical arc-shaped contact surfaces inside the N-type epitaxial layer (2); An N+ source region (4) is arranged on the upper surface of the N-type epitaxial layer (2) and is in contact with the two arc-shaped contact surfaces; A gate electrode (6) is arranged on the upper surface of the N+ source region (4), a source electrode (7) is arranged on a part of the upper surface of the P-type gate region (3), and a channel region formed by the gate electrode (6) and the source electrode (7) is filled with a passivation layer (5); The P-type gate region (3) is formed by deep ion implantation utilizing the channel effect.

2. The planar silicon carbide JFET device according to claim 1, characterized in that: The P-type gate region (3) comprises: a P+ region and a P- region; The P-type ion concentration in the P+ region is greater than the P-type ion concentration in the P- region; The P+ region is arranged on a side close to the upper surface of the N-type epitaxial layer (2).

3. The planar silicon carbide JFET device according to claim 1 or 2, characterized in that: The P-type ion concentration in the P-type gate region (3) is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the P-type gate region (3) is 1.0 to 6.0 μm, and the junction depth of the P-type gate region (3) is 2 μm to 3 μm; The P-type ions are boron ions or aluminum ions.

4. The planar silicon carbide JFET device according to claim 1, characterized in that: The N-type ion concentration of the N+ source region (4) is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the N+ source region (4) is 0.5 to 2.0 μm, and the junction depth of the N+ source region (4) is 0.1 μm to 0.5 μm; The N-type ions are nitrogen ions or phosphorus ions.

5. The planar silicon carbide JFET device according to claim 1, characterized in that: The gate (6) is a Ti / Ni / Al metal alloy.

6. The planar silicon carbide JFET device according to claim 1, characterized in that: The passivation layer (5) is made of SiO2 or SiN x。 7. A method for preparing a planar silicon carbide JFET device, characterized in that: For preparing the planar silicon carbide JFET device according to any one of claims 1 to 6, comprising: S101, polishing and cleaning the N-type substrate (1); S102, growing an N-type epitaxial layer (2) on the N-type substrate (1); S103, forming an N+ source region (4) inside the N-type epitaxial layer (2) by ion implantation, and forming a P-type gate region (3) inside the N-type epitaxial layer (2) by deep ion implantation using a channel effect; S104, performing sacrificial oxidation on the surface of the N-type epitaxial layer (2) using wet oxygen to form a sacrificial layer; S105, removing the sacrificial layer and depositing a passivation layer (5); S106, opening windows in the passivation layer (5) to form a gate ohmic contact window and a source ohmic contact window; S107, depositing metal in the gate ohmic contact window and the source ohmic contact window, and annealing to form a gate (6) and a source (7); S108, flipping the current planar silicon carbide JFET device, performing back metal processing, and forming a drain (8).

8. The method for preparing a planar silicon carbide JFET device according to claim 7, characterized in that: The P-type ion concentration in the P-type gate region (3) is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the P-type gate region (3) is 1.0 to 6.0 μm, and the junction depth of the P-type gate region (3) is 2 μm to 3 μm; The P-type ions are boron ions or aluminum ions.

9. The method for preparing a planar silicon carbide JFET device according to claim 7, characterized in that: The N-type ion concentration of the N+ source region (4) is 1×10 18 cm -3 ~1×10 20 cm -3 , the width of the N+ source region (4) is 0.5 to 2.0 μm, and the junction depth of the N+ source region (4) is 0.1 μm to 0.5 μm; The N-type ions are nitrogen ions or phosphorus ions.

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