Chip and preparation and design method thereof, electronic equipment and circuit layout database

Abstract

The invention provides a chip, a preparation and design method thereof, electronic equipment and a circuit layout database, relates to the field of semiconductors, and can avoid short circuit of M vertical transistors connected in series. The chip comprises a standard unit, the standard unit comprises M vertical transistors which are connected in series and arranged in the X direction, a dielectric layer, and a power line and an output line which are arranged on the same layer and located on different wiring tracks, and M is an even number. In the Z direction perpendicular to the substrate, the vertical transistor comprises a first electrode, a grid electrode, a second electrode and a channel layer penetrating through the second electrode, the grid electrode and the first electrode which are sequentially arranged in a stacked mode. The first pole is located between the substrate and the grid electrode, the first pole of the ith vertical transistor and the first pole of the (i + 1) th vertical transistor are shared, and i is an odd number smaller than M. The dielectric layer comprises a first through hole and a second through hole which are staggered in the Y direction. The power line is electrically connected with the second electrode of the first vertical transistor through the first through hole, and the output line is electrically connected with the second electrode of the Mth vertical transistor through the second through hole.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a chip and its preparation and design methods, electronic equipment, and a circuit layout database. Background Art

[0002] With the development of integrated circuits, the characteristic size of transistors continues to shrink. The size of traditional lateral nanowire field-effect transistors has basically reached the process limit. It has been proven to be extremely difficult to further reduce the contacted poly pitch (CPP) of the pseudo gate, and it may lead to an increase in the resistance and capacitance of the transistor.

[0003] The source, gate, and drain of a vertical nanosheet field-effect transistor are arranged vertically, which reduces the space occupied horizontally and provides the possibility of further reducing the CPP. At the same time, it can also reduce the parasitic capacitance of the transistor, which is currently a hot topic in logic device research.

[0004] By combining vertical nanosheet transistors with other components, a basic logic gate circuit standard cell can be designed. However, based on the existing wiring design, when the standard cell includes an even number of N-type transistors in series or an even number of P-type transistors in series, without adding additional wiring tracks, the vertical nanosheet transistor that should be electrically connected to the power line and the vertical nanosheet transistor that should be electrically connected to the output line will be short-circuited. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a chip and its preparation and design methods, electronic equipment, and circuit layout database, which can avoid short circuit of M vertical transistors connected in series without adding additional wiring tracks.

[0006] In a first aspect, the present application provides a chip, which includes a standard unit arranged on a substrate, and the standard unit includes: M vertical transistors connected in series and arranged side by side along a first direction, where M is an even number. Along a second direction perpendicular to the substrate, the vertical transistor includes a first electrode, a gate, a second electrode, and a channel layer, and the first electrode, the gate, and the second electrode are stacked on the substrate in sequence, and the channel layer runs through the first electrode, the gate, and the second electrode. The first electrode is located between the substrate and the gate, and the first electrode of the i-th vertical transistor is shared with the first electrode of the i+1-th vertical transistor, where i is an odd number less than M. The standard unit also includes a dielectric layer covering the M vertical transistors; the dielectric layer is provided with a first through hole and a second through hole, and the first through hole and the second through hole are staggered in a third direction. The first direction is perpendicular to the second direction, and the first direction and the second direction are both perpendicular to the third direction. The standard unit also includes a power supply line and an output line arranged in the same layer and located on different wiring tracks; the power supply line is electrically connected to the second electrode of the first vertical transistor through the first through hole, and the output line is electrically connected to the second electrode of the M-th vertical transistor through the second through hole.

[0007] Different from the related art, in the related art, the first electrode of the vertical transistor is electrically connected to the power supply line through the first through hole, or the first electrode of the vertical transistor is electrically connected to the output line through the second through hole, and the second electrode of the vertical transistor is electrically connected to the series line through the second through hole.

[0008] In the present application, the first pole of the i-th vertical transistor and the first pole of the i+1-th vertical transistor are arranged on the substrate, and the two share the same conductive film layer, and there is no need to be electrically connected through a series wiring. In addition, the second pole of the first vertical transistor is electrically connected to the power wiring through a second through hole, and the second pole of the M-th vertical transistor is electrically connected to the output wiring through a second through hole. The power wiring and the output wiring are arranged on the same layer and are located on different wiring tracks. It can also be said that the power wiring and the output wiring are arranged on the same layer and are arranged at intervals along the third direction (the third direction, for the convenience of description, the third direction is used for description below). Wherein, i is an odd number less than M. Although the power wiring and the output wiring of the present application are located on different wiring tracks, since the solution of the present application does not need to set up a series wiring, it is possible to avoid short circuits of the M vertical transistors in series without adding additional wiring tracks.

[0009] In some possible implementations, the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in a third direction, so that the first through hole corresponding to the second pole of the first vertical transistor and the second through hole corresponding to the second pole of the Mth vertical transistor are staggered in the third direction, thereby achieving the goal of having the power line and the output line located on different wiring tracks.

[0010] In other possible implementations, the first vertical transistor and the Mth vertical transistor are not staggered in the third direction (or, in other words, are arranged opposite each other), but the first through hole and the second through hole are staggered in the third direction, thereby achieving the goal of having the power supply line and the output line located in different wiring tracks.

[0011] In some possible implementations, the dielectric layer is further provided with a first gate through hole and a second gate through hole, and the first gate through hole and the second gate through hole are staggered in the third direction. The standard unit also includes a first gate trace and a second gate trace located on different wiring tracks; the first gate trace is electrically connected to the gate of the i-th vertical transistor through the first gate through hole, and the second gate trace is electrically connected to the gate of the i+1-th vertical transistor through the second gate through hole. The first gate trace and the second gate trace are arranged on the same layer as the power trace and the output trace.

[0012] Optionally, the second gate line, the first gate line, the power line, and the output line are arranged in sequence along the third direction. The output line is located outside the power line and other lines, that is, compared with the power line and other lines, the output line is closest to the edge of the chip.

[0013] Alternatively, the second gate line, the first gate line, the output line, and the power line are arranged in sequence along the third direction. Among them, the power line is located outside the output line and other lines. It can also be said that compared with the output line and other lines, the power line is closest to the edge of the chip. In this way, multiple components in a standard cell (for example, multiple transistors in parallel in a standard cell) or multiple standard cells can share the power line.

[0014] In some possible implementations, if the second gate line, the power line, and the output line are arranged in sequence along the third direction, the first gate line and the power line share the same wiring track and are disconnected. If the second gate line, the output line, and the power line are arranged in sequence along the third direction, the first gate line and the power line share the same wiring track and are disconnected. In this way, the standard cell only needs to occupy 6 wiring tracks, which greatly reduces the size of the chip in the third direction and reduces the chip area.

[0015] In some possible implementations, the standard cell is a two-input NAND gate. M=2, the two vertical transistors connected in series include a first vertical transistor and a second vertical transistor, the power supply line includes a first power supply line, and the output line includes a first output line; the standard cell also includes a first transistor, a second transistor, a second power supply line, and a second output line. The gate of the first transistor is electrically connected to the gate of the first vertical transistor, the first electrode of the first transistor is electrically connected to the second power supply line, and the second electrode of the first transistor is electrically connected to the second output line. The gate of the second transistor is electrically connected to the gate of the second vertical transistor, the first electrode of the second transistor is electrically connected to the second power supply line, and the second electrode of the second transistor is electrically connected to the second output line. The second electrode of the first vertical transistor is electrically connected to the first power supply line through a first through hole, the first electrode of the first vertical transistor is shared with the first electrode of the second vertical transistor, and the second electrode of the second vertical transistor is electrically connected to the first output line through a second through hole.

[0016] For the first transistor and the second transistor connected in parallel, assuming that the first transistor and the second transistor are also vertical transistors, the first electrode of the first transistor can share the same conductive film layer with the first electrode of the second transistor, and the first electrode of the first transistor can be electrically connected to the power supply line (i.e., the second power supply line) through a through hole with the first electrode of the second transistor, thereby achieving electrical connection with the second voltage terminal. The second electrode of the first transistor and the second electrode of the second transistor are electrically connected to the output line (i.e., the second output line) through a through hole, respectively, thereby achieving electrical connection with the output terminal. The gate of the first transistor is electrically connected to the first gate line through the first gate through hole, and the gate of the second transistor is electrically connected to the second gate line through the second gate through hole.

[0017] For the first vertical transistor and the second vertical transistor connected in series, the first electrode of the first vertical transistor and the first electrode of the second vertical transistor share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode of the first vertical transistor and the first electrode of the second vertical transistor. The second electrode of the first vertical transistor is electrically connected to the power supply line (i.e., the first power supply line) through the second through hole, thereby achieving electrical connection with the first voltage terminal. The second electrode of the second vertical transistor is electrically connected to the output line (i.e., the first output line) through the second through hole, thereby achieving electrical connection with the output terminal. The gate of the first vertical transistor is electrically connected to the first gate line through the first gate through hole, and the gate of the second vertical transistor is electrically connected to the second gate line through the second gate through hole.

[0018] In some possible implementations, the first transistor and the first vertical transistor share the same gate, and the gate of the first transistor and the gate of the first vertical transistor are electrically connected to the first gate wiring through a first gate through hole. The second transistor and the second vertical transistor share the same gate, and the gate of the second transistor and the gate of the second vertical transistor are electrically connected to the second gate wiring through a second gate through hole. The first gate wiring and the output wiring are located in different wiring tracks; or the first gate wiring and the output wiring are located in the same wiring track and are disconnected.

[0019] Among them, the first gate through hole corresponding to the gate of the first vertical transistor and the second through hole corresponding to the second pole of the second vertical transistor do not need to be staggered in the third direction, so that the first gate wiring electrically connected to the gate of the first vertical transistor through the first gate through hole and the output wiring electrically connected to the second pole of the second vertical transistor through the second through hole are located on the same wiring track, thereby eliminating one wiring track, reducing the size of the chip in the third direction, and reducing the area occupied by the chip.

[0020] In some possible implementations, the standard cell is a two-input AND-NOR gate. M=2, the two vertical transistors connected in series include a first vertical transistor and a second vertical transistor, and the two vertical transistors connected in series include a third vertical transistor and a fourth vertical transistor. The second electrode of the second vertical transistor and the second electrode of the fourth vertical transistor are electrically connected to the power supply line through a first through hole; the first electrode of the second vertical transistor is shared with the first electrode of the first vertical transistor; the second electrode of the first vertical transistor and the second electrode of the third vertical transistor are electrically connected to the output line through a second through hole; the first electrode of the third vertical transistor is shared with the first electrode of the fourth vertical transistor.

[0021] For the first transistor, the second transistor, the third transistor, and the fourth transistor connected in parallel, the first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the third transistor, and the first electrode of the fourth transistor share the same conductive film layer. The second electrode of the first transistor and the second electrode of the second transistor are electrically connected to the output wiring through a through hole, and the second electrode of the third transistor and the second electrode of the fourth transistor are electrically connected to the power wiring through a through hole, thereby achieving electrical connection with the second voltage terminal. The gate of the second transistor and the gate of the third transistor are electrically connected to the first gate wiring through the first gate through hole, respectively, and the gate of the first transistor and the gate of the fourth transistor are electrically connected to the second gate wiring through the second gate through hole, respectively. Among them, the through hole corresponding to the second electrode of the first transistor and the through hole corresponding to the second electrode of the second transistor do not need to be staggered in the third direction, and the through hole corresponding to the second electrode of the third transistor and the through hole corresponding to the second electrode of the fourth transistor do not need to be staggered in the third direction.

[0022] For the first vertical transistor and the second vertical transistor connected in series, the first electrode of the first vertical transistor and the first electrode of the second vertical transistor share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode of the first vertical transistor and the first electrode of the second vertical transistor. For the third vertical transistor and the fourth vertical transistor connected in series, the first electrode of the third vertical transistor and the first electrode of the fourth vertical transistor share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode of the third vertical transistor and the first electrode of the fourth vertical transistor.

[0023] The second electrode of the first vertical transistor and the second electrode of the third vertical transistor are electrically connected to the output wiring through the second through hole, and the second electrode of the second vertical transistor and the second electrode of the fourth vertical transistor are electrically connected to the power wiring through the first through hole, so as to achieve electrical connection with the first voltage terminal. The second through hole corresponding to the second electrode of the first vertical transistor and the first through hole corresponding to the second electrode of the second vertical transistor are staggered in the third direction; the first through hole corresponding to the second electrode of the fourth vertical transistor and the second through hole corresponding to the second electrode of the third vertical transistor are staggered in the third direction.

[0024] The gate of the first vertical transistor and the gate of the fourth vertical transistor are electrically connected to the second gate wiring through the second gate through hole, and the gate of the second vertical transistor and the gate of the third vertical transistor are electrically connected to the first gate wiring through the first gate through hole.

[0025] In some possible implementations, when M is greater than 2, the standard unit also includes a conductive layer arranged between the vertical transistor and the dielectric layer, and the second electrode of the jth vertical transistor and the second electrode of the j+1th vertical transistor are electrically connected through the conductive layer; wherein j is an even number less than M.

[0026] For example, M=6, 6 vertical transistors are connected in series, i is 1, 3, 5, and j is 2, 4. Specifically, the second electrode of the first vertical transistor is electrically connected to the power supply line through the first through hole, the first electrode of the first vertical transistor and the first electrode of the second vertical transistor share the same conductive film layer, the second electrode of the second vertical transistor is electrically connected to the second electrode of the third vertical transistor through the conductive layer, the first electrode of the third vertical transistor and the first electrode of the fourth vertical transistor share the same conductive film layer, the second electrode of the fourth vertical transistor is electrically connected to the second electrode of the fifth vertical transistor through the conductive layer, the first electrode of the fifth vertical transistor and the first electrode of the sixth vertical transistor share the same conductive film layer, and the second electrode of the sixth vertical transistor is electrically connected to the output line through the second through hole.

[0027] In some possible implementations, the standard unit is a four-input NAND gate. M=4, and the four vertical transistors connected in series include a first vertical transistor, a second vertical transistor, a third vertical transistor, and a fourth vertical transistor. The second electrode of the first vertical transistor is electrically connected to the power supply line through a first through hole, and the second electrode of the fourth vertical transistor is electrically connected to the output line through a second through hole. The first electrode of the first vertical transistor is shared with the first electrode of the second vertical transistor, and the first electrode of the third vertical transistor is shared with the first electrode of the fourth vertical transistor. The second electrode of the second vertical transistor and the second electrode of the third vertical transistor are electrically connected through a conductive layer.

[0028] For the first transistor, the second transistor, the third transistor, and the fourth transistor connected in parallel, the first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the third transistor, and the first electrode of the fourth transistor share the same conductive film layer, and the first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the third transistor, and the first electrode of the fourth transistor are all electrically connected to the power supply wiring through a through hole, thereby achieving electrical connection with the second voltage terminal. The second electrode of the first transistor, the second electrode of the second transistor, the second electrode of the third transistor, and the second electrode of the fourth transistor are electrically connected to the output wiring through a through hole. The gate of the first transistor and the gate of the third transistor are electrically connected to the first gate wiring through a first gate through hole, and the gate of the second transistor and the gate of the fourth transistor are electrically connected to the second gate wiring through a second gate through hole.

[0029] For the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor connected in series, the first electrode of the first vertical transistor and the first electrode of the second vertical transistor share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode of the first vertical transistor and the first electrode of the second vertical transistor; the first electrode of the third vertical transistor and the first electrode of the fourth vertical transistor share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode of the third vertical transistor and the first electrode of the fourth vertical transistor.

[0030] The second pole of the first vertical transistor is electrically connected to the power supply line through the second through hole, thereby achieving electrical connection with the second voltage terminal. The second pole of the fourth vertical transistor is electrically connected to the output line through the second through hole, thereby achieving electrical connection with the output terminal. The standard cell also includes a conductive layer arranged between the vertical transistor and the dielectric layer, and the second pole of the second vertical transistor (i.e., the jth vertical transistor) and the second pole of the third vertical transistor (i.e., the j+1th vertical transistor) are electrically connected through the conductive layer. Wherein, the conductive layer is in direct contact with the second pole of the second vertical transistor and the second pole of the third vertical transistor, without the need for electrical connection through a through hole.

[0031] In a second aspect, the present application provides an electronic device, which includes a circuit board and the chip described in the first aspect, wherein the chip is arranged on the circuit board.

[0032] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0033] In a third aspect, the present application provides a method for preparing a chip, the chip includes a standard unit, and the method for preparing the standard unit includes: forming M vertical transistors in series and arranged side by side along a first direction on a substrate, M is an even number; along a second direction perpendicular to the substrate, the vertical transistor includes a first electrode, a gate, a second electrode, and a channel layer that runs through the second electrode, the gate, and the first electrode, which are stacked in sequence; the first electrode is located between the substrate and the gate, and the first electrode of the i-th vertical transistor is shared with the first electrode of the i+1-th vertical transistor, i is an odd number less than M. Forming a dielectric layer covering the M vertical transistors; the dielectric layer is provided with a first through hole and a second through hole, and the first through hole and the second through hole are staggered in a third direction; the first direction is perpendicular to the second direction, and the first direction and the second direction are both perpendicular to the third direction. Forming a power supply line and an output line on the same layer and located on different wiring tracks on the dielectric layer; the power supply line is electrically connected to the second electrode of the first vertical transistor through the first through hole, and the output line is electrically connected to the second electrode of the M-th vertical transistor through the second through hole.

[0034] In some possible implementations, forming channel layers of M vertical transistors includes: forming M channel layer middle patterns on a substrate; the channel layer middle patterns are arranged side by side along a first direction and are of equal length in a third direction. The M channel layer middle patterns are cut to obtain channel layers of M vertical transistors; along the third direction, the length of the channel layer is less than the length of the channel layer middle pattern; the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction.

[0035] In some possible implementations, the dielectric layer is further provided with a first gate through hole and a second gate through hole, and the first gate through hole and the second gate through hole are staggered in the third direction. The standard unit also includes a first gate trace and a second gate trace located on different wiring tracks; the first gate trace is electrically connected to the gate of the i-th vertical transistor through the first gate through hole, and the second gate trace is electrically connected to the gate of the i+1-th vertical transistor through the second gate through hole. The first gate trace and the second gate trace are arranged on the same layer as the power trace and the output trace.

[0036] In some possible implementations, the second gate wiring, the power wiring, and the output wiring are sequentially arranged along the third direction; the first gate wiring and the power wiring share the same wiring track and are disconnected. Alternatively, the second gate wiring, the output wiring, and the power wiring are sequentially arranged along the third direction; the first gate wiring and the output wiring share the same wiring track and are disconnected.

[0037] In some possible implementations, when M is greater than 2, after forming M vertical transistors connected in series and arranged side by side along a first direction on a substrate, and before forming a dielectric layer covering the M vertical transistors, the preparation method also includes: forming a conductive layer; the second electrode of the jth vertical transistor and the second electrode of the j+1th vertical transistor are electrically connected through the conductive layer; wherein j is an even number less than M.

[0038] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0039] In a fourth aspect, the present application provides a circuit layout database, characterized in that it includes a plurality of standard cells, each of which includes a layout and a circuit diagram of the standard cell; the standard cell includes M vertical transistors connected in series, where M is an even number. The layout of the standard cell includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer stacked in sequence. The first layer includes one or more first sublayers arranged side by side along a first direction, and the first electrode of the i-th vertical transistor and the first electrode of the i+1-th vertical transistor share the same first sublayer, where i is an odd number less than M. The second layer includes the gates of the M vertical transistors, and the third layer includes the second electrodes of the M vertical transistors. The fourth layer includes a first through hole and a second through hole, and the first through hole and the second through hole are staggered in a third direction; wherein, in the layout, the first direction is perpendicular to the third direction. The fifth layer includes a power supply line and an output line located on different wiring tracks; the power supply line coincides with the first through hole and the second electrode of the first vertical transistor, and the output line coincides with the second through hole and the second electrode of the M-th vertical transistor.

[0040] In some possible implementations, the channel layers of the M vertical transistors are located in the first layer, the second layer, and the third layer, and a single channel layer runs through the second electrode, the gate electrode, and the first electrode of the vertical transistor in which it is located; wherein the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction. Alternatively, the layout of the standard cell also includes a sixth layer located between the third layer and the fourth layer, and the sixth layer includes the channel layers of the M vertical transistors; wherein the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction.

[0041] In some possible implementations, the fourth layer further includes a first gate through hole and a second gate through hole, and the first gate through hole and the second gate through hole are staggered in the third direction. The fifth layer further includes a first gate trace and a second gate trace located on different wiring tracks; the first gate trace overlaps with the first gate through hole and the gate of the i-th vertical transistor, and the second gate trace overlaps with the second gate through hole and the gate of the i+1-th vertical transistor.

[0042] In some possible implementations, the second gate wiring, the power wiring, and the output wiring are sequentially arranged along the third direction; the first gate wiring and the power wiring share the same wiring track and are disconnected. Alternatively, the second gate wiring, the output wiring, and the power wiring are sequentially arranged along the third direction; the first gate wiring and the output wiring share the same wiring track and are disconnected.

[0043] In some possible implementations, the circuit layout database also includes layer information, and the layer information includes graphic border information, graphic fill information, and graphic color information of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

[0044] The fourth aspect and any implementation of the fourth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0045] In a fifth aspect, the present application provides a chip design method, comprising: receiving a target instruction; in response to the target instruction, calling one or more standard cells in the circuit layout database of the fourth aspect to design another circuit layout using the one or more standard cells.

[0046] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0047] In a sixth aspect, the present application provides a layout design method, including: obtaining a circuit diagram of a standard cell; the standard cell includes M vertical transistors connected in series, M being an even number. According to the circuit diagram, a layout of the standard cell is drawn; the layout drawing method of the standard cell includes: drawing a first layer, the first layer includes one or more first sublayers arranged side by side along a first direction, the first electrode of the i-th vertical transistor and the first electrode of the i+1-th vertical transistor share the same first sublayer, i being an odd number less than M. Drawing a second layer and a third layer in sequence, the second layer includes the gates of the M vertical transistors, and the third layer includes the second electrodes of the M vertical transistors. Drawing a fourth layer, the fourth layer includes a first through hole and a second through hole, the first through hole and the second through hole are staggered in a third direction; wherein, in the layout, the first direction is perpendicular to the third direction. Drawing a fifth layer, the fifth layer includes a power supply line and an output line located on different wiring tracks; the power supply line coincides with the first through hole and the second electrode of the first vertical transistor, and the output line coincides with the second through hole and the second electrode of the M-th vertical transistor.

[0048] In some possible implementations, the channel layers of the M vertical transistors are located in the first layer, the second layer, and the third layer, and a single channel layer runs through the second electrode, the gate electrode, and the first electrode of the vertical transistor in which it is located; wherein the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction. Alternatively, after drawing the third layer and before drawing the fourth layer, the layout design method further includes: drawing a sixth layer, the sixth layer including the channel layers of the M vertical transistors; wherein the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction.

[0049] In some possible implementations, the fourth layer further includes a first gate through hole and a second gate through hole, and the first gate through hole and the second gate through hole are staggered in the third direction. The fifth layer further includes a first gate trace and a second gate trace located on different wiring tracks; the first gate trace overlaps with the first gate through hole and the gate of the i-th vertical transistor, and the second gate trace overlaps with the second gate through hole and the gate of the i+1-th vertical transistor.

[0050] In some possible implementations, the second gate wiring, the power wiring, and the output wiring are sequentially arranged along the third direction; the first gate wiring and the power wiring share the same wiring track and are disconnected. Alternatively, the second gate wiring, the output wiring, and the power wiring are sequentially arranged along the third direction; the first gate wiring and the output wiring share the same wiring track and are disconnected.

[0051] In some possible implementations, after drawing the layout of the standard cell according to the circuit diagram, the layout design method further includes: storing the layout and layer information of the standard cell in a circuit layout database.

[0052] In some possible implementations, the layer information includes graphic border information, graphic fill information, and graphic color information of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

[0053] The sixth aspect and any implementation of the sixth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the sixth aspect and any implementation of the sixth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0054] In a seventh aspect, the present application provides a circuit layout design device, comprising: a memory and a processor, wherein the memory is electrically connected to the processor. The memory stores program instructions, and when the program instructions are executed by the processor, the electronic device executes the chip design method described in the fifth aspect.

[0055] The seventh aspect and any implementation of the seventh aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the seventh aspect and any implementation of the seventh aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0056] In an eighth aspect, the present application provides a computer-readable storage medium, comprising a computer program, characterized in that when the computer program is run on an electronic device, the electronic device executes the chip design method described in the fifth aspect.

[0057] The eighth aspect and any implementation of the eighth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the eighth aspect and any implementation of the eighth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0058] In a ninth aspect, the present application provides a computer program product, characterized in that when the computer program product is run on a computer, the computer is enabled to execute the chip design method as described in the fifth aspect.

[0059] The ninth aspect and any implementation of the ninth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the ninth aspect and any implementation of the ninth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a top view of a standard unit composed of Finfet;

[0061] Figure 2 The structural development process of lateral nanosheet transistors;

[0062] Figure 3 The development process from lateral nanosheet transistors to vertical nanosheet transistors;

[0063] Figure 4 A three-dimensional diagram of a vertical nanosheet transistor is provided for an embodiment of the present application;

[0064] Figure 5 A layout of two vertical transistors arranged opposite to each other;

[0065] Figure 6a A perspective view of a standard cell including two transistors in series is provided for the related art;

[0066] Figure 6b A layout of a standard cell including two transistors in series is provided for the related art;

[0067] Figure 7 A layout of a standard cell including two transistors in series is provided for the related art;

[0068] Figure 8a A three-dimensional diagram of a standard unit provided in an embodiment of the present application;

[0069] Figure 8b A layout of a standard cell provided in an embodiment of the present application;

[0070] Figure 9a A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0071] Figure 9b A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0072] Fig.9cA process diagram for preparing a channel layer provided in an embodiment of the present application;

[0073] Figure 9d A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0074] Fig.9e A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0075] Figure 9f A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0076] Figure 9g A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0077] Figure 9h A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0078] Figure 9i A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0079] Fig.10a A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0080] Fig.10b A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0081] Fig.10c A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0082] Fig.11a A circuit diagram of a standard unit provided in an embodiment of the present application;

[0083] Fig.11b for Fig.11a A layout corresponding to the circuit diagram;

[0084] Fig.11c for Fig.11a A three-dimensional diagram corresponding to the circuit diagram;

[0085] Fig.12a A circuit diagram of another standard unit provided in an embodiment of the present application;

[0086] Figure 12b for Fig.12a The layout corresponding to the circuit diagram;

[0087] Fig.13 for Fig.11a Another layout corresponding to the circuit diagram;

[0088] Fig.14a A circuit diagram of another standard unit provided in an embodiment of the present application;

[0089] Fig.14b for Fig.14a The layout corresponding to the circuit diagram.

[0090] Fig.15 A flow chart of the preparation of the chip provided in the embodiment of the present application;

[0091] Fig.16 A diagram of the chip preparation process provided in the embodiment of the present application;

[0092] Fig.17 A diagram of the chip preparation process provided in the embodiment of the present application;

[0093] Fig.18 A schematic diagram of a circuit layout database exemplarily shown in an embodiment of the present application;

[0094] Fig.19a A process diagram of drawing a layout provided in an embodiment of the present application;

[0095] Fig.19b A process diagram of drawing a layout provided in an embodiment of the present application;

[0096] Fig.19c A process diagram of drawing a layout provided in an embodiment of the present application;

[0097] Fig. 20 An interface diagram including layout and layer information provided in an embodiment of the present application;

[0098] Fig.21 A schematic block diagram of a device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0099] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0100] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0101] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0102] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0103] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0104] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a chip.

[0105] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0106] For the convenience of explanation, the following description takes a mobile phone as an example of an electronic device. The mobile phone may include a circuit board, and a processor, a memory, etc. may be integrated on the circuit board. Of course, the mobile phone may also include other components, and other circuit structures may be integrated on the circuit board, which is not limited in the embodiments of the present application.

[0107] Both the processor and the memory are composed of complex logic circuits. The logic circuit includes at least one standard cell, and a complex logic circuit is realized by combining multiple standard cells. Among them, the standard cell may include an inverter (INV), a NAND gate (NAND), a NOR gate (NOR), etc.

[0108] like Figure 1 As shown, the size of the standard cell in the X direction and the Y direction directly affects the area of ​​the chip. The size of the standard cell in the X direction is determined by the CPP, and the size of the standard cell in the Y direction is determined by the spacing (metal pitch) between the conductive metal layers and the number of metal tracks (metal track number). Among them, the metal track includes multiple routing lines, such as power routing lines, output routing lines, etc. In the embodiment of the present application, the power routing line may include the operating voltage VDD, the ground terminal VSS, the ground terminal GND, etc. inside the standard cell, and the output routing line is the routing line used by the standard cell to output signals.

[0109] Under the same CPP, the smaller the number of metal tracks, the smaller the size of the standard cell in the chip in the Y direction, and the smaller the area occupied by the standard cell. Figure 1 As shown, the number of metal tracks of the mainstream standard cell composed of fin field-effect transistor (Finfet) is mostly as low as 6T (6 metal tracks), realizing high-density standard cells, thereby manufacturing high-density circuits or chips.

[0110] Each standard cell includes at least one transistor. With the development of integrated circuits, the characteristic size of transistors continues to shrink. Figure 2 As shown, the size of traditional lateral nanosheet transistors has basically reached the process limit. Further shrinking the CPP to a smaller size (e.g., below 45nm) has proven to be extremely difficult and may result in an increase in the resistance and capacitance of the transistor.

[0111] Based on this, Figure 3 As shown, vertical nanosheet transistors are used instead of lateral nanosheet transistors. Since the source, gate, and drain of the vertical nanosheet transistor are arranged along the longitudinal direction (Z direction), the space occupied in the lateral direction (X direction) is reduced, providing the possibility of further reducing the CPP, while also reducing the parasitic capacitance of the transistor, which is currently a hot topic in logic device research.

[0112] like Figure 4As shown, the vertical nanosheet transistor includes a first electrode 11, a gate electrode 12, and a second electrode 13 sequentially stacked on a substrate 10. The first electrode 11 and the gate electrode 12 can be electrically isolated by a dielectric material, and the gate electrode 12 and the second electrode 13 can be electrically isolated by a dielectric material. The first electrode 11 is a source electrode, and the second electrode 13 is a drain electrode; or the first electrode 11 is a drain electrode, and the second electrode 13 is a source electrode.

[0113] Figure 4 In addition to the vertical nanosheet transistor, multiple through holes are also shown for electrically connecting the first pole 11, the gate 12, and the second pole 13 to the wiring. The multiple through holes include a first through hole 21, a second through hole 23, and a gate through hole 22. The power wiring is electrically connected to the first pole 11 through the first through hole 21, the output wiring is electrically connected to the second pole 13 through the second through hole 23, and the gate 12 can be electrically connected to the gate wiring through the gate through hole 22. In addition, the first through hole 21, the second through hole 23, and the gate through hole 22 are arranged in sequence along the Y direction.

[0114] Based on the premise that the first through hole 21, the second through hole 23, and the gate through hole 22 are arranged in sequence along the Y direction, as shown in FIG. Figure 5 As shown, an N-type vertical nanosheet transistor and a P-type vertical nanosheet transistor are usually arranged opposite to each other along the Y direction, and the gate 12 of the two is shared. In the Y direction, the first through hole 21 corresponding to the N-type vertical nanosheet transistor, the second through hole 23 corresponding to the N-type vertical nanosheet transistor, the gate through hole 22, the second through hole 23 corresponding to the P-type vertical nanosheet transistor, and the first through hole 21 corresponding to the P-type vertical nanosheet transistor are arranged in sequence. Among them, the first through hole 21 is located at the periphery of the second through hole 23.

[0115] For standard cells with more complex circuit connections, such as a two-input NAND gate (NAND2) and a two-input NOR gate (NOR2), the standard cells include an even number of N-type vertical nanosheet transistors connected in series or an even number of P-type vertical nanosheet transistors connected in series.

[0116] Multiple vertical nanosheet transistors of the same N-type or P-type are usually arranged along the X direction. Figure 6a and Figure 6bThe schematic diagram of two vertical nanosheet transistors connected in series through wiring is shown. When the two vertical nanosheet transistors are turned on, the power wiring 31 is electrically connected to the first electrode 11 of the first vertical nanosheet transistor through the first through hole 21, and a signal is input. The signal is transmitted from the first electrode 11 of the first vertical nanosheet transistor, through the channel layer 14 and the second electrode 13 of the first vertical nanosheet transistor, to the series wiring 33 electrically connected to the second electrodes 13 of the two vertical nanosheet transistors, so that the signal is transmitted from the second electrode 13 of the first vertical nanosheet transistor to the second electrode 13 of the second vertical nanosheet transistor through the series wiring 33. Then, the signal is transmitted from the second electrode 13 of the second vertical nanosheet transistor, through the channel layer 14 of the second vertical nanosheet transistor, to the first electrode 11 of the second vertical nanosheet transistor, and is output through the output wiring.

[0117] Based on the existing wiring design, without adding additional wiring tracks, because the two first through holes 21 are arranged opposite to the power line 31, the first electrode 11 of the second vertical nanosheet transistor is electrically connected to the power line 31 through the first through hole 21, rather than to the output line, thereby causing the two vertical nanosheet transistors to short-circuit. It should be understood that the wiring track refers to: a path used for wiring in a chip.

[0118] in, Figure 6a and Figure 6b The bold dashed line with an arrow in the figure indicates the signal transmission path. Figure 6a and Figure 6b The dashed boxes without arrows in the figure represent the respective through holes arranged in the dielectric layer, and the two conductive structures located on opposite sides of the through holes can be electrically connected through the through holes. The wiring tracks below are the metal tracks mentioned above.

[0119] The other corresponding figures below are still marked according to this rule and will not be described in detail one by one.

[0120] In order to solve the above short circuit problem, the related technology proposes the following three solutions:

[0121] First, as Figure 7 As shown, an additional wiring track is added so that the power line 31, the output line 32, and the series line 33 are staggered in the Y direction. However, the additional wiring track increases the size of the standard unit in the Y direction, which makes it less competitive.

[0122] Second, by using the backside power grid technology, a wiring track is designed on the side of the substrate 10 away from the transistor (the back side). However, the process of designing a wiring track on the back side of the substrate 10 is relatively difficult and is still in the experimental stage and has not been widely used.

[0123] Third, increase the number of metal layers and dielectric layers in the chip, increase the number of through holes in the dielectric layer, first use a metal layer to lead the signal to an open position, and then rely on the upper metal layer to connect. However, the design with more metal layers and through holes not only increases the design and manufacturing costs of the chip, but also causes a large transmission delay of the signal, affecting the performance and speed of the device.

[0124] Based on this, Figure 8a and Figure 8b As shown, an embodiment of the present application provides a chip, the chip includes a standard unit arranged on a substrate, the standard unit includes M vertical transistors connected in series and arranged along a first direction (X direction, for the convenience of description, the following description is based on the X direction), M is an even number. Among them, the M vertical transistors can all be N-type vertical transistors, or the M vertical transistors can all be P-type vertical transistors.

[0125] In some possible implementations, one chip may include one or more standard cells. In the present application, the M vertical transistors all belong to the same standard cell.

[0126] The vertical transistor of the embodiment of the present application can be a vertical nanowire transistor or the vertical nanosheet transistor mentioned above, etc. The layout and stereogram provided in the present application are all based on the vertical transistor being a vertical nanosheet transistor as an example. Along the second direction perpendicular to the substrate 10 (Z direction, for the convenience of description, the following description is based on the Z direction), the first pole 11, the gate 12, and the second pole 13 of the vertical transistor are stacked on the substrate 10 in sequence, and the first pole 11 is arranged between the substrate 10 and the gate 12, and the second pole 13 is arranged on the side of the gate 12 away from the substrate 10.

[0127] The standard cell also includes a dielectric layer covering the M vertical transistors, a power supply line 31 and an output line 32 located on the dielectric layer. The dielectric layer is provided with a first through hole 21 and a second through hole 23. The power supply line 31 and the output line 32 are arranged on the same layer and are located on different wiring tracks. In other words, the power supply line 31 and the output line 32 are arranged on the same layer and are spaced apart in a third direction (Y direction, for the convenience of description, the description is in the Y direction below).

[0128] It should be understood that the power supply line 31 and the output line 32 are arranged in the same layer, that is, the power supply line 31 and the output line 32 are deposited and photolithographically obtained by the same semiconductor process. Structurally, the power supply line 31 and the output line 32 are in the same metal layer, and the surface of the power supply line 31 facing the substrate 10 and the surface of the output line 32 facing the substrate 10 have the same distance from the substrate 10, and the surface of the power supply line 31 facing away from the substrate 10 and the surface of the output line 32 facing away from the substrate 10 have the same distance from the substrate 10. The first gate line and the second gate line mentioned below are also arranged in the same layer as the power supply line 31 and the output line 32, and their concepts are the same and will not be repeated.

[0129] Different from related technologies, Figure 6a and Figure 6b As shown, in the related art, the first pole 11 of the vertical transistor is electrically connected to the power supply line 31 through the first through hole 21, or the first pole 11 of the vertical transistor is electrically connected to the output line through the second through hole 23, and the second pole 13 of the vertical transistor is electrically connected to the series line 33 through the second through hole 23.

[0130] In this application, if Figure 8a and Figure 8b As shown, the first electrode 11 of the i-th vertical transistor and the first electrode 11 of the i+1-th vertical transistor are arranged on the substrate 10, and the two share the same conductive film layer, and do not need to be electrically connected through the series wiring 33. In addition, the second electrode 13 of the first vertical transistor is electrically connected to the power wiring 31 through the second through hole 23, and the second electrode 13 of the M-th vertical transistor is electrically connected to the output wiring 32 through the second through hole 23. The power wiring 31 and the output wiring 32 are arranged on the same layer and are located on different wiring tracks. It can also be said that the power wiring 31 and the output wiring 32 are arranged on the same layer and are spaced apart along the third direction (Y direction, for the convenience of description, the Y direction is used for description below). Wherein, i is an odd number less than M.

[0131] Taking M=2 as an example, when the two vertical transistors are turned on, the power supply line 31 inputs the signal to the second electrode 13 of the first vertical transistor through the second through hole 23, and the signal is transmitted from the first electrode 11 of the first vertical transistor to the first electrode 11 of the second vertical transistor through the channel layer 14 and the first electrode 11 of the first vertical transistor. Then, the signal is transmitted from the first electrode 11 of the second vertical transistor to the second electrode 13 of the second vertical transistor through the channel layer 14 of the second vertical transistor, and is output through the output line 32.

[0132] Although the power supply line 31 and the output line 32 of the present application are located in different wiring tracks, since the solution of the present application does not need to set up the series line 33, the short circuit of the M vertical transistors in series can be avoided without adding additional wiring tracks.

[0133] In order to realize that the power supply line 31 and the output line 32 are located in different wiring tracks, the first through hole 21 and the second through hole 23 can be staggered in the Y direction. This can be achieved in the following two ways:

[0134] In the first manner, the first vertical transistor and the Mth vertical transistor are not staggered in the Y direction (or in other words, are arranged opposite to each other), but the first through hole 21 and the second through hole 23 are staggered in the Y direction.

[0135] In the second method, the first vertical transistor and the Mth vertical transistor are staggered in the Y direction so that the first through hole 21 corresponding to the second pole 13 of the first vertical transistor and the second through hole 23 corresponding to the second pole 13 of the Mth vertical transistor are staggered in the Y direction.

[0136] like Figure 8b As shown, if the first vertical transistor and the M-th vertical transistor are staggered in the Y direction, the channel layer 14 of the first vertical transistor and the channel layer 14 of the M-th vertical transistor are also staggered in the Y direction.

[0137] The preparation of two channel layers 14 staggered in the Y direction can be achieved by the following process:

[0138] Figure 9a-9i Taking the preparation of four channel layers 14 as an example, the preparation process of the channel layer 14 is shown. Figure 9a As shown, a first mask layer 41, a second mask layer 42 and a photoresist 43 may be sequentially formed on the semiconductor film layer 141. Figure 9b As shown, the photoresist 43 is exposed and developed to obtain a photoresist pattern 431. Fig.9c and Figure 9d As shown, under the protection of the photoresist pattern 431, the second mask layer 42 is etched to obtain the second mask pattern 421, and the photoresist pattern 431 is removed. Fig.9e As shown, with the second mask pattern 421 as the main axis (mandrel), a spacer 44 is formed on the side of the second mask pattern 421 away from the substrate 10. Figure 9f As shown, dry etching is used to etch the spacer layer 44 to obtain spacer patterns 441, and the spacer patterns 441 are located on opposite sides of each first mask pattern 421. Figure 9g As shown, the second mask pattern 421 is removed. Figure 9h As shown, under the protection of the spacer pattern 441, the first mask layer 41 is etched to obtain the first mask pattern 411. Figure 9iAs shown, the spacing pattern 441 is removed, and under the protection of the first mask pattern 411 , the semiconductor film layer 141 is partially etched to obtain a channel layer middle pattern 1411 .

[0139] Figure 9a-9i Taking the self-aligned double patterning (SADP) technology as an example, the process of preparing the channel layer 14 is described. In other possible implementations, the channel layer 14 can also be prepared by using the self-aligned quadruple patterning (SAQP) technology or other technologies, which is not limited in the embodiments of the present application.

[0140] Fig.10a FIG. 1 shows a top view of four channel layers 14, wherein the four channel layer intermediate patterns 1411 are arranged side by side in the X direction and have the same length in the Y direction. Fig.10b As shown, the portions covered by the shadows in the four channel layers 14 are removed to obtain four channel layers 14 ( Fig.10c ).

[0141] In some possible implementations, such as Figure 8b As shown, the standard cell further includes a gate line 34, which is arranged on the same layer as the power line 31 and the output line 32 and is located on different wiring tracks. In other words, the gate line 34 is arranged on the same layer as the power line 31 and the output line 32 and is arranged at intervals in the Y direction.

[0142] like Figure 8b As shown, the gate wiring 34 may include a first gate wiring 341 and a second gate wiring 342, and a first gate through hole 221 and a second gate through hole 222 are also provided in the dielectric layer. The first gate wiring 341 and the second gate wiring 342 are located in different wiring tracks, that is, the first gate wiring 341 and the second gate wiring 342 are arranged at intervals in the Y direction. Correspondingly, the first gate through hole 221 and the second gate through hole 222 are arranged staggered in the Y direction. The first gate wiring 341 is electrically connected to the gate 12 of the i-th vertical transistor through the first gate through hole 221, and the second gate wiring 342 is electrically connected to the gate 12 of the i+1-th vertical transistor through the second gate through hole 222.

[0143] In some possible implementations, the second gate wiring 341, the first gate wiring 342, the power wiring 31, and the output wiring 32 are sequentially arranged along the Y direction. Among them, the output wiring 32 is located at the periphery of other wirings such as the power wiring 31, that is, compared with other wirings such as the power wiring 31, the output wiring 32 is closest to the edge of the chip.

[0144] Or, if Figure 8b As shown, the second gate line 341, the first gate line 342, the output line 32, and the power line 31 are arranged in sequence along the Y direction. Among them, the power line 31 is located at the periphery of other lines such as the output line 32. It can also be said that compared with other lines such as the output line 32, the power line 31 is closest to the edge of the chip. In this way, multiple components in a standard unit (for example, multiple transistors in parallel in a standard unit) or multiple standard units can share the power line 31.

[0145] In some possible implementations, if M=2, the above-mentioned two vertical transistors are connected in series, and the first electrode 11 of the first vertical transistor and the first electrode 11 of the second vertical transistor share the same conductive film layer; the second electrode 13 of the first vertical transistor is electrically connected to the power line 31 through the first through hole 21, and the second electrode 13 of the second vertical transistor is electrically connected to the output line 32 through the second through hole 23.

[0146] If M>2, in order to realize the series connection of M vertical transistors, in addition to the first electrode 11 of the i-th vertical transistor being shared with the first electrode 11 of the i+1-th vertical transistor, the standard cell further includes a conductive layer disposed between the vertical transistor and the dielectric layer. The second electrode 13 of the j-th vertical transistor is electrically connected to the second electrode 13 of the j+1-th vertical transistor through the conductive layer. Wherein, j is an even number less than M.

[0147] For example, M=6, 6 vertical transistors are connected in series, i is 1, 3, 5, and j is 2, 4. Specifically, the second electrode 13 of the first vertical transistor is electrically connected to the power supply wiring 31 through the first through hole 21, the first electrode 11 of the first vertical transistor and the first electrode 11 of the second vertical transistor share the same conductive film layer, the second electrode 13 of the second vertical transistor is electrically connected to the second electrode 13 of the third vertical transistor through the conductive layer, the first electrode 11 of the third vertical transistor and the first electrode 11 of the fourth vertical transistor share the same conductive film layer, the second electrode 13 of the fourth vertical transistor is electrically connected to the second electrode 13 of the fifth vertical transistor through the conductive layer, the first electrode 11 of the fifth vertical transistor and the first electrode 11 of the sixth vertical transistor share the same conductive film layer, and the second electrode 13 of the sixth vertical transistor is electrically connected to the output wiring 32 through the second through hole 23.

[0148] It should be noted that the conductive layer is disposed between the M vertical transistors and the dielectric layer, and the wiring tracks such as the power wiring 31 and the output wiring are located on the side of the dielectric layer away from the substrate 10. It can also be said that the M vertical transistors and the conductive layer are located in the M0 layer of the chip; the first through hole 21, the second through hole 23, etc. penetrate the dielectric layer and are located in the V0 layer; the power wiring 31 and the output wiring 32 are located in the M1 layer. Therefore, the conductive layer does not occupy the wiring track.

[0149] The following describes the application scenarios of the chip provided in the embodiment of the present application in combination with a specific logic circuit:

[0150] The first application scenario, such as Fig.11a As shown, the standard unit is NAND2. The NAND2 circuit includes two vertical transistors, a first transistor P1, a second transistor P2, a first voltage terminal VSS, a second voltage terminal VDD, and an output terminal OUT. Among them, the two vertical transistors are a first vertical transistor N1 and a second vertical transistor N2, and the first vertical transistor N1 and the second vertical transistor N2 can both be N-type transistors. The first transistor P1 and the second transistor P2 can both be P-type transistors, and the first transistor P1 and the second transistor P2 can be vertical transistors or other transistors, which is not limited in the embodiments of the present application.

[0151] The gate 12 of the first transistor P1 is electrically connected to the gate 12 of the first vertical transistor N1 , the first electrode 11 of the first transistor P1 is electrically connected to the second voltage terminal VDD, and the second electrode 13 of the first transistor P1 is electrically connected to the output terminal OUT.

[0152] The gate 12 of the second transistor P2 is electrically connected to the gate 12 of the second vertical transistor N2 , the first electrode 11 of the second transistor P2 is electrically connected to the second voltage terminal VDD, and the second electrode 13 of the second transistor P2 is electrically connected to the output terminal OUT.

[0153] The second electrode 13 of the first vertical transistor N1 is electrically connected to the first voltage terminal VSS, the first electrode 11 of the first vertical transistor N1 is electrically connected to the first electrode 11 of the second vertical transistor N2, and the second electrode 13 of the second vertical transistor N2 is electrically connected to the output terminal OUT.

[0154] It can be seen from the circuit connection relationship that the first transistor P1 is connected in parallel with the second transistor P2, and the first vertical transistor N1 is connected in series with the second vertical transistor N2.

[0155] Fig.11b shows the layout of the above NAND2 circuit, Fig.11c FIG. 2 shows a three-dimensional diagram of the NAND2. Fig.11b and Fig.11cAs shown, for the first transistor P1 and the second transistor P2 connected in parallel, assuming that the first transistor P1 and the second transistor P2 are also vertical transistors, the first electrode 11 of the first transistor P1 can share the same conductive film layer with the first electrode 11 of the second transistor P2, and the first electrode 11 of the first transistor P1 can be electrically connected to the power supply line VDD (i.e., the second power supply line) through a through hole with the first electrode 11 of the second transistor P2, thereby achieving electrical connection with the second voltage terminal VDD. The second electrode 13 of the first transistor P1 and the second electrode 13 of the second transistor P2 are respectively electrically connected to the output line 32 (i.e., the second output line) through a through hole, thereby achieving electrical connection with the output terminal OUT. The gate 12 of the first transistor P1 is electrically connected to the first gate line 341 through the first gate through hole 221, and the gate 12 of the second transistor P2 is electrically connected to the second gate line 342 through the second gate through hole 222.

[0156] The through hole corresponding to the second electrode 13 of the first transistor P1 and the through hole corresponding to the second electrode 13 of the second transistor P2 do not need to be staggered in the Y direction.

[0157] like Fig.11b and Fig.11c As shown, for the first vertical transistor N1 and the second vertical transistor N2 connected in series, the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2 share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2. The second electrode 13 of the first vertical transistor N1 is electrically connected to the power supply line VSS (i.e., the first power supply line) through the second through hole 21, thereby achieving electrical connection with the first voltage terminal VSS. The second electrode 13 of the second vertical transistor N2 is electrically connected to the output line 32 (i.e., the first output line) through the second through hole 23, thereby achieving electrical connection with the output terminal OUT. The gate 12 of the first vertical transistor N1 is electrically connected to the first gate line 341 through the first gate through hole 221, and the gate 12 of the second vertical transistor N2 is electrically connected to the second gate line 342 through the second gate through hole 222.

[0158] The first through hole 21 corresponding to the second electrode 13 of the first vertical transistor N1 and the second through hole 23 corresponding to the second electrode 13 of the second vertical transistor N2 are staggered in the Y direction.

[0159] In some possible implementations, the gate 12 of the first transistor P1 and the gate 12 of the first vertical transistor N1 share the same gate A and the same first gate wiring 341, and the gate 12 of the second transistor P2 and the gate 12 of the second vertical transistor N2 share the same gate B and the same second gate wiring 342.

[0160] On this basis, a dielectric layer is further arranged on the side of the six traces away from the substrate 10, and the dielectric layer is provided with a through hole located in the V1 layer, and the standard unit also includes a trace OUT arranged in the M2 layer. The output trace 32 electrically connected to the second electrode 13 of the first transistor P1 and the second electrode 13 of the second transistor P2, and the output trace 32 electrically connected to the second electrode 13 of the second vertical transistor N2, can also be electrically connected to the trace OUT of the M2 layer through the through hole of the V1 layer.

[0161] It should be understood that the connection mode of the first transistor P1 and the second transistor P2 with each routing through the through hole is different from the connection mode of the M vertical transistors provided in the embodiment of the present application with each routing through the through hole. The power routing VDD (second power routing) and the power routing VSS (first power routing) are different routings, and the output routing 32 (second output routing) electrically connected to the second electrode 13 of the first transistor P1 and the second electrode 13 of the second transistor P2 and the output routing 32 (first output routing) electrically connected to the second electrode 13 of the second vertical transistor N2 are different routings.

[0162] The above-mentioned power line VDD (second power line), the output line 32 (second output line) electrically connected to the second pole 13 of the first transistor P1 and the second pole 13 of the second transistor P2, the first gate line 341, the second gate line 342, the output line 32 (first output line) electrically connected to the second pole 13 of the second vertical transistor N2, and the power line VSS (first power line) are 6 lines in total, occupying 6 wiring tracks (6T) in total, and these 6 lines are arranged on the same layer in the M1 layer.

[0163] The second application scenario, such as Fig.12a As shown, the standard unit is a two-input AND-NOR gate (AOI2). The AOI2 circuit includes four vertical transistors, a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a first voltage terminal VSS, a second voltage terminal VDD, and an output terminal OUT.

[0164] Among them, the four vertical transistors are respectively a first vertical transistor N1, a second vertical transistor N2, a third vertical transistor N3, and a fourth vertical transistor N4, and the four vertical transistors may all be N-type transistors. The first transistor P1, the second transistor P2, the third transistor P3, and the fourth transistor P4 may all be P-type transistors, and the first transistor P1, the second transistor P2, the third transistor P3, and the fourth transistor P4 may be vertical transistors or other transistors, which are not limited in the embodiment of the present application, and the following description is made by taking the first transistor P1, the second transistor P2, the third transistor P3, and the fourth transistor P4 as vertical transistors as an example.

[0165] The gate 12 of the first transistor P1 is electrically connected to the gate 12 of the first vertical transistor N1, the first electrode 11 of the first transistor P1 is electrically connected to the first electrode 11 of the second transistor P2, the second electrode 13 of the first transistor P1 is electrically connected to the second electrode 13 of the second transistor P2, and the gate 12 of the second transistor P2 is electrically connected to the gate 12 of the second vertical transistor N2.

[0166] The gate 12 of the third transistor P3 is electrically connected to the gate 12 of the third vertical transistor N3, the first electrode 11 of the third transistor P3 is electrically connected to the first electrode 11 of the fourth transistor P4, the second electrode 13 of the third transistor P3 is electrically connected to the second electrode 13 of the fourth transistor P4. The gate 12 of the fourth transistor P4 is electrically connected to the gate of the fourth vertical transistor N4.

[0167] On this basis, the first electrode 11 of the first transistor P1 and the first electrode 11 of the second transistor P2 are also electrically connected to the first electrode 11 of the third transistor P3 and the first electrode 11 of the fourth transistor P4. The second electrode 13 of the first transistor P1 and the second electrode 13 of the second transistor P2 are also electrically connected to the output terminal OUT, and the first electrode 11 of the third transistor P3 and the first electrode 11 of the fourth transistor P4 are also electrically connected to the second voltage terminal VDD.

[0168] The second electrode 13 of the second vertical transistor N2 is electrically connected to the first voltage terminal VSS, the first electrode 11 of the second vertical transistor N2 is electrically connected to the first electrode 11 of the first vertical transistor N1, and the second electrode 13 of the first vertical transistor N1 and the second electrode 13 of the third vertical transistor N3 are both electrically connected to the output terminal OUT.

[0169] The first electrode 11 of the third vertical transistor N3 is electrically connected to the first electrode 11 of the fourth vertical transistor N4 , and the second electrode 13 of the fourth vertical transistor N4 is electrically connected to the first voltage terminal VSS.

[0170] From the circuit connection relationship, it can be seen that the first transistor P1 is connected in parallel with the second transistor P2, the third transistor P3 is connected in parallel with the fourth transistor P4, the first vertical transistor N1 is connected in series with the second vertical transistor N2, and the third vertical transistor N3 is connected in series with the fourth vertical transistor N4.

[0171] Figure 12b FIG. 2 shows the layout of the AOI2 circuit. Figure 12bAs shown, for the first transistor P1, the second transistor P2, the third transistor P3, and the fourth transistor P4 connected in parallel, the first electrode 11 of the first transistor P1, the first electrode 11 of the second transistor P2, the first electrode 11 of the third transistor P3, and the first electrode 11 of the fourth transistor P4 share the same conductive film layer. The second electrode 13 of the first transistor P1 and the second electrode 13 of the second transistor P2 are electrically connected to the output wiring 32 through a through hole, and the second electrode 13 of the third transistor P3 and the second electrode 13 of the fourth transistor P4 are electrically connected to the power wiring VDD through a through hole, thereby achieving electrical connection with the second voltage terminal VDD. The gate 12 of the second transistor P2 and the gate 12 of the third transistor P3 are electrically connected to the first gate wiring 341 through the first gate through hole 221, respectively, and the gate 12 of the first transistor P1 and the gate 12 of the fourth transistor P4 are electrically connected to the second gate wiring 342 through the second gate through hole 222, respectively. Among them, the through hole corresponding to the second pole 13 of the first transistor P1 and the through hole corresponding to the second pole 13 of the second transistor P2 do not need to be staggered in the Y direction, and the through hole corresponding to the second pole 13 of the third transistor P3 and the through hole corresponding to the second pole 13 of the fourth transistor P4 do not need to be staggered in the Y direction.

[0172] It should be noted that the first gate wiring 341 electrically connected to the gate 12 of the second transistor P2 and the first gate wiring 341 electrically connected to the gate 12 of the third transistor P3 are located on the same wiring track, but they are electrically isolated from each other, or it can be said that there is no electrical connection between them. The second gate wiring 342 electrically connected to the gate 12 of the first transistor P1 and the second gate wiring 342 electrically connected to the gate 12 of the fourth transistor P4 are located on the same wiring track, but they are electrically isolated from each other, or it can be said that there is no electrical connection between them.

[0173] like Figure 12b As shown, for the first vertical transistor N1 and the second vertical transistor N2 connected in series, the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2 share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2. For the third vertical transistor N3 and the fourth vertical transistor N4 connected in series, the first electrode 11 of the third vertical transistor N3 and the first electrode 11 of the fourth vertical transistor N4 share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode 11 of the third vertical transistor N3 and the first electrode 11 of the fourth vertical transistor N4.

[0174] The second electrode 13 of the first vertical transistor N1 and the second electrode 13 of the third vertical transistor N3 are electrically connected to the output wiring 32 through the second through hole 23, and the second electrode 13 of the second vertical transistor N2 and the second electrode 13 of the fourth vertical transistor N4 are electrically connected to the power wiring VSS through the first through hole 21, thereby achieving electrical connection with the first voltage terminal VSS. Among them, the second through hole 23 corresponding to the second electrode 13 of the first vertical transistor N1 and the first through hole 21 corresponding to the second electrode 13 of the second vertical transistor N2 are staggered in the Y direction; the first through hole 21 corresponding to the second electrode 13 of the fourth vertical transistor N4 and the second through hole 23 corresponding to the second electrode 13 of the third vertical transistor N3 are staggered in the Y direction.

[0175] The gate 12 of the first vertical transistor N1 and the gate 12 of the fourth vertical transistor N4 are electrically connected to the second gate wiring 342 through the second gate through hole 222 , and the gate 12 of the second vertical transistor N2 and the gate 12 of the third vertical transistor N3 are electrically connected to the first gate wiring 341 through the first gate through hole 221 .

[0176] It should be noted that the first gate wiring 341 electrically connected to the gate 12 of the second vertical transistor N2 and the first gate wiring 341 electrically connected to the gate 12 of the third vertical transistor N3 are located in the same wiring track, but they are electrically isolated from each other, or it can be said that there is no electrical connection between them. The second gate wiring 342 electrically connected to the gate 12 of the first vertical transistor N1 and the second gate wiring 342 electrically connected to the gate 12 of the fourth vertical transistor N4 are located in the same wiring track, but they are electrically isolated from each other, or it can be said that there is no electrical connection between them.

[0177] Among them, the gate 12 of the first transistor P1 and the gate 12 of the first vertical transistor N1 share the same gate A and the same second gate wiring 342, the gate 12 of the second transistor P2 and the gate 12 of the second vertical transistor N2 share the same gate B and the same first gate wiring 341, the gate 12 of the third transistor P3 and the gate 12 of the third vertical transistor N3 share the same gate C and the same first gate wiring 341, and the gate 12 of the fourth transistor P4 and the gate 12 of the fourth vertical transistor N4 share the same gate D and the same second gate wiring 342.

[0178] It should be understood that the connection method of the first transistor P1, the second transistor P2, the third transistor P3, and the fourth transistor P4 with each routing through the through hole is different from the connection method of the M series vertical transistors with each routing through the through hole provided in the embodiment of the present application. The power routing VDD and the power routing VSS are different routings, and the output routing 32 electrically connected to the second electrode 13 of the first transistor P1 and the second electrode 13 of the second transistor P2 and the output routing 32 electrically connected to the second electrode 13 of the first vertical transistor N1 and the second electrode 13 of the third vertical transistor N3 are different routings.

[0179] The above-mentioned power line VDD, the output line 32 electrically connected to the second electrode 13 of the first transistor P1 and the second electrode 13 of the second transistor P2, the first gate line 341, the second gate line 342, the output line 32 electrically connected to the second electrode 13 of the first vertical transistor N1 and the second electrode 13 of the third vertical transistor N3, and the power line VSS, a total of 6 lines, occupy a total of 6 wiring tracks (6T), and these 6 lines are arranged on the same layer in the M1 layer.

[0180] The above text introduces the situation where the standard cell occupies 6 wiring tracks through two application scenarios. In other embodiments, the output line 32 or the power line 31 electrically connected to the M vertical transistors in series can also share the same wiring track with the first gate line 341 or the second gate line 342. In this way, the standard cell only needs to occupy 6 wiring tracks, which greatly reduces the size of the chip in the Y direction and reduces the chip area.

[0181] If the second gate wiring 342 , the power wiring 31 , and the output wiring 32 are arranged in sequence along the Y direction, the first gate wiring 341 and the power wiring 31 share the same wiring track and are disconnected.

[0182] If the second gate wiring 342 , the output wiring 32 , and the power wiring 31 are arranged in sequence along the Y direction, the first gate wiring 341 and the power wiring 31 share the same wiring track and are disconnected.

[0183] As mentioned above, the power line 31 is located outside other lines such as the output line 32, and multiple components in a standard cell (for example, multiple transistors connected in parallel in a standard cell) or multiple standard cells can share the power line 31. Therefore, optionally, the second gate line 342, the output line 32, and the power line 31 are arranged in the Y direction in sequence, and the first gate line 341 and the power line 31 share the same wiring track and are disconnected.

[0184] The following describes the application scenarios of the chip provided in the embodiment of the present application in combination with a specific logic circuit:

[0185] The third application scenario, such as Fig.11a As shown, the standard cell of the third application scenario is still NAND2, and its circuit connection relationship is the same as that of the first application scenario, which will not be repeated here.

[0186] Fig.13 The layout of the NAND2 circuit is shown in FIG. Fig.13 As shown, for the first transistor P1 and the second transistor P2 connected in parallel, the layout design is the same as that of the first application scenario, which will not be repeated here.

[0187] like Fig.13 As shown, for the first vertical transistor N1 and the second vertical transistor N2 connected in series, the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2 share the same conductive film layer, and the standard unit does not include through holes corresponding to the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2. The second electrode 13 of the first vertical transistor N1 is electrically connected to the power supply line VSS through the second through hole 21, and the second electrode 13 of the second vertical transistor N2 is electrically connected to the output line 32 through the second through hole 23. The gate 12 of the first vertical transistor N1 is electrically connected to the first gate line 341 through the first gate through hole 221, and the gate 12 of the second vertical transistor N2 is electrically connected to the second gate line 342 through the second gate through hole 222.

[0188] Among them, the first gate through hole 221 corresponding to the gate 12 of the first vertical transistor N1 and the second through hole 23 corresponding to the second pole 13 of the second vertical transistor N2 do not need to be staggered in the Y direction, so that the first gate wiring 341 electrically connected to the gate 12 of the first vertical transistor N1 through the first gate through hole 221 and the output wiring 32 electrically connected to the second pole 13 of the second vertical transistor N2 through the second through hole 23 are located on the same wiring track, thereby eliminating one wiring track, reducing the size of the chip in the Y direction, and reducing the area occupied by the chip.

[0189] That is, the above-mentioned power line VDD, the output line 32 electrically connected to the second pole 13 of the first transistor P1 and the second pole 13 of the second transistor P2, the first gate line 341, the second gate line 342, the output line 32 electrically connected to the second pole 13 of the second vertical transistor N2, and the power line VSS occupy a total of 5 wiring tracks (5T).

[0190] The other explanations of the third application scenario are the same as those of the first application scenario and will not be repeated here.

[0191] The fourth application scenario is different from the above three application scenarios in that the above three application scenarios introduce two vertical transistors connected in series, while the fourth application scenario introduces a standard unit including four vertical transistors connected in series.

[0192] like Fig.14a As shown, the standard unit is a four-input NAND gate (NAND4), the NAND4 circuit includes a first transistor P1, a second transistor P2, a third transistor P3, and a fourth transistor P4 connected in parallel, and the standard unit also includes a first vertical transistor N1, a second vertical transistor N2, a third vertical transistor N3, and a fourth vertical transistor N4 connected in series, as well as a first voltage terminal VSS, a second voltage terminal VDD, and an output terminal OUT.

[0193] The first electrode 11 of the first transistor P1, the first electrode 11 of the second transistor P2, the first electrode 11 of the third transistor P3, and the first electrode 11 of the fourth transistor P4 are all electrically connected to the output terminal OUT, and the second electrode 13 of the first transistor P1, the second electrode 13 of the second transistor P2, the second electrode 13 of the third transistor P3, and the second electrode 13 of the fourth transistor P4 are all electrically connected to the second voltage terminal VDD.

[0194] The gate 12 of the fourth vertical transistor N4 is electrically connected to the gate 12 of the fourth transistor P4 , the first electrode 11 of the fourth vertical transistor N4 is electrically connected to the first electrode 11 of the third vertical transistor N3 , and the second electrode 13 of the fourth vertical transistor N4 is electrically connected to the output terminal OUT.

[0195] The gate electrode 12 of the third vertical transistor N3 is electrically connected to the gate electrode 12 of the third transistor P3 , and the second electrode 13 of the third vertical transistor N3 is electrically connected to the second electrode 13 of the second vertical transistor N2 .

[0196] The gate 12 of the second vertical transistor N2 is electrically connected to the gate 12 of the second transistor P2 , and the first electrode 11 of the second vertical transistor N2 is electrically connected to the first electrode 11 of the first vertical transistor N1 .

[0197] The gate electrode 12 of the first vertical transistor N1 is electrically connected to the gate electrode 12 of the first transistor P1 , and the second electrode 13 of the first vertical transistor N1 is electrically connected to the first voltage terminal VSS.

[0198] Fig.14b The layout of the above standard unit is shown in FIG. Fig.14bAs shown, for the first transistor P1, the second transistor P2, the third transistor P3, and the fourth transistor P4 connected in parallel, the first electrode 11 of the first transistor P1, the first electrode 11 of the second transistor P2, the first electrode 11 of the third transistor P3, and the first electrode 11 of the fourth transistor P4 share the same conductive film layer, and the first electrode 11 of the first transistor P1, the first electrode 11 of the second transistor P2, the first electrode 11 of the third transistor P3, and the first electrode 11 of the fourth transistor P4 are all electrically connected to the power supply wiring VDD through a through hole, thereby achieving electrical connection with the second voltage terminal VDD. The second electrode 13 of the first transistor P1, the second electrode 13 of the second transistor P2, the second electrode 13 of the third transistor P3, and the second electrode 13 of the fourth transistor P4 are respectively electrically connected to the output wiring 32 through a through hole. The gate 12 of the first transistor P1 and the gate 12 of the third transistor P3 are electrically connected to the first gate wiring 341 through the first gate through hole 221 , and the gate 12 of the second transistor P2 and the gate 12 of the fourth transistor P4 are electrically connected to the second gate wiring 342 through the second gate through hole 222 .

[0199] Among them, the through hole corresponding to the second pole 13 of the first transistor P1, the through hole corresponding to the second pole 13 of the second transistor P2, the through hole corresponding to the second pole 13 of the third transistor P3, and the through hole corresponding to the second pole 13 of the fourth transistor P4 do not need to be staggered in the Y direction.

[0200] like Fig.14b As shown, for the first vertical transistor N1, the second vertical transistor N2, the third vertical transistor N3, and the fourth vertical transistor N4 connected in series, the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2 share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode 11 of the first vertical transistor N1 and the first electrode 11 of the second vertical transistor N2; the first electrode 11 of the third vertical transistor N3 and the first electrode 11 of the fourth vertical transistor N4 share the same conductive film layer, and the standard unit does not include a through hole corresponding to the first electrode 11 of the third vertical transistor N3 and the first electrode 11 of the fourth vertical transistor N4.

[0201] The second electrode 13 of the first vertical transistor N1 is electrically connected to the power supply wiring VSS through the second through hole 21, thereby achieving electrical connection with the second voltage terminal VDD. The second electrode 13 of the fourth vertical transistor N4 is electrically connected to the output wiring 32 through the second through hole 23, thereby achieving electrical connection with the output terminal OUT. The standard cell also includes a conductive layer 15 arranged between the vertical transistors and the dielectric layer, and the second electrode 13 of the second vertical transistor N2 (i.e., the jth vertical transistor) and the second electrode 13 of the third vertical transistor N3 (i.e., the j+1th vertical transistor) are electrically connected through the conductive layer 15. Among them, the conductive layer 15 is in direct contact with the second electrode 13 of the second vertical transistor N2 and the second electrode 13 of the third vertical transistor N3, without the need for electrical connection through a through hole, Fig.14b It can be seen that no dotted frame representing the through hole is drawn at the second electrode 13 of the second vertical transistor N2 and the second electrode 13 of the third vertical transistor N3 .

[0202] The first through hole 21 corresponding to the second electrode 13 of the first vertical transistor N1 and the second through hole 23 corresponding to the second electrode 13 of the fourth vertical transistor N4 are staggered in the Y direction.

[0203] The gate 12 of the first vertical transistor N1 and the gate 12 of the third vertical transistor N3 are electrically connected to the first gate wiring 341 through the first gate through hole 221, and the gate 12 of the second vertical transistor N2 and the gate 12 of the fourth vertical transistor N4 are electrically connected to the second gate wiring 342 through the second gate through hole 222.

[0204] Optionally, the first gate through hole 221 corresponding to the gate 12 of the first vertical transistor N1, the first gate through hole 221 corresponding to the gate 12 of the third vertical transistor N3, and the second through hole 23 corresponding to the second electrode 13 of the fourth vertical transistor N4 do not need to be staggered in the Y direction, so that the first gate wiring 341 electrically connected to the gate 12 of the first vertical transistor N1 and the third vertical transistor N3 through the first gate through hole 221 and the output wiring 32 electrically connected to the second electrode 13 of the fourth vertical transistor N4 through the second through hole 23 are located on the same wiring track, thereby eliminating one wiring track, reducing the size of the chip in the Y direction, and reducing the area occupied by the chip.

[0205] Of course, the first gate wiring 341 and the output wiring 32 may also be located in different wiring tracks. The specific design method can refer to the first application scenario and the second application scenario, which will not be repeated here.

[0206] In some possible implementations, such as Fig.14bAs shown, the channel layer 14 of the second vertical transistor N2 and the channel layer 14 of the third vertical transistor N3 may be arranged in the Y direction without being staggered with the channel layer 14 of the first vertical transistor N1, and may be arranged in the Y direction with the channel layer 14 of the fourth vertical transistor N4. Alternatively, the channel layer 14 of the second vertical transistor N2 and the channel layer 14 of the third vertical transistor N3 may be arranged in the Y direction without being staggered with the channel layer 14 of the fourth vertical transistor N4, and may be arranged in the Y direction with the channel layer 14 of the first vertical transistor N1.

[0207] In another embodiment, the present application also provides a method for preparing a chip, such as Fig.15 As shown, this can be achieved through the following steps:

[0208] S110, such as Fig.16 As shown, M vertical transistors are formed in series and arranged side by side along the X direction on the substrate 10, where M is an even number. Along the Z direction, the vertical transistor includes a first electrode 11, a gate 12, a second electrode 13 stacked in sequence, and a channel layer 14 that penetrates the second electrode 13, the gate 12, and the first electrode 11. The first electrode 11 is located between the substrate 10 and the gate 12, and the first electrode 11 of the i-th vertical transistor is shared with the first electrode 11 of the i+1-th vertical transistor, where i is an odd number less than M.

[0209] In some possible implementations, in order to realize that the power supply line 31 and the output line 32 are located in different wiring tracks, the first through hole 21 and the second through hole 23 can be staggered in the Y direction. This can be achieved in the following two ways:

[0210] In the first manner, the first vertical transistor and the Mth vertical transistor are not staggered in the Y direction (or in other words, are arranged opposite to each other), but the first through hole 21 and the second through hole 23 are staggered in the Y direction.

[0211] In the second method, the first vertical transistor and the Mth vertical transistor are staggered in the Y direction, so that the first through hole 21 corresponding to the second pole 13 of the first vertical transistor and the second through hole 23 corresponding to the second pole 13 of the Mth vertical transistor are staggered in the Y direction.

[0212] like Figure 8b As shown, if the first vertical transistor and the Mth vertical transistor are staggered in the Y direction, the channel layer 14 of the first vertical transistor and the channel layer 14 of the Mth vertical transistor are also staggered in the Y direction.

[0213] Specifically, the preparation of two channel layers 14 staggered in the Y direction can be achieved by the following process:

[0214] Figure 9a-9iTaking the preparation of four channel layers 14 as an example, the preparation process of the channel layer 14 is shown. Figure 9a As shown, a first mask layer 34, a second mask layer 42 and a photoresist 43 may be sequentially formed on the semiconductor film layer 141. Figure 9b As shown, the photoresist 43 is exposed and developed to obtain a photoresist pattern 434. Fig.9c and Figure 9d As shown, under the protection of the photoresist pattern 434, the second mask layer 42 is etched to obtain the second mask pattern 421, and the photoresist pattern 434 is removed. Fig.9e As shown, with the second mask pattern 421 as the main axis (mandrel), a spacer 44 is formed on the side of the second mask pattern 421 away from the substrate 10. Figure 9f As shown, dry etching is used to etch the spacer layer 44 to obtain spacer patterns 441, and the spacer patterns 441 are located on opposite sides of each first mask pattern 421. Figure 9g As shown, the second mask pattern 421 is removed. Figure 9h As shown, under the protection of the spacer pattern 441, the first mask layer 34 is etched to obtain the first mask pattern 341. Figure 9i As shown, the spacing pattern 441 is removed, and under the protection of the first mask pattern 341 , the semiconductor film layer 141 is partially etched to obtain a channel layer middle pattern 1411 .

[0215] Figure 9a-9i Taking the SADP technology as an example, the process of preparing the channel layer 14 is described. In other possible implementations, the SAQP technology or other technologies may also be used to prepare the channel layer 14, which is not limited in the embodiments of the present application.

[0216] It should be understood that if M>2, the channel layer 14 of the second vertical transistor to the channel layer 14 of the M-1th vertical transistor are aligned with (not misaligned with) the first vertical transistor or the Mth vertical transistor in the Y direction. Figure 9a-9i The four vertical transistors corresponding to the four channel layers 14 shown may include three groups of M vertical transistors, where M=2.

[0217] Next, after forming the channel layer 14, a first electrode 11, a first spacer, a dummy gate, a second spacer, and a second electrode 13 are sequentially formed on the substrate 10 around the channel layer 14. Afterwards, the dummy gate is removed, and the gate 12 is filled in the original position of the dummy gate. The pattern of the dummy gate is the same as that of the gate 12, the materials of the first spacer and the second spacer both include dielectric materials, the first spacer is used to electrically isolate the first electrode 11 from the gate 12, and the second spacer is used to electrically isolate the gate 12 from the second electrode 13.

[0218] S120, such as Fig.17 As shown, a dielectric layer covering M vertical transistors is formed. The dielectric layer is provided with a first through hole 21 and a second through hole 23, which are staggered in the Y direction; the X direction is perpendicular to the Z direction, and both the X direction and the Z direction are perpendicular to the Y direction.

[0219] In some possible implementations, a dielectric film layer may be first deposited on the M vertical transistors, and then a photolithography process may be used to form the first through hole 21 and the second through hole 23 in the dielectric film layer to obtain a dielectric layer.

[0220] S130, such as Figure 8a As shown, a power supply line 31 and an output line 32 are formed on the dielectric layer in the same layer and located on different wiring tracks. The power supply line 31 is electrically connected to the second electrode 13 of the first vertical transistor through the first through hole 21, and the output line 32 is electrically connected to the second electrode 13 of the Mth vertical transistor through the second through hole 23.

[0221] In some possible implementations, a metal layer may be first formed on the dielectric layer, and then the metal layer may be patterned using a photolithography process to obtain the power wiring 31 and the output wiring 32 .

[0222] In some embodiments, while forming the first through hole 21 and the second through hole 23, a first gate through hole 221 and a second gate through hole 222 are formed in the dielectric film layer by a photolithography process, and the first gate through hole 221 and the second gate through hole 222 are staggered in the Y direction. The standard cell also includes a first gate wiring 341 and a second gate wiring 342 located on different wiring tracks; the first gate wiring 221 is electrically connected to the gate 12 of the i-th vertical transistor through the first gate through hole 341, and the second gate wiring 342 is electrically connected to the gate 12 of the i+1-th vertical transistor through the second gate through hole 222.

[0223] Among them, the first gate wiring 341 and the second gate wiring 342 are arranged on the same layer as the power wiring 31 and the output wiring 32, and the metal layer is patterned by using a photolithography process to form the power wiring 31 and the output wiring 32 while also forming the first gate wiring 341 and the second gate wiring 342.

[0224] In some possible implementations, the second gate wiring 341, the first gate wiring 342, the power wiring 31, and the output wiring 32 are sequentially arranged along the Y direction. Among them, the output wiring 32 is located at the periphery of other wirings such as the power wiring 31, that is, compared with other wirings such as the power wiring 31, the output wiring 32 is closest to the edge of the chip.

[0225] Or, if Figure 8bAs shown, the second gate line 341, the first gate line 342, the output line 32, and the power line 31 are arranged in sequence along the Y direction. Among them, the power line 31 is located at the periphery of other lines such as the output line 32. It can also be said that compared with other lines such as the output line 32, the power line 31 is closest to the edge of the chip. In this way, multiple components in a standard unit (for example, multiple transistors in parallel in a standard unit) or multiple standard units can share the power line 31.

[0226] In some possible implementations, the output line 32 or the power line 31 electrically connected to the M vertical transistors in series can also share the same wiring track with the first gate line 341 or the second gate line 342. In this way, the number of wiring tracks in the standard unit can be reduced, the size of the chip in the Y direction can be greatly reduced, and the chip area can be reduced.

[0227] If the second gate wiring 342 , the power wiring 31 , and the output wiring 32 are arranged in sequence along the Y direction, the first gate wiring 341 and the power wiring 31 share the same wiring track and are disconnected.

[0228] If the second gate wiring 342 , the output wiring 32 , and the power wiring 31 are arranged in sequence along the Y direction, the first gate wiring 341 and the power wiring 31 share the same wiring track and are disconnected.

[0229] In some embodiments, in some possible implementation methods, if M=2, the above-mentioned two vertical transistors are connected in series, and the first electrode 11 of the first vertical transistor and the first electrode 11 of the second vertical transistor share the same conductive film layer; the second electrode 13 of the first vertical transistor is electrically connected to the power line 31 through the first through hole 21, and the second electrode 13 of the second vertical transistor is electrically connected to the output line 32 through the second through hole 23.

[0230] If M>2, in order to realize the series connection of M vertical transistors, in addition to the first electrode 11 of the i-th vertical transistor being shared with the first electrode 11 of the i+1-th vertical transistor, the standard cell further includes a conductive layer 15 disposed between the vertical transistor and the dielectric layer. The second electrode 13 of the j-th vertical transistor is electrically connected to the second electrode 13 of the j+1-th vertical transistor through the conductive layer 15. Wherein, j is an even number less than M.

[0231] For example, M=6, 6 vertical transistors are connected in series, i is 1, 3, 5, and j is 2, 4. Specifically, the second electrode 13 of the first vertical transistor is electrically connected to the power supply wiring 31 through the first through hole 21, the first electrode 11 of the first vertical transistor and the first electrode 11 of the second vertical transistor share the same conductive film layer, the second electrode 13 of the second vertical transistor is electrically connected to the second electrode 13 of the third vertical transistor through the conductive layer 15, the first electrode 11 of the third vertical transistor and the first electrode 11 of the fourth vertical transistor share the same conductive film layer, the second electrode 13 of the fourth vertical transistor is electrically connected to the second electrode 13 of the fifth vertical transistor through the conductive layer 15, the first electrode 11 of the fifth vertical transistor and the first electrode 11 of the sixth vertical transistor share the same conductive film layer, and the second electrode 13 of the sixth vertical transistor is electrically connected to the output wiring 32 through the second through hole 23.

[0232] It should be noted that the conductive layer 15 is disposed between the M vertical transistors and the dielectric layer, and the wiring tracks such as the power wiring 31 and the output wiring are located on the side of the dielectric layer away from the substrate 10. It can also be said that the M vertical transistors and the conductive layer 15 are located in the M0 layer of the chip; the first through hole 21, the second through hole 23, etc. penetrate the dielectric layer and are located in the V0 layer; the power wiring 31 and the output wiring 32 are located in the M1 layer. Therefore, the conductive layer 15 does not occupy the wiring track.

[0233] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as the explanations and beneficial effects of a chip in the aforementioned embodiment, and will not be repeated here.

[0234] In another embodiment, the present application also provides a circuit layout database, such as Fig.18 As shown, the circuit layout database (represented by Library) contains one or more folders (e.g., folder 1, folder 2, folder 3, folder 4), each folder includes one or more standard cells (e.g., AND gate, NAND gate, NAND2, NAND4, AIO2), and each standard cell includes the layout (layout), circuit diagram (schematic), and electrical component graphic symbol (symbol) of the standard cell. For example, the electrical component graphic symbol of the inverter is represented by a triangle.

[0235] by Fig.18 Taking the circuit layout database shown as an example, the circuit layout database includes folder 1, folder 2, folder 3, and folder 4. Folder 4 includes AND, NAND, NAND2, NAND4, AIO2, etc., among which the layout, circuit diagram, and electrical component graphic symbols of the standard unit AIO2 are presented in the View column.

[0236] In some possible implementations, the circuit layout database may be a database of functional devices required by the electronic device, or a database of standard cells set on one or more chips. Of course, the circuit layout database may also be other, and the embodiment of the present application does not limit the circuit specifically indicated by the circuit layout database. Among them, the functional devices required by the electronic device may be, for example, a memory, a processor, etc.

[0237] like Figure 8b As shown, the layout of the standard cell includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer stacked in sequence. The standard cell includes M vertical transistors connected in series, where M is an even number. The first layer includes one or more first sublayers arranged side by side along the X direction, and the first electrode 11 of the i-th vertical transistor and the first electrode 11 of the i+1-th vertical transistor share the same first sublayer, where i is an odd number less than M. The second layer includes the gates 12 of the M vertical transistors, and the third layer includes the second electrodes 13 of the M vertical transistors. The fourth layer includes a first through hole 21 and a second through hole 23, and the first through hole 21 and the second through hole 23 are staggered in the Y direction; wherein, in the layout, the X direction is perpendicular to the Y direction. The fifth layer includes a power trace 31 and an output trace 32 located on different wiring tracks.

[0238] The power supply line 31 coincides with the first through hole 21 and the second electrode 13 of the first vertical transistor, so that in the chip, the power supply line 31 is electrically connected to the second electrode 13 of the first vertical transistor through the first through hole 21. The output line 32 coincides with the second through hole 23 and the second electrode 13 of the Mth vertical transistor, so that in the chip, the output line 32 is electrically connected to the second electrode 13 of the Mth vertical transistor through the second through hole 23.

[0239] Those skilled in the art should know that Figure 8b As shown, the layout is a planar structure, which reflects the stacking relationship of each structure in the standard unit without using layers. As mentioned above, the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are stacked in sequence, which is reflected on the chip. The patterns contained in the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are stacked along the Z direction.

[0240] When drawing the layout, you can also draw it in the order of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

[0241] Specifically, after obtaining the circuit diagram of the standard unit, such as Fig.19a As shown, according to the circuit diagram, one or more first sublayers arranged side by side along the X direction in the first layer are first drawn, and the first electrode 11 of the i-th vertical transistor and the first electrode 11 of the i+1-th vertical transistor share the same first sublayer.

[0242] Then, if Fig.19b As shown, according to the circuit diagram, the gate electrodes 12 of the M vertical transistors in the second layer and the second electrodes 13 of the M vertical transistors in the third layer are drawn in sequence. The first spacer layer and the second spacer layer may not be drawn in the layout.

[0243] Among some possible implementations, Fig.19b As shown, the channel layer 14 is located on the chip through the second electrode 13, the gate 12, and the first electrode 11, and in the layout of the standard unit, the channel layer 14 can be located in the first layer, the second layer, and the third layer; or, the channel layer 14 can also be located in the sixth layer, and the sixth layer is drawn after the third layer and before the fourth layer.

[0244] Then, if Fig.19c As shown, according to the circuit diagram, the first through hole 21 and the second through hole 23 in the fourth layer are drawn. There is no need to draw the dielectric layer in the layout.

[0245] Among some possible implementations, Fig.19c As shown, the fourth layer may further include a first gate through hole 221 and a second gate through hole 222. The first gate through hole 221 and the second gate through hole 222 are staggered in the Y direction.

[0246] Then, if Figure 8b As shown, according to the circuit diagram, the power supply wiring 31 and the output wiring 32 in the fifth layer are drawn.

[0247] Among some possible implementations, Figure 8b As shown, the fifth layer also includes a first gate trace 341 and a second gate trace 342 located on different wiring tracks. The first gate trace 341 overlaps with the first gate through hole 221 and the gate 12 of the i-th vertical transistor, so that in the chip, the first gate trace 341 is electrically connected to the gate 12 of the i-th vertical transistor through the first gate through hole 221. The second gate trace 342 overlaps with the second gate through hole 222 and the gate 12 of the i+1-th vertical transistor, so that in the chip, the second gate trace 342 is electrically connected to the gate 12 of the i+1-th vertical transistor through the second gate through hole 222.

[0248] In some possible implementations, the second gate wiring 342, the power wiring 31, and the output wiring 32 are arranged in sequence along the Y direction, and the first gate wiring 341 and the power wiring 31 share the same wiring track and are disconnected. Alternatively, the second gate wiring 342, the output wiring 32, and the power wiring 31 are arranged in sequence along the Y direction, and the first gate wiring 341 and the output wiring 32 share the same wiring track and are disconnected. In this way, the number of wiring tracks in the standard unit can be reduced, the size of the chip in the Y direction can be greatly reduced, and the chip area can be reduced.

[0249] In some embodiments, if M>2, in order to realize the series connection of M vertical transistors, in addition to the first electrode 11 of the i-th vertical transistor and the first electrode 11 of the i+1-th vertical transistor sharing the same first sub-pattern, the layout of the standard cell also includes a seventh layer, the seventh layer includes one or more second sub-patterns, and the second electrode 13 of the j-th vertical transistor and the second electrode 13 of the j+1-th vertical transistor share the same second sub-pattern. Wherein, j is an even number less than M. Wherein, the second sub-pattern corresponds to the conductive layer 15 in the aforementioned chip.

[0250] In some embodiments, the circuit layout database also includes layer information, which includes graphic border information, graphic filler information, and graphic color information of the first layer, the second layer, the third layer, the fourth layer, the fifth layer, and the sixth layer. The layer information can be stored in the circuit layout database in text format.

[0251] For example, Fig. 20 As shown, the graphic borders of all graphics in the first layer including the first pole (bottom source drain, btm SD) 11 are solid lines, the graphic fillings are denser dots, and the graphic color is black; the graphic borders of all graphics in the second layer including the gate (Gate) 12 are solid lines, the graphic fillings are sparser dots, and the graphic color is black; the graphic borders of all graphics in the third layer including the second pole (top source drain, top SD) 13 are solid lines, the graphic fillings are oblique lines, and the graphic color is black.

[0252] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as the explanations and beneficial effects of a chip in the aforementioned embodiment, and will not be repeated here.

[0253] In another embodiment, the present application provides a chip design method. After obtaining the above-mentioned circuit layout database, the designer can directly call one or more required standard cells from the circuit layout database to design other circuit layouts using the one or more standard cells. Specifically, based on the designer's operation, the device storing the circuit layout database receives a target instruction, and in response to the target instruction, calls one or more standard cells in the circuit layout database described in the previous embodiment.

[0254] It is understandable that, in order to realize the above functions, the electronic device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0255] In one example, Fig.21 A schematic block diagram of a device 300 according to an embodiment of the present application is shown. The device 300 may include: a processor 301 and a transceiver / transceiver pin 302 , and optionally, a memory 303 .

[0256] The components of the device 300 are coupled together via a bus 304, wherein the bus 304 includes a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, all buses are referred to as bus 304 in the figure.

[0257] Optionally, the memory 303 may be used for instructions in the aforementioned method embodiment. The processor 301 may be used to execute instructions in the memory 303, and control the receiving pin to receive a signal, and control the sending pin to send a signal.

[0258] The apparatus 300 may be the electronic device or a chip of the electronic device in the above method embodiment.

[0259] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0260] This embodiment also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the chip design method in the above-mentioned embodiment.

[0261] This embodiment also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the above-mentioned related steps to implement the chip design method in the above-mentioned embodiment.

[0262] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor can execute the computer execution instructions stored in the memory so that the chip executes the chip design method in the above-mentioned method embodiments.

[0263] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.

[0264] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0265] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0266] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0267] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0268] Any content of each embodiment of the present application, as well as any content of the same embodiment, can be freely combined. Any combination of the above content is within the scope of the present application.

[0269] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0270] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip, characterized in that: The invention comprises a standard cell arranged on a substrate, wherein the standard cell comprises: M vertical transistors are connected in series and arranged side by side along a first direction, where M is an even number; along a second direction perpendicular to the substrate, the vertical transistor comprises a first electrode, a gate, a second electrode stacked in sequence, and a channel layer running through the second electrode, the gate, and the first electrode; the first electrode is located between the substrate and the gate, the first electrode of the i-th vertical transistor is shared with the first electrode of the i+1-th vertical transistor, and i is an odd number less than M; a dielectric layer covering the M vertical transistors; the dielectric layer is provided with a first through hole and a second through hole, the first through hole and the second through hole are staggered in a third direction; the first direction is perpendicular to the second direction, and the first direction and the second direction are both perpendicular to the third direction; A power line and an output line are arranged in the same layer and located on different wiring tracks; the power line is electrically connected to the second pole of the first vertical transistor through the first through hole, and the output line is electrically connected to the second pole of the Mth vertical transistor through the second through hole.

2. The chip according to claim 1, characterized in that: The channel layer of the first vertical transistor and the channel layer of the Mth vertical transistor are staggered in the third direction.

3. The chip according to claim 1 or 2, characterized in that: The dielectric layer is further provided with a first gate through hole and a second gate through hole, wherein the first gate through hole and the second gate through hole are staggered in the third direction; The standard cell further includes a first gate wiring and a second gate wiring located on different wiring tracks; the first gate wiring is electrically connected to the gate of the i-th vertical transistor through the first gate through hole, and the second gate wiring is electrically connected to the gate of the i+1-th vertical transistor through the second gate through hole; The first gate wiring and the second gate wiring are arranged on the same layer as the power wiring and the output wiring.

4. The chip according to claim 3, characterized in that: The second gate wiring, the power wiring, and the output wiring are arranged in sequence along the third direction; The first gate wiring and the power wiring share the same wiring track and are disconnected.

5. The chip according to claim 3, characterized in that: The second gate wiring, the output wiring, and the power wiring are arranged in sequence along the third direction; The first gate wiring and the output wiring share the same wiring track and are disconnected.

6. The chip according to claim 3 or 5, characterized in that: The power supply wiring is located outside the output wiring.

7. The chip according to claim 6, characterized in that: The standard cell is a two-input NAND gate; M=2, the two vertical transistors connected in series include a first vertical transistor and a second vertical transistor, the power supply line includes a first power supply line, and the output line includes a first output line; the standard unit also includes a first transistor, a second transistor, a second power supply line, and a second output line; The gate of the first transistor is electrically connected to the gate of the first vertical transistor, the first electrode of the first transistor is electrically connected to the second power supply wiring, and the second electrode of the first transistor is electrically connected to the second output wiring; The gate of the second transistor is electrically connected to the gate of the second vertical transistor, the first electrode of the second transistor is electrically connected to the second power supply wiring, and the second electrode of the second transistor is electrically connected to the second output wiring; The second electrode of the first vertical transistor is electrically connected to the first power supply line through the first through hole, the first electrode of the first vertical transistor is shared with the first electrode of the second vertical transistor, and the second electrode of the second vertical transistor is electrically connected to the first output line through the second through hole.

8. The chip according to claim 7, characterized in that: The first transistor and the first vertical transistor share the same gate, and the gate of the first transistor and the gate of the first vertical transistor are electrically connected to the first gate wiring through the first gate through hole; The second transistor and the second vertical transistor share the same gate, and the gate of the second transistor and the gate of the second vertical transistor are electrically connected to the second gate wiring through the second gate through hole; The first gate wiring and the output wiring are located in different wiring tracks; or the first gate wiring and the output wiring are located in the same wiring track and are disconnected.

9. The chip according to any one of claims 3 to 6, characterized in that: The standard cell is a two-input AND-NOR gate; M=2, the two vertical transistors connected in series include a first vertical transistor and a second vertical transistor, and the two vertical transistors connected in series include a third vertical transistor and a fourth vertical transistor; The second electrode of the second vertical transistor and the second electrode of the fourth vertical transistor are electrically connected to the power supply line through the first through hole; the first electrode of the second vertical transistor is shared with the first electrode of the first vertical transistor; the second electrode of the first vertical transistor and the second electrode of the third vertical transistor are electrically connected to the output line through the second through hole; the first electrode of the third vertical transistor is shared with the first electrode of the fourth vertical transistor.

10. The chip according to any one of claims 3 to 6, characterized in that: When M is greater than 2, the standard cell further includes a conductive layer disposed between the vertical transistor and the dielectric layer; The second electrode of the jth vertical transistor and the second electrode of the j+1th vertical transistor are electrically connected through the conductive layer; wherein j is an even number less than M.

11. The chip according to claim 10, characterized in that: The standard cell is a four-input NAND gate; M=4, the four vertical transistors connected in series include a first vertical transistor, a second vertical transistor, a third vertical transistor, and a fourth vertical transistor; The second electrode of the first vertical transistor is electrically connected to the power supply line through the first through hole, and the second electrode of the fourth vertical transistor is electrically connected to the output line through the second through hole; The first electrode of the first vertical transistor is shared by the first electrode of the second vertical transistor, and the first electrode of the third vertical transistor is shared by the first electrode of the fourth vertical transistor; The second electrode of the second vertical transistor and the second electrode of the third vertical transistor are electrically connected through the conductive layer.

12. An electronic device, characterized in that: It comprises a circuit board and the chip according to any one of claims 1 to 11, wherein the chip is arranged on the circuit board.

13. A method for preparing a chip, characterized in that: The chip includes a standard unit, and the preparation method of the standard unit includes: M vertical transistors are formed in series and arranged side by side along a first direction on a substrate, where M is an even number; along a second direction perpendicular to the substrate, the vertical transistor includes a first electrode, a gate, a second electrode, and a channel layer that runs through the second electrode, the gate, and the first electrode, which are stacked in sequence; the first electrode is located between the substrate and the gate, and the first electrode of the i-th vertical transistor is shared with the first electrode of the i+1-th vertical transistor, where i is an odd number less than M; A dielectric layer covering the M vertical transistors is formed; the dielectric layer is provided with a first through hole and a second through hole, the first through hole and the second through hole are staggered in a third direction; the first direction is perpendicular to the second direction, and the first direction and the second direction are both perpendicular to the third direction; A power line and an output line are formed on the dielectric layer in the same layer and located on different wiring tracks; the power line is electrically connected to the second pole of the first vertical transistor through the first through hole, and the output line is electrically connected to the second pole of the Mth vertical transistor through the second through hole.

14. The preparation method according to claim 13, characterized in that: Forming the channel layers of the M vertical transistors, comprising: Forming M channel layer middle patterns on the substrate; the channel layer middle patterns are arranged side by side along the first direction and are of equal length in the third direction; The middle patterns of the M channel layers are cut to obtain the channel layers of the M vertical transistors; along the third direction, the length of the channel layer is less than the length of the middle pattern of the channel layer; the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction.

15. The preparation method according to claim 13 or 14, characterized in that: The dielectric layer is further provided with a first gate through hole and a second gate through hole, wherein the first gate through hole and the second gate through hole are staggered in the third direction; The standard cell further includes a first gate wiring and a second gate wiring located on different wiring tracks; the first gate wiring is electrically connected to the gate of the i-th vertical transistor through the first gate through hole, and the second gate wiring is electrically connected to the gate of the i+1-th vertical transistor through the second gate through hole; The first gate wiring and the second gate wiring are arranged on the same layer as the power wiring and the output wiring.

16. The preparation method according to claim 14, characterized in that: The second gate line, the power line, and the output line are arranged in sequence along the third direction; the first gate line and the power line share the same wiring track and are disconnected; or, The second gate wiring, the output wiring, and the power wiring are arranged in sequence along the third direction; the first gate wiring and the output wiring share the same wiring track and are disconnected.

17. The preparation method according to any one of claims 13 to 16, characterized in that: When M is greater than 2, after forming M vertical transistors connected in series and arranged side by side along the first direction on the substrate and before forming a dielectric layer covering the M vertical transistors, the preparation method further includes: A conductive layer is formed; the second electrode of the jth vertical transistor and the second electrode of the j+1th vertical transistor are electrically connected through the conductive layer; wherein j is an even number less than M.

18. A circuit layout database, characterized in that: It includes a plurality of standard cells, each of which includes a layout and a circuit diagram of the standard cell; the standard cell includes M vertical transistors connected in series, where M is an even number; The layout of the standard cell includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer stacked in sequence; The first layer includes one or more first sublayers arranged side by side along a first direction, the first electrode of the i-th vertical transistor and the first electrode of the i+1-th vertical transistor share the same first sublayer, and i is an odd number less than M; The second layer includes gate electrodes of the M vertical transistors, and the third layer includes second electrodes of the M vertical transistors; The fourth layer includes a first through hole and a second through hole, and the first through hole and the second through hole are staggered in a third direction; wherein, in the layout, the first direction is perpendicular to the third direction; The fifth layer includes a power line and an output line located on different wiring tracks; the power line coincides with the first through hole and the second pole of the first vertical transistor, and the output line coincides with the second through hole and the second pole of the Mth vertical transistor.

19. The circuit layout database according to claim 18, characterized in that: The channel layers of the M vertical transistors are located in the first layer, the second layer, and the third layer, and a single channel layer runs through the second electrode, the gate, and the first electrode of the vertical transistor in which it is located; wherein the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction; or, The layout of the standard unit also includes a sixth layer located between the third layer and the fourth layer, and the sixth layer includes the channel layer of the M vertical transistors; wherein the channel layer of the first vertical transistor is staggered with the channel layer of the Mth vertical transistor in the third direction.

20. The circuit layout database according to claim 18 or 19, characterized in that: The fourth layer further includes a first gate through hole and a second gate through hole, wherein the first gate through hole and the second gate through hole are staggered in the third direction; The fifth layer also includes a first gate routing and a second gate routing located on different wiring tracks; the first gate routing overlaps with the first gate through hole and the gate of the i-th vertical transistor, and the second gate routing overlaps with the second gate through hole and the gate of the i+1-th vertical transistor.

21. The circuit layout database according to claim 20, characterized in that: The second gate line, the power line, and the output line are arranged in sequence along the third direction; the first gate line and the power line share the same wiring track and are disconnected; or, The second gate wiring, the output wiring, and the power wiring are arranged in sequence along the third direction; the first gate wiring and the output wiring share the same wiring track and are disconnected.

22. The circuit layout database according to any one of claims 18 to 21, characterized in that: The circuit layout database also includes layer information, and the layer information includes graphic border information, graphic fill information, and graphic color information of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

23. A chip design method, characterized in that: include: receiving target instructions; In response to the target instruction, one or more standard cells in the circuit layout database of any one of claims 18-22 are called.

24. A circuit layout design device, characterized in that: include: A memory and a processor, wherein the memory is electrically connected to the processor; The memory stores program instructions, and when the program instructions are executed by the processor, the electronic device executes the chip design method described in claim 23.

25. A computer-readable storage medium comprising a computer program, characterized in that: When the computer program runs on an electronic device, the electronic device executes the chip design method according to claim 23.

26. A computer program product, characterized in that When the computer program product is run on a computer, the computer is enabled to execute the chip design method as claimed in claim 23 .

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