Complementary field effect transistor and inverter circuit

Abstract

The invention relates to the technical field of integrated circuit devices, and discloses a complementary field effect transistor and an inverter circuit, and the complementary field effect transistor comprises a P-type tunneling field effect transistor which comprises an N-type doped source region, a first socket layer, a first body region, a first grid electrode, a first oxide layer and a P-type doped drain region; the N-type tunneling field effect transistor comprises a P-type doped source region, a second socket layer, a second body region, a second grid electrode, a second oxide layer and an N-type doped drain region; wherein the first body region is connected with the second body region to form an intrinsic region of the complementary field effect transistor, and the first drain terminal electrode is connected with the second drain terminal electrode. According to the embodiment of the invention, an intrinsic region does not need to be doped, only the P-type tunneling field effect transistor and the N-type tunneling field effect transistor need to be subjected to source-drain doping, so that a complementary field effect transistor structure can be formed, and the electrical property of the phase inverter formed by the complementary field effect transistor can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit devices, for example, to a complementary field effect transistor and an inverter circuit. Background Art

[0002] The working principle of CMOS (Complementary Metal Oxide Semiconductor) inverter is based on the complementary characteristics of PMOS (Positive-channel Metal Oxide Semiconductor) and NMOS (Negative-channel Metal Oxide Semiconductor). CMOS inverter consists of a PMOS transistor and a parallel NMOS transistor. When the input signal is high, the NMOS transistor is turned on, the PMOS transistor is cut off, and the output signal is low; when the input signal is low, the PMOS transistor is turned on, the NMOS transistor is cut off, and the output signal is high. By controlling the input signal, the CMOS inverter can achieve the logic inversion between the input and output signals.

[0003] In the related art, a CMOS inverter is formed by performing N-type doping on a P-type substrate to form an N-well, then performing source and drain doping in the N-well to form a PMOS structure, and performing source and drain doping on a P-type substrate to form an NMOS structure.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The CMOS inverter structure in the related art needs to implement a complex doping structure, which easily forms a variety of parasitic junctions and affects the electrical characteristics of the inverter.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a complementary field effect transistor and an inverter circuit to improve the electrical characteristics of an inverter composed of complementary field effect transistors.

[0009] In some embodiments, a complementary field effect transistor includes: a P-type tunneling field effect transistor, including an N-type doped source region, a first pocket layer, a first body region, a first gate, a first oxide layer, and a P-type doped drain region; the N-type doped source region is used to connect to the first source terminal electrode and is connected to the first body region through the first pocket layer; the first gate is connected to the first body region through the first oxide layer; the P-type doped drain region is used to connect to the first drain terminal electrode and is connected to the first body region; an N-type tunneling field effect transistor, including a P-type doped source region, a second pocket layer, a second body region, a second gate, a second oxide layer, and an N-type doped drain region; the P-type doped source region is used to connect to the second source terminal electrode and is connected to the second body region through the second pocket layer; the second gate is connected to the second body region through the second oxide layer; the N-type doped drain region is used to connect to the second drain terminal electrode and is connected to the second body region; wherein the first body region is connected to the second body region to form an intrinsic region of the complementary field effect transistor; the first drain terminal electrode is connected to the second drain terminal electrode.

[0010] Optionally, the first body region and the second body region are both L-shaped, and the vertical portion of the first body region is connected to the vertical portion of the second body region; wherein the N-type doped source region is arranged at the end of the horizontal portion of the first body region, and a first pocket layer is arranged between the N-type doped source region and the first body region, and the P-type doped drain region is arranged at the top of the vertical portion of the first body region; and / or, the P-type doped source region is arranged at the end of the horizontal portion of the second body region, and a second pocket layer is arranged between the P-type doped source region and the second body region, and the N-type doped drain region is arranged at the top of the vertical portion of the second body region.

[0011] Optionally, the first source terminal electrode is arranged on a side of the N-type doped source region relative to the first pocket layer; and / or the second source terminal electrode is arranged on a side of the P-type doped source region relative to the second pocket layer.

[0012] Optionally, the first drain terminal electrode is disposed on the top of the P-type doped drain region; and / or the second drain terminal electrode is disposed on the top of the N-type doped drain region.

[0013] Optionally, the first oxide layer is L-shaped, the horizontal portion of the first oxide layer is arranged on the top of the horizontal portion of the first body region, and the horizontal portion of the first oxide layer covers a portion of the surface of the first pocket layer; the vertical portion of the first oxide layer is connected to the vertical portion of the first body region, and the top of the vertical portion of the first oxide layer is flush with the top of the vertical portion of the first body region; and / or, the second oxide layer is L-shaped, the horizontal portion of the second oxide layer is arranged on the top of the horizontal portion of the second body region, and the horizontal portion of the second oxide layer covers a portion of the surface of the second pocket layer; the vertical portion of the second oxide layer is connected to the vertical portion of the second body region, and the top of the vertical portion of the second oxide layer is flush with the top of the vertical portion of the second body region.

[0014] Optionally, the first gate is arranged at the top of the horizontal part of the first oxide layer, the top of the first gate is flush with the top of the vertical part of the first oxide layer, and the side of the first gate is flush with the side of the horizontal part of the first oxide layer; and / or, the second gate is arranged at the top of the horizontal part of the second oxide layer, the top of the second gate is flush with the top of the vertical part of the second oxide layer, and the side of the second gate is flush with the side of the horizontal part of the second oxide layer.

[0015] Optionally, the first pocket layer is P-type doped, and the thickness of the first pocket layer is in the range of [7nm, 12nm]; and / or, the second pocket layer is N-type doped, and the thickness of the second pocket layer is in the range of [7nm, 12nm].

[0016] Optionally, there is a first distance between the first gate and the N-type doped source region, and the range of the first distance is [4nm, 8nm]; and / or there is a second distance between the second gate and the P-type doped source region, and the range of the second distance is [4nm, 8nm].

[0017] Optionally, a work function of a material of the first gate is greater than a work function of a material of the second gate.

[0018] In some embodiments, the inverter circuit includes: a complementary field effect transistor as described above; wherein the first gate electrode and the second gate electrode are connected, serving as the input terminal of the inverter circuit; the first drain electrode and the second drain electrode are connected, serving as the output terminal of the inverter circuit; the first source electrode is connected to a power supply; and the second source electrode is grounded.

[0019] The complementary field effect transistor and inverter circuit provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The complementary field-effect transistor (CTFET) provided in the embodiment of the present disclosure includes a P-type tunneling field-effect transistor (PTFET) and an N-type tunneling field-effect transistor (NTFET), and the first body region of the PTFET is connected to the second body region of the NTFET to form the intrinsic region of the CTFET. Therefore, the CTFET does not need to dope the intrinsic region, and only needs to dope the source and drain of the PTFET and the NTFET to form the CTFET structure provided in the embodiment of the present disclosure. The inverter circuit formed by the CTFET simplifies the doping structure compared with the N-well and P-well doping processes in the related art, which can reduce the formation of parasitic junctions, help to improve the switching speed of the circuit and reduce power consumption. Reducing parasitic junctions can also reduce the reliability problems of the circuit when running at high speed, such as reducing leakage current and improving noise tolerance, thereby improving the overall performance of the circuit. In addition, since there is no need to dope the device body region, the manufacturing process of CTFET is simplified, which helps to reduce manufacturing costs and improve production efficiency. The CTFET structure can also reduce the area of ​​the inverter by sharing a body region with PTFET and NTFET, thereby achieving high-density integration of integrated circuits.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a schematic structural diagram of a complementary field effect transistor provided by an embodiment of the present disclosure;

[0024] Figure 2 It is a schematic diagram of the structure of an equivalent PTFET in a complementary field effect transistor provided by an embodiment of the present disclosure;

[0025] Figure 3 It is a schematic diagram of the structure of an equivalent NTFET in a complementary field effect transistor provided by an embodiment of the present disclosure;

[0026] Figure 4 It is a circuit diagram of an inverter circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0028] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0029] Unless otherwise stated, the term "plurality" means two or more.

[0030] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0031] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0032] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0033] Combination Figure 1 , Figure 2 , Figure 3 As shown, an embodiment of the present disclosure provides a complementary field effect transistor, including a P-type tunneling field effect transistor and an N-type tunneling field effect transistor.

[0034] The P-type tunneling field effect transistor includes an N-type doped source region N1, a first pocket layer k1, a first body region Sc1, a first gate G1, a first oxide layer O1, and a P-type doped drain region P1; the N-type doped source region N1 is used to connect to the first source terminal electrode S1, and is connected to the first body region Sc1 through the first pocket layer k1; the first gate G1 is connected to the first body region Sc1 through the first oxide layer O1; the P-type doped drain region P1 is used to connect to the first drain terminal electrode D1, and is connected to the first body region Sc1.

[0035] The N-type tunneling field effect transistor includes a P-type doped source region P2, a second pocket layer k2, a second body region Sc2, a second gate G2, a second oxide layer O2, and an N-type doped drain region N2; the P-type doped source region P2 is used to connect to the second source terminal electrode S2, and is connected to the second body region Sc2 through the second pocket layer k2; the second gate G2 is connected to the second body region Sc2 through the second oxide layer O2; the N-type doped drain region N2 is used to connect to the second drain terminal electrode D2, and is connected to the second body region Sc2.

[0036] The first body region Sc1 is connected to the second body region Sc2 to form an intrinsic region of a complementary field effect transistor; and the first drain electrode D1 is connected to the second drain electrode D2.

[0037] In the embodiment of the present disclosure, the first body region Sc1 of the PTFET is connected to the second body region Sc2 of the NTFET to form the intrinsic region of the CTFET. Therefore, the CTFET does not need to dope the intrinsic region, and only needs to dope the source and drain of the PTFET and the NTFET to form the CTFET structure provided by the embodiment of the present disclosure. The inverter circuit formed by the CTFET simplifies the doping structure compared with the N-well and P-well doping processes in the related art, which can reduce the formation of parasitic junctions, help to improve the switching speed of the circuit and reduce power consumption. Reducing parasitic junctions can also reduce the reliability problems of the circuit when running at high speed, such as reducing leakage current and improving noise tolerance, thereby improving the overall performance of the circuit. In addition, since there is no need to dope the device body region, the manufacturing process of the CTFET is simplified, which helps to reduce manufacturing costs and improve production efficiency. The CTFET structure can also reduce the area of ​​the inverter by sharing a body region with the PTFET and the NTFET, thereby realizing high-density integration of integrated circuits.

[0038] Optionally, combined Figure 1 As shown, the first body region Sc1 and the second body region Sc2 are both L-shaped, and the vertical portion of the first body region Sc1 is connected to the vertical portion of the second body region Sc2.

[0039] In this embodiment, the first body region Sc1 and the second body region Sc2 are designed to be L-shaped. Figure 1 The vertical portion of the first body region Sc1 is connected to the vertical portion of the second body region Sc2 in the form of the circuit, thereby enhancing the symmetry of the circuit. The first body region Sc1 of the PTFET and the second body region Sc2 of the NTFET are connected to form the intrinsic region of the CTFET, thereby enhancing the complementarity of the CTFET and making the electrical characteristics of the PTFET and the NTFET more matched.

[0040] Optionally, combined Figure 1As shown, the N-type doped source region N1 is arranged at the end of the horizontal part of the first body region Sc1, and the first pocket layer k1 is arranged between the N-type doped source region N1 and the first body region Sc1, and the P-type doped drain region P1 is arranged at the top of the vertical part of the first body region Sc1; and / or, the P-type doped source region P2 is arranged at the end of the horizontal part of the second body region Sc2, and the second pocket layer k2 is arranged between the P-type doped source region P2 and the second body region Sc2, and the N-type doped drain region N2 is arranged at the top of the vertical part of the second body region Sc2.

[0041] Optionally, the first pocket layer k1 is P-type doped, and the P-type impurity concentration range is [3×10 16 cm -3 , 3×10 19 cm -3 ]; and / or, the second pocket layer k2 is N-type doped, and the N-type impurity concentration range is [3×10 16 cm -3 , 3×10 19 cm -3 ].

[0042] In this embodiment, the N-type doped source region N1 of the PTFET is connected to the first body region Sc1 through the first pocket layer k1, and the P-type doped source region P2 of the NTFET is connected to the second body region Sc2 through the second pocket layer k2. Therefore, the first pocket layer k1 and the second pocket layer k2 are a highly doped region located near the source region, which can increase the tunneling probability of holes or electrons, thereby increasing the on-current of the transistor. The pocket layer with a high doping concentration can increase the hole concentration near the source region, and form more holes under the action of the gate voltage, thereby increasing the on-current of the transistor. By increasing the tunneling probability of holes, the pocket layer helps to improve the switching speed and overall performance of the transistor. In addition, the highly doped pocket layer helps to reduce the short channel effect, and the reliability of the transistor can be improved by optimizing the doping concentration.

[0043] Optionally, combined Figure 2 , Figure 3 As shown, the thickness L5 of the first pocket layer k1 is in the range of [7 nm, 12 nm]; and / or, the thickness L6 of the second pocket layer k2 is in the range of [7 nm, 12 nm].

[0044] In this embodiment, the thickness of the pocket layer directly affects the tunneling probability of holes or electrons. A thinner pocket layer can increase the tunneling probability, thereby increasing the on-current of the transistor. By adjusting the thickness of the pocket layer, the threshold voltage can be optimized to achieve better control characteristics and lower power consumption. The appropriate thickness of the pocket layer can also reduce the short channel effect and improve the reliability of the transistor. In CTFET, the thickness of the pocket layer helps to achieve a better match between PTFET and NTFET, thereby improving the performance of the entire circuit.

[0045] Optionally, combined Figure 1 As shown, the first source terminal electrode S1 is disposed on one side of the N-type doped source region N1 relative to the first pocket layer k1; and / or the second source terminal electrode S2 is disposed on one side of the P-type doped source region P2 relative to the second pocket layer k2.

[0046] Optionally, combined Figure 1 As shown, the first drain electrode D1 is disposed on the top of the P-type doped drain region P1; and / or the second drain electrode D2 is disposed on the top of the N-type doped drain region N2.

[0047] Optionally, the N-type impurity concentration of the N-type doping source region N1 is in the range of [1×10 18 cm -3 , 1×10 21 cm -3 ], the P-type impurity concentration range of the P-type doped drain region P1 is [1×10 17 cm -3 , 1×10 20 cm -3 ]; and / or, the P-type impurity concentration range of the P-type doping source region P2 is [1×10 18 cm -3 , 1×10 21 cm -3 ], the N-type impurity concentration range of the N-type doped drain region N2 is [1×10 17 cm -3 , 1×10 20 cm -3 ].

[0048] In this embodiment, the doping types of PTFET and NTFET are both PIN type, that is, P-type doping region, intrinsic region, and N-type doping region. The difference is that the source and drain doping types of the two are opposite. Taking the N-type doped source region N1 and the P-type doped drain region P1 of PTFET as an example, the high concentration of N-type doping helps to create a high electron concentration region in the source region, thereby forming a conductive channel under the control of the gate voltage, and the relatively low P-type doping concentration helps to form a lower hole concentration in the drain region, thereby optimizing the conductivity of the device and reducing leakage current. Appropriate doping concentration can adjust the threshold voltage of the device, thereby achieving better control characteristics. By optimizing the doping concentration, the switching speed of the device can also be increased, power consumption can be reduced, and overall performance can be improved.

[0049] Optionally, combined Figure 2 , Figure 3 As shown, the thickness T1 of the N-type doped source region N1 ranges from [10nm, 20nm], and the width L1 ranges from [40nm, 60nm]; and / or, the thickness T2 of the P-type doped drain region P1 ranges from [20nm, 40nm], and the width L2 ranges from [20nm, 40nm]; and / or, the thickness T3 of the P-type doped source region P2 ranges from [10nm, 20nm], and the width L3 ranges from [40nm, 60nm]; and / or, the thickness T4 of the N-type doped drain region N2 ranges from [20nm, 40nm], and the width L4 ranges from [20nm, 40nm].

[0050] In this embodiment, the thickness and width of the source region determine the movement path of the charge carriers from the source region to the channel, and the appropriate size can improve the movement efficiency of the charge carriers. The thickness and width of the drain region directly affect the collection efficiency of the charge carriers from the channel to the drain region, and the appropriate drain region size can increase the switching speed of the transistor and reduce the leakage current. In addition, the size of the source region and the drain region will also affect the electrical properties of the transistor, such as the threshold voltage and conductivity, and the appropriate size can achieve better electrical properties.

[0051] Optionally, combined Figure 1As shown, the first oxide layer O1 is L-shaped, the horizontal portion of the first oxide layer O1 is arranged on the top of the horizontal portion of the first body region Sc1, and the horizontal portion of the first oxide layer O1 covers a portion of the surface of the first pocket layer k1; the vertical portion of the first oxide layer O1 is connected to the vertical portion of the first body region Sc1, and the top of the vertical portion of the first oxide layer O1 is flush with the top of the vertical portion of the first body region Sc1; and / or, the second oxide layer O2 is L-shaped, the horizontal portion of the second oxide layer O2 is arranged on the top of the horizontal portion of the second body region Sc2, and the horizontal portion of the second oxide layer O2 covers a portion of the surface of the second pocket layer k2; the vertical portion of the second oxide layer O2 is connected to the vertical portion of the second body region Sc2, and the top of the vertical portion of the second oxide layer O2 is flush with the top of the vertical portion of the second body region Sc2.

[0052] Optionally, combined Figure 2 , Figure 3 As shown, the thickness T7 of the first oxide layer O1 is in the range of [3 nm, 7 nm]; and / or, the thickness T8 of the second oxide layer O2 is in the range of [3 nm, 7 nm].

[0053] In this embodiment, the oxide layer acts as an insulating layer between the gate and the body region, preventing the current from flowing directly from the gate to the body region, ensuring that the gate can control the charge distribution on the body region through an electric field rather than current. The oxide layer forms a capacitor together with the gate and the body region, and the change of the gate voltage will change the charge on this capacitor, thereby controlling the charge distribution on the body region and the conductivity of the transistor. The thickness and quality of the oxide layer directly affect the threshold voltage of the transistor. By adjusting the thickness of the oxide layer, the switching characteristics of the transistor can be accurately controlled. In addition, the oxide layer prevents the charge of the gate from being injected into the body region, and the high-quality oxide layer can also reduce the gate leakage current and reduce the parasitic capacitance of the transistor. The thickness of the oxide layer directly affects the capacitance between the gate and the channel. A thinner oxide layer can increase the capacitance, thereby improving the switching speed of the transistor.

[0054] Optionally, combined Figure 1 As shown, the first gate G1 is arranged at the top of the horizontal part of the first oxide layer O1, the top of the first gate G1 is flush with the top of the vertical part of the first oxide layer O1, and the side of the first gate G1 is flush with the side of the horizontal part of the first oxide layer O1; and / or, the second gate G2 is arranged at the top of the horizontal part of the second oxide layer O2, the top of the second gate G2 is flush with the top of the vertical part of the second oxide layer O2, and the side of the second gate G2 is flush with the side of the horizontal part of the second oxide layer O2.

[0055] Optionally, combined Figure 2 , Figure 3As shown, the length L7 of the first gate G1 ranges from [20nm, 40nm], and the vertical depth T5 of the first gate G1 ranges from [20nm, 40nm]; and / or, the length L8 of the second gate G2 ranges from [20nm, 40nm], and the vertical depth T6 of the second gate G2 ranges from [20nm, 40nm].

[0056] In this embodiment, the length of the gate directly determines the length of the channel, thereby affecting the switching speed and conductivity of the transistor. A shorter gate length can increase the switching speed. The size of the gate can affect the threshold voltage of the transistor. By adjusting the length and vertical depth of the gate, the threshold voltage can be optimized to achieve better control characteristics and lower power consumption. Appropriate gate size also helps to reduce short channel effects and improve the reliability of the transistor. In CTFET, the size of the gate helps to achieve a better match between PTFET and NTFET, thereby improving the performance of the entire circuit.

[0057] Optionally, combined Figure 2 , Figure 3 As shown, there is a first spacing L9 between the first gate G1 and the N-type doped source region N1, and the range of the first spacing L9 is [4nm, 8nm]; and / or, there is a second spacing L10 between the second gate G2 and the P-type doped source region P2, and the range of the second spacing L10 is [4nm, 8nm].

[0058] In this embodiment, the gate and the source region are not directly connected, but there is a certain distance between them. Under the action of the gate voltage, the charge carriers can tunnel from the source region to the body region through this spacing area to form a conductive channel. Therefore, this spacing can enhance the tunneling probability between the source end and the body region. By increasing the tunneling probability, this spacing can also increase the on-current of the CTFET, thereby improving the switching speed and overall performance of the CTFET.

[0059] Optionally, the work function of the material of the first gate G1 is greater than the work function of the material of the second gate G2.

[0060] Optionally, the work function range of the material of the first gate G1 is [4.7 eV, 7 eV]; and / or the work function range of the material of the second gate G2 is [3 eV, 4.2 eV].

[0061] In this embodiment, the gate materials with different work functions are used to achieve the complementary characteristics of PTFET and NTFET. The work function of the gate material refers to the energy required for electrons to jump from the metal gate to the semiconductor body. Different work function materials enable the transistor to respond to different voltage thresholds. Using a high work function material as the first gate of the PTFET, it is possible to attract electrons to form a conductive channel by a lower voltage, thereby reducing the threshold voltage. Using a low work function material as the second gate of the NTFET, it is possible to repel electrons by a higher voltage and increase the threshold voltage. PTFET is designed to attract holes, so a high work function material is required to reduce the gate voltage. NTFET is designed to attract electrons, so a low work function material is required to increase the gate voltage. High work function materials have a higher operating voltage, which helps to reduce the leakage current of the PTFET and improve the energy efficiency of the circuit. Low work function materials have a lower operating voltage, which helps to increase the switching speed of the NTFET. Therefore, by adjusting the work function of the gate material, the threshold voltage can be optimized to achieve better control characteristics and lower power consumption. The work function of the gate material also affects the switching characteristics of the transistor. An appropriate work function range helps to improve the switching speed and conductivity of the transistor.

[0062] Combination Figure 4 As shown, an embodiment of the present disclosure provides an inverter circuit, including: a complementary field effect transistor as described above; wherein the first gate G1 and the second gate G2 are connected, serving as the input terminal of the inverter circuit; the first drain electrode D1 and the second drain electrode D2 are connected, serving as the output terminal of the inverter circuit; the first source electrode S1 is connected to a power supply; and the second source electrode S2 is grounded.

[0063] In this embodiment, the first gate G1 of the PTFET and the second gate G2 of the NTFET are connected and serve as the input of the inverter circuit, so that the input signal can control the switch state of the PTFET and the NTFET at the same time, thereby realizing the logic inversion function. The first drain electrode D1 of the PTFET and the second drain electrode D2 of the NTFET are connected and serve as the output of the inverter circuit, so that the output signal can be switched between the two transistors, thereby realizing the output of high level and low level. The first source electrode S1 of the PTFET is connected to the power supply, usually connected to the positive power supply voltage. The second source electrode S2 of the NTFET is grounded and connected to the zero potential. When the PTFET or NTFET is turned on, electrons will be transmitted between the source terminal, the gate terminal, and the drain terminal in an "L" type flow. When the input terminal is at a low level, the first gate G1 is pulled low, so that the PTFET is turned on, and the second gate G2 is pulled high, so that the NTFET is turned off, and the current flows from the power supply through the PTFET to the output terminal, so that the output terminal is at a high level. When the input terminal is at a high level, the first gate G1 is pulled high, so that the PTFET is turned off, and the second gate G2 is pulled low, so that the NTFET is turned on, and the current flows from the output terminal through the NTFET to the ground, making the output terminal at a low level. In this way, the CTFET structure can realize the basic function of the CMOS inverter, that is, to invert the logic state of the input signal. This configuration is not only simple, but also can effectively realize the inversion of the signal while maintaining low power consumption and high reliability.

[0064] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A complementary field effect transistor, characterized in that: include: A P-type tunneling field effect transistor comprises an N-type doped source region, a first pocket layer, a first body region, a first gate, a first oxide layer, and a P-type doped drain region; the N-type doped source region is used to be connected to a first source terminal electrode and is connected to the first body region through the first pocket layer; the first gate is connected to the first body region through the first oxide layer; the P-type doped drain region is used to be connected to a first drain terminal electrode and is connected to the first body region; An N-type tunneling field effect transistor, comprising a P-type doped source region, a second pocket layer, a second body region, a second gate, a second oxide layer, and an N-type doped drain region; the P-type doped source region is used to connect to a second source terminal electrode, and is connected to the second body region through the second pocket layer; the second gate is connected to the second body region through the second oxide layer; the N-type doped drain region is used to connect to a second drain terminal electrode, and is connected to the second body region; The first body region is connected to the second body region to form an intrinsic region of a complementary field effect transistor; and the first drain terminal electrode is connected to the second drain terminal electrode.

2. The complementary field effect transistor according to claim 1, characterized in that: The first body region and the second body region are both L-shaped, and the vertical portion of the first body region is connected to the vertical portion of the second body region; Among them, the N-type doped source region is arranged at the end of the horizontal part of the first body region, and the first pocket layer is arranged between the N-type doped source region and the first body region, and the P-type doped drain region is arranged at the top of the vertical part of the first body region; and / or, the P-type doped source region is arranged at the end of the horizontal part of the second body region, and the second pocket layer is arranged between the P-type doped source region and the second body region, and the N-type doped drain region is arranged at the top of the vertical part of the second body region.

3. The complementary field effect transistor according to claim 2, characterized in that: The first source terminal electrode is arranged on one side of the N-type doped source region relative to the first pocket layer; and / or, The second source terminal electrode is arranged on one side of the P-type doped source region relative to the second pocket layer.

4. The complementary field effect transistor according to claim 2, characterized in that: The first drain terminal electrode is disposed on the top of the P-type doped drain region; and / or, The second drain terminal electrode is arranged on the top of the N-type doped drain region.

5. The complementary field effect transistor according to claim 2, characterized in that: The first oxide layer is L-shaped, the horizontal portion of the first oxide layer is arranged on the top of the horizontal portion of the first body region, and the horizontal portion of the first oxide layer covers a portion of the surface of the first pocket layer; the vertical portion of the first oxide layer is connected to the vertical portion of the first body region, and the top of the vertical portion of the first oxide layer is flush with the top of the vertical portion of the first body region; and / or, The second oxide layer is L-shaped, and the horizontal portion of the second oxide layer is arranged on the top of the horizontal portion of the second body region, and the horizontal portion of the second oxide layer covers a portion of the surface of the second pocket layer; the vertical portion of the second oxide layer is connected to the vertical portion of the second body region, and the top of the vertical portion of the second oxide layer is flush with the top of the vertical portion of the second body region.

6. The complementary field effect transistor according to claim 5, characterized in that: The first gate is disposed on the top of the horizontal portion of the first oxide layer, the top of the first gate is flush with the top of the vertical portion of the first oxide layer, and the side of the first gate is flush with the side of the horizontal portion of the first oxide layer; and / or, The second gate is arranged on the top of the horizontal part of the second oxide layer, the top of the second gate is flush with the top of the vertical part of the second oxide layer, and the side of the second gate is flush with the side of the horizontal part of the second oxide layer.

7. The complementary field effect transistor according to any one of claims 1 to 6, characterized in that: The first pocket layer is P-type doped, and the thickness of the first pocket layer is in the range of [7nm, 12nm]; and / or, The second pocket layer is N-type doped, and the thickness range of the second pocket layer is [7nm, 12nm].

8. The complementary field effect transistor according to any one of claims 1 to 6, characterized in that: There is a first distance between the first gate and the N-type doped source region, and the range of the first distance is [4 nm, 8 nm]; and / or, There is a second distance between the second gate and the P-type doped source region, and the range of the second distance is [4nm, 8nm].

9. The complementary field effect transistor according to any one of claims 1 to 6, characterized in that: The work function of the material of the first gate is greater than the work function of the material of the second gate.

10. An inverter circuit, characterized in that: include: A complementary field effect transistor as described in any one of claims 1 to 9; wherein the first gate electrode and the second gate electrode are connected as the input terminal of the inverter circuit; the first drain electrode and the second drain electrode are connected as the output terminal of the inverter circuit; the first source electrode is connected to the power supply; and the second source electrode is grounded.

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