Preparation method of solar cell, solar cell and photovoltaic module

Abstract

The invention discloses a preparation method of a solar cell, the solar cell and a photovoltaic module, and the preparation method comprises the following steps: providing a silicon wafer, the surface of which comprises a first region and a second region; sequentially forming a doping structure, a dielectric layer and a mask on the surface of the silicon wafer; carrying out patterning opening on the mask by adopting a laser process, and removing the mask in a first region; removing all the dielectric layer in the first region by adopting a wet etching process, and forming a window penetrating to the doping structure along the thickness direction of the silicon wafer in the dielectric layer; removing the mask in a second area on the surface of the dielectric layer; and preparing an electrode in contact with the doping structure at the window of the dielectric layer. According to the method, suede damage and passivation loss caused by windowing of the dielectric layer through laser and other processes can be remarkably reduced, a metallized structure with excellent electrical performance is obtained, the filling factor and the open-circuit voltage are remarkably improved, and the battery efficiency and the assembly power are greatly improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a method for preparing a solar cell, a solar cell and a photovoltaic module. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. Electrode metallization is one of the important processes of crystalline silicon solar cells.

[0003] In the existing metallization process, the dielectric layer is usually prepared first, then the dielectric layer is patterned (i.e., the window opening process), and finally the electrode is prepared in the window. The patterning process usually uses high-temperature processes such as lasers to form windows. During the patterning process, the silicon wafer will inevitably be damaged, thereby affecting the subsequent growth of the electrode at the window, resulting in excessive contact resistance and significantly reducing the fill factor of the battery, resulting in reduced battery efficiency and component efficiency.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a method for preparing a solar cell, a solar cell and a photovoltaic module. Summary of the invention

[0005] The purpose of the present invention is to provide a method for preparing a solar cell, a solar cell and a photovoltaic module, so as to obtain a metallization structure with excellent electrical performance and improve the cell efficiency and module power.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows: A method for preparing a solar cell, the method comprising the following steps: Providing a silicon wafer, wherein a surface of the silicon wafer includes a first area and a second area; forming a doping structure, a dielectric layer and a mask in sequence on the surface of the silicon wafer; Using a laser process to pattern the mask and remove the mask in the first area; Using a wet etching process to remove all dielectric layers in the first region, and forming a window in the dielectric layer that penetrates the doping structure along the thickness direction of the silicon wafer; removing the mask of the second area on the surface of the dielectric layer; An electrode in contact with the doping structure is prepared at the window of the dielectric layer.

[0007] In one embodiment, the mask is an amorphous silicon mask or a paraffin mask, and the thickness of the mask is 5nm-50nm.

[0008] In one embodiment, the amorphous silicon mask is an intrinsic amorphous silicon mask or a hydrogenated amorphous silicon mask.

[0009] In one embodiment, the amorphous silicon mask is deposited by using a PECVD process or a hot wire CVD process; or, The paraffin mask is prepared by inkjet printing process.

[0010] In one embodiment, the dielectric layer includes SiN X 、SiO X 、SiNO X One or more layers in the dielectric layer, the thickness of the dielectric layer is 20nm~150nm.

[0011] In one embodiment, the dielectric layer is deposited by using a PECVD process or a hot-filament CVD process.

[0012] In one embodiment, the preparation method further comprises: The mask is patterned and opened by using a laser process to remove the mask in the first area and a portion of the dielectric layer under the mask.

[0013] In one embodiment, the laser power of the laser process is 2W to 7W, and the pulse width is 10ps to 700ps; and / or, In the laser process, an ultraviolet picosecond laser or a green picosecond laser is used to perform patterned film opening.

[0014] In one embodiment, in the wet etching process, the etching solution is an acid solution, the reaction temperature is 25° C. to 45° C., and the reaction time is 100 s to 400 s.

[0015] In one embodiment, the acid solution is a hydrofluoric acid solution or a fluoride salt solution containing an acidic substance; and / or, The mass fraction of the acid solution is 1% to 4%.

[0016] In one embodiment, the width of the window is equal to the width of the laser film opening process; and / or, The width of the window is 1 μm to 25 μm.

[0017] In one embodiment, the preparation method further comprises: The mask in the second area on the surface of the dielectric layer is removed by using an alkaline solution, the reaction temperature is 60° C. to 80° C., and the reaction time is 100 s to 600 s.

[0018] In one embodiment, the alkaline solution is a sodium hydroxide solution or a potassium hydroxide solution; and / or, The mass fraction of the alkaline solution is 1% to 3%.

[0019] In one embodiment, the preparation method further comprises: The pyramid textured light-trapping structure is prepared on the surface of the silicon wafer by an alkali texture process.

[0020] In one embodiment, the preparation method further comprises: The silicon wafer after removing the mask is annealed at a temperature of 180° C. to 220° C. for a time of 10 min to 20 min.

[0021] In one embodiment, the preparation of the electrode includes: A seed layer is prepared at the window of the dielectric layer by using an electroplating or chemical plating process; The first metal layer is prepared on the outer side of the seed layer by electroplating or chemical plating.

[0022] In one embodiment, the preparation of the electrode further comprises: The second metal layer is prepared on the outer sides of the seed layer and the first metal layer by using an electroplating or chemical plating process.

[0023] In one embodiment, the material of the seed layer and the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The total thickness of the seed layer and the first metal layer is 1 μm to 15 μm; and / or, The thickness of the seed layer is 100nm to 500nm; and / or, The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer.

[0024] In one embodiment, the material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The thickness of the second metal layer is 1 μm to 5 μm.

[0025] In one embodiment, the electrode includes a first electrode portion that penetrates the window along the thickness direction of the silicon wafer and contacts the doping structure, and a second electrode portion that is located above the first electrode portion and extends to the surface of the dielectric layer, and the maximum width of the second electrode portion is greater than the maximum width of the first electrode portion.

[0026] In one embodiment, the width W1 of the top of the second electrode portion is smaller than the width W2 of the bottom of the second electrode portion, and the width of the top of the first electrode portion is equal to the width of the bottom of the first electrode portion.

[0027] In one embodiment, the maximum width of the first electrode portion is 1 μm to 25 μm, and the maximum width of the second electrode portion is less than or equal to 30 μm or is 5 μm to 15 μm; and / or, The distance between two adjacent electrodes is 500 μm to 1000 μm; and / or, The total thickness of the electrode is 5 μm to 20 μm.

[0028] In one embodiment, the solar cell is any one of a HJT cell, a PERC cell, a TOPCon cell, and an IBC cell.

[0029] In one embodiment, the doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer stacked in sequence on the surface of the silicon wafer, the window penetrates the transparent conductive layer along the thickness direction of the silicon wafer, and the electrode contacts the transparent conductive layer.

[0030] In one embodiment, the thickness of the transparent conductive layer is 15nm to 150nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO and TTO.

[0031] Another embodiment of the present invention provides a technical solution as follows: A solar cell is prepared by the above-mentioned preparation method.

[0032] Another embodiment of the present invention provides a technical solution as follows: A photovoltaic component comprises the above-mentioned solar cell.

[0033] Compared with the prior art, the present invention has the following beneficial effects: The present invention introduces a mask and adopts a wet etching process to open windows in the dielectric layer, which can significantly reduce the velvet damage and passivation loss caused by using laser and other processes to open windows in the dielectric layer, obtain a metallized structure with excellent electrical properties, and significantly improve the fill factor and open circuit voltage, thereby greatly improving the battery efficiency and component power. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 This is a schematic diagram of the structure of a heterojunction battery in Comparative Example 1 of the present invention; Figure 2 Schematic diagram of the structure of a heterojunction battery in Example 1 of the present invention; Figure 3 for Figure 2 A local enlarged schematic diagram of the middle A; Figure 4 is a schematic structural diagram of the first transparent conductive layer and the first dielectric layer in Example 1 of the present invention; Figure 5 is a schematic structural diagram of the first electrode in Example 1 of the present invention; Figure 6 is another structural schematic diagram of the first electrode in Example 1 of the present invention; Figure 7a~7h is a process flow chart of the heterojunction battery preparation method in Example 1 of the present invention; Figure 8 This is a schematic diagram of the structure of removing the mask and part of the dielectric layer by laser process in Embodiment 2 of the present invention; Fig. 9 Schematic diagram of the structure of a heterojunction battery in Example 4 of the present invention; Fig.10 for Fig. 9 A local enlarged schematic diagram of point B in the middle.

[0036] Description of reference numerals: 10'-silicon wafer, 21'-first intrinsic layer, 22'-second intrinsic layer, 31'-first doped layer, 32'-second doped layer, 41'-first transparent conductive layer, 42'-second transparent conductive layer, 51'-first electrode, 52'-second electrode; 10-silicon wafer, 21-first intrinsic layer, 22-second intrinsic layer, 31-first doped layer, 32-second doped layer, 41-first transparent conductive layer, 42-second transparent conductive layer, 501-inner dielectric layer, 502-outer dielectric layer, 51-first dielectric layer, 511-first window, 52-second dielectric layer, 521-second window, 601-seed layer, 602-first metal layer, 603-second metal layer, 61-first electrode, 611-first electrode portion, 612-second electrode portion, 62-second electrode, 71-first mask, 72-second mask. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0039] The present invention discloses a method for preparing a solar cell, comprising the following steps: Providing a silicon wafer, wherein a surface of the silicon wafer includes a first region and a second region; A doping structure, a dielectric layer and a mask are sequentially formed on the surface of the silicon wafer; The mask is patterned and opened by a laser process to remove the mask in the first area; Using a wet etching process to remove all dielectric layers in the first region, forming a window in the dielectric layer that penetrates the doping structure along the thickness direction of the silicon wafer; removing the mask of the second area on the surface of the dielectric layer; An electrode in contact with the doping structure is prepared at the window of the dielectric layer.

[0040] The invention also discloses a solar cell prepared by the preparation method, and a photovoltaic module comprising the solar cell.

[0041] The present invention introduces a mask and adopts a wet etching process to open windows in the dielectric layer, which can significantly reduce the velvet damage and passivation loss caused by using laser and other processes to open windows in the dielectric layer, obtain a metallized structure with excellent electrical properties, and significantly improve the fill factor and open circuit voltage, thereby greatly improving the battery efficiency and component power.

[0042] The present invention is further described below with reference to specific examples.

[0043] Comparative Example 1: The solar cell in this comparative example is described by taking a heterojunction cell as an example. Figure 1 The structure diagram of the heterojunction battery in this comparative example is shown, and the heterojunction battery includes: The silicon wafer 10' comprises a front side (i.e., a light-receiving side) and a back side (i.e., a backlight side) which are arranged opposite to each other; A first intrinsic layer 21', a first doped layer 31' and a first transparent conductive layer 41' stacked sequentially on the front surface; A second intrinsic layer 22', a second doped layer 32' and a second transparent conductive layer 42' sequentially stacked on the back surface; The first electrode 51' is in contact with the first transparent conductive layer 41'; The second electrode 52 ′ contacts the second transparent conductive layer 42 ′.

[0044] Exemplarily, the silicon wafer 10' is N-type doped; the first intrinsic layer 21' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the first doped layer 31' is an N-type doped amorphous silicon layer or a microcrystalline silicon layer; the second intrinsic layer 22' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the second doped layer 32' is a P-type doped amorphous silicon layer or a microcrystalline silicon layer; the first transparent conductive layer 41' and the second transparent conductive layer 42' can be a combination of one or more transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc.; the first electrode 51' and the second electrode 52' are both conventional gate line electrodes.

[0045] Embodiment 1:

[0046] The solar cell in this embodiment is described by taking a heterojunction cell as an example. Figure 2 , Figure 3 As shown, the heterojunction battery includes: A silicon wafer 10, comprising a front side (i.e., a light-receiving side) and a back side (i.e., a backlight side) arranged opposite to each other, wherein the front side and the back side respectively comprise a first region (a metal region) and a second region (a non-metal region); A first intrinsic layer 21, a first doped layer 31 and a first transparent conductive layer 41 are sequentially stacked on the front side; A second intrinsic layer 22, a second doped layer 32 and a second transparent conductive layer 42 are sequentially stacked on the back side; A first dielectric layer 51 and a first electrode 61. The first dielectric layer 51 is provided with a first window 511 penetrating to the surface of the first transparent conductive layer 41 in a first region. The first electrode 61 penetrates the first window 511 in the first dielectric layer 51 along the thickness direction of the silicon wafer and contacts the first transparent conductive layer 41. The second dielectric layer 52 and the second electrode 62 are provided with a second window 521 penetrating to the surface of the second transparent conductive layer 42 in the first region of the second dielectric layer 52. The second electrode 62 penetrates the second window 521 in the second dielectric layer 52 along the thickness direction of the silicon wafer and contacts the second transparent conductive layer 42.

[0047] In this embodiment, the silicon wafer 10 is an N-type single crystal silicon wafer, with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm. In other embodiments, double-sided texturing can be performed by an alkali texturing process to form a pyramid texturing light trapping structure (not shown) on the surface of the silicon wafer, and the size of the pyramid structure is preferably 0.5μm to 5μm.

[0048] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon layers or intrinsic microcrystalline silicon layers, the first doped layer 31 is an N-type doped (such as phosphorus-doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is a P-type doped (such as boron-doped) amorphous silicon layer or microcrystalline silicon layer.

[0049] It is understandable that in other embodiments, the silicon wafer 10 may also be a P-type silicon wafer, in which case the first doped layer 31 is a P-type doped (such as boron-doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is an N-type doped (such as phosphorus-doped) amorphous silicon layer or microcrystalline silicon layer.

[0050] In this embodiment, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be a combination of one or more transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc., preferably an ITO transparent conductive layer; the thickness is 15nm~150nm, preferably 40nm.

[0051] The silicon wafer, intrinsic layer, doped layer and transparent conductive layer in this embodiment are exactly the same as those in comparative example 1 and will not be described again here. The difference from comparative example 1 is that a first dielectric layer 51 and a second dielectric layer 52 are added in this embodiment, and the structures of the first electrode 61 and the second electrode 62 are also different.

[0052] The second dielectric layer 52 and the second electrode 62 are completely the same as the first dielectric layer 51 and the first electrode 61. Figures 2 to 4 As shown, the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer are taken as an example for detailed description.

[0053] The first dielectric layer 51 includes SiN X 、SiO X 、SiNO X The first dielectric layer 51 may be a layer in the multi-layer composite film, and the thickness of the first dielectric layer 51 is 20nm-150nm. Preferably, when the first dielectric layer 51 is a multi-layer composite film structure, it includes an outer dielectric layer and an inner dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

[0054] In this embodiment, the first dielectric layer 51 is SiN X layer, refractive index n is 1.9, thickness is 55nm, SiN X The layer can be deposited on the first transparent conductive layer 41 by using a PECVD process or a hot wire CVD process.

[0055] Ginseng Figure 4As shown, a first window 511 is formed on the dielectric layer in this embodiment, penetrating the first transparent conductive layer 41 along the thickness direction of the silicon wafer 10, and the depth of the first window 511 is the thickness of the first dielectric layer 51. The width of the first window 511 is 1 μm to 25 μm, preferably 2 nm to 10 nm. Exemplarily, the width of the first window 511 is 5 μm and the depth is 55 nm.

[0056] In this embodiment, the first electrode 61 is a gate line electrode. Figure 2 , Figure 3 and Figure 5 As shown, the first electrode 61 includes a first electrode portion 611 extending along the thickness direction of the silicon wafer to the inside of the first dielectric layer 51 and in contact with the first transparent conductive layer 41, and a second electrode portion 612 located above the first electrode portion 611 and extending to the surface of the first dielectric layer 51, and the maximum width of the second electrode portion 612 is greater than the maximum width of the first electrode portion 611. In addition, the surface of the first transparent conductive layer 41 away from the silicon wafer is a plane, and the bottom surface of the first electrode portion 611 is flush with the bottom surface of the first dielectric layer 51.

[0057] In addition, the silicon wafer surface in this embodiment is explained by taking the polished surface as an example. In the actual battery structure, the silicon wafer surface is usually prepared with a velvet light-trapping structure, that is, the silicon wafer surface is non-planar. For example, a pyramid velvet light-trapping structure can be formed on the silicon wafer surface through an alkali velveting process. At this time, the surface of the first transparent conductive layer 41 deposited thereon away from the silicon wafer also has a corresponding pyramid structure. The bottom surface of the first electrode portion 611 corresponds to the velvet light-trapping structure. The bottom surface of the first electrode portion 611 is flush with the bottom surface of the first dielectric layer 51, that is, the overall structure is roughly the same as a whole velvet light-trapping structure.

[0058] It is understandable that the first electrode portion 611 in this embodiment is located in all first windows 511, that is, the first electrode portion 611 completely fills the first window 511. In other embodiments, the first electrode portion 611 may also be located in part of the first window 511, that is, the first electrode portion 611 does not completely fill the first window 511.

[0059] Furthermore, the width W1 of the top of the second electrode portion 612 is smaller than the width W2 of the bottom of the second electrode portion 612, and the side surface of the second electrode portion 612 is roughly inclined. At the same time, the width W2 of the bottom of the second electrode portion 612 is larger than the width of the first electrode portion 611 (that is, the width of the first window 511). In this embodiment, the width of the first electrode portion 611 is a certain value W3 along the thickness direction of the silicon wafer. With this arrangement, the maximum width of the first electrode portion 611 is W3, and the maximum width of the second electrode portion 612 is W2.

[0060] Specifically, the thickness of the first electrode portion 611 (i.e., the thickness of the first dielectric layer) is 20nm~150nm, preferably 55nm, and the maximum width W3 of the first electrode portion 611 (i.e., the width of the first window 511) is 1μm~25μm, preferably 10μm; the maximum width W2 of the bottom of the second electrode portion 612 is less than or equal to 30μm, preferably 5μm~15μm, and the width W1 of the top of the second electrode portion 612 is preferably between W3 and W2, such as 12μm.

[0061] In addition, in this embodiment, the total thickness of the first electrodes is 5 μm to 20 μm, preferably 10 μm, and the distance between two adjacent first electrodes is 500 μm to 1000 μm.

[0062] In some embodiments, the side surfaces of the first electrode portion 611 and the second electrode portion 612 may be other shapes, and the top surface of the second electrode portion 612 may also be other shapes, such as a regular or irregular curved surface.

[0063] The first electrode 61 in the present invention is a gate line electrode, which can be a main gate line or a fine gate line. The line width and spacing of the main gate line and the fine gate line are designed according to actual needs and will not be described in detail here.

[0064] Ginseng Figure 6 As shown, the first electrode 61 in this embodiment is prepared by electroplating or chemical plating process, and the first electrode 61 includes a seed layer 601 that is entirely or partially located in the first dielectric layer and a first metal layer 602 that is located on the seed layer 601, and the total thickness of the seed layer 601 and the first metal layer 602 is 1μm to 15μm. Furthermore, it also includes a second metal layer 603 coated on the outside of the seed layer 601 and the first metal layer 602.

[0065] Specifically, the seed layer 601 and the first metal layer 602 are made of the same material, which can be one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and the thickness of the seed layer is 100nm to 500nm; the second metal layer 603 is made of one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and the thickness of the second metal layer is 1μm to 5μm. Preferably, the seed layer 601 and the first metal layer 602 are both Cu metal layers, and the total thickness of the seed layer 601 and the first metal layer 602 is 7μm, the second metal layer 603 is a Sn metal layer, and the thickness is 3μm, and the total thickness of the entire first electrode is 10μm.

[0066] In a preferred embodiment, the thickness of the seed layer 601 is greater than the thickness of the first dielectric layer 51 (i.e., the depth of the first window 511), and the seed layer 601 prepared in this way not only fills the inside of the first window 511, but also covers the surface of the first dielectric layer 51 beside the first window 511. In this case, the first electrode portion 611 is entirely the seed layer, the outer side of the second electrode portion 612 is the second metal layer, and the inner side is the first metal layer and part of the seed layer.

[0067] In other embodiments, the thickness of the seed layer may also be equal to the thickness of the first dielectric layer 51 , or less than the thickness of the first dielectric layer 51 , so that the seed layer is only formed inside the first window 511 .

[0068] The first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer in this embodiment are described in detail above. The second dielectric layer 52 and the second electrode 62 on the back side of the silicon wafer are exactly the same as the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer, and will not be described again here.

[0069] Furthermore, the first electrode 61 and the second electrode 62 in the present invention can also be prepared by screen printing process, by printing conductive paste at the window of the dielectric layer and forming a metallization structure after curing. The electrode material can be one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The screen printing process is a conventional process and will not be described here.

[0070] The preparation method of the heterojunction battery in this embodiment is as follows: 1. Ginseng Figure 7a As shown, a silicon wafer is provided.

[0071] The silicon wafer 10 in this embodiment is an N-type single crystal silicon wafer, with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm.

[0072] Preferably, the silicon wafer 10 is double-sided texturing by an alkali texturing process, specifically: The surface oxide layer is removed by using a 5% diluted HF solution, and a pyramid velvet light-trapping structure (not shown) is formed on the surface by anisotropic etching of single crystal silicon using KOH or NaOH or tetramethylammonium hydroxide (TMAH) plus alcohol. Preferably, the size of the pyramid structure is preferably 0.5μm ~ 5μm.

[0073] 2. Ginseng Figure 7b As shown, a first intrinsic layer 21 , a first doped layer 31 and a first transparent conductive layer 41 are sequentially formed on the front side of the silicon wafer 10 , and a second intrinsic layer 22 , a second doped layer 32 and a second transparent conductive layer 42 are sequentially formed on the back side of the silicon wafer 10 .

[0074] Preferably, in this embodiment, the intrinsic layer and the doping layer are deposited by a plasma chemical vapor deposition (PECVD) process, and the transparent conductive layer is deposited by a reactive plasma deposition (RPD) process or a magnetron sputtering process, as follows: First, SiH4 (silane) gas is introduced into a vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire front area of ​​the silicon wafer 10 by a PECVD process, and then SiH4 gas, H2 gas and PH3 (phosphine) gas are introduced into the vacuum chamber, and an N-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer by a PECVD process; Then, the wafer is turned over, the tray is changed, SiH4 (silane) gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire back side of the silicon wafer 10 by a PECVD process. Then, SiH4 gas, H2 gas and B2H6 (diborane) gas are introduced into the vacuum chamber, and a P-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer by a PECVD process. Finally, the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer are coated by reactive plasma deposition (RPD) or magnetron sputtering. The back side is shielded by the edge of the carrier design (shielded by a mask), and the specific shielding area around is 0.8 mm. The transparent conductive layer is an ITO (99.5:0.5) layer with a thickness of 40 nm.

[0075] In this embodiment, the carrier concentration of the first transparent conductive layer and the second transparent conductive layer is 0.6E20cm -3 ~5E20cm -3 , preferably 3E20cm -3 , the mobility is 30cm 2 / Vs ~ 120cm 2 / Vs, preferably 80cm 2 / Vs, contact resistivity is 0.8mΩ·cm 2 ~ 4mΩ·cm 2 , preferably 2 mΩ·cm 2 , the refractive index is 1.9 ~ 2.1.

[0076] 3. Ginseng Figure 7c As shown, a first dielectric layer 51 and a second dielectric layer 52 are formed on the first transparent conductive layer 41 and the second transparent conductive layer 42 respectively.

[0077] The first dielectric layer 51 and the second dielectric layer 52 are deposited on the first transparent conductive layer 41 and the second transparent conductive layer 42 respectively by using PECVD process or hot wire CVD process. The dielectric layer material can be SiN X 、SiO X 、SiNO X The layer can also be a multi-layer composite film.

[0078] For example, the dielectric layer in this embodiment is SiN X The thickness of the first dielectric layer 51 and the second dielectric layer 52 are both 55 nm, and the refractive index is 1.9.

[0079] 4. Ginseng Figure 7d As shown, a first mask 71 and a second mask 72 are formed on the first dielectric layer 51 and the second dielectric layer 52 respectively.

[0080] The first mask 71 and the second mask 72 have the characteristics of being resistant to acid but not resistant to alkali, that is, the mask will not be etched in an acid solution, but will be etched in an alkaline solution. The mask can be an amorphous silicon mask or a paraffin mask, wherein the amorphous silicon mask can be an intrinsic amorphous silicon (a-Si) mask or a hydrogenated amorphous silicon (a-Si:H) mask.

[0081] In this embodiment, a PECVD process or a hot-wire CVD process is used to deposit an intrinsic amorphous silicon (a-Si) mask or a hydrogenated amorphous silicon (a-Si:H) mask on the first dielectric layer 51 and the second dielectric layer 52, respectively. The mask thickness is 5 nm and the refractive index is 4.2.

[0082] In other embodiments, an inkjet printing process may also be used to deposit wax masks on the first dielectric layer 51 and the second dielectric layer 52 , respectively, which will not be described in detail herein.

[0083] 5. Ginseng Figure 7e As shown, the first mask 71 and the second mask 72 are patterned and opened by a laser process to remove the mask in the first area (metal area).

[0084] Specifically, in the laser process, an ultraviolet picosecond laser or a green picosecond laser is used to remove the mask on the front and back metal areas. The laser power is 2W ~ 7W, the pulse width is 10ps ~ 700ps, the width of the film is 1μm ~ 25μm, and the film opening depth of the laser process is greater than or equal to the thickness of the mask.

[0085] Exemplarily, the laser process in this embodiment uses an ultraviolet picosecond laser with a laser power of 2 W, a pulse width of 10 ps, ​​a film opening width of 5 μm, and a film opening depth of 5 nm.

[0086] 6. Ginseng Figure 7f As shown, the wet etching process is used to remove all the first dielectric layer 51 and the second dielectric layer 52 in the first area, and a first window 511 is formed in the first dielectric layer 51 that penetrates through the first transparent conductive layer 41 along the thickness direction of the silicon wafer, and a second window 521 is formed in the second dielectric layer 52 that penetrates through the second transparent conductive layer 42 along the thickness direction of the silicon wafer.

[0087] Specifically, the etching solution in the wet etching process is an acid solution, the acid solution is a hydrofluoric acid solution, and may also contain a fluorine salt solution of an acidic substance, such as a solution containing acetic acid and ammonium fluoride, the mass fraction of the acid solution is 1% to 4%, the reaction temperature is 25°C to 45°C, and the reaction time is 100s to 400s. Exemplarily, a hydrofluoric acid solution with a mass fraction of 2.4% is selected in this embodiment.

[0088] Since the mask in the first area (metal area) is removed by laser technology, while the mask in the second area (non-metal area) is not removed, and the mask is acid-resistant but not alkali-resistant, the mask in the second area will protect the dielectric layer underneath, and the dielectric layer in the first area will be etched away by the acid solution, exposing the transparent conductive layer underneath.

[0089] 7. Ginseng Figure 7g As shown, the first mask 71 in the second area (non-metal area) on the surface of the first dielectric layer 51 and the second mask 72 in the second area (non-metal area) on the surface of the second dielectric layer 52 are removed to expose the first dielectric layer 51 and the second dielectric layer 52 in the second area.

[0090] Specifically, the first mask 71 on the surface of the first dielectric layer 51 and the second mask 72 on the surface of the second dielectric layer 52 are removed by using an alkaline solution, the alkaline solution is a sodium hydroxide solution or a potassium hydroxide solution, the mass fraction of the alkaline solution is 1% to 3%, the reaction temperature is 60° C. to 80° C., and the reaction time is 100 s to 600 s. By way of example, in this embodiment, a sodium hydroxide solution or a potassium hydroxide solution with a mass fraction of 2.1% is selected.

[0091] 8. After removing the mask, the silicon wafer is annealed in an annealing furnace at a temperature of 180°C to 220°C for 10 minutes to 20 minutes. A densified film layer can be formed through the annealing process.

[0092] 9. Ginseng Figure 7h As shown, a first electrode 61 in contact with the first transparent conductive layer 41 is prepared at the first window 511 of the first dielectric layer 51 , and a second electrode 62 in contact with the second transparent conductive layer 42 is prepared at the second window 521 of the second dielectric layer 52 .

[0093] First, a seed layer is prepared at the window of the dielectric layer by using an electroplating or chemical plating process; Then, a first metal layer is prepared on the outer side of the seed layer by using an electroplating or chemical plating process; Finally, a second metal layer is prepared on the outer sides of the seed layer and the first metal layer by using an electroplating or chemical plating process.

[0094] The seed layer is described by taking copper as an example, and the thickness of the copper seed layer is 100nm to 500nm; The first metal layer takes electroplating copper as an example. The electroplating copper solution includes copper sulfate, sulfuric acid, copper balls and additives that can optimize the crystal structure of the copper layer. 2+ The concentration of is 50g / L, the concentration of sulfuric acid is 40g / L, the thickness is 7μm, and the width is 15μm; The second metal layer is electroplated tin as an example. The electroplating tin solution includes tin methanesulfonate and tin plating additives. 2+ The concentration of is 30 g / L, the concentration of methanesulfonic acid is 200 g / L, and the thickness is 3 μm.

[0095] Finally, the heterojunction battery was alkaline washed, and the prepared battery cell was subjected to light injection treatment. The temperature of the light injection treatment was 210° C., and the time of the light injection treatment was 90 s.

[0096] The electrode in this embodiment is illustrated by taking a seed layer and two metal layers as an example. In other embodiments, the electrode may also include only a seed layer and a first metal layer, or other metal layers may be further prepared outside the second metal layer, which will not be described in detail here.

[0097] Comparative Example 2: The structure and preparation method of the heterojunction battery in this comparative example are basically the same as those in Example 1, except that, in the preparation method of the heterojunction battery in this comparative example, the first mask 71 and the second mask 72 are not deposited, steps 4 to 7 in Example 1 are omitted, and the laser process is directly used to pattern the dielectric layer and open the film.

[0098] The specific steps of patterning and opening the dielectric layer in this comparative example are: The first dielectric layer 51 and the second dielectric layer 52 are patterned and opened by laser technology to form a first window 511 penetrating the surface of the first transparent conductive layer 41 and a second window 521 penetrating the surface of the second transparent conductive layer 42 .

[0099] Embodiment 2:

[0100] The structure and preparation method of the heterojunction battery in this embodiment are basically the same as those in Example 1, except that the laser process in step 5 in Example 1 only removes the mask in the first area. Figure 8 As shown, in this embodiment, the laser process is used to remove not only the first mask 71 and the second mask 72 of the first region (metal region), but also part of the first dielectric layer 51 and the second dielectric layer 52 thereunder are removed synchronously by the laser process. However, the laser process cannot completely remove the first dielectric layer 51 and the second dielectric layer 52 of the first region to avoid damaging the doping structure of the first region (metal region).

[0101] Embodiment 3:

[0102] The structure and preparation method of the heterojunction battery in this embodiment are basically the same as the structure and preparation method of the heterojunction battery in Example 1, except that after all the dielectric layers in the first area are removed by a wet etching process, the first transparent conductive layer 41 in the first window 511 and the second transparent conductive layer 42 in the second window 521 are modified.

[0103] Specifically, the exposed transparent conductive layer in the window is modified by laser technology, so that the transparent conductive layer obtains higher carrier concentration, higher mobility and lower contact resistivity. By way of example, in this embodiment, an infrared laser is used for modification, with a pulse width of 100ns to 800ns and an energy density of 0.54J / cm 2 ~ 6J / cm 2 .

[0104] The carrier concentration of the transparent conductive layer in the window after modification is 2.5E20cm -3 ~ 6.5E20cm -3 , preferably 4.5E20cm -3 , the mobility is 40cm 2 / Vs ~ 150cm 2 / Vs, preferably 88cm 2 / Vs, contact resistivity is 0.4mΩ·cm 2 ~ 3mΩ·cm 2 , preferably 1.5 mΩ·cm 2 .

[0105] It can be seen that after laser modification, the carrier concentration can be increased by 1.5E20cm -3 , the mobility can be increased by 8cm 2 / Vs, the contact resistivity can be reduced by 0.5mΩ·cm 2 .

[0106] Embodiment 4:

[0107] The solar cell in this embodiment is described by taking a heterojunction cell as an example. Fig. 9 , Fig.10 As shown, the structure of the heterojunction battery in this embodiment is basically the same as that in Embodiment 1, except that the dielectric layer in Embodiment 1 is a single-layer film structure, while the dielectric layer in this embodiment is a two-layer composite film.

[0108] Specifically, in this embodiment, SiNO is used on the front side of the battery. X Layer and SiN XThe layers are respectively used as the outer dielectric layer 502 and the inner dielectric layer 501, SiNO X The refractive index n of the layer is 1.8, the thickness is 15nm, and the SiN X The refractive index n of the layer is 1.9, the thickness is 35 nm, and the thickness of the entire first dielectric layer 51 is 50 nm. X Layer and SiN X The layers can be deposited sequentially on the first transparent conductive layer 41 by using a PECVD process or a hot wire CVD process. The second dielectric layer on the back of the battery has the same structure as the first dielectric layer, which will not be described in detail here.

[0109] In the above embodiment, an insulating dielectric layer is introduced on the surface of the transparent conductive layer. The dielectric layer can be used to act as an insulating mask for electroplating, thereby realizing copper electrode electroplating on the heterojunction battery, and obtaining a metallized structure with excellent electrical properties (high conductivity, low contact resistivity) and fine grid lines (the grid line width is preferably 5μm ~ 15μm); at the same time, the dielectric layer can reduce reflection through the optimal design of the refractive index to maximize optical utilization, thereby compensating for the short board of the low short-circuit current Isc of the heterojunction battery.

[0110] By introducing a mask and using a wet etching process to open windows in the dielectric layer, the expensive ink printing, exposure, development and patterning steps can be replaced. Compared with conventional methods, it is easier to obtain a fine grid line structure and the process cost is lower. At the same time, the traditional ink etching and seed layer back etching processes are omitted, reducing the process cost.

[0111] In addition, in Comparative Example 2, a laser process is used to directly open a window in the dielectric layer. Since a velvet light-trapping structure is usually formed on the surface of a silicon wafer, and the surface of the transparent conductive layer deposited thereon has a velvet light-trapping structure similar to that of the silicon wafer surface, the laser process will inevitably cause damage to the velvet light-trapping structure on the surface of the transparent conductive layer (for example, the top of the pyramid in the pyramid velvet structure will be removed by laser treatment), thereby affecting the subsequent growth of the electrode at the window, resulting in excessive contact resistance and significantly reducing the fill factor of the battery. In addition, excessive energy in the laser process will cause passivation damage, significantly reducing the open circuit voltage and fill factor of the battery.

[0112] The present invention adds an amorphous silicon mask or a paraffin mask on the dielectric layer, first uses a laser process to pattern the amorphous silicon mask, then uses a wet etching process to open a window on the dielectric layer, and finally removes the mask. The entire window opening process will not damage the velvet surface, and there is no passivation loss, which greatly improves the battery efficiency.

[0113] IV performance tests were conducted on different heterojunction batteries, and the test data are shown in the following table:

[0114] in: Control group 1 is the heterojunction battery in comparative example 1, the front and back gate electrodes are prepared by screen printing with low-temperature silver paste, the gate line width is 25 μm, and the number is 60; Control group 2 is the heterojunction battery in comparative example 1, the gate line electrodes on the front and back sides are both prepared by copper interconnection technology, the gate line width is 20 μm, and the number is 100; Control group 3 is the heterojunction battery in comparative example 2, the front and back sides both contain dielectric layers, the dielectric layers are windowed by laser technology, the gate line width is 20 μm, and the number is 140; Experimental group 1 is the heterojunction battery in Example 1, and both the front and back sides include a dielectric layer, the dielectric layer is opened with a mask, the gate line width is 20 μm, and the number is 140.

[0115] It can be seen that by introducing the dielectric layer in the control group 3 and the experimental group 1, compared with the control group 1 and the control group 2, finer gate line electrodes with smaller line width and spacing can be prepared.

[0116] Compared with control group 1, control group 2 has finer gate lines, lower series resistance Rs, and a 0.44% increase in fill factor FF and a 0.17% increase in battery efficiency Eta compared to conventional printing technology. Compared with control group 2, control group 3 can further refine the gate line by introducing a dielectric layer compared with traditional copper interconnection technology. Although the laser process has some damage to the bottom structure, the existence of the dielectric layer reduces the open circuit voltage Voc by 0.9mV and the fill factor FF by 0.81%, but the optical gain (short circuit current density Jsc) can be increased by 0.21mA / cm 2 , and the final battery efficiency Eta decreased by 0.14%.

[0117] Compared with control group 3, experimental group 1 introduced an amorphous silicon mask to open windows in the dielectric layer, which avoided velvet damage and passivation loss during the laser window opening process, while obtaining optical benefits. The open circuit voltage Voc and fill factor FF were significantly improved, and the battery efficiency Eta was increased by 0.19%.

[0118] It should be understood that the solar cells in the above-mentioned comparative examples and embodiments are described by taking heterojunction cells (HJT cells) as an example. In heterojunction cells, the doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer located on the surface of the silicon wafer. The present invention is also applicable to other types of solar cells, such as PERC cells, TOPCon cells, IBC cells, etc.

[0119] For example, in TOPCon cells, the dielectric layer window and electrode structure are applicable to the front and back sides of the cell. The front doping structure includes a boron diffusion layer, and the back doping structure includes a tunneling layer and a phosphorus diffusion layer. The electrodes penetrate the dielectric layer and contact the boron diffusion layer and the phosphorus diffusion layer respectively. In IBC cells, the doping structure includes a P-type doping region and an N-type doping region, both of which are located on the back side of the cell. Therefore, only the dielectric layer needs to be prepared on the back side of the cell, and the two electrodes penetrate the dielectric layer and contact the P-type doping region and the N-type doping region respectively. In PERC cells, the dielectric layer window and electrode structure are applicable to the front and back sides of the cell. The dielectric layer is located on the phosphorus emitter on the front side and the aluminum back field on the back side, and the electrodes penetrate the dielectric layer and contact the phosphorus emitter and the aluminum back field respectively.

[0120] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0121] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Providing a silicon wafer, wherein a surface of the silicon wafer includes a first area and a second area; forming a doping structure, a dielectric layer and a mask in sequence on the surface of the silicon wafer; Using a laser process to pattern the mask and remove the mask in the first area; Using a wet etching process to remove all dielectric layers in the first region, and forming a window in the dielectric layer that penetrates the doping structure along the thickness direction of the silicon wafer; removing the mask of the second area on the surface of the dielectric layer; An electrode in contact with the doping structure is prepared at the window of the dielectric layer.

2. The method for preparing a solar cell according to claim 1, characterized in that: The mask is an amorphous silicon mask or a paraffin mask, and the thickness of the mask is 5nm-50nm.

3. The method for preparing a solar cell according to claim 2, characterized in that: The amorphous silicon mask is an intrinsic amorphous silicon mask or a hydrogenated amorphous silicon mask.

4. The method for preparing a solar cell according to claim 2, characterized in that: The amorphous silicon mask is deposited by using a PECVD process or a hot wire CVD process; or, The paraffin mask is prepared by inkjet printing process.

5. The method for preparing a solar cell according to claim 1, characterized in that: The dielectric layer includes SiN X 、SiO X 、SiNO X One or more layers in the dielectric layer, the thickness of the dielectric layer is 20nm~150nm.

6. The method for preparing a solar cell according to claim 5, characterized in that: The dielectric layer is deposited by using a PECVD process or a hot-wire CVD process.

7. The method for preparing a solar cell according to claim 1, characterized in that: The preparation method further comprises: The mask is patterned and opened by using a laser process to remove the mask in the first area and a portion of the dielectric layer under the mask.

8. The method for preparing a solar cell according to claim 1 or 7, characterized in that: The laser power of the laser process is 2W to 7W, and the pulse width is 10ps to 700ps; and / or, In the laser process, an ultraviolet picosecond laser or a green picosecond laser is used to perform patterned film opening.

9. The method for preparing a solar cell according to claim 1, characterized in that: In the wet etching process, the etching solution is an acid solution, the reaction temperature is 25° C. to 45° C., and the reaction time is 100 s to 400 s.

10. The method for preparing a solar cell according to claim 9, characterized in that: The acid solution is a hydrofluoric acid solution or a fluoride salt solution containing an acidic substance; and / or, The mass fraction of the acid solution is 1% to 4%.

11. The method for preparing a solar cell according to claim 1, characterized in that: The width of the window is equal to the width of the laser film opening process; and / or, The width of the window is 1 μm to 25 μm.

12. The method for preparing a solar cell according to claim 1, characterized in that: The preparation method further comprises: The mask in the second area on the surface of the dielectric layer is removed by using an alkaline solution, the reaction temperature is 60° C. to 80° C., and the reaction time is 100 s to 600 s.

13. The method for preparing a solar cell according to claim 12, characterized in that: The alkaline solution is a sodium hydroxide solution or a potassium hydroxide solution; and / or, The mass fraction of the alkaline solution is 1% to 3%.

14. The method for preparing a solar cell according to claim 1, characterized in that: The preparation method further comprises: The pyramid textured light-trapping structure is prepared on the surface of the silicon wafer by an alkali texture process.

15. The method for preparing a solar cell according to claim 1, characterized in that: The preparation method further comprises: The silicon wafer after removing the mask is annealed at a temperature of 180° C. to 220° C. for a time of 10 min to 20 min.

16. The method for preparing a solar cell according to claim 1, characterized in that: The preparation of the electrode comprises: A seed layer is prepared at the window of the dielectric layer by using an electroplating or chemical plating process; The first metal layer is prepared on the outer side of the seed layer by electroplating or chemical plating.

17. The method for preparing a solar cell according to claim 16, characterized in that: The preparation of the electrode also includes: The second metal layer is prepared on the outer sides of the seed layer and the first metal layer by using an electroplating or chemical plating process.

18. The method for preparing a solar cell according to claim 16, characterized in that: The material of the seed layer and the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The total thickness of the seed layer and the first metal layer is 1 μm to 15 μm; and / or, The thickness of the seed layer is 100nm to 500nm; and / or, The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer.

19. The method for preparing a solar cell according to claim 17, characterized in that: The material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The thickness of the second metal layer is 1 μm to 5 μm.

20. The method for preparing a solar cell according to claim 1, characterized in that: The electrode includes a first electrode portion that penetrates the window along the thickness direction of the silicon wafer and contacts the doping structure, and a second electrode portion that is located above the first electrode portion and extends to the surface of the dielectric layer, wherein the maximum width of the second electrode portion is greater than the maximum width of the first electrode portion.

21. The method for preparing a solar cell according to claim 20, characterized in that: The width W1 of the top of the second electrode portion is smaller than the width W2 of the bottom of the second electrode portion, and the width of the top of the first electrode portion is equal to the width of the bottom of the first electrode portion.

22. The method for preparing a solar cell according to claim 20, characterized in that: The maximum width of the first electrode portion is 1 μm to 25 μm, and the maximum width of the second electrode portion is less than or equal to 30 μm or is 5 μm to 15 μm; and / or, The distance between two adjacent electrodes is 500 μm to 1000 μm; and / or, The total thickness of the electrode is 5 μm to 20 μm.

23. The method for preparing a solar cell according to claim 1, characterized in that: The solar cell is any one of a HJT cell, a PERC cell, a TOPCon cell, and an IBC cell.

24. The method for preparing a solar cell according to claim 1, characterized in that: The doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer stacked in sequence on the surface of the silicon wafer, the window penetrates the transparent conductive layer along the thickness direction of the silicon wafer, and the electrode contacts the transparent conductive layer.

25. The method for preparing a solar cell according to claim 24, characterized in that: The thickness of the transparent conductive layer is 15nm to 150nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO and TTO.

26. A solar cell, characterized in that: The solar cell is prepared by the method for preparing a solar cell according to any one of claims 1 to 25.

27. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell described in claim 26.

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