Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, the projection of the data line on the substrate is not overlapped with the projection of the anode of the light-emitting device on the substrate, so that the stray capacitance between the data line and the anode can be reduced, the total capacitance on the data line can be reduced, the rising time and the falling time of a charging signal can be reduced when the data line is used for inputting a signal, and the charging efficiency is improved. Therefore, the charging rate is improved, wrong charging is avoided, and abnormal display is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to their advantages such as self-luminescence, wide color gamut, low power consumption, and flexible display. OLED display devices are driven by pixel driving circuits, but in the use of OLED display devices, it is found that the impedance of signal lines such as data lines and scan lines is large, and the parasitic capacitance between the data lines and scan lines and other signals is large. When driving the OLED display device, it is easy to cause the rise time and fall time of the data lines and scan lines to increase, which in turn leads to insufficient pixel charging, poor display, and may also cause mischarging and display abnormalities. And for large-sized display devices, the impedance and parasitic capacitance of the data lines and scan lines will increase further, further leading to insufficient pixel charging or even the problem of being unable to charge the pixels or mischarging, resulting in display abnormalities.

[0003] Therefore, existing display devices have a technical problem that the parasitic capacitance of the signal line is large, resulting in poor display. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which are used to solve the technical problem that large parasitic capacitance of signal lines in existing display devices leads to poor display.

[0005] In order to achieve the above objective, according to a first aspect of the present application, a display panel is provided, the display panel comprising:

[0006] substrate;

[0007] A driving circuit layer, disposed on one side of the substrate, the driving circuit layer comprising a pixel driving circuit and a data line electrically connected to the pixel driving circuit;

[0008] A light-emitting functional layer is arranged on a side of the driving circuit layer away from the substrate, wherein the light-emitting functional layer comprises a light-emitting device, and an anode of the light-emitting device is connected to the corresponding pixel driving circuit;

[0009] The projection of the data line on the substrate does not overlap with the projection of the anode of the light-emitting device on the substrate.

[0010] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0011] The embodiments of the present application provide a display panel and a display device; the display panel can reduce the parasitic capacitance between the data line and the anode by making the projection of the data line on the substrate non-overlapping with the projection of the anode of the light-emitting device on the substrate, thereby reducing the total capacitance on the data line. When using the data line input signal, the rise time and fall time of the charging signal can be reduced, thereby improving the charging rate, avoiding mischarging, and avoiding display abnormalities.

[0012] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0014] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0015] Figure 1 It is a stacking diagram of each film layer of the comparative display device provided in the embodiment of the present application.

[0016] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application.

[0017] Figure 3 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application.

[0018] Figure 4 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application.

[0019] Figure 5 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application.

[0020] Figure 6 A stacking diagram of various film layers of a pixel unit of a display panel provided in an embodiment of the present application.

[0021] Figure 7 for Figure 6 An exploded view of the active layer of a display panel.

[0022] Figure 8 for Figure 6 An exploded view of the first gate layer of the display panel in FIG.

[0023] Fig. 9 for Figure 6 An exploded view of the second gate layer of the display panel in FIG.

[0024] Fig.10 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG.

[0025] Fig.11 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG.

[0026] Fig.12 for Figure 6 Exploded view of the pixel electrode layer of the display panel.

[0027] Fig.13 This is an exploded view of another first source and drain layer in the display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] In the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" means that the two are directly connected, and "electrical connection" means that the two can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] In order to explain the principle of the technical problem of the embodiment of the present application, the embodiment of the present application provides a comparative display device. It is understandable that the comparative display device cannot be used as the prior art of the embodiment of the present application. Figure 1 As shown, the comparative display device includes a plurality of sub-pixel units, each of which includes a pixel driving circuit and a light-emitting device, and the pixel driving circuit includes a data signal line 202, a first scanning line 203, a second scanning line 204, and a high potential power signal line 205. Figure 1 It can be seen that the positive projection of the data signal line 202 will overlap with the anode 201 of the light-emitting device, so the data signal line 202 will generate coupling capacitance with the anode 201 of the light-emitting device, resulting in an increase in the total capacitance of the data signal line 202, which will correspondingly increase the voltage drop of the signal transmitted on the data signal line 202, increase the rise time and fall time of the signal output by the data signal line 202, and result in insufficient pixel charging rate, and even the problem of crosstalk caused by mischarging. Figure 1 It can be seen that the first scan line 203 and the second scan line 204 are both double-layer designs, and the overlapping area with the data signal line 202 is large, which further increases the total capacitance of the data signal line 202, and the scan line is also affected by the parasitic capacitance, which leads to the problem of crosstalk. And as the size of the display device increases, the impedance and parasitic capacitance of the data line and the scan line will increase further, further leading to insufficient pixel charging or even the problem of being unable to charge the pixel or mischarging, thereby causing display abnormality. Therefore, the existing display device has the technical problem that the parasitic capacitance of the signal line is large, resulting in poor display.

[0031] The embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0032] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 3 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Figure 4 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Figure 5 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application. Figure 6 A stacking diagram of various film layers of a pixel unit of a display panel provided in an embodiment of the present application. Figure 7 for Figure 6 An exploded view of the active layer of a display panel. Figure 8 for Figure 6 An exploded view of the first gate layer of the display panel in FIG. Fig. 9 for Figure 6 An exploded view of the second gate layer of the display panel in FIG. Fig.10 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG. Fig.11 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG. Fig.12 for Figure 6 Exploded view of the pixel electrode layer of the display panel. Fig.13 This is an exploded view of another first source and drain layer in the display panel provided in an embodiment of the present application.

[0033] like Figures 2 to 13As shown, an embodiment of the present application provides a display panel, the display panel 1 includes a substrate 11, a driving circuit layer 12 and a light-emitting function layer 14, the driving circuit layer 12 is arranged on one side of the substrate 11, the driving circuit layer 12 includes a pixel driving circuit 120 and a data line Data connected to the pixel driving circuit 120; the light-emitting function layer 14 is arranged on a side of the driving circuit layer 12 away from the substrate 11, the light-emitting function layer 14 includes a light-emitting device LED, and the anode of the light-emitting device LED is connected to the pixel driving circuit 120;

[0034] The projection of the data line Data on the substrate 11 does not overlap with the projection of the anode ANO of the light emitting device LED on the substrate 11 .

[0035] An embodiment of the present application provides a display panel, which can reduce the parasitic capacitance between the data line and the anode by making the projection of the data line on the substrate non-overlapping with the projection of the anode of the light-emitting device on the substrate, thereby reducing the total capacitance on the data line. When using the data line input signal, the rise time and fall time of the charging signal can be reduced, thereby improving the charging rate, avoiding mischarging, and avoiding display abnormalities.

[0036] Specifically, the projection of the data line on the substrate and the projection of the anode of the light-emitting device on the substrate do not overlap, which means that the distance between the projection of the data line on the substrate and the projection of the anode of the light-emitting device on the substrate is greater than or equal to 0. The distance between the projection of the data line on the substrate and the projection of the anode of the light-emitting device on the substrate can be greater than 0.

[0037] Specifically, it can be understood that in the pixel driving circuit, each transistor has a gate, a first electrode, and a second electrode. However, in the actual preparation process, in order to reduce the space occupied by the transistor, some transistor electrodes will not be set separately, but the electrodes and signal lines of each transistor are directly connected. For example, in the pixel driving circuit, the first electrode of the driving transistor T1 and the second electrode of the switching transistor T2 are connected to the first node A. When preparing the driving transistor and the switching transistor, there is no need to set the first electrode of the driving transistor and the second electrode of the switching transistor separately. The active pattern of the driving transistor is directly connected to the active pattern of the switching transistor. The connection between the active pattern of the driving transistor and the switching transistor can be regarded as the first node A, thereby reducing the electrodes of the transistor and reducing the space occupied by the transistor. Similarly, other structures not marked in the film layer diagram also adopt the above design, which can be referred to the above description and will not be repeated in the following embodiments.

[0038] Specifically, in the actual preparation process, in order to reduce the space occupied by transistors, another method is to make the electrodes of multiple transistors share, or the electrodes of the transistors and the signal lines share the same structure, for example, the first electrode of the compensation transistor is connected to the second electrode of the first initialization transistor, but in the actual design, there is no need to separately set the first electrode of the compensation transistor and the second electrode of the first initialization transistor, but instead use one structure as the first electrode of the compensation transistor and the second electrode of the first initialization transistor. Similarly, for other cases where the same structure is used as the electrodes and / or signal lines of multiple transistors, please refer to the above description and will not be repeated in the following embodiments.

[0039] Specifically, the display panel includes a plurality of repeating units, and one repeating unit may include a pixel unit, such as the attached pixel unit in the embodiment of the present application. Figure 6 The pixel unit shown is, or is a pixel unit in which the initialization connection line is electrically connected to the first electrode of the first initialization transistor. A repeating unit may also include two pixel units, the difference between the two pixel units is that the initialization connection line in one pixel unit is electrically connected to the first electrode of the first initialization transistor, and the first electrode of the first initialization transistor is connected to the first initialization signal line, thereby reducing the voltage drop of the first initialization signal line, and the initialization connection line in the other pixel unit is electrically connected to the second initialization signal line, thereby reducing the voltage drop of the second initialization signal line, and for other parts, the two pixel units may be the same. The following embodiment is described by taking a repeating unit including two pixel units as an example.

[0040] Specifically, the display panel 1 may include a plurality of pixel units 140, each pixel unit 140 may include a first sub-pixel unit 140a, a second sub-pixel unit 140b and a third sub-pixel unit 140c, the first sub-pixel unit 140a, the second sub-pixel unit 140b and the third sub-pixel unit 140c all include a pixel driving circuit 120 and a light-emitting device LED, and the designs of the light-emitting devices of the first sub-pixel unit 140a, the second sub-pixel unit 140b and the third sub-pixel unit 140c may be different, specifically, the light-emitting colors of the light-emitting devices of the first sub-pixel unit 140a, the second sub-pixel unit 140b and the third sub-pixel unit 140c may be different, and / or the areas of the light-emitting devices may be different, and / or the thicknesses of the light-emitting devices may be different.

[0041] Specifically, the light-emitting colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit may be red, green, and blue, respectively, but the embodiments of the present application are not limited thereto. For example, the light-emitting colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit may be red, blue, and green, respectively, or the light-emitting colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit may be blue, green, and red, respectively.

[0042] Specifically, in the embodiments of the present application, it should be noted that, except for the differences explicitly described, the design of all pixel units can refer to the design of the pixel unit provided in the embodiments of the present application. Similarly, the design of all pixel driving circuits can refer to the design of the pixel driving circuit in the embodiments of the present application. For example, the difference between two pixel driving circuits is that the high potential power line of one pixel driving circuit is different from the high potential power line in the other pixel driving circuit, while the other designs of the two pixel driving circuits are the same. In describing the design of the pixel driving circuit, it can be considered that except for the difference in the high potential power line, the other designs of the two pixel driving circuits are the same. Similarly, the differences and the same designs of the pixel units can be determined, and they will not be repeated in the following embodiments.

[0043] Specifically, the above-mentioned embodiment is explained by taking the reduction of the parasitic capacitance between the data line and the anode of the light-emitting device as an example, but the embodiments of the present application are not limited to this. The parasitic capacitance between the data line and the scanning line can be reduced, and the parasitic capacitance between the scanning line and the high-potential power line can be reduced, thereby reducing the total capacitance on the data line and / or the scanning line, reducing the parasitic capacitance of each signal line in the display panel, and improving the display effect.

[0044] Specifically, the light emitting functional layer 14 includes a light emitting device LED, and the pixel electrode layer 141 in the light emitting functional layer 14 includes an anode ANO of the light emitting device LED.

[0045] Specifically, Figure 2 As shown, the display panel 1 includes a display area AA and a non-display area NA, and the pixel unit is arranged in the display area AA.

[0046] Specifically, since the embodiments of the present application describe the display panel from the perspective of the circuit, film layer structure, and design of each film layer of the display panel, some structures may belong to both one structure and another structure. This is because they are defined from different angles. For example, the pixel driving circuit belongs to the driving circuit layer. This is considered from the film layer structure. The pixel driving circuit is formed by the structure in the driving circuit layer. In addition, the pixel unit includes a pixel driving circuit. This is considered from the design of the pixel unit. Each pixel unit needs to be driven by a corresponding pixel driving circuit. It can be understood that the pixel driving circuits belonging to the two structures of the driving circuit layer and the pixel unit are the same pixel driving circuit. Similarly, other similar defined descriptions can be found in the above descriptions and will not be repeated in the following embodiments.

[0047] In some embodiments, Figures 2 to 13 As shown, the driving circuit layer 12 includes a first gate layer 124 and a first source-drain layer 128, and the first gate layer 124 is disposed between the substrate 11 and the first source-drain layer 128;

[0048] The first gate layer 124 includes a first scan connection line SL1, the first source-drain layer 128 includes a first scan signal line Scan(n), the first scan connection line SL1 is connected to the first scan signal line Scan(n), the projection of the first scan signal line Scan(n) on the substrate 11 overlaps with the projection of the data line Data on the substrate 11, and the projection of the first scan connection line SL1 on the substrate 11 does not overlap with the projection of the data line Data on the substrate 11. By making the projection of the first scan connection line on the substrate not overlap with the projection of the data line on the substrate, the parasitic capacitance between the scan signal line and the data line can be reduced.

[0049] Specifically, compared with the comparative display device, the first scan line 203 adopts a double-layer design, and the two parts of the first scan line 203 avoid the routing of the second node so that the two parts cannot overlap, resulting in two overlaps between the first scan line 203 and a data signal line. In the embodiment of the present application, the first scan signal line is designed as a single-layer, and the first scan connection line is connected to the first scan signal line to realize the driving of the transistor. The projection of the first scan connection line on the substrate does not overlap with the projection of the data line on the substrate, which can reduce the parasitic capacitance between the scan signal line and the data line.

[0050] In some embodiments, Figures 2 to 13 As shown, the driving circuit layer 12 further includes a second source-drain layer 132, the second source-drain layer 132 is arranged on a side of the first source-drain layer 128 away from the first gate layer 124, the second source-drain layer 132 further includes a high potential power line VDD, the first scan connection line SL1 includes a connection portion SL1a and a functional portion SL1b, the connection portion SL1a connects the functional portion SL1b and the first scan signal line Scan(n);

[0051] Among them, the projection of the connecting part SL1a on the substrate 11 does not overlap with the projection of the high potential power line VDD on the substrate 11, and the projection of part of the functional part SL1b on the substrate 11 does not overlap with the projection of the high potential power line VDD on the substrate 11, thereby reducing the overlapping area between the scanning signal line and the high potential power line and reducing parasitic capacitance.

[0052] In some embodiments, Figures 2 to 13As shown, the first source and drain layer 128 also includes a second scan signal line Reset-Q, and the first gate layer 124 also includes a second scan connection line SL2, the second scan connection line SL2 is connected to the second scan signal line Reset-Q, the projection of the second scan signal line Reset-Q on the substrate 11 overlaps with the projection of the data line Data on the substrate 11, and the projection of the second scan connection line SL2 on the substrate 11 does not overlap with the projection of the data line Data on the substrate 11.

[0053] Specifically, compared with the comparative display device in which the second scan line 204 adopts a double-layer design, the two parts of the second scan line located in different metal layers will overlap with the data line respectively, so that the second scan line will overlap with the data line at two places (although there will be overlapping parts in the two overlaps), resulting in a large parasitic capacitance between the second scan line and the data signal line. In the embodiment of the present application, the second scan signal line is designed as a single-layer, and the second scan connection line is connected to the second scan signal line to realize the driving of the transistor. The projection of the second scan connection line on the substrate does not overlap with the projection of the data line on the substrate, thereby reducing the parasitic capacitance between the scan signal line and the data line.

[0054] In some embodiments, Figures 2 to 13 As shown, the driving circuit layer 12 also includes a first initialization signal line VI-Q, and the distance between the projection of the second scanning signal line Reset-Q on the substrate 11 and the projection of the first initialization signal line VI-Q on the substrate 11 is smaller than the distance between the projection of the second scanning signal line Reset-Q on the substrate 11 and the projection of the first scanning signal line Scan(n) on the substrate 11.

[0055] Specifically, compared with the comparative display device in which the spacing between the first scan line and the second scan line is relatively close in order to make the first scan line a double-layer design, which may cause a short circuit problem, the embodiment of the present application increases the spacing between the first scan signal line and the second scan signal line by making the spacing between the first scan signal line and the second scan signal line smaller than the spacing between the second scan signal line and the projection of the first initialization signal line on the substrate, thereby reducing the risk of short circuit between the two.

[0056] In some embodiments, Figures 2 to 13As shown, the display panel includes a plurality of pixel units 140 arranged in an array, the pixel unit 140 includes a plurality of sub-pixel units (for example, a first sub-pixel unit 140a, a second sub-pixel unit 140b and a third sub-pixel unit 140c), the driving circuit layer 12 includes a first via hole and a high potential power line VDD, the first scanning signal line Scan(n) passes through the first via hole and is connected to the first scanning connection line SL1, and the first via hole is arranged between the data line Data and the high potential power line VDD in the same sub-pixel unit.

[0057] In some embodiments, Figures 2 to 13 As shown, the pixel driving circuit 120 includes a compensation transistor T3 and a driving transistor T1, a first light-emitting control transistor T5 and a second light-emitting control transistor T6 connected in series between a high potential power line VDD and the anode of the light-emitting device LED;

[0058] The driving circuit layer 12 includes a first gate layer 124, a first source-drain layer 128, and a second source-drain layer 132. The first gate layer 124 is disposed between the substrate 11 and the first source-drain layer 128. The first source-drain layer 128 is disposed between the first gate layer 124 and the second source-drain layer 132. The first gate layer 124 includes a gate T1G of the driving transistor T1. The first source-drain layer 128 includes a first electrode T3S of the compensation transistor T3 and a second electrode T6D of the second light-emitting control transistor T6. The second source-drain layer 132 includes a high potential power line VDD and an anode connection line ANO-L.

[0059] Among them, the display panel 1 also includes a second via hole, a third via hole and a fourth via hole, the first electrode T3S of the compensation transistor T3 is connected to the gate of the driving transistor T1 through the second via hole, the anode of the light-emitting device LED is connected to the anode connection line ANO-L through the third via hole, the anode connection line ANO-L is connected to the second electrode T6D of the second light-emitting control transistor T6 through the fourth via hole, the second via hole is correspondingly arranged to the gate T1G of the driving transistor T1, and the third via hole and the fourth via hole are correspondingly arranged to the anode connection line ANO-L.

[0060] Specifically, it is understandable that since each via hole is filled with a structure and each film layer is stacked, the position of each via hole cannot be seen. It is understandable that the position of each via hole can be determined according to the position of each structure.

[0061] In some embodiments, Figure 5As shown, the pixel driving circuit 120 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, the gate T2G of the switching transistor T2 is connected to the first scanning signal line Scan(n), the first electrode of the switching transistor T2 is connected to the data line Data, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at a first node A; the gate of the compensation transistor T3 is connected to the first scanning signal line Scan(n), the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at a second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1 at a third node B; the gate of the first initialization transistor T4 is connected to the second scanning signal line Reset-Q, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-Q, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at a second node Q;

[0062] Among them, the projection of the first scanning signal line Scan(n) on the substrate 11 overlaps with the projection of the data line Data on the substrate 11, and / or the projection of the second scanning signal line Reset-Q on the substrate 11 overlaps with the projection of the data line Data on the substrate 11. By making the projection of the first scanning signal line on the substrate overlap with the projection of the data line on the substrate, and / or the projection of the second scanning signal line on the substrate overlap with the projection of the data line on the substrate, the overlapping area of ​​the first scanning signal line and the data line can be reduced, and / or the overlapping area of ​​the second scanning signal line and the data line can be reduced, thereby reducing the parasitic capacitance of the first scanning signal line and the data line, and / or reducing the parasitic capacitance of the second scanning signal line and the data line, reducing the total capacitance of the first scanning signal line, and / or reducing the total capacitance of the second scanning signal line, reducing the total capacitance of the data line, and preventing crosstalk caused by insufficient pixel charging time or even charging error, improving display uniformity, and improving display effect.

[0063] Specifically, the projection of a first scanning signal line on the substrate and the projection of a data line on the substrate can be made to overlap at a point, thereby reducing the overlapping area of ​​the first scanning signal line and the data line, thereby reducing the parasitic capacitance of the first scanning signal line and the data line, reducing the total capacitance of the first scanning signal line, and reducing the total capacitance of the data line, which can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0064] Specifically, the projection of the second scanning signal line on the substrate can be overlapped with the projection of the data line on the substrate, thereby reducing the overlapping area of ​​the second scanning signal line and the data line, thereby reducing the parasitic capacitance of the second scanning signal line and the data line, reducing the total capacitance of the second scanning signal line, and reducing the total capacitance of the data line, which can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0065] Specifically, the projection of the first scanning signal line on the substrate can overlap with the projection of the data line on the substrate, and the projection of the second scanning signal line on the substrate can overlap with the projection of the data line on the substrate, so that the overlapping area of ​​the first scanning signal line and the data line can be reduced, and the overlapping area of ​​the second scanning signal line and the data line can be reduced, thereby reducing the parasitic capacitance of the first scanning signal line and the data line, reducing the parasitic capacitance of the second scanning signal line and the data line, reducing the total capacitance of the first scanning signal line, reducing the total capacitance of the second scanning signal line, and reducing the total capacitance of the data line, which can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0066] Specifically, it can be seen that the first scan line 203 in the comparative display device adopts a double-layer design, and the two parts of the first scan line 203 are arranged to avoid the routing of the second node so that the two parts cannot overlap, resulting in two overlaps between the first scan line 203 and a data signal line. The parasitic capacitance between the first scan line and the data signal line is relatively large. The embodiment of the present application reduces the overlapping area between the first scan signal line and the data line by making the projection of a first scan signal line on the substrate overlap with the projection of a data line on the substrate at one point, thereby reducing the parasitic capacitance between the first scan signal line and the data line, reducing the total capacitance of the first scan signal line, reducing the total capacitance of the data line, preventing crosstalk caused by insufficient pixel charging time or even incorrect charging, improving display uniformity, and improving display effects.

[0067] Specifically, it can be seen that the second scan line 204 in the comparative display device adopts a double-layer design, and the two parts of the second scan line located in different metal layers will overlap with the data line respectively, so that the second scan line will overlap with the data line at two places (although there will be overlapping parts in the two overlaps), resulting in a large parasitic capacitance between the second scan line and the data signal line. The embodiment of the present application can reduce the parasitic capacitance between the second scan signal line and the data line by making the projection of a second scan signal line on the substrate overlap with the projection of a data line on the substrate, thereby reducing the total capacitance of the second scan signal line and the total capacitance of the data line, preventing crosstalk caused by insufficient pixel charging time or even incorrect charging, improving display uniformity, and improving display effects.

[0068] Specifically, it can be understood that the display panel includes a plurality of first scan signal lines, each of which can drive a row of pixel units, the first scan signal line Scan(n) is the nth first scan signal line among the plurality of first scan signal lines, n is greater than or equal to 1, and n is a positive integer, the first scan signal line Scan(n) can be connected to a gate drive circuit, and a signal can be input through the gate drive circuit, or a signal can be directly input through a drive chip. Similarly, the display panel can include a plurality of second scan signal lines and a plurality of third scan signal lines, each of which drives a row of pixel units, the second scan signal line and the third scan signal line can also be connected to a gate drive circuit or input a signal through a drive chip, and the gate drive circuit connected to the second scan signal line and the third scan signal line can be the same as the gate drive circuit connected to the first scan signal line, or can be different from the gate drive circuit connected to the first scan signal line.

[0069] In some embodiments, Figures 3 to 13 As shown, the display panel 1 further includes a high potential power line VDD, the high potential power line VDD is electrically connected to the pixel driving circuit 120, the projection of the high potential power line VDD on the substrate 11 overlaps with the projection of the first scanning signal line Scan(n) on the substrate, and the width K1 of the portion corresponding to the high potential power line VDD and the first scanning signal line Scan(n) is less than or equal to the width of other portions of the high potential power line VDD (e.g. Fig.11 The width K1 of the portion corresponding to the high-potential power line VDD and the first scanning signal line is equal to the width K1 of the portion corresponding to the high-potential power line VDD and the first electrode of the first light-emitting control transistor; the width K1 of the portion corresponding to the high-potential power line VDD and the first scanning signal line is less than the width K2 of the portion corresponding to the high-potential power line VDD and the second electrode plate of the storage capacitor). By making the width of the portion corresponding to the high-potential power line and the first scanning signal line less than or equal to the width of other portions of the high-potential power line, the parasitic capacitance of the first scanning signal line and the high-potential power line is small, thereby reducing the total capacitance of the first scanning signal line and the high-potential power line, preventing crosstalk caused by insufficient pixel charging time or even charging error, improving display uniformity, and improving display effect.

[0070] Specifically, Figure 1 , Figure 6As shown, it can be seen that the width of the overlapping portion of the high potential power signal line 205 and the first scanning line 203 in the comparative display device is larger, resulting in a larger parasitic capacitance between the two. In the embodiment of the present application, the width of the portion corresponding to the high potential power signal line and the first scanning signal line is made smaller than or equal to the width of the other portion of the high potential power line, so that the parasitic capacitance between the first scanning signal line and the high potential power line is smaller, thereby reducing the total capacitance of the first scanning signal line and the high potential power line, preventing crosstalk caused by insufficient pixel charging time or even incorrect charging, improving display uniformity, and improving display effect.

[0071] Specifically, the width of the portion of the high potential power signal line corresponding to the first scanning signal line can be the minimum width of the high potential power line, and the width of the portion of the high potential power signal line corresponding to the first electrode of the first light-emitting control transistor can be the minimum width or greater than the minimum width of the high potential power line.

[0072] Specifically, the width of the portion of the high potential power signal line corresponding to the first scanning signal line is 7 micrometers.

[0073] In some embodiments, Figures 3 to 13 As shown, the display panel 1 includes a plurality of pixel units 140 arranged in an array, the pixel unit 140 includes a first sub-pixel unit 140a, a second sub-pixel unit 140b and a third sub-pixel unit 140c, the first sub-pixel unit 140a includes a first light-emitting device 241, the second sub-pixel unit 140b includes a second light-emitting device 242, the third sub-pixel unit 140c includes a third light-emitting device 243, and the areas of the anode ANO1 of the first light-emitting device 241, the anode ANO2 of the second light-emitting device 242 and the anode ANO3 of the third light-emitting device 243 are different from each other. Since the luminous efficiency of different light-emitting devices is different, by making the areas of the anode of the first light-emitting device, the anode of the second light-emitting device and the anode of the third light-emitting device different from each other, the volume of the light-emitting device can be set according to the luminous efficiency of each light-emitting device, so that the luminous brightness of each light-emitting device can be consistent, thereby improving the display effect.

[0074] Specifically, it can be understood that the light emitting device LED includes a first light emitting device, a second light emitting device and a third light emitting device, and the anodes of the light emitting devices include an anode of the first light emitting device, an anode of the second light emitting device and an anode of the third light emitting device.

[0075] Specifically, Figure 3 , Figure 4As shown, the light-emitting function layer 14 includes a pixel electrode layer 141, a pixel definition layer 142, a light-emitting material layer 143 and a common electrode layer 144. The light-emitting material layer 143 includes a first light-emitting material layer 143a, a second light-emitting material layer 143b and a third light-emitting material layer 143c. The light-emitting colors of the first light-emitting material layer 143a, the second light-emitting material layer 143b and the third light-emitting material layer 143c are different from each other. Specifically, the pixel electrode layer forms the anode of the light-emitting device, the light-emitting material layer forms the light-emitting material of the light-emitting device, and the common electrode forms the cathode of the light-emitting device.

[0076] Specifically, taking the examples where the luminous colors of the first luminescent material layer 143a, the second luminescent material layer 143b and the third luminescent material layer 143c are red, green and blue respectively, since the luminous efficiency of each luminescent material is different, specifically, the luminous efficiency of the blue luminescent material is the smallest, and the luminous efficiency of the red luminescent material is the largest, the area of ​​the anode of the first light-emitting device can be made smaller than the area of ​​the anode of the second light-emitting device, and the area of ​​the anode of the second light-emitting device is smaller than the area of ​​the anode of the third light-emitting device.

[0077] In some embodiments, Figures 3 to 13 As shown, in the first direction X, the width of the anode ANO1 of the first light emitting device 241 is smaller than the width of the anode ANO2 of the second light emitting device 242; the width of the anode ANO2 of the second light emitting device 242 is smaller than the width of the anode ANO3 of the third light emitting device 243, and the angle between the first direction X and the extension direction of the data line Data is greater than 0 and less than or equal to 90 degrees. By making the width of the anode of the first light emitting device smaller than the width of the anode of the second light emitting device, and the width of the anode of the second light emitting device smaller than the width of the anode of the third light emitting device, the volume of the light emitting device can be set according to the light emitting efficiency of each light emitting device, so that the light emitting brightness of each light emitting device can be consistent, thereby improving the display effect.

[0078] In some embodiments, Figures 3 to 13As shown, the distance between the anode ANO1 of the first light-emitting device 241 and the anode ANO2 of the second light-emitting device 242 is equal to the distance between the anode ANO2 of the second light-emitting device 242 and the anode ANO3 of the third light-emitting device 243; the distance between the anode ANO1 of the first light-emitting device 241 and the anode ANO2 of the second light-emitting device 242 is equal to the distance between the anode ANO3 of the third light-emitting device 243 and the anode ANO1 of the first light-emitting device 241. By making the distance between the anode of the first light-emitting device and the anode of the second light-emitting device equal to the distance between the anode of the second light-emitting device and the anode of the third light-emitting device, and the distance between the anode of the first light-emitting device and the anode of the second light-emitting device equal to the distance between the anode of the third light-emitting device and the anode of the first light-emitting device, data lines can be set between the light-emitting devices to reduce the impedance of the initialization signal line without occupying too much space, thereby improving the aperture ratio. In some embodiments, as Figure 5 As shown, the pixel driving circuit 120 further includes:

[0079] a first light emission control transistor T5, wherein a gate of the first light emission control transistor T5 is connected to the light emission control signal line EM, a first electrode of the first light emission control transistor T5 is connected to the high potential power line VDD, and a second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T1 and a first node A;

[0080] A second light emission control transistor T6, wherein a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B;

[0081] a second initialization transistor T7, wherein a gate of the second initialization transistor T7 is connected to a third scanning signal line Reset-A, a first electrode of the second initialization transistor T7 is connected to a second initialization signal line VI-A, a second electrode of the second initialization transistor T7 and a second electrode of the second light emitting control transistor T6 are connected to a fourth node C, and a second electrode of the second initialization transistor T7 and an anode of the light emitting device LED are connected to the fourth node C;

[0082] A storage capacitor Cst, one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at a second node Q.

[0083] Specifically, Figure 5 As shown, the cathode of the light emitting device LED is connected to the low potential power line VSS.

[0084] In some embodiments, Figure 3 As shown, the driving circuit layer 12 includes an active layer 122, a first gate layer 124, a second gate layer 126, a first source-drain layer 128 and a second source-drain layer 132. The first gate layer 124 is arranged on a side of the active layer 122 away from the substrate, the second gate layer 126 is arranged on a side of the first gate layer 124 away from the active layer 122, the first source-drain layer 128 is arranged on a side of the second gate layer 126 away from the first gate layer 124, and the second source-drain layer 132 is arranged on a side of the first source-drain layer 128 away from the second gate layer 126.

[0085] Specifically, Figure 3 As shown, the driving circuit layer 12 also includes a buffer layer 121, a first gate insulating layer 123, a second gate insulating layer 125, an interlayer insulating layer 127, a passivation layer 129, a first planarizing layer 131, a second planarizing layer 133 and a third planarizing layer 134. The buffer layer 121 is arranged between the substrate 11 and the active layer 122, the first gate insulating layer 123 is arranged between the active layer 122 and the first gate layer 124, the second gate insulating layer 125 is arranged between the first gate layer 124 and the second gate layer 126, the interlayer insulating layer 127 is arranged between the second gate layer 126 and the first source and drain layer 128, the passivation layer 129 is arranged between the first source and drain layer 128 and the first planarizing layer 131, the first planarizing layer 131 is arranged between the second source and drain layer 132 and the passivation layer 129, and the second planarizing layer 133 is arranged between the second source and drain layer 132 and the third planarizing layer 134.

[0086] Specifically, Figure 3 As shown, the light-emitting functional layer 14 further includes a pixel definition layer 142 , a light-emitting material layer 143 and a common electrode layer 144 .

[0087] Specifically, the pixel definition layer 142 may include a first pixel definition layer 142 a and a second pixel definition layer 142 b , and the pixel definition layer may also be designed as a single layer.

[0088] In some embodiments, Figure 6 to Figure 7As shown, the driving circuit layer 12 also includes an active layer 122, the display panel 1 includes a plurality of pixel units 140 arranged in an array, each of the pixel units 140 includes three pixel driving circuits 120, and in each of the pixel driving circuits 120, the active layer 122 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T3A of a compensation transistor T3, an active pattern T4A of a first initialization transistor T4, an active pattern T5A of a first light emitting control transistor T5, and an active pattern T5A of a second light emitting control transistor T5. The active pattern T6A of the driving transistor T6, the active pattern T7A of the second initialization transistor T7, the first portion VI-Q-1 of the first initialization signal line VI-Q and the first portion VI-A-1 of the second initialization signal line VI-A, the active pattern T1A of the driving transistor T1, the first portion VI-Q-1 of the first initialization signal line VI-Q and the first portion VI-A-1 of the second initialization signal line VI-A are arranged along the first direction X, the active pattern T2A of the switching transistor T2, the active pattern T4A of the first initialization transistor T4, the first portion VI-Q-1 of the second initialization signal line VI-A and the first portion VI-A-1 of the second initialization signal line VI-A are arranged along the first direction X, The active pattern T5A of the first light emission control transistor T5, the active pattern T6A of the second light emission control transistor T6, and the active pattern T7A of the second initialization transistor T7 are arranged along the second direction Y, the active pattern T3A of the compensation transistor T3 includes a portion arranged along the first direction X and a portion arranged along the second direction Y, and the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switching transistor T2, the active pattern T3A of the compensation transistor T3, the active pattern T5A of the first light emission control transistor T5, and the active pattern T7A of the second light emission control transistor T6. The active pattern T6A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4, the active pattern T6A of the second light emission control transistor T6 is connected to the active pattern T7A of the second initialization transistor T7, the first part VI-Q-1 of the first initialization signal line VI-Q is connected to the active pattern T4A of the first initialization transistor T4, and the first part VI-A-1 of the second initialization signal line VI-A is connected to the active pattern T7A of the second initialization transistor T7;

[0089] An included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0090] Specifically, Figure 6 , Figure 7 As shown, it can be seen that in a row of pixel units, the first part VI-Q-1 of the first initialization signal line VI-Q is continuous, and the first part VI-A-1 of the second initialization signal line VI-A is continuous.

[0091] Specifically, Figures 6 to 13The portion of two rows of pixel units is intercepted, so it can be seen that the second initialization transistor is located above the compensation transistor.

[0092] In some embodiments, Figures 3 to 6 , Figure 8 As shown, the driving circuit layer 12 also includes a first gate layer 124. In each of the pixel driving circuits 120, the first gate layer 124 includes a gate T1G of the driving transistor T1, a gate T2G of the switching transistor T2, a gate T3G of the compensation transistor T3, a gate T4G of the first initialization transistor T4, a gate T5G of the first light-emitting control transistor T5, a gate T6G of the second light-emitting control transistor T6, a gate T7G of the second initialization transistor T7, a first plate Cst1 of the storage capacitor Cst, a first portion EM1 of the light-emitting control line EM and a first portion Reset-A-1 of the third scanning signal line Reset-A. The first portion Reset-A-1 of the third scanning signal line Reset-A, the gate T4G of the first initialization transistor T4, the gate T3G of the compensation transistor T3, the gate T1G of the driving transistor T1 and the first portion EM1 of the light-emitting control line EM are sequentially spaced along the second direction Y.

[0093] Specifically, Figure 6 , Figure 8 As shown, it can be seen that in a row of pixel units, the first part Reset-A-1 of the third scanning signal line Reset-A is continuous, and the first part EM1 of the light emitting control line EM is continuous.

[0094] Specifically, Figure 8 As shown, the gate T2G of the switching transistor T2 is connected to the gate T3G of the compensation transistor T3.

[0095] Specifically, Figure 8 As shown, it can be seen that some structures are marked with multiple tags. This is because the electrode and the signal line share this structure, and the signals transmitted on the structure are the same (without considering the voltage drop problem). For example, the gate T7G of the second initialization transistor T7 and the first part EM1 of the light-emitting control line EM identify the same structure. This is because the first part of the light-emitting control line EM and the part corresponding to the second initialization transistor T7 serve as the gate T7G of the second initialization transistor T7. Similarly, the meaning of other structures marked with multiple tags can be determined.

[0096] Specifically, Figures 6 to 8 As shown, it can be understood that the gate of each transistor is arranged corresponding to the active pattern of each transistor, for example, the gate T3G of the compensation transistor is arranged corresponding to the active pattern T3A of the compensation transistor T3.

[0097] In some embodiments, Figures 5 to 8 As shown, the gate T3G of the compensation transistor T3 includes a first gate T3Ga and a second gate T3Gb, and the first gate T3Ga is connected to the second gate T3Gb. By making the gate of the compensation transistor a double-gate design, the gate control capability of the display panel can be improved and the leakage current can be reduced.

[0098] In some embodiments, Figures 5 to 8 As shown, the gate T4G of the first initialization transistor T4 includes a third gate T4Ga and a fourth gate T4Gb, and the third gate T4Ga is connected to the fourth gate T4Gb. By making the gate of the first initialization transistor a double-gate design, the gate control capability of the display panel can be improved and the leakage current can be reduced.

[0099] In some embodiments, Figures 3 to 6 , Fig. 9 As shown, the driving circuit layer 12 further includes a second gate layer 126. In each of the pixel driving circuits 120, the second gate layer 126 includes a second portion VI-Q-2 of the first initialization signal line VI-Q, a first power connection line VDD-L1, a second plate Cst2 of the storage capacitor Cst, and a repair line Record. The first power connection line VDD-L1 is connected to the second plate Cst2 of the storage capacitor Cst. The second portion VI-Q-2 of the first initialization signal line VI-Q, the first power connection line VDD-L1, and the repair line Record are sequentially arranged at intervals along the second direction Y. The second portion VI-Q-2 of the first initialization signal line VI-Q is connected to the first portion VI-Q-1 of the first initialization signal line VI-Q. By connecting the first portion of the first initialization signal line and the second portion of the second initialization signal line, the impedance of the first initialization signal line can be reduced.

[0100] Specifically, Figure 6 , Fig. 9 As shown, it can be seen that in a row of pixel units, the second part VI-Q-2 of the first initialization signal line VI-Q is continuous.

[0101] Specifically, Figure 6 , Fig. 9 As shown, it can be seen that the first power connection line VDD-L1 is connected to the second plate Cst2 of the storage capacitor Cst, a second via is provided on the second plate Cst2 of the storage capacitor Cst, the second plate Cst2 of the storage capacitor Cst is arranged corresponding to the first plate Cst1 of the storage capacitor Cst, and the first electrode of the compensation transistor can pass through the second via to be connected to the gate of the driving transistor.

[0102] Specifically, Fig. 9As shown, by setting a repair line Record in the pixel unit, when an abnormality occurs in a sub-pixel unit or a pixel unit, the connection between the anode of the light-emitting device corresponding to the sub-pixel unit and the pixel driving circuit can be disconnected, and the repair line can be directly connected to the anode of the sub-pixel unit to directly drive the sub-pixel unit to avoid dark spots. When the sub-pixel unit or the pixel unit does not have an abnormality, the repair line Record can be left floating.

[0103] In some embodiments, Figures 3 to 6 , Fig.10 As shown, the driving circuit layer 12 also includes a first source-drain layer 128. In each of the pixel driving circuits 120, the first source-drain layer 128 includes a first electrode T2S of a switching transistor T2, a first electrode T3S of a compensation transistor T3, a first electrode T4S of a first initialization transistor T4, a second electrode T4D of a first initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T6D of a second light-emitting control transistor T6, a first electrode T7S of a second initialization transistor T7, a second electrode T7D of a second initialization transistor T7, a second portion VI-A-2 of a second initialization signal line VI-A, a first scan signal line Scan(n), a second scan signal line Reset-Q, and a second portion R of a third scan signal line Reset-A. eset-A-2, the second part EM2 of the light-emitting control line EM, and the second power connection line VDD-L2; the second part Reset-A-2 of the third scanning signal line Reset-A, the second part VI-A-2 of the second initialization signal line VI-A, the first electrode T4S of the first initialization transistor T4, the second scanning signal line Reset-Q, the first scanning signal line Scan(n), the first electrode T2S of the switching transistor T2, the second power connection line VDD-L2, the second part EM2 of the light-emitting control line EM and the first electrode T5S of the first light-emitting control transistor T5 are arranged in sequence along the second direction Y, and the second power connection line VDD-L2 is connected to the second plate Cst2 of the storage capacitor Cst.

[0104] Specifically, Figures 6 to 10 As shown, the first electrode and the second electrode of each transistor are connected to the active pattern of each transistor.

[0105] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the second part Reset-A-2 of the third scanning signal line Reset-A is connected to the first part Reset-A-1 of the third scanning signal line Reset-A, thereby reducing the impedance of the third scanning signal line.

[0106] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the second part VI-A-2 of the second initialization signal line VI-A is continuous, and the second part VI-A-2 of the second initialization signal line VI-A is connected to the first part VI-A-1 of the second initialization signal line VI-A, thereby reducing the impedance of the second initialization signal line.

[0107] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the second scanning signal line Reset-Q is continuous, and the second scanning signal line Reset-Q is connected to the gate T4G of the first initialization transistor T4 in each pixel driving circuit.

[0108] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the first scanning signal lines Scan(n) are continuous, and the first scanning signal lines Scan(n) are connected to the gates T2G of the switch transistors T2 in each pixel driving circuit.

[0109] Specifically, Figures 6 to 10 As shown, it can be seen that the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1 through the second via hole.

[0110] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the second power connection line VDD-L2 is continuous, and the second power connection line VDD-L2 is connected to the second electrode Cst2 of the storage capacitor Cst, so that the second power connection line VDD-L2 is connected to the first power connection line VDD-L1, reducing the impedance of the high-potential power line.

[0111] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the second portion EM2 of the light emitting control line EM is continuous, and the second portion EM2 of the light emitting control line EM is connected to the first portion EM1 of the light emitting control line EM, thereby reducing the impedance of the light emitting control line.

[0112] Specifically, Figures 6 to 13 As shown, it can be seen that the second scan signal line Reset-Q adopts a single-layer routing design. Compared with the second scan line in the comparative display device adopting a double-layer design, the parasitic capacitance between the second scan line and the data signal line is larger. The embodiment of the present application can reduce the parasitic capacitance between the second scan signal line and the data line, reduce the total capacitance of the second scan signal line, reduce the total capacitance of the data line, prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0113] In some embodiments, the display panel 1 includes a plurality of pixel units 140 arranged in an array, the driving circuit layer 12 also includes a first gate layer 124, a second gate layer 126, a first source and drain layer 128, and a second source and drain layer 132, the second gate layer 126 includes a first power connection line VDD-L1, the first source and drain layer 128 includes a second power connection line VDD-L2, and the second power connection line VDD-L2 connects the first power connection line VDD-L1 and the high potential power line VDD.

[0114] In some embodiments, Figures 3 to 6 , Fig.11 As shown, the driving circuit layer 12 also includes a second source-drain layer 132. In each of the pixel units 140, the second source-drain layer 132 includes three data lines Data, three high-potential power lines VDD, one low-potential power line VSS, one initialization connection line VI-AL and three anode connection lines ANO-L. The three data lines Data and the three high-potential power lines VDD are alternately arranged along the first direction X. The low-potential power line VSS is arranged between one of the data lines Data and one of the high-potential power lines VDD, the initialization connection line VI-AL is arranged between another of the data lines Data and another of the high-potential power lines VDD, each of the anode connection lines ANO-L is arranged between one of the high-potential power lines VDD and one of the data lines Data, and the three high-potential power lines VDD are connected to the second power connection line VDD-L2.

[0115] Specifically, Figure 6 , Fig.11 As shown, the data line Data, the high potential power line VDD, the low potential power line VSS, the initialization connection line VI-AL and the anode connection line ANO-L are all arranged along the second direction Y.

[0116] Specifically, Figures 6 to 11 As shown, it can be seen that the data line Data is connected to the first electrode T2S of the switch transistor T2, and the high potential power line VDD is connected to the second power connection line VDD-L2, so that the high potential power line VDD can be meshed to reduce the impedance of the high potential power line. It can be understood that the signals on the first power connection line and the second power connection line are signals of the high potential power line, and the first power connection line and the second power connection line can be regarded as part of the high potential power line.

[0117] In some embodiments, Figures 3 to 6 , Figure 11 to Figure 12As shown, the light-emitting functional layer 14 includes a pixel electrode layer 141. In each of the pixel units 140, the pixel electrode layer 141 includes three anodes ANO of the light-emitting devices LED. Each anode ANO of the light-emitting device LED is connected to an anode connecting line ANO-L, and the anode connecting line ANO-L is connected to a second electrode T6D of the second light-emitting control transistor T6.

[0118] Specifically, a projection of the anode of the light-emitting device on the substrate overlaps with a projection of the high-potential power line on the substrate.

[0119] Specifically, Fig.12 As shown, it can be seen that the anode ANO of the light-emitting device LED is arranged along the second direction Y, and the anodes ANO of multiple light-emitting devices LED are arranged at intervals along the first direction X. The anode ANO of each light-emitting device LED is connected to the anode connecting line ANO-L, and the anode connecting line ANO-L is connected to the second electrode T6D of the second light-emitting control transistor T6, thereby realizing the connection between the light-emitting device and the second light-emitting control transistor.

[0120] Specifically, the projection of the anode of the second light emitting device on the substrate overlaps with the projection of the initialization connection line on the substrate, and the projection of the anode of the third light emitting device on the substrate overlaps with the projection of the low potential power line on the substrate.

[0121] In some embodiments, the pixel driving circuit further includes a first light emitting control transistor.

[0122] In some embodiments, Figures 3 to 13As shown, the display panel 1 includes a plurality of pixel units 140 arranged in an array, the pixel unit 140 includes a first sub-pixel unit 140a, a second sub-pixel unit 140b and a third sub-pixel unit 140c, the first sub-pixel unit 140a includes a first light-emitting device 241, the second sub-pixel unit 140b includes a second light-emitting device 242, the third sub-pixel unit 140c includes a third light-emitting device 243, and the pixel driving circuit 120 includes a first pixel driving circuit 120a electrically connected to an anode of the first light-emitting device 241, an anode of the second light-emitting device 242, and an anode of the third light-emitting device 243, respectively. The second pixel driving circuit 120b and the third pixel driving circuit 120c, the data line Data includes a first data line Data-R, a second data line Data-G and a third data line Data-B electrically connected to the first pixel driving circuit 120a, the second pixel driving circuit 120b and the third pixel driving circuit 120c, respectively, and the high potential power line VDD includes a first high potential power line VDD1, a second high potential power line VDD2 and a third high potential power line VDD3 electrically connected to the first pixel driving circuit 120a, the second pixel driving circuit 120b and the third pixel driving circuit 120c, respectively;

[0123] Among them, the distance between the part where the first high potential power line VDD1 is connected to the second power connection line VDD2 and the first data line Data-R is greater than the distance between the part where the first high potential power line VDD1 is connected to the first electrode T5S of the first light-emitting control transistor T5 and the first data line Data-R, the distance between the part where the second high potential power line VDD2 is connected to the second power connection line VDD-L2 and the second data line Data-G is equal to the distance between the part where the second high potential power line VDD2 is connected to the first electrode T5S of the first light-emitting control transistor T5 and the second data line Data-G, and the distance between the part where the third high potential power line VDD3 is connected to the second power connection line VDD-L2 and the third data line Data-B is equal to the distance between the part where the third high potential power line VDD3 is connected to the first electrode T5S of the first light-emitting control transistor T5 and the third data line Data-B; so that the distance between the openings of the second planarization layer and the third planarization layer and the side walls of the pixel definition layer meet the requirements.

[0124] Specifically, the first data line Data-R, the second data line Data-G and the third data line Data-B can correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit respectively. It can be understood that when the display panel displays, the brightness of different sub-pixel units can be the same or different. Therefore, there may be a situation where different sub-pixel units are driven by different driving voltages. In this case, different voltages can be input to the first data line Data-R, the second data line Data-G and the third data line Data-B so that each sub-pixel unit displays the corresponding brightness.

[0125] Specifically, the first high potential power line VDD1, the second high potential power line VDD2 and the third high potential power line VDD3 may correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit respectively, and the first high potential power line VDD1, the second high potential power line VDD2 and the third high potential power line VDD3 may be the same or different.

[0126] In some embodiments, the pixel driving circuit further includes a second light emitting control transistor.

[0127] In some embodiments, Figure 6 , Fig.10 As shown, in each of the pixel units 140, the first source-drain layer 128 includes three second electrodes T6D of the second light-emitting control transistors T6 respectively located in three pixel driving circuits 120, and the area of ​​the second electrode T6D of one of the second light-emitting control transistors T6 is larger than the areas of the second electrodes T6D of the other two of the second light-emitting control transistors T6. By making the area of ​​the second electrode of one of the second light-emitting control transistors larger than the areas of the second electrodes of the other two second light-emitting control transistors, each of the second light-emitting control transistors can be connected to the anode of the light-emitting device through the anode connection line.

[0128] In some embodiments, Figures 6 to 13As shown, in two adjacent pixel units 140, a first connection line L1 is provided in one pixel unit 140, and a second connection line L2 is provided in the other pixel unit 140, the first connection line L1 is connected to the initialization connection line VI-AL in the corresponding pixel unit 140 and the second part VI-A-2 of the second initialization signal line VI-A, and the second connection line L2 is connected to the initialization connection line VI-AL in the corresponding pixel unit 140 and the first electrode T4S of the first initialization transistor T4. By making one of the two adjacent pixel units have a first connection line provided in the pixel unit, the first connection line connects the initialization connection line and the second part of the second initialization signal line, so that the initialization connection line can reduce the impedance of the second initialization signal line, and making the other pixel unit have a second connection line, the second connection line connects the initialization connection line and the first electrode of the first initialization transistor, so that the initialization connection line can reduce the impedance of the first initialization signal line.

[0129] Specifically, the initialization connection line and the second initialization signal line can be connected outside the display area to realize the mesh structure design of the second initialization signal line, and the initialization connection line and the first initialization signal line can be connected outside the display area to realize the mesh structure design of the first initialization signal line.

[0130] Specifically, the display panel may include a plurality of repeating units, each repeating unit includes two pixel units, and the difference between the two pixel units is that: a first connection line is provided in one pixel unit, and a second connection line is provided in the other pixel unit, the first connection line is connected to the initialization connection line in the corresponding pixel unit and the second part of the second initialization signal line, the second connection line is connected to the initialization connection line in the corresponding pixel unit and the first electrode of the first initialization transistor, and the initialization connection lines in the two pixel units will be designed accordingly to connect the first connection line and the second connection line respectively, and for other parts, the designs in the two pixel units may be the same. Accordingly, the design of all pixel units of the display panel can be determined according to the design of the repeating unit.

[0131] Specifically, the above embodiment is described by taking the repeating unit including two pixel units as an example, but the embodiment of the present application is not limited thereto. The repeating unit may include only one pixel unit. The design of the pixel unit can refer to Figure 6 The pixel unit shown in the figure, or the design of the pixel unit can be that a second connection line is set in the pixel unit, and the second connection line is connected to the initialization connection line and the first electrode of the first initialization transistor. The rest can be seen in Figure 6 The pixel unit.

[0132] In some embodiments, Figures 6 to 13As shown, the pixel driving circuit 120 further includes a switch transistor T2, and the gates T2G of the switch transistors T2 in the plurality of pixel driving circuits 120 are arranged at intervals. By arranging the gates of the switch transistors in the plurality of pixel driving circuits at intervals, it is avoided that the gates of the switch transistors in the pixel driving circuit overlap with the data line, the parasitic capacitance of the first scanning signal line and the data line is reduced, the total capacitance of the first scanning signal line is reduced, the total capacitance of the data line is reduced, and the crosstalk caused by insufficient pixel charging time or even wrong charging can be prevented, thereby improving display uniformity and display effect.

[0133] Specifically, compared with the comparative display device in which the first scan line 203 adopts a double-layer design, so that the first scan line 203 overlaps with a data signal line at two places, in the embodiment of the present application, when setting the first scan signal line Scan(n), the gate T2G of the switching transistor T2, and the gate T3G of the compensation transistor, the portion serving as the gate T2G of the switching transistor T2 and the gate T3G of the compensation transistor is retained in the first gate layer, and the portion connecting the gates T2G of two adjacent switching transistors T2 is removed, so that the portion serving as the gate T2G of the switching transistor T2 and the gate T3G of the compensation transistor will not overlap with the data line, thereby reducing the parasitic capacitance of the first scan signal line and the data line.

[0134] Specifically, Figure 4 As shown, the display panel 1 further includes an encapsulation layer 15 , and the encapsulation layer 15 includes a first inorganic layer, an organic layer and a second inorganic layer.

[0135] Specifically, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0136] Specifically, the material of the active layer includes silicon semiconductor material, specifically low-temperature polysilicon; or the material of the active layer includes oxide semiconductor material, specifically metal oxide semiconductor material, more specifically indium gallium zinc oxide.

[0137] Specifically, the driving transistor, the switching transistor, the compensation transistor, the first initialization transistor, the first light emission control transistor, the second light emission control transistor and the second initialization transistor may be P-type transistors or N-type transistors.

[0138] Specifically, the above embodiments describe the display panel in detail from aspects of the circuit, film layer structure, specific design of each film layer, connection relationship and relative relationship between each film layer, etc. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, in each of the pixel units, the first source and drain layer includes three second electrodes of the second light-emitting control transistors respectively located in three pixel driving circuits, the area of ​​the second electrode of one of the second light-emitting control transistors is larger than the area of ​​the second electrodes of the other two second light-emitting control transistors, and in two adjacent pixel units, a first connecting line is provided in one of the pixel units, and a second connecting line is provided in the other pixel unit, the first connecting line is connected to the initialization connecting line and the second part of the second initialization signal line in the corresponding pixel unit, and the second connecting line is connected to the initialization connecting line and the first electrode of the first initialization transistor in the corresponding pixel unit.

[0139] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0140] Specifically, the display panel includes an organic light emitting diode display panel.

[0141] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0142] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0143] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0144] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A driving circuit layer, disposed on one side of the substrate, the driving circuit layer comprising a pixel driving circuit and a data line electrically connected to the pixel driving circuit; A light-emitting functional layer is arranged on a side of the driving circuit layer away from the substrate, wherein the light-emitting functional layer comprises a light-emitting device, and an anode of the light-emitting device is connected to the corresponding pixel driving circuit; The projection of the data line on the substrate does not overlap with the projection of the anode of the light-emitting device on the substrate.

2. The display panel according to claim 1, characterized in that: The driving circuit layer comprises a first gate layer and a first source-drain layer, wherein the first gate layer is arranged between the substrate and the first source-drain layer; Among them, the first gate layer includes a first scan connection line, the first source and drain layer includes a first scan signal line, the first scan connection line is connected to the first scan signal line, the projection of the first scan signal line on the substrate overlaps with the projection of the data line on the substrate, and the projection of the first scan connection line on the substrate does not overlap with the projection of the data line on the substrate.

3. The display panel according to claim 2, characterized in that: The driving circuit layer further includes a second source-drain electrode layer, the second source-drain electrode layer is arranged on a side of the first source-drain electrode layer away from the first gate layer, the second source-drain electrode layer further includes a high-potential power supply line, the first scanning connection line includes a connecting portion and a functional portion, the connecting portion connects the functional portion and the first scanning signal line; The projection of the connection portion on the substrate does not overlap with the projection of the high potential power line on the substrate, and the projection of part of the functional portion on the substrate does not overlap with the projection of the high potential power line on the substrate.

4. The display panel according to claim 2, characterized in that: The first source and drain layer also includes a second scan signal line, and the first gate layer also includes a second scan connection line, the second scan connection line is connected to the second scan signal line, the projection of the second scan signal line on the substrate overlaps with the projection of the data line on the substrate, and the projection of the second scan connection line on the substrate does not overlap with the projection of the data line on the substrate.

5. The display panel according to claim 4, characterized in that: The driving circuit layer also includes a first initialization signal line, and the distance between the projection of the second scanning signal line on the substrate and the projection of the first initialization signal line on the substrate is smaller than the distance between the projection of the second scanning signal line on the substrate and the projection of the first scanning signal line on the substrate.

6. The display panel according to claim 2, characterized in that: The display panel includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixel units, the driving circuit layer includes a first via hole and a high-potential power line, the first scanning signal line passes through the first via hole and is connected to the first scanning connection line, and the first via hole is arranged between the data line and the high-potential power line in the same sub-pixel unit.

7. The display panel according to claim 1, characterized in that: The pixel driving circuit includes a compensation transistor and a driving transistor, a first light emission control transistor and a second light emission control transistor connected in series between a high potential power line and the anode of the light emitting device; The driving circuit layer includes a first gate layer, a first source-drain layer, and a second source-drain layer, wherein the first gate layer is disposed between the substrate and the first source-drain layer, the first source-drain layer is disposed between the first gate layer and the second source-drain layer, the first gate layer includes the gate of the driving transistor, the first source-drain layer includes a first electrode of the compensation transistor and a second electrode of the second light-emitting control transistor, and the second source-drain layer includes a high-potential power supply line and an anode connection line; Among them, the display panel also includes a second via hole, a third via hole and a fourth via hole, the first electrode of the compensation transistor is connected to the gate of the driving transistor through the second via hole, the anode of the light-emitting device is connected to the anode connecting line through the third via hole, the anode connecting line is connected to the second electrode of the second light-emitting control transistor through the fourth via hole, the second via hole is arranged corresponding to the gate of the driving transistor, and the third via hole and the fourth via hole are arranged corresponding to the anode connecting line.

8. The display panel according to claim 1, characterized in that: The display panel includes a plurality of pixel units arranged in an array, the driving circuit layer also includes a first gate layer, a second gate layer, a first source-drain layer and a second source-drain layer, the second gate layer includes a first power connection line, the first source-drain layer includes a second power connection line, in each of the pixel units, the second source-drain layer includes three data lines, three high-potential power lines, one low-potential power line, one initialization connection line and three anode connection lines, the second power connection line connects the first power connection line and the high-potential power line, the three data lines and the three high-potential power lines are alternately arranged along a first direction, the low-potential power line is arranged between one of the data lines and one of the high-potential power lines, the initialization connection line is arranged between another of the data lines and another of the high-potential power lines, and each of the anode connection lines is arranged between one of the high-potential power lines and one of the data lines.

9. The display panel according to claim 8, characterized in that: The light-emitting functional layer includes a pixel electrode layer. In each pixel unit, the pixel electrode layer includes three anodes of the light-emitting devices. The anode of each light-emitting device is connected to an anode connecting wire. The projection of the anode of the light-emitting device on the substrate overlaps with the projection of the high-potential power line on the substrate.

10. The display panel according to claim 9, characterized in that: The pixel driving circuit also includes a first light-emitting control transistor, the pixel unit includes a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, the first sub-pixel unit includes a first light-emitting device, the second sub-pixel unit includes a second light-emitting device, and the third sub-pixel unit includes a third light-emitting device, the pixel driving circuit includes a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit respectively electrically connected to the anode of the first light-emitting device, the anode of the second light-emitting device and the anode of the third light-emitting device, the three data lines include a first data line, a second data line and a third data line respectively electrically connected to the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit, and the three high-potential power lines include a first high-potential power line, a second high-potential power line and a third high-potential power line respectively electrically connected to the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit; Among them, the spacing between the portion where the first high-potential power line is connected to the second power connection line and the first data line is greater than the spacing between the portion where the first high-potential power line is connected to the first electrode of the first light-emitting control transistor and the first data line, the spacing between the portion where the second high-potential power line is connected to the second power connection line and the second data line is equal to the spacing between the portion where the second high-potential power line is connected to the first electrode of the first light-emitting control transistor and the second data line, and the spacing between the portion where the third high-potential power line is connected to the second power connection line and the third data line is equal to the spacing between the portion where the third high-potential power line is connected to the first electrode of the first light-emitting control transistor and the third data line.

11. The display panel according to claim 9, characterized in that: The pixel driving circuit also includes a second light emitting control transistor. In each of the pixel units, the first source and drain layer includes second electrodes of three second light emitting control transistors respectively located in the three pixel driving circuits, and the area of ​​the second electrode of one of the second light emitting control transistors is larger than the areas of the second electrodes of the other two second light emitting control transistors.

12. The display panel according to any one of claims 1 to 11, characterized in that: The pixel driving circuit further includes a switching transistor, and gates of the switching transistors in a plurality of the pixel driving circuits are arranged at intervals.

13. A display device, characterized in that: A display panel comprising any one of claims 1 to 12.

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