Testing device and method for conduction emission voltage of chip pin

Abstract

The invention discloses a testing device and method for chip pin conduction emission voltage, the testing device comprises a testing circuit board provided with a power supply, a testing probe and a receiver, the testing probe comprises a testing probe and an impedance matching network, the testing probe is directly contacted with a to-be-tested pin of a to-be-tested chip, and the impedance matching network is connected with the receiver. The input end of the impedance matching network is connected with the test probe, the output end of the impedance matching network is connected with the receiver, a chip to be tested is placed on the test circuit board, the power supply supplies power to the chip to be tested to form a noise source, and the receiver performs frequency sweeping within a preset frequency range to obtain chip emission voltage test data. The external emission voltage amplitude at the chip pin is measured by using the chip-level test probe, an evaluation method and a measurement means are provided for the conducted emission output suppression capability of useless signals and the electromagnetic compatibility between circuits in the integrated circuit design stage of the chip, and the evaluation method and the measurement means can also be used as a basis for screening the electromagnetic compatibility of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of measuring and evaluating electromagnetic compatibility characteristics of chip-level products, and in particular to a testing device and method for conducting emission voltage of chip pins. Background Art

[0002] As the integration of integrated circuits (ICs) gradually increases, the integration density increases, the requirements for processing speed and functions continue to increase, and the operating frequency inside integrated circuits is getting higher and higher. Since the higher the signal frequency, the stronger the radiation characteristics, the increase in frequency makes the interference problem of the chip more serious, which brings the need for electromagnetic compatibility assessment for the core chips of radars, computers and other equipment in the equipment system. In the field of electromagnetic interference detection of integrated circuits, the electromagnetic emission caused by the pulse current injected from the integrated circuit pins into the wiring or cable of the printed circuit board is usually called conducted interference. This is because the electromagnetic emission of the chip is generated by the rapid changes in the voltage and current inside the integrated circuit. These changes stimulate RF current inside and outside the circuit. The conducted emission caused by the RF current forms a conduction loop on the printed circuit board (PCB) and cable through the IC pins. These loops can be regarded as transmitting loop antennas, which will produce unintentional emissions to the outside. The conducted interference of integrated circuits can be evaluated by measuring the voltage of the integrated circuit pins. However, there is currently a lack of chip-level electromagnetic compatibility characteristic testing methods, and the electromagnetic compatibility characteristics of the chips to be used cannot be evaluated. Components that lack electromagnetic compatibility index evaluation are prone to bring a series of quality risks to subsequent combination-level, subsystem-level, and system-level products. Therefore, it is necessary to carry out electromagnetic compatibility testing of chip-level products, and it is urgent to propose testing methods for chip products to achieve accurate measurement of the value of electromagnetic signals emitted by chip pins, to reasonably evaluate the electromagnetic compatibility of chips, to provide technical support for subsequent equipment-level test verification and rectification, and to ensure the working performance of the equipment. Summary of the invention

[0003] The purpose of the present invention is to provide a test device and method for the conduction emission voltage of chip pins, and to provide an evaluation method and measurement means for the conduction emission output suppression capability of useless signals and the electromagnetic compatibility between circuits.

[0004] In a first aspect, an embodiment of the present invention provides a test device for chip pin-conducted emission voltage, comprising a test circuit board provided with a power supply, a test probe, and a receiver, wherein the test probe comprises a test probe and an impedance matching network, the test probe directly contacts the test pin of the chip to be tested, the input end of the impedance matching network is connected to the test probe, and the output end is connected to the receiver, the chip to be tested is placed on the test circuit board, the power supply supplies power to the chip to be tested to form a noise source, and the receiver sweeps within a preset frequency range to obtain emission voltage test data.

[0005] In some embodiments, the component parameter values ​​of the impedance matching network are matched according to the chip to be tested, specifically: the internal resistance R1 of the impedance matching network is 120Ω, R2 is 51Ω, the capacitor C1 connected in series with R1 and R2 in the impedance matching network is 6.8nF, and the impedance Rmi of the receiver is 50Ω.

[0006] In some embodiments, a host computer equipped with test software is also included, and the host computer is electrically connected to the receiver. The test software controls the receiver to collect the signal voltage amplitude of each frequency point, and performs data processing to form a test data curve graph to obtain the external transmission voltage curve of the chip pin to be tested in the frequency range of 150kHz to 1GHz.

[0007] In some embodiments, the test circuit board includes a peripheral circuit, a ground plane and a ground adapter, the ground adapter connects the chip to be tested and the ground plane, the ground plane is grounded, and the power supply is arranged on the peripheral circuit.

[0008] In some embodiments, the test probe further includes a connecting cable and a vector network analyzer, and the vector network analyzer calibrates the connecting cable loss.

[0009] In some embodiments, the test software includes an automatic correction coefficient module, which corrects the emission voltage test data, specifically including correction of the connection cable loss and the test probe's direct contact with the test pin loss of the chip under test.

[0010] In a second aspect, an embodiment of the present invention provides a method for testing the conduction emission voltage of a chip pin, the method being applied to the testing device described in the first aspect, and the method comprising the following steps:

[0011] S1, determining the connection cable loss and the test pin loss of the test probe directly contacting the chip to be tested, and inputting the loss data into the test software;

[0012] S2, the chip to be tested is mounted on the test circuit board, and is preheated by the power supply and reaches a stable working state;

[0013] S3, the test probe directly contacts the pin to be tested of the chip to be tested for testing;

[0014] S4. Obtaining an output voltage of the receiver, and obtaining a test frequency corresponding to the output voltage;

[0015] S5. acquiring the voltage threshold corresponding to the test frequency based on the mapping relationship between the test frequency and the voltage threshold, and determining whether the output voltage is greater than the voltage threshold;

[0016] If the output voltage is greater than the voltage threshold, executing step S6;

[0017] If the output voltage is less than or equal to the voltage threshold, executing step S7;

[0018] S6, determining that the pin to be tested does not meet the electromagnetic compatibility requirements;

[0019] S7. Determine whether the pin to be tested meets the electromagnetic compatibility requirement.

[0020] In some embodiments, the step S1 of determining the connection cable loss and the test pin loss of the test probe directly contacting the chip under test specifically includes:

[0021] The vector network analyzer calibrates the connection cable loss, and the test probe directly contacts the test pin loss of the chip to be tested, which is obtained from the factory test report of the test probe.

[0022] In some embodiments, the reaching of a stable working state in step S2 includes determining that the monitored current value is stable if it remains unchanged.

[0023] In some embodiments, the voltage threshold in step S5 is a voltage limit within the test frequency range, which is preset according to the performance of the chip under test.

[0024] The present invention has the advantages that:

[0025] The chip pin conduction emission measurement method based on the direct coupling method of the present invention proposes a test device for the chip pin conduction emission voltage, uses a chip conduction voltage test probe, and tests the power supply port and the signal port by a contact measurement method. The signal input end of the test probe is a millimeter-level probe probe, the probe size is small, and it needs to be overlapped with the chip pin under test, and the signal output end is a coaxial interface connected to the receiver. The receiver sweeps the frequency range of 150k to 1GHz, and the scanned data is combined with the correction coefficient in the system to obtain the final test result. The final test result is used to determine whether the chip pin external emission voltage value exceeds the standard and evaluate whether the components meet the chip electromagnetic compatibility design requirements. The vector network analyzer calibrates the connection cable loss, and the test probe directly contacts the test pin loss of the chip to be tested, which is obtained from the test probe factory test report. The test device and test method are simple and direct. Using chip-level test probes to measure the external emission voltage amplitude at the chip pins provides an evaluation method and measurement means for the chip's integrated circuit design stage, the ability to suppress the conduction emission output of useless signals and the electromagnetic compatibility between circuits. It can also be used as a basis for chip electromagnetic compatibility screening, solving the electromagnetic compatibility problems caused by chip conduction emission, and providing technical support for subsequent system-level and equipment-level test verification. Chips with excellent electromagnetic compatibility performance are the basic resources to ensure the performance and quality of electronic product systems, and play a vital role in system construction. The realization and improvement of system functions and performance rely on the continuous improvement and improvement of components such as chips. Chips with excellent electromagnetic compatibility performance have become an important driving force for the development of electronic product systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic structural diagram of a chip pin voltage testing device according to an embodiment of the present invention;

[0027] Figure 2 This is a circuit connection diagram of a chip pin voltage testing device according to an embodiment of the present invention;

[0028] Figure 3 A physical schematic diagram of a test circuit board and a test probe according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of a test probe directly contacting a chip according to an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of the test software interface of an embodiment of the present invention.

[0031] In the figure: 1-test probe; 2-receiver; 3-test circuit board; 4-test probe (part of the test probe); 5-impedance matching network; 6-chip to be tested; 61-pin to be tested; 7-peripheral circuit; 8-ground plane; 9-ground adapter; 10-power supply; 11-noise source. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is further described below in conjunction with specific implementation methods.

[0033] Embodiment 1

[0034] The embodiment of the present invention provides a test device for chip pin conduction emission voltage, see Figure 1 and Figure 2 , including a test circuit board with a power supply, a test probe, and a receiver. The test probe includes a test probe and an impedance matching network. The test probe directly contacts the test pin of the chip to be tested. The input end of the impedance matching network is connected to the test probe, and the output end is connected to the receiver. The chip to be tested is placed on the test circuit board. The power supply supplies power to the chip to be tested to form a noise source. The receiver sweeps the frequency within a preset frequency range to obtain the chip transmission voltage test data.

[0035] In some preferred embodiments, the test circuit board includes a peripheral circuit, a ground plane and a ground adapter, the ground adapter connects the chip to be tested and the ground plane, the ground plane is grounded, and the power supply is set on the peripheral circuit. Figure 3 and Figure 4 The minimum requirement for the test circuit board is to use a double-layer board. When making the PCB, the IC components should be on the first layer, and all components required for functions other than the IC should be installed on the last layer of the test board. Therefore, it is necessary to feed the I / O and other required pins from the first layer to the last layer. In order to improve the convenience and repeatability of the test, the size specifications of the circuit board are unified.

[0036] In some preferred embodiments, the component parameter values ​​of the impedance matching network are matched according to the chip to be tested, specifically: the internal resistance R1 of the impedance matching network is 120Ω, R2 is 51Ω, the capacitor C1 connected in series with R1 and R2 in the impedance matching network is 6.8nF, and the impedance Rmi of the receiver is 50Ω. Regardless of the type of chip, whether it is a chip power supply pin or a signal output pin, as long as the frequency range is between 150k and 1G, the test device of the present invention can be used to test the external transmission voltage amplitude of its pin. The tested pin is terminated with a typical antenna impedance of 150Ω. The 150Ω impedance represents the statistical average of the common mode impedance of the wiring harness. In order to connect to a receiver with an input impedance of 50Ω, an impedance matching network is used to enable it to match the signal line impedance and the device impedance. Usually, the impedance matching network is integrated in the probe.

[0037] According to the technical index requirements, the receiver sweeps in the frequency range of 150k~1GHz, and the scanning bandwidth and measurement time requirements are as shown in Table 1.

[0038] Table 1 Bandwidth and measurement time

[0039] Frequency range 6dB bandwidth / kHz Dwell time / s Minimum measurement time 150kHz~30MHz 10 0.02 2s / MHz 30MHz~1GHz 100 0.02 0.2s / MHz

[0040] In some preferred embodiments, the testing device also includes a host computer installed with testing software, the host computer is electrically connected to the receiver, the testing software controls the receiver to collect the signal voltage amplitude of each frequency point, and performs data processing to form a test data curve graph to obtain the external transmission voltage curve of the chip pin to be tested in the frequency range of 150kHz to 1GHz.

[0041] In some preferred embodiments, the test probe further includes a connecting cable and a vector network analyzer, and the vector network analyzer calibrates the loss of the connecting cable.

[0042] The test software includes an automatic correction coefficient module, which corrects the transmission voltage test data, specifically including the correction of the connection cable loss and the test probe directly contacting the test pin loss of the chip to be tested.

[0043] Embodiment 2

[0044] The embodiment of the present invention provides a test method for the conduction emission voltage of a chip pin. The test method is applied to the above-mentioned test device, and the test method includes the following steps:

[0045] S1. Determine the connection cable loss and the test probe directly contacting the test pin loss of the chip to be tested, and input the loss data into the test software, specifically into the automatic correction coefficient module, i.e., the correction coefficient file;

[0046] Determine the connection cable loss and the loss of the test probe directly contacting the test pin of the chip under test, specifically including the connection cable loss calibrated by the vector network analyzer. The loss of the test probe directly contacting the test pin of the chip under test is obtained from the test probe factory test report. The report includes the loss of the test probe directly contacting the test pin of the chip under test in the frequency range of 150k~1GHz, that is, the insertion loss.

[0047] S2. The chip to be tested is installed on the test circuit board, preheated by the power supply and reaches a stable working state; usually, the current value monitored by a multimeter remains unchanged and is judged to be stable.

[0048] S3, the test probe directly contacts the pin of the chip to be tested for testing, and the scanning range is 150k~1GHz;

[0049] S4. The host computer obtains the output voltage of the receiver and the test frequency corresponding to the output voltage; see Figure 5 ;

[0050] S5. Based on the mapping relationship between the test frequency and the voltage threshold, the voltage threshold corresponding to the test frequency is obtained, and it is determined whether the output voltage is greater than the voltage threshold; the voltage threshold is a voltage limit within the test frequency range, which is preset by the performance of the chip to be tested;

[0051] If the output voltage is greater than the voltage threshold, executing step S6;

[0052] If the output voltage is less than or equal to the voltage threshold, executing step S7;

[0053] S6, determining that the pin to be tested does not meet the electromagnetic compatibility requirements;

[0054] S7. Determine whether the pin to be tested meets the electromagnetic compatibility requirement.

[0055] In short, the scanned data is combined with the correction coefficient file in the system to obtain the final test results, which are used to determine whether the external emission voltage value of the chip pin exceeds the standard and to evaluate whether the components meet the chip electromagnetic compatibility design requirements. The voltage limit within the measurement frequency range is usually set by the component user, and its voltage limit is determined according to the actual use environment of the chip product and the equipment-level electromagnetic compatibility requirements. The test software controls the receiver to collect the signal voltage amplitude of each frequency point in a sweeping step manner, and performs data processing to form a test data curve graph to obtain the external emission voltage curve of the chip pin in the frequency range of 150kHz to 1GHz. The receiver scanning parameters can be adjusted in the parameter settings, including frequency range, scanning step length, etc.

Claims

1. A test device for conducting emission voltage of chip pins, characterized in that: The invention comprises a test circuit board provided with a power supply, a test probe, and a receiver. The test probe comprises a test probe and an impedance matching network. The test probe directly contacts the pin to be tested of the chip to be tested. The input end of the impedance matching network is connected to the test probe, and the output end is connected to the receiver. The chip to be tested is placed on the test circuit board. The power supply supplies power to the chip to be tested to form a noise source. The receiver sweeps the frequency within a preset frequency range to obtain transmission voltage test data.

2. A test device for chip pin conduction emission voltage according to claim 1, characterized in that: The component parameter values ​​of the impedance matching network are matched according to the chip to be tested, specifically: the internal resistance R1 of the impedance matching network is 120Ω, R2 is 51Ω, the capacitor C1 connected in series with R1 and R2 in the impedance matching network is 6.8nF, and the impedance Rmi of the receiver is 50Ω.

3. A test device for chip pin conduction emission voltage according to claim 2, characterized in that: It also includes a host computer equipped with test software, which is electrically connected to the receiver. The test software controls the receiver to collect the signal voltage amplitude of each frequency point, and performs data processing to form a test data curve graph to obtain the external transmission voltage curve of the chip pin to be tested within the frequency range of 150kHz to 1GHz.

4. A test device for chip pin conduction emission voltage according to any one of claims 1 to 3, characterized in that: The test circuit board comprises a peripheral circuit, a ground plane and a ground adapter, the ground adapter connects the chip to be tested and the ground plane, the ground plane is grounded, and the power supply is arranged on the peripheral circuit.

5. A test device for chip pin conduction emission voltage according to claim 4, characterized in that: The test probe further includes a connecting cable and a vector network analyzer, and the vector network analyzer calibrates the connecting cable loss.

6. A test device for chip pin conduction emission voltage according to claim 5, characterized in that: The test software includes an automatic correction coefficient module, which corrects the emission voltage test data, specifically including the correction of the connection cable loss and the test pin loss of the test probe directly contacting the chip under test.

7. A method for testing the conduction emission voltage of a chip pin, characterized in that: The test method is applied to the test device according to claim 6, and the test method comprises the following steps: S1, determining the connection cable loss and the test pin loss of the test probe directly contacting the chip to be tested, and inputting the loss data into the test software; S2, the chip to be tested is mounted on the test circuit board, and is preheated by the power supply and reaches a stable working state; S3, the test probe directly contacts the pin to be tested of the chip to be tested for testing; S4. Obtaining an output voltage of the receiver, and obtaining a test frequency corresponding to the output voltage; S5. acquiring the voltage threshold corresponding to the test frequency based on the mapping relationship between the test frequency and the voltage threshold, and determining whether the output voltage is greater than the voltage threshold; If the output voltage is greater than the voltage threshold, executing step S6; If the output voltage is less than or equal to the voltage threshold, executing step S7; S6, determining that the pin to be tested does not meet the electromagnetic compatibility requirements; S7. Determine whether the pin to be tested meets the electromagnetic compatibility requirement.

8. A method for testing the conduction emission voltage of a chip pin according to claim 7, characterized in that: The step S1 of determining the connection cable loss and the test pin loss of the test probe directly contacting the chip under test specifically includes: The vector network analyzer calibrates the connection cable loss, and the test probe directly contacts the test pin loss of the chip to be tested, which is obtained from the factory test report of the test probe.

9. A method for testing the conduction emission voltage of chip pins according to claim 7, characterized in that: The reaching of the stable working state in step S2 includes determining that the monitored current value is stable if it remains unchanged.

10. A method for testing the conduction emission voltage of a chip pin according to claim 7, characterized in that: The voltage threshold in step S5 is a voltage limit value within the test frequency range, which is preset according to the performance of the chip to be tested.

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