Programmer with logic detection function and logic detection method of programmer

Abstract

The invention relates to a programmer with a logic detection function and a logic detection method of the programmer. The programmer comprises a processor and a field programmable gate array which are connected. The field programmable gate array is used for being connected with a chip to be programmed; the field programmable gate array is used for collecting and outputting a pin logic signal of the chip to be programmed; and the processor is used for transmitting the acquired pin logic signal to an upper computer through a programmer interface, so that the upper computer realizes read-write control of the chip to be programmed and display and waveform analysis of the pin logic signal. By adopting the programmer, hardware does not need to be additionally added for logic detection, so that the cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment programming, and in particular to a programmer with a logic detection function and a logic detection method for the programmer. Background Art

[0002] A programmer is a device that provides read and write functions for programmable integrated circuits. It is mainly used for programming integrated circuits such as single-chip microcomputers and memories. Existing general-purpose programmers mainly rely on external computers and dedicated software during the programming process, and lack a mechanism for real-time detection of the internal status of the device and programming logic. This may lead to programming failures or device damage due to device failures, connection problems, or data transmission errors in complex programming environments.

[0003] The traditional method is to use various additional measuring devices, such as logic analyzers and oscilloscopes, to analyze and troubleshoot problems by viewing the signal data collected by other measuring devices; or to add additional detection circuits to the programmer to identify and alarm through the detection circuits. However, the traditional method has the problem of high cost. Summary of the invention

[0004] Based on this, it is necessary to provide a programmer with a logic detection function and a logic detection method for the programmer that can reduce costs in order to solve the above technical problems.

[0005] A programmer with a logic detection function, the programmer comprising a processor and a field programmable gate array connected to each other; the field programmable gate array is used to connect to a chip to be programmed; The field programmable gate array is used to collect and output the pin logic signal of the chip to be programmed; The processor is used to transmit the collected pin logic signal to the host computer through the programmer interface, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signal.

[0006] A logic detection method for a programmer is applied to a programmer, wherein the programmer comprises a processor and a field programmable gate array connected to each other; the field programmable gate array is used to connect to a chip to be programmed; Collecting and outputting the pin logic signal of the chip to be programmed through the field programmable gate array; The collected pin logic signal is transmitted to a host computer through the processor and the interface of the programmer, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signal.

[0007] The above-mentioned programmer with logic detection function and logic detection method for the programmer, the programmer is usually used together with a host computer, and the pin logic signals of the chip to be programmed are collected and output through the field programmable gate array to realize the real-time acquisition function of the chip; the processor transmits the collected pin logic signals to the host computer, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signals. The display and waveform analysis through the host computer rely on the existing hardware and do not require additional hardware to realize the programmer logic detection, thereby reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is an application environment diagram of a programmer with a logic detection function in one embodiment; Figure 2 is an application schematic diagram of a level conversion circuit in an embodiment; Figure 3 A schematic diagram of a BDM protocol waveform interface in an embodiment; Figure 4 A schematic diagram of a flow chart of a logic detection method of a programmer in one embodiment; Figure 5 A diagram of the application environment of a logic detection method of a programmer in one embodiment. DETAILED DESCRIPTION

[0009] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0010] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0011] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0012] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0013] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0014] The programmer with logic detection function provided in this application can be applied to Figure 1 application environment. Figure 1 The following is an application environment diagram of a programmer with a logic detection function in an embodiment. It includes a programmer 100, a chip to be programmed 110 and a host computer 120. The programmer 100 includes a processor 102 and an FPGA (Field-Programmable Gate Array) 104. The host computer 120, the processor 102, the FPGA 104 and the chip to be programmed 110 are connected in sequence. The processor 102 can be an MCU (Microcontroller Unit) chip or a CPU (Central Processing Unit), etc., which is not limited here. The host computer 120 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and portable wearable devices.

[0015] In one embodiment, the programmer 100 includes a processor 102 and a field programmable gate array 104 connected to each other; the field programmable gate array 104 is used to connect to a chip to be programmed 110; The field programmable gate array 104 is used to collect and output the pin logic signals of the chip 110 to be programmed; The processor 102 is used to transmit the collected pin logic signals to the host computer 120 through the programmer 100 interface, so that the host computer 120 can realize the read and write control of the chip 110 to be programmed and display and analyze the waveform of the pin logic signals.

[0016] The interface of the programmer 100 may be, but is not limited to, a USB (Universal Serial Bus) interface and a Gigabit Ethernet port.

[0017] Specifically, the processor 102 and the field programmable gate array 104 can be connected via a high-speed AXI (Advanced Extensible Interface) bus. The field programmable gate array 104 collects the pin logic signals of the chip to be programmed 110 in real time, and compresses the collected pin logic signals using the ‌RLE algorithm (Run Length Encoding), and informs the processor 102 to read the pin logic signals through a DMA (Direct Memory Access) interrupt. The processor 102 transmits the collected pin logic signals collected by the FPGA 104 to the host computer 120 through a high-speed USB interface and a gigabit network port, so that the host computer 120 can realize the read and write control of the chip to be programmed 110 and display and waveform analysis of the pin logic signals.

[0018] In this embodiment, the programmer is usually used together with the host computer, and the pin logic signals of the chip to be programmed are collected and output through the field programmable gate array to realize the real-time collection function of the chip; the processor transmits the collected pin logic signals to the host computer, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signals. The display and waveform analysis by the host computer rely on the existing hardware and do not require additional hardware to realize the programmer logic detection, which reduces the cost and is convenient for users and R&D personnel to analyze the underlying hardware protocol timing of the chip during the programming process, and can quickly locate the problem when the programming fails; in addition, the operation is simple and convenient, and does not require relevant personnel to use additional instruments and equipment, nor does it require complicated operating procedures, and can automatically realize real-time sampling of signals.

[0019] In one embodiment, the programmer 100 includes a level conversion circuit 106, the field programmable gate array 104 is connected to the level conversion circuit 106, and the level conversion circuit 106 is used to connect to the chip to be programmed 110; The level conversion circuit 106 is used to perform level conversion processing on the signal output by the field programmable gate array 104 and output the converted signal to the chip to be programmed 110; and receive the signal output by the chip to be programmed 110 and compare it with the comparison level to obtain the pin logic signal.

[0020] Specifically, the main control chip of the programmer 100 includes the connected processor 102 and field programmable gate array 104. For the safety of the main control chip of the programmer 100 and to adapt to the programming voltage requirements of different chips, the pins of the chip to be programmed 110 are not directly connected to the main control chip of the programmer 100, but are connected through a level conversion circuit 106. Figure 2As shown, it is an application schematic diagram of the level conversion circuit in one embodiment. Among them, VCC is set as the power supply voltage of FPGA104, VDD is the power supply for the chip 110 to be programmed, and GND is the normal ground terminal. FPGA104 outputs a signal PFOUT, which is converted to PORT through a level conversion circuit 106 to realize the output function. VH is a comparison level, VH=VDD / 2, when PORT is higher than the VH level, PFIN is a logic high level; when PORT is lower than the VH level, PFIN is a logic low level, and the pin logic signal is obtained to realize the input function. Among them, FPGA104 samples the PFIN level, that is, samples the external and PORT logic signals, without increasing the existing programmer 100 circuit hardware, and at the same time does not affect the function of the existing circuit.

[0021] In this embodiment, the level conversion circuit is used to perform level conversion processing on the signal output by the field programmable gate array, output the converted signal to the chip to be programmed, and receive the signal output by the chip to be programmed and compare it with the comparison level to obtain the pin logic signal, thereby protecting the security of the programmer main control chip and realizing the communication function between the chip to be programmed and the programmer.

[0022] In one embodiment, the processor 102 is used to transmit the collected pin logic signals of different communication protocols to the host computer 120 through the programmer 100 interface, so that the host computer 120 calls the plug-in of the corresponding communication protocol to parse the pin logic signal.

[0023] Among them, the host computer 120 supports plug-ins of different protocols, such as different communication protocols including but not limited to SWIM (Scalable Weakly-consistent Infection-style Process Group Membership Protocol), MDI (Medium Dependent Interface) and BDM (Background Debugging Mode). Various protocols can be parsed through plug-ins of different protocols. If the pin logic signal is a SWIM communication protocol, the host computer 120 calls the plug-in of the SWIM communication protocol to parse the pin logic signal.

[0024] Specifically, the processor 102 is used to transmit the collected pin logic signals of different communication protocols to the host computer 120 through the programmer 100 interface. The host computer 120 saves the data (such as pin logic signals) sent by the programmer 100 in a timely manner and generates a local data file for later inspection. In addition, the host computer 120 has installed plug-ins of different communication protocols, and by calling the plug-ins of different communication protocols, the pin logic signals are parsed, and the pin logic signals are directly displayed on the host computer 120, and waveform analysis is performed. Figure 3 As shown, a schematic diagram of a BDM protocol waveform interface in an embodiment is shown. The interface is located in the host computer 120 and is a schematic diagram of the interface of the BDM plug-in, including the waveform of the BDM pin signal, the waveform of the VCC pin signal, the waveform of the RESET pin signal, and the waveform of the BKGD pin signal. It also includes decoding, measurement, search, display and other functions to assist developers in troubleshooting problems.

[0025] In this embodiment, the processor is used to transmit the collected pin logic signals of different communication protocols to the host computer through the programmer interface, so that the host computer can call the plug-in of the corresponding communication protocol, parse the pin logic signal, and then realize the logic detection function of the programmer under different communication protocols; in addition, the plug-in can be edited and updated by itself to realize the analysis of different protocols and quickly identify and troubleshoot problems.

[0026] In one embodiment, the host computer 120 is also used to issue an error reminder when an abnormal signal appears in the pin logic signal.

[0027] Specifically, the host computer 120 is also used to issue an error reminder when determining that an abnormal signal appears in the pin logic signal through the plug-in of the corresponding communication protocol.

[0028] In this embodiment, by installing plug-ins of different communication protocols in the host computer, an error reminder can be given when an abnormal signal appears in the pin logic signal, thereby realizing the logic detection of the programmer and quickly troubleshooting the problem.

[0029] In one embodiment, the processor 102 is used to receive a signal acquisition instruction issued by the host computer 120; the signal acquisition instruction includes one or more of a sampling rate, a sampling time, a sampling voltage, and a sampling channel; The field programmable gate array 104 is used to collect and output pin logic signals of the chip to be programmed 110 based on the signal collection instruction.

[0030] The sampling channel refers to the channel for sampling.

[0031] Specifically, the processor 102 is used to receive programming and signal acquisition instructions issued by the host computer 120, and transmit the programming instructions and signal acquisition instructions to the field programmable gate array 104. It can be understood that the programming instructions and the signal acquisition instructions can be sent at the same time or at different times; when sent at the same time, the programming and signal acquisition of the chip to be programmed 110 can be realized at the same time, and the pin logic signal in the programming process can be obtained. The programmer 100 writes the programming program to the chip to be programmed 110 in response to the programming signal, so the programming instructions transmitted by the host computer 120 can be used to realize the read and write control of the chip to be programmed 110. The field programmable gate array 104 is used to collect the pin logic signal of the chip to be programmed 110 based on the signal acquisition instruction, and output the pin logic signal to the processor 102, so that the processor 102 transmits the pin logic signal to the host computer 120.

[0032] In this embodiment, the processor receives the signal acquisition instruction sent by the host computer, and the field programmable gate array collects and outputs the pin logic signal of the chip to be programmed based on the signal acquisition instruction, which can realize the control of signal acquisition and further realize the logic detection function of the programmer.

[0033] In one embodiment, Figure 4 FIG. 1 is a flow chart of a logic detection method of a programmer in an embodiment. Taking the application to a programmer as an example, the programmer includes a processor and a field programmable gate array connected to each other, and the field programmable gate array is used to connect to a chip to be programmed; the following steps are included: Step 402, collecting and outputting the pin logic signal of the chip to be programmed through the field programmable gate array; Step 404, the collected pin logic signals are transmitted to the host computer through the processor and the interface of the programmer, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signals.

[0034] In this embodiment, the programmer is usually used together with the host computer, and the pin logic signals of the chip to be programmed are collected and output through the field programmable gate array to realize the real-time collection function of the chip; the processor transmits the collected pin logic signals to the host computer, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signals. The display and waveform analysis by the host computer rely on the existing hardware and do not require additional hardware to realize the programmer logic detection, which reduces the cost and is convenient for users and R&D personnel to analyze the underlying hardware protocol timing of the chip during the programming process, and can quickly locate the problem when the programming fails; in addition, the operation is simple and convenient, and does not require relevant personnel to use additional instruments and equipment, nor does it require complicated operating procedures, and can automatically realize real-time sampling of signals.

[0035] In one embodiment, the programmer includes a level conversion circuit, the field programmable gate array is connected to the level conversion circuit, and the level conversion circuit is used to connect to the chip to be programmed; The method further includes: Performing level conversion processing on the signal output by the field programmable gate array through the level conversion circuit, and outputting the converted signal to the chip to be programmed; The signal output by the chip to be programmed is received through the level conversion circuit, and compared with the comparison level to obtain the pin logic signal. The pin logic signal output by the level conversion circuit is collected and output through the field programmable gate array.

[0036] In this embodiment, the level conversion circuit is used to perform level conversion processing on the signal output by the field programmable gate array, output the converted signal to the chip to be programmed, and receive the signal output by the chip to be programmed and compare it with the comparison level to obtain the pin logic signal, thereby protecting the security of the programmer main control chip and realizing the communication function between the chip to be programmed and the programmer.

[0037] In one embodiment, the collected pin logic signals are transmitted to the upper computer through the processor and the interface of the programmer, so that the upper computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signals, including: The collected pin logic signals of different communication protocols are transmitted to the host computer through the processor and the interface of the programmer, so that the host computer can call the plug-in of the corresponding communication protocol, parse the pin logic signal, realize the read and write control of the chip to be programmed, and display and waveform analysis of the pin logic signal.

[0038] In this embodiment, the processor is used to transmit the collected pin logic signals of different communication protocols to the host computer through the programmer interface, so that the host computer can call the plug-in of the corresponding communication protocol, parse the pin logic signal, and then realize the logic detection function of the programmer under different communication protocols; in addition, the plug-in can be edited and updated by itself to realize the analysis of different protocols and quickly identify and troubleshoot problems.

[0039] In one embodiment, the host computer is also used to issue an error warning when an abnormal signal appears in the pin logic signal.

[0040] In this embodiment, by installing plug-ins of different communication protocols in the host computer, an error reminder can be given when an abnormal signal appears in the pin logic signal, thereby realizing the logic detection of the programmer and quickly troubleshooting the problem.

[0041] In one embodiment, the collection and output of logic signals of each pin of the chip to be programmed by a field programmable gate array includes: Receive the signal acquisition instruction sent by the host computer through the processor; the signal acquisition instruction includes one or more of sampling rate, sampling time, sampling voltage level, and sampling channel; The pin logic signals of the chip to be programmed are collected and output based on the signal collection instructions through the field programmable gate array.

[0042] In this embodiment, the processor receives the signal acquisition instruction sent by the host computer, and the field programmable gate array collects and outputs the pin logic signal of the chip to be programmed based on the signal acquisition instruction, which can realize the control of signal acquisition and further realize the logic detection function of the programmer.

[0043] In one embodiment, a logic detection method of a programmer is applied to a programmer, wherein the programmer includes a processor and a field programmable gate array connected to each other; the field programmable gate array is used to connect to a chip to be programmed, and includes: Step (a1), receiving a signal acquisition instruction sent by a host computer through a processor; the signal acquisition instruction includes one or more of a sampling rate, a sampling time, a sampling voltage level, and a sampling channel.

[0044] Step (a2), collecting and outputting the pin logic signal output by the level conversion circuit based on the signal acquisition instruction through the field programmable gate array; wherein the pin logic signal is obtained by receiving the signal output by the chip to be programmed through the level conversion circuit and comparing it with the comparison level.

[0045] Step (a3) ​​transmits the collected pin logic signals of different communication protocols to the host computer through the processor and the interface of the programmer, so that the host computer calls the plug-in of the corresponding communication protocol, parses the pin logic signal, realizes the read and write control of the chip to be programmed and displays and analyzes the waveform of the pin logic signal; the host computer is also used to issue an error reminder when an abnormal signal appears in the pin logic signal.

[0046] In this embodiment, the programmer is usually used together with the host computer, and the pin logic signals of the chip to be programmed are collected and output through the field programmable gate array to realize the real-time collection function of the chip; the processor transmits the collected pin logic signals to the host computer, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signals. The display and waveform analysis by the host computer rely on the existing hardware and do not require additional hardware to realize the programmer logic detection, which reduces the cost and is convenient for users and R&D personnel to analyze the underlying hardware protocol timing of the chip during the programming process, and can quickly locate the problem when the programming fails; in addition, the operation is simple and convenient, and does not require relevant personnel to use additional instruments and equipment, nor does it require complicated operating procedures, and can automatically realize real-time sampling of signals.

[0047] In one embodiment, the common logic detection methods in the field of general programmers are as follows: Method 1: Use various special measuring devices: such as logic analyzers, oscilloscopes, etc. Mount the device acquisition probe on the communication signal. When the programmer communicates with the integrated circuit, analyze and troubleshoot the problem by viewing the signal data collected by other measuring devices. Method 2: By adding additional detection circuits to the device hardware, the signal is detected and processed. When a specific abnormality occurs in the signal, it can be identified and an alarm can be issued through the detection circuit.

[0048] The disadvantages of the above method are: Method 1: This method requires the use of other instruments and equipment, which is costly. Using other devices is cumbersome and inefficient. It requires high requirements for developers, and usually requires certain professional knowledge to use these devices. At the same time, external devices are easy to affect the measured signal, which may be different from the actual signal. It is difficult to sample and analyze the internal signal of the programmer.

[0049] Method 2: It requires additional detection circuits, which is costly. The hardware circuit is fixed and cannot meet various abnormal situations. It is impossible to collect and analyze signals in real time.

[0050] Therefore, the purpose of this embodiment is to provide a method for implementing a universal programmer device with a logic detection function, which is low in cost and easy to use. Figure 5 As shown, it is an application environment diagram of the logic detection method of the programmer in one embodiment. Taking the processor as MCU as an example, Figure 5 It includes a host computer 120, a programmer 100 and a chip to be programmed 110 connected in sequence. The programmer 100 includes a main control chip and a level conversion circuit 106. The main control chip includes MCU102 and FPGA104. The host computer 120, MCU102, FPGA104, the level conversion circuit 106 and the chip to be programmed 110 are connected in sequence. The programmer 100 device adopts the ZYNQ7020 main control chip and the level conversion circuit 106 to realize the chip programming and chip pin logic signal real-time acquisition functions. The host computer 120 software displays waveforms and data, which is convenient for users and R&D personnel to analyze the underlying hardware protocol timing of the chip during the programming process, and can quickly locate the problem when the programming fails. The method of this embodiment can be used to self-check the status of the universal programmer 100 normally, conveniently and efficiently, to ensure the accuracy of the programming process of the universal programmer 100 and the health of the device itself. The method mainly includes the following parts: 1. Programmer logic signal sampling In order to ensure the safety of the programmer 100 ZYNQ7020 main control chip and adapt to the programming voltage requirements of different chips, the pins of the chip to be programmed 110 are not directly connected to the programmer 100 main control chip, but through the level conversion circuit 106. Figure 2 shown.

[0051] VCC is set as the power supply voltage of FPGA104, VDD is used to supply power to the chip 110 to be programmed, and GND is the normal ground. FPGA104 outputs the signal PFOUT, which is converted to PORT by the level conversion chip to realize the output function. VH is the comparison level, VH=VDD / 2, when PORT is higher than VH level, PFIN is a logic high level; when PORT is lower than VH level, PFIN is a logic low level to realize the input function; FPGA104 samples the PFIN level, that is, samples the external PORT logic signal, without adding the existing programmer 100 circuit hardware and without affecting the function of the existing circuit.

[0052] 2. Programmer logic signal transmission The programmer 100 ZYNQ7020 main control chip integrates MCU102 and FPGA104. The internal MCU102 and FPGA104 are connected through a high-speed AXI bus. FPGA104 collects PFIN signals in real time, compresses the sampled data using the RLE algorithm, and informs MCU102 to read the data through the DMA interrupt method. The main control chip MCU102 uploads the logic signal data collected by FPGA104 to the host computer 120 software through the high-speed USB2.0 interface and the Gigabit network port for display and analysis.

[0053] 3. Host computer software The host computer 120 software saves the data sent by the programmer 100 in time and generates a local data file for later inspection. Taking advantage of the relatively efficient performance of the computer, the host computer 120 software can also parse the data in real time and intuitively display the waveform of the signal. The host computer 120 software can support plug-ins of various protocols, such as SWIM, MDI, BDM and other common communication protocols. The plug-in can parse various protocols. When an abnormal signal is identified, an error reminder will be immediately reported. The interface is as follows: Figure 3 shown.

[0054] 4. Introduction to the system solution operation process 1. Connect the host computer 120 (such as a computer) and the programmer 100 via USB or an Ethernet port, open the host computer 120 software, and connect the programmer 100 to the integrated circuit to be programmed.

[0055] 2. Operate the host computer 120 software to select the corresponding option and click to program the integrated circuit to be programmed.

[0056] 3. The upper computer 120 software sends programming and signal acquisition instructions. The signal acquisition instructions include parameters such as sampling rate (unit Khz), sampling time (unit s), sampling voltage level (3.3V or 5V), sampling channels (<=8), etc. The programmer 100 programs the integrated circuit to be programmed, and the FPGA 104 collects the logic high and low levels of the PFIN pin in real time according to the signal acquisition parameters. The principle is described in the "Programmer Logic Signal Sampling" section.

[0057] 4. Programmer 100 processes and transmits data as described in the "Programmer Logic Signal Transmission" section.

[0058] 5. Programming is completed and acquisition stops. The host computer 120 software processes and displays the waveform as described in the "Host Computer Software Part" section. 6. Take out the programmed chip.

[0059] When problems occur in step 4 programming, the logic analyzer function of the host computer 120 software can directly give prompts for simple and common problems. At the same time, you can also manually view the logic signal data acquisition file to analyze the waveform, quickly and easily identify and eliminate the problem.

[0060] Compared with the conventional technology, the beneficial effects of this embodiment are as follows: 1) Low cost, relying on existing programmer hardware, no need to develop new hardware.

[0061] 2) The operation is simple and convenient, and does not require the relevant personnel to use additional instruments and equipment, and has low requirements for personnel 3) Efficient operation, no complicated operation process required, and can automatically realize real-time sampling of signals 4) Flexible to use, can automatically analyze problems. Strong scalability. Can edit and update plug-ins to analyze different protocols, can quickly identify and troubleshoot problems. In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method embodiments are implemented.

[0062] In one embodiment, a computer program product or computer program is provided, the computer program product or computer program includes computer instructions, the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in the above-mentioned method embodiments. Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes in the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0063] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A programmer with logic detection function, characterized in that: The programmer includes a processor and a field programmable gate array connected to each other; the field programmable gate array is used to connect to the chip to be programmed; The field programmable gate array is used to collect and output the pin logic signal of the chip to be programmed; The processor is used to transmit the collected pin logic signal to the host computer through the programmer interface, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signal.

2. The programmer according to claim 1, characterized in that: The programmer comprises a level conversion circuit, the field programmable gate array is connected to the level conversion circuit, and the level conversion circuit is used to connect to the chip to be programmed; The level conversion circuit is used to perform level conversion processing on the signal output by the field programmable gate array, and output the converted signal to the chip to be programmed; as well as The signal output by the chip to be programmed is received and compared with a comparison level to obtain the pin logic signal.

3. The programmer according to claim 1, characterized in that: The processor is used to transmit the collected pin logic signals of different communication protocols to the host computer through the programmer interface, so that the host computer calls the plug-in corresponding to the communication protocol to parse the pin logic signals.

4. The programmer according to claim 3, characterized in that: The host computer is also used to issue an error warning when an abnormal signal appears in the pin logic signal.

5. The programmer according to claim 1, characterized in that: The processor is used to receive the signal acquisition instruction issued by the host computer; the signal acquisition instruction includes one or more of sampling rate, sampling time, sampling voltage, and sampling channel; The field programmable gate array is used to collect and output the pin logic signal of the chip to be programmed based on the signal collection instruction.

6. A logic detection method for a programmer, characterized in that: Applied to a programmer, the programmer comprises a processor and a field programmable gate array connected to each other; the field programmable gate array is used to connect to a chip to be programmed; Collecting and outputting the pin logic signal of the chip to be programmed through the field programmable gate array; The collected pin logic signal is transmitted to a host computer through the processor and the interface of the programmer, so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signal.

7. The method according to claim 6, characterized in that The programmer comprises a level conversion circuit, the field programmable gate array is connected to the level conversion circuit, and the level conversion circuit is used to connect to the chip to be programmed; The method further comprises: Performing level conversion processing on the signal output by the field programmable gate array through the level conversion circuit, and outputting the converted signal to the chip to be programmed; The signal output by the chip to be programmed is received by the level conversion circuit and compared with the comparison level to obtain the pin logic signal.

8. The method according to claim 6, characterized in that The method of transmitting the collected pin logic signal to a host computer through the processor and the interface of the programmer so that the host computer can realize the read and write control of the chip to be programmed and display and waveform analysis of the pin logic signal includes: The pin logic signals of different communication protocols collected are transmitted to the host computer through the processor and the interface of the programmer, so that the host computer calls the plug-in corresponding to the communication protocol, parses the pin logic signal, realizes the read and write control of the chip to be programmed, and displays and performs waveform analysis on the pin logic signal.

9. The method according to claim 8, characterized in that The host computer is also used to issue an error warning when an abnormal signal appears in the pin logic signal.

10. The method according to claim 6, characterized in that The collecting and outputting the pin logic signal of the chip to be programmed through the field programmable gate array includes: Receiving, by the processor, a signal acquisition instruction issued by the host computer; the signal acquisition instruction includes one or more of a sampling rate, a sampling time, a sampling voltage level, and a sampling channel; The pin logic signal of the chip to be programmed is collected and outputted through the field programmable gate array based on the signal collection instruction.

Images