Data receiving circuit of memory architecture based on chiplet

Abstract

The present disclosure relates to a data receiving circuit of a chiplet-based storage architecture, the data receiving circuit may include: a forwarding fast clock domain configured to output data transmitted from a data transmission circuit in synchronization with a forwarding fast clock signal; and the local clock domain is configured to synchronously generate a synchronous acquisition enable signal with the local fast clock signal, and synchronously output the data sent from the forwarding fast clock domain with the local slow clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0137164, filed on October 13, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a data receiving circuit based on a chiplet storage architecture. Background Art

[0004] The limited system resources in various implementations of data storage systems or devices may not be able to meet the needs of such data storage systems or devices (including data storage systems or devices implemented with the latest system flexibility features). For example, when the storage architecture is configured in the form of a monolithic integrated circuit, a single-bone integrated circuit, or a system on a chip (SoC), the storage architecture has a host device connected to the storage architecture and an interface that is subordinate to the storage medium standard. This reveals an example of the limitation that the storage architecture is only valid for a host device and storage medium of a specific standard. Summary of the invention

[0005] According to an embodiment of the disclosed technology, a data receiving circuit may include: a forwarded fast clock domain, configured to output data sent from a data sending circuit in synchronization with a forwarded fast clock signal; and a local clock domain, configured to generate a synchronized fetch enable signal in synchronization with a local fast clock signal, and to output data sent from the forwarded fast clock domain in synchronization with a local slow clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram illustrating a data receiving circuit according to an embodiment of the disclosed technology.

[0007] Figure 2 It is shown Figure 1 FIG. 1 is a diagram of a generation timing of an acquisition enable signal in a buffer level comparator included in a forwarding fast clock domain of FIG.

[0008] Figure 3 It is shown Figure 1 A diagram of a target level configuration adjustment process in a buffer level comparator included in a forwarding fast clock domain.

[0009] Figure 4 It is shown Figure 1A timing diagram of the operation of the data receiving circuit. DETAILED DESCRIPTION

[0010] In the description of the following embodiments, it should be understood that the terms "first" and "second" are intended to identify elements, but are not used to define the specific number or order of elements. In addition, when an element is referred to as being "above", "on", "above", "below" or "below" another element, it is intended to represent a relative positional relationship, but is not intended to limit the specific case where the one element directly contacts another element or there is at least one intermediate element between two elements. Therefore, the terms such as "above", "on", "above", "below", "below" used herein are only used to describe specific embodiments and are not intended to limit the scope of the present disclosure. Further, when an element is referred to as "connected" or "coupled" to another element, the one element may be directly electrically connected or mechanically connected or coupled to another element, or may be indirectly electrically connected or mechanically connected or coupled to another element by one or more additional elements between two elements.

[0011] In addition, when a parameter is referred to as "predetermined", it may be intended to mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the beginning of the process or algorithm, or may be set during the operation of the process or algorithm.

[0012] Logical "high" levels and logical "low" levels can be used to describe the logical levels of electrical signals. A signal with a logical "high" level can be distinguished from a signal with a logical "low" level. For example, when a signal with a first voltage corresponds to a signal with a logical "high" level, a signal with a second voltage can correspond to a signal with a logical "low" level. In an embodiment, the logical "high" level can be set to a voltage level higher than the voltage level of the logical "low" level. On the other hand, depending on the embodiment, the logical level of the signal can be set to be different or opposite. For example, a signal with a logical "high" level in one embodiment can be set to have a logical "low" level in another embodiment.

[0013] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0014] Figure 1 is a block diagram illustrating a data receiving circuit 5000 according to an embodiment of the disclosed technology.

[0015] Reference Figure 1, the data receiving circuit 5000 may include a forwarding fast clock domain 5100 and a local clock domain 5200. Forwarding a fast clock domain refers to a situation where a clock signal with a higher frequency (faster clock) is used in a slower clock domain. As described below, in an embodiment, the local clock domain 5200 of the data receiving circuit 5000 includes a local fast clock domain 5210 and a local slow clock domain 5220 (slower clock). In an embodiment, the data receiving circuit 5000 may be included in a chiplet-based storage architecture, which includes a front-end chip and a plurality of back-end chips, as shown in the above example. The front-end chip may interface with a host device at a relatively high speed, and each of the plurality of back-end chips may interface with a memory device at a relatively low speed. The front-end chip and each of the plurality of back-end chips may send or receive data to each other through a link. The data receiving circuit 5000 according to an embodiment may be provided in a link included in each of the plurality of back-end chips of a chiplet-based storage architecture, but is not limited thereto.

[0016] The data receiving circuit 5000 may receive data from a data transmitting device (not shown) operating at a relatively high speed (hereinafter referred to as "high speed"), and transmit the received data to a data receiving device operating at a relatively low speed (hereinafter referred to as "low speed"). The forwarding fast clock domain 5100 of the data receiving circuit 5000 may transmit the data transmitted at a high speed to the local clock domain 5200 of the data receiving circuit 5000 in synchronization with the forwarding fast clock signal CLK_FF. The forwarding fast clock signal CLK_FF may have substantially the same period as the clock signal used in the data transmitting device. The local clock domain 5200 may transmit the data transmitted from the forwarding fast clock domain 5100 to the data receiving device (not shown) in synchronization with the local slow clock signal CLK_LS. The local slow clock signal CLK_LS may have substantially the same period as the clock used in the data receiving device. Therefore, the local slow clock signal CLK_LS may have a longer period than the forwarding fast clock signal CLK_FF. The local slow clock signal CLK_LS and the forwarding fast clock signal CLK_FF may have a phase difference from each other, or may have the same phase.

[0017] Generally, due to the clock speed difference between the forwarding fast clock domain 5100 and the local clock domain 5200, a synchronization operation is performed in the local clock domain 5200. When the synchronization operation in the local clock domain 5200 is performed synchronously with the local slow clock signal CLK_LS applied to the data receiving device, the time required for the synchronization operation may be unnecessarily increased, resulting in an increase in the data processing delay time (hereinafter referred to as "delay"). The local clock domain 5200 of the data receiving circuit 5000 according to the embodiment may include a local fast clock domain 5210 that performs the synchronization operation and a local slow clock domain 5220 that performs the data transmission operation to the data receiving device. The synchronization operation in the local fast clock domain 5210 may be performed synchronously with the local fast clock signal CLK_LF, which has a faster speed than the local slow clock signal CLK_LS. Therefore, compared with the case where the synchronization operation is performed synchronously with the local slow clock signal CLK_LS, the delay caused by the synchronization operation can be reduced. In an embodiment, the local fast clock signal CLK_LF may have a period corresponding to 1 / N (N is a natural number greater than 2) of the period of the local slow clock signal CLK_LS. In an embodiment, the local fast clock signal CLK_LF may have the same period as the forwarded fast clock signal CLK_FF, and may have a different phase from the forwarded fast clock signal CLK_FF. In addition, by performing logic processing on data during synchronization in the local fast clock domain 5210, an increase in delay due to logic processing in the local clock domain 5200 may also be suppressed.

[0018] Specifically, the forwarding fast clock domain 5100 may include a high-speed interface 5110 for interfacing with a data transmitting device, a forwarding data buffer 5120 for buffering data transmitted from the data transmitting device, and a buffer level comparator 5130 for generating an acquisition enable signal FE_EN for synchronization in the local clock domain 5200. The generation of the acquisition enable signal FE_EN means changing the logic level of the acquisition enable signal FE_EN from a first logic level (e.g., a logic "low" level) to a second logic level (e.g., a logic "high" level), which will be used in a similar manner for other signals discussed below.

[0019] The high-speed interface 5110 may receive data DATA transmitted from a data transmitting device, and transmit the received data DATA to a forwarding data buffer 5120. In addition, each time the high-speed interface 5110 transmits data DATA to the forwarding data buffer 5120, the high-speed interface 5110 may generate a data valid signal VALID, and transmit the data valid signal VALID to the buffer level comparator 5130. The forwarding data buffer 5120 may temporarily store the data DATA transmitted from the high-speed interface 5110. The forwarding data buffer 5120 may transmit the temporarily stored data DATA to the local fast clock domain 5210 in synchronization with the forwarding fast clock signal CLK_FF. In an embodiment, the forwarding data buffer 5120 may include a buffer block whose buffer depth is a specific size D, and the number of channels is a specific number C, and the number of channels C is arranged to be as many as the number of channels N. In this case, the number of registers constituting the forwarding data buffer 5120 may become "N×D×C".

[0020] The buffer level comparator 5130 can generate an acquisition enable signal FE_EN based on the data valid signal VALID sent from the high-speed interface 5110 to send the generated acquisition enable signal FE_EN to the local fast clock domain 5210. The buffer level comparator 5130 can receive the target level configuration TLC of the forwarding data buffer 5120 to generate the acquisition enable signal FE_EN. In this case, the buffer level comparator 5130 can derive the number of valid data based on the data valid signal VALID. The buffer level comparator 5130 can compare the obtained number of valid data with the target level configuration TLC. As a result of the comparison, when the number of valid data does not meet the target level configuration TLC, the buffer level comparator 5130 may not generate the acquisition enable signal FE_EN (i.e., the logic level of the acquisition enable signal FE_EN remains at the first logic level (i.e., the logic "low" level)). On the other hand, as a result of the comparison, when the number of valid data satisfies (i.e., matches) the target level configuration TLC, the buffer level comparator 5130 can generate an acquisition enable signal FE_EN (i.e., change the logic level of the acquisition enable signal FE_EN from a first logic level (i.e., a logic "low" level) to a second logic level (i.e., a logic "high" level)).

[0021] The buffer level configuration TLC sent to the buffer level comparator 5130 may be readjusted through a training process, and thus, the generation time of the acquisition enable signal FE_EN in the buffer level comparator 5130 may be changed. For example, when the buffer level of the forwarding data buffer 5120 is delayed, the buffer level comparator 5130 may receive an increased target level configuration TLC. On the other hand, when the buffer level of the forwarding data buffer 5120 is reduced, the buffer level comparator 5130 may receive a reduced target level configuration TLC. In an embodiment, the buffer level comparator 5130 may be configured to output the acquisition enable signal FE_NE at a point in time when the data timing deviation range of the forwarding data buffer 5120 for data sent from the high-speed interface 5110 has passed, which will be referred to below. Figure 2 Explain in more detail.

[0022] The local clock domain 5200 may include a local fast clock domain 5210 operating in synchronization with a local fast clock signal CLK_LF and a local slow clock domain 5220 operating in synchronization with a local slow clock signal CLK_LS. The local fast clock domain 5210 may include a synchronization circuit 5211 and a logic circuit 5212. The local slow clock domain 5220 may include a local data buffer 5221.

[0023] The synchronization circuit 5211 included in the local fast clock domain 5210 may receive the acquisition enable signal FE_EN output from the buffer magnitude comparator 5130 of the forwarding fast clock domain 5100. The synchronization circuit 5211 may perform a synchronization operation on the acquisition enable signal FE_EN and send a synchronization acquisition enable signal FE_EN_SYNC to the local data buffer 5221 of the local slow clock domain 5220. In an embodiment, the synchronization circuit 5211 may include a plurality of flip-flops connected in series with each other. Figure 1 In the figure, the synchronization circuit 5211 includes two flip-flops, but this is only an example, and the synchronization circuit 5211 may include more than two flip-flops.

[0024] The plurality of flip-flops may perform synchronization operations in synchronization with the local fast clock signal CLK_LF. The first flip-flop among the plurality of flip-flops may receive the acquisition enable signal FE_EN from the buffer magnitude comparator 5130 through the data input terminal and latch the acquisition enable signal FE_EN. The first flip-flop may be synchronized with the local fast clock signal CLK_LF to send the latched acquisition enable signal FE_EN to the data input terminal of the second flip-flop through the data output terminal. The last flip-flop among the plurality of flip-flops (for example, when Figure 1When the synchronization circuit 5211 includes two triggers, the last trigger is the second trigger) can latch the acquisition enable signal FE_EN sent from the first trigger. The last trigger can output the latched acquisition enable signal FE_EN as the synchronous acquisition enable signal FE_EN_SYNC in synchronization with the local fast clock signal CLK_LF.

[0025] The logic circuit 5212 included in the local fast clock domain 5210 may receive the data DATA output from the forwarding data buffer 5120 of the forwarding fast clock domain 5100 to perform logic processing. The logic circuit 5212 may send the data after the logic processing to the local data buffer 5221 of the local slow clock domain 5220. The time period for performing the logic processing in the logic circuit 5212 may overlap with the time period for performing the synchronization operation in the synchronization circuit 5211. In an embodiment, the logic circuit 5212 may start to perform the logic processing after the synchronization circuit 5211 starts to perform the synchronization operation, and may complete the logic processing after the synchronization operation is completed in the synchronization circuit 5211. However, this is only an example, and the logic processing in the logic circuit 5212 may be completed before the synchronization operation is completed in the synchronization circuit 5211. In an embodiment, the logic circuit 5212 may include a decoder circuit, a descrambling circuit, a deserialization circuit, and the like.

[0026] The local data buffer 5221 included in the local slow clock domain 5220 can receive data DATA from the logic circuit 5212 of the local fast clock domain 5210 and temporarily store the data DATA. The local data buffer 5221 can send the temporarily stored data DATA to the data receiving device based on the synchronous acquisition enable signal FE_EN_SYNC and the local slow clock signal CLK_LS. The local data buffer 5221 can output the data DATA in synchronization with the local slow clock signal CLK_LS when the synchronous acquisition enable signal FE_EN_SYNC is at a second logic level (e.g., a logic "high" level). Therefore, when the synchronous acquisition enable signal FE_EN_SYNC is at a first logic level (i.e., a logic "low" level), the local data buffer 5221 may not output the data DATA regardless of the local slow clock signal CLK_LS.

[0027] Figure 2 It is shown Figure 1 4 is a diagram of a generation timing of a fetch enable signal FE_EN in a buffer level comparator 5130 included in a forwarding fast clock domain 5100.

[0028] Reference Figure 2 and Figure 1, assuming that the first data DATA_A and the second data DATA_B are transmitted from the high-speed interface 5110 of the forwarding fast clock domain 5100 to the forwarding data buffer 5120 at different timings. In the example, the first data DATA_A is transmitted from the high-speed interface 5110 to the forwarding data buffer 5120 at a first time point T1. The second data DATA_B is transmitted from the high-speed interface 5110 to the forwarding data buffer 5120 at a second time point T2 later than the first time point T1. In this case, the data timing deviation of the registers included in the forwarding data buffer 5120 for the first data DATA_A and the second data DATA_B corresponds to a time period from the first time point T1 to the second time point T2.

[0029] As reference Figure 1 As described above, the forwarding data buffer 5120 may include a number of registers corresponding to "N×D×C" ("N" is the number of paths, "D" is the size of the buffer depth, and "C" is the number of channels). As the number of registers increases, it is not easy to adjust the data timing deviation at a certain level (e.g., picosecond (ps) level). In this case, Figure 2 As shown by the thin solid line in the middle, when the time point at which the logic level of the acquisition enable signal FE_EN changes from a first logic level (e.g., a logic "low" level) to a second logic level (e.g., a logic "high" level) is within the data timing deviation, for the second data DATA_B input later at the time point, the data will be input into the forwarding data buffer 5120 later than the acquisition enable signal FE_EN used in the synchronization operation. In this case, the time point at which the data is sent to the logic circuit 5212 may be later than the time point at which the acquisition enable signal FE_EN is sent to the synchronization circuit 5211 of the local fast clock domain 5210. Therefore, the time required for the logic processing of the data in the logic circuit 5212 can be reduced. Therefore, in the example, as Figure 2 As shown by the thick line in the middle, at the time point when the data timing deviation range has passed, the logic level of the acquisition enable signal FE_EN changes from the first logic level (e.g., logic "low" level) to the second logic level (e.g., logic "high" level). Therefore, all data can be input to the forwarding data buffer 5120 before the acquisition enable signal FE_EN is generated. Therefore, the logic processing operation in the logic circuit 5212 can be performed while the synchronization circuit 5211 is operating.

[0030] Figure 3 yes Figure 1 FIG. 5 is a diagram showing an adjustment process of a target level configuration TLC in a buffer level comparator 5130 included in a forwarded fast clock domain 5100. In an embodiment, it is assumed that the original target level configuration TLC in the buffer level comparator 5130 is set to "4".

[0031] Reference Figure 3 and Figure 1 , first, it is assumed that data is sent to the forwarding data buffer 5120 at one cycle interval of the forwarding fast clock signal CLK_FF. Therefore, according to the buffer order in an ideal case where there is no timing error, data can be sent to the forwarding data buffer 5120 as follows: the first data 0 is input during the first cycle of the forwarded fast clock signal CLK_FF, the second data 1 is input during the second cycle, the third data 2 is input during the third cycle, the fourth data 3 is input during the fourth cycle, the fifth data 4 is input during the fifth cycle, the sixth data 5 is input during the sixth cycle, and the seventh data 6 is input during the seventh cycle.

[0032] However, in actual applications, timing errors may occur due to PVT (process, voltage, temperature) variations, off-chip delays, simulation errors, etc. For example, when a timing error corresponding to one cycle of the forwarding fast clock signal CLK_FF occurs, data may be sent to the forwarding data buffer 5120 in the following manner: no data is input during the first cycle of the forwarding fast clock signal CLK_FF, first data 0 is input during the second cycle, second data 1 is input during the third cycle, third data 2 is input during the fourth cycle, fourth data 3 is input during the fifth cycle, fifth data 4 is input during the sixth cycle, sixth data 5 is input during the seventh cycle, and seventh data 6 is input during the eighth cycle. Therefore, the first data 0 to the seventh data 6 are all delayed by a time corresponding to one cycle of the forwarding fast clock signal CLK_FF, and then input to the forwarding data buffer 5120.

[0033] Because the original target magnitude is configured as "4", at the end of the fourth cycle of the forwarded fast clock signal CLK_FF, the logic level of the acquisition enable signal (hereinafter referred to as "the first acquisition enable signal FE_EN1") changes from the first logic level (e.g., logic "low" level) to the second logic level (e.g., logic "high" level), and at this time, the number of data valid signals VALID, that is, the number of data inputs corresponds to "4". However, when a timing error corresponding to one cycle of the forwarded fast clock signal CLK_FF occurs, when only three data are input instead of four data, an error occurs in the change of the logic level of the first acquisition enable signal FE_EN1 from the first logic level (e.g., logic "low" level) to the second logic level (e.g., logic "high" level). In this case, as shown in reference Figure 1As described, when the target magnitude configuration is modified from "4" to "5" through the training process, at the end of the fifth cycle of the forwarding fast clock signal CLK_FF, the logic level of the acquisition enable signal (hereinafter referred to as the "second acquisition enable signal FE_EN2") changes from the first logic level (e.g., logic "low" level) to the second logic level (e.g., logic "high" level), and at this time, the number of data valid signals VALID, that is, the number of data inputs corresponds to "4". Therefore, in the state of inputting four data (i.e., the first data 0 to the fourth data 3), the logic level of the first acquisition enable signal FE_EN1 changes from the first logic level (e.g., logic "low" level) to the second logic level (e.g., logic "high" level). Therefore, by modifying the target magnitude configuration from "4" to "5", the problem caused by the timing error can be solved.

[0034] Figure 4 It is shown Figure 1 The operation of the data receiving circuit 5000 and the delay reduction process caused thereby are shown in the timing diagram. In the embodiment, it is assumed that the local fast clock signal CLK_LF has a period corresponding to 1 / 2 of the period of the local slow clock signal CLK_LS and has the same period as the forwarded fast clock signal CLK_FF. In addition, it is assumed that the forwarded fast clock signal CLK_FF is faster than the local fast clock signal CLK_LF and the local slow clock signal CLK_LS by a phase corresponding to 1 / 4 of the period of the forwarded fast clock signal CLK_FF. In the embodiment, the reference is not considered. Figure 2 Describes the timing deviation of the data.

[0035] Reference Figure 4 and Figure 1 At the first time point T1 when the first rising edge of the forwarding fast clock signal CLK_FF is generated, data A (hereinafter referred to as "first data DATA1") is output from the forwarding data buffer 5120 of the forwarding fast clock domain 5100. The first data DATA1 output from the forwarding data buffer 5120 is sent to the logic circuit 5212 of the local fast clock domain 5210. Figure 4, the data sent to the logic circuit 5212 is represented as the second data DATA2. At the first time point T1, the buffer magnitude comparator 5130 of the forwarding fast clock domain 5100 sends the acquisition enable signal FE_EN of the second logic level (e.g., logic "high" level) to the synchronization circuit 5211 of the local fast clock domain 5210. At the first time point T1 when the acquisition enable signal FE_EN of the second logic level (e.g., logic "high" level) is input, the synchronization circuit 5211 starts to perform the synchronization operation. Assuming that the synchronization operation in the synchronization circuit 5211 is performed during one cycle of the local fast clock signal CLK_LF, at the third time point T3 when the second rising edge of the local fast clock signal CLK_LF is generated, the synchronization circuit 5211 outputs the synchronization acquisition enable signal FE_EN_SYNC of the second logic level (e.g., logic "high" level), and sends the synchronization acquisition enable signal FE_EN_SYNC to the local data buffer 5221 of the local slow clock domain 5220.

[0036] The logic circuit 5212 of the local fast clock domain 5210 starts to perform logic processing on the second data DATA2 from the second time point T2 when the first rising edge of the local fast clock signal CLK_LF is generated. The logic circuit 5212 sends the logic-processed data (hereinafter referred to as "valid data") to the local data buffer 5221 of the local slow clock domain 5220 at the fourth time point T4 when the logic processing is completed.

[0037] The local data buffer 5221 of the local slow clock domain 5220 outputs the valid data (hereinafter referred to as "third data DATA3") transmitted from the logic circuit 5212 of the local fast clock domain 5210 in synchronization with the local slow clock signal CLK_LS. At the fifth time point T5 when a rising edge is first generated after the third time point T3 when the logic level of the synchronization acquisition enable signal FE_EN_SYNC changes from a logic "low" level to a logic "high" level, the valid data (for example, the third data DATA3) is output from the local data buffer 5221.

[0038] According to the operation of the data receiving circuit 5000, the synchronization operation in the synchronization circuit 5211 of the local fast clock domain 5210 may be performed in a time period (from a first time point T1 when the first data DATA1 (A) is transmitted from the forwarding data buffer 5120 of the forwarding fast clock domain 5100 to a third time point T3 when the second rising edge of the local fast clock signal CLK_LF is generated. Figure 4The logic processing in the logic circuit 5212 of the local fast clock domain 5210 may be performed during a time period from a second time point T2 at which the first rising edge of the local fast clock signal CLK_LF is generated to a fourth time point T4 at which the second data DATA2 after the logic processing is output from the logic circuit 5212 ( Figure 4 That is, the synchronization operation and the logic processing can be executed simultaneously and in parallel during the time period from the second time point T2 to the third time point T3.

[0039] On the other hand, in the case of a typical data receiving circuit that does not apply the local fast clock signal CLK_LF, the synchronization operation is performed synchronously with the local slow clock signal CLK_LS. Therefore, in the time period (T1) from the first time point when the logic level of the acquisition enable signal FE_EN changes to the logic "high" level to the fifth time point T5 when the first rising edge of the local slow clock signal CLK_LS is generated after the synchronous acquisition enable signal FE_EN_SYNC of the logic "high" level is generated, Figure 4 In addition, because the logic processing is performed after the synchronization operation is completed, the logic processing is performed during the time period from the fifth time point T5 when the synchronization processing is completed to the sixth time point T6 when the logic processing ends ( Figure 4 At the seventh time point T7 when the first rising edge of the local slow clock signal CLK_LS is generated after the sixth time point T6, data is output from the local data buffer of the local clock domain. Therefore, due to the time period between the fifth time point T5 when the data receiving circuit 5000 according to the disclosed technology outputs data and the seventh time point T7 when the data is output from the typical data receiving circuit, a total delay difference is generated.

[0040] The above describes a limited number of possible embodiments of this teaching only for illustrative purposes. It will be appreciated by those skilled in the art that various modifications, additions and substitutions may be made. Although this patent document contains many details, these should not be interpreted as limitations on the scope of this teaching or the content that may be claimed, but rather as descriptions of features that may be specific to a particular embodiment. The specific features described in the context of a separate embodiment in this patent document may also be implemented in combination in a single embodiment. On the contrary, the individual features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in a variety of embodiments. In addition, although the above features may be described as, or even initially stated to work in a particular combination, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a change in a sub-combination or a sub-combination.

Claims

1. A data receiving circuit, comprising: The forwarding fast clock domain outputs the data sent from the data sending circuit synchronously with the forwarding fast clock signal; as well as The local clock domain communicates with the forwarding fast clock domain, generates a synchronous acquisition enable signal in synchronization with the local fast clock signal, and outputs data sent from the forwarding fast clock domain in synchronization with the local slow clock signal.

2. The data receiving circuit according to claim 1, wherein: The period of the local slow clock signal is longer than the period of the forwarded fast clock signal.

3. The data receiving circuit according to claim 2, wherein: The local fast clock signal has a period corresponding to 1 / N of a period of the local slow clock signal, where N is a natural number greater than 2.

4. The data receiving circuit according to claim 3, wherein: The local fast clock signal has the same period as the forwarded fast clock signal but has a different phase than the forwarded fast clock signal.

5. The data receiving circuit according to claim 1, wherein: The forwarding fast clock domain includes: a high-speed interface that performs high-speed interfacing on data transmitted from the data transmission circuit; and The forwarding data buffer performs buffering on the data sent through the high-speed interface and outputs the data to the local clock domain in synchronization with the forwarding fast clock signal.

6. The data receiving circuit according to claim 5, wherein: The high-speed interface outputs a data valid signal, and the data valid signal indicates whether the data transmitted from the data transmission circuit is valid.

7. The data receiving circuit according to claim 6, wherein: The forwarded fast clock domain further includes a buffer level comparator that generates and outputs a fetch enable signal based on the data valid signal.

8. The data receiving circuit according to claim 7, wherein: The buffer level comparator outputs the acquisition enable signal at a point in time when a data timing deviation range of the forwarding data buffer for data transmitted from the high-speed interface has passed.

9. The data receiving circuit according to claim 7, wherein: The buffer level comparator compares the amount of valid data obtained based on the data valid signal with the target level configuration of the forwarding data buffer, and generates the acquisition enable signal based on the comparison result to send the acquisition enable signal to the synchronization circuit.

10. The data receiving circuit according to claim 9, wherein: The buffer level comparator adjusts the target level configuration through a training process.

11. The data receiving circuit according to claim 10, wherein: The buffer level comparator: When the buffer level of the forwarding data buffer is delayed, increasing the target level configuration, and When the buffer level of the forwarding data buffer is reduced, the target level configuration is reduced.

12. The data receiving circuit according to claim 9, wherein: The local clock domain includes: Local fast clock domain, including synchronous circuits and logic circuits; and The local slow clock domain includes the local data buffer.

13. The data receiving circuit according to claim 12, wherein: The synchronization circuit includes a plurality of flip-flops connected in series with each other and operating in synchronization with the local fast clock signal, A first flip-flop among the plurality of flip-flops receives the acquisition enable signal, and A last flip-flop among the plurality of flip-flops outputs a synchronous acquisition enable signal to send the synchronous acquisition enable signal to the local data buffer.

14. The data receiving circuit according to claim 12, wherein: The logic circuit receives the data output from the forwarding data buffer to perform logic processing, and sends the logic-processed data to the local data buffer.

15. The data receiving circuit according to claim 14, wherein: The logic circuit starts executing logic processing after the synchronization operation starts to be executed in the synchronization circuit, and completes the logic processing after the synchronization operation is completed.

16. The data receiving circuit according to claim 15, wherein: The local data buffer outputs data in synchronization with the local slow clock signal after the logic processing is completed.

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