Temperature detection system module division method and division system

Abstract

The invention belongs to the technical field of intelligent temperature detection, and discloses a temperature detection system module division method and system. According to the method, through the design of interface transmission, instruction analysis, peripheral control and an interface conversion module, the designed interface time sequence of the peripheral device is converted into a universal interface time sequence, or the universal interface time sequence is converted into the interface time sequence of the peripheral device, so that an FPGA internal module does not pay attention to the time sequence of the peripheral interface any more, and the reliability of the FPGA is improved. And finally completing division of multiple modules in temperature detection. According to the invention, other modules in the FPGA do not need to concern the time sequence of the peripheral interface any more. According to the modular design, the readability of codes can be improved, the design thought is clearer, division of labor and independent testing of large-scale design are facilitated, and maintenance and reuse of design files are facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of intelligent temperature detection, and in particular relates to a temperature detection system module division method and division system. Background Art

[0002] With the advancement of science and technology, temperature detection has become increasingly important in all walks of life. Especially in the fields of industrial control, meteorological observation, environmental testing, etc., accurate temperature detection and real-time feedback play a vital role.

[0003] Modular design is an important method for designing complex digital systems. It is beneficial to the division of labor, testing, and code reading, maintenance, and reuse of complex designs. Module division is very important. It is related to whether the ability of project members to collaborate in design can be maximized. More importantly, it directly determines the integration of the design, the time and efficiency of implementation, and the reuse of the design.

[0004] Through the above analysis, the problems and defects of the prior art are as follows: in the modular design of the prior art, the code readability is poor, which is not convenient for the division of labor and cooperation and independent temperature testing of large-scale designs, and the maintenance and reuse of temperature detection design files are poor. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the embodiments disclosed in the present invention provide a temperature detection system module partitioning method and a partitioning system, and more particularly, relate to a temperature detection system module partitioning method based on FPGA, and a key code implementation method in software design.

[0006] The technical scheme is as follows: The module division method of the temperature detection system converts the interface timing of the peripheral device into the universal interface timing, or converts the universal interface timing into the peripheral device interface timing through the design of interface transmission, instruction parsing, peripheral control, and interface conversion modules, so that the internal module of the FPGA no longer pays attention to the timing of the peripheral interface, and completes the division of multiple modules in temperature detection; specifically, the following steps are included: S1, defines the functional requirements information in the interaction between the host computer and FPGA; S2, build a block diagram of the hardware system structure of adding peripheral devices, and determine the peripheral device information required in addition to FPGA according to the functional requirements; the peripheral devices include computers, digital tubes, temperature sensors, and buzzers; S3, designing an interface conversion module based on adding a peripheral device hardware system, and obtaining a hardware system designed after adding the interface conversion module; S4, designing an instruction system according to the hardware system designed after adding the interface conversion module; obtaining the hardware system added with the register parsing module; S5, based on the hardware system with the register parsing module added, configure the peripheral device registers; S6, adjusting and improving the design of the module according to the hardware system configured by the peripheral device register, and obtaining the hardware system after the module adjustment and improvement; S7, after adjusting and improving the module, the hardware system is designed for rate matching and used in temperature detection engineering.

[0007] In step S1, the functional requirement information in the interaction between the host computer and the FPGA is defined, including: the host computer sends instructions to the FPGA, wherein the instructions include: switching digital tube display data, buzzer switch control, resetting the temperature sensor, turning on temperature conversion, reading the converted temperature value, setting the upper and lower limits of the alarm temperature; reading and writing the temperature sensor, digital tube display and switch control, calculating the temperature value and sending the calculated temperature value to the host computer; setting the upper and lower limits of the temperature.

[0008] In step S3, the interface conversion module includes: Serial port interface module in the communication between the host computer and FPGA; Digital tube interface module, used to complete the output of digital tube position selection and segment selection; The single bus 1bit interface module is used to convert the temperature sensor single bus protocol into 1bit and perform 1bit data transmission; Buzzer interface module, used to enable the buzzer switch; The host computer sends instructions to the FPGA to configure the temperature sensor, configure the upper and lower limits of the temperature alarm, and send instructions to control the digital tube display to turn off and the buzzer to turn on and off. A register parsing module is added to the FPGA; the register parsing module parses the configuration register value and then configures the temperature sensor.

[0009] In step S6, the module is adjusted and the design is improved, including: The ASCII code sent by the host computer is converted into the corresponding hexadecimal through the ASCII code to 8-bit hexadecimal module FPGA; The packet header detection module detects the packet header of the received packet converted into the corresponding hexadecimal format, and retains the packet that meets the correct packet header conditions, otherwise the packet is discarded, thus completing the filtering of the received valid packet; After the package is tested, the instructions are parsed by the register parsing module and sent to the temperature sensor, digital tube display switch control module, digital tube interface module and buzzer interface module respectively according to the instruction function requirements; The 8-bit data sent by the register parsing module is converted to 1-bit by the 8-bit to 1-bit module and then sent to the single bus conversion interface module, and then to the temperature sensor; The real-time temperature comparison module determines whether the real-time temperature is greater than the upper limit or less than the lower limit, and issues a temperature alarm. The 1-bit data transmitted by the temperature sensor to the FPGA through the single bus conversion interface module is converted into 8-bit data through the data processing module; The 8-bit temperature value converted by the data processing module is converted into ASCII code through the 8-bit hexadecimal data conversion module, and the ASCII code format data is sent to the host computer through the serial port sending module; The hexadecimal code after data processing is converted into BCD code by the hexadecimal to BCD code module and sent to the digital tube interface module.

[0010] Furthermore, the 8-bit data sent from the register parsing module is converted into 1-bit by the 8-bit to 1-bit conversion module. To ensure the transmission rate, the conversion method includes: Assume that any temperature single bus line of the input 8-bit to 1-bit module The length of the data packet is , then the The segmenter is divided into index bits Information Bit The two parts are: (1) Let index number be The width of the sub-buffer is , then the total width of the buffer satisfies: (2) In the formula, is the total width of the buffer; Define entry into each sub-buffer The number of vectors , let the length be of The statistical probability of occurrence is , input 8bit to 1bit module The expected length is ,but satisfy: (3) In the formula, is the statistical probability, , is the initial length of the message, The length is of The specific number of data bits entering the buffer, is the total width of the buffer, The total length of the buffer.

[0011] Further, the way to improve the transmission rate: the communication register analysis module cache storage and transmitted super packets , are just input 8bit to 1bit module In block information; The data is implicit in the super data packet In the inherent order, to increase the transmission rate of communication; then the transmission rate It is expressed as: (4) In the formula, is the expected length.

[0012] Furthermore, the 8-bit data sent by the register parsing module is converted into 1-bit by the 8-bit to 1-bit conversion module. To ensure that communication is maintained at all times, the conversion method includes: The register parsing module periodically sends the length information of each sub-byte data block after dynamic adjustment of the buffer area to the single bus 1bit interface module so that the single bus 1bit interface module can complete the implicit information The recovery of the data transmission overhead is called feedback data overhead, which is recorded as ; Each transmission is used for the single bus 1bit interface module to complete the implicit information The recovered feedback data is valid at least until the next sub-buffer dynamic adjustment. The resulting decreased communication efficiency is expressed as: (5) In the formula, Feedback data overhead bits for each column sub-buffer, is the communication time, is the effective height of the buffer area, is the total width of the buffer; The feedback data is transmitted in differential form. The maximum value of the difference between the binary values ​​of the sub-buffers in the same column after the current dynamic adjustment and the previous adjustment is used as the number of bits of overhead for each sub-buffer in the current adjustment. After multiple adjustments, Then it decreases and finally stabilizes.

[0013] Furthermore, the 8-bit data sent from the register parsing module is converted into 1-bit by the 8-bit to 1-bit conversion module. To avoid communication delay, the conversion method further includes: Assume that the transmission rate of the super data packet on the channel is , the transmission time of each data packet in the channel is , then: (6) In the formula, It is a super data packet; Get the maximum delay of the buffer byte data block waiting for: (7) In the formula, is the transmission time of each data packet in the channel, The maximum buffer height after the cache area is dynamically adjusted; Considering the communication efficiency and transmission rate comprehensively, the communication delay is kept at Within, there are: (8) In the formula, The primary delay for waiting for a byte data block in the buffer; In order to make full use of the cache resources and improve the information transmission rate, the storage capacity in the memory is the storage overhead, which is recorded as ; Storage overhead The value of is related to the memory capacity and communication delay, and is: (9) Quantitatively analyze the communication overhead and communication delay, and plan a solution with the minimum communication overhead, the best communication delay, and the best communication efficiency; according to the transmission rate , Maximum delay and storage overhead The relationship between , defines the utility function of communication efficiency , the optimization objective function is expressed as: (10) In the formula, For communication efficiency; The effective buffer height after dynamic adjustment of the buffer area Whether it affects the overall communication efficiency of both parties.

[0014] In step S7, the rate matching design is performed on the hardware system after the module adjustment and improvement, including: (1) Determine whether handshake signals are required on the interface for communicating with peripheral devices; (2) Determine whether the temperature sensor can always respond to operation instructions; (3) Set a handshake signal between the single bus bit interface conversion module and the 8-bit to 1-bit module; (4) Set a handshake signal between the serial port sending module and the hexadecimal to ASCII code module; introduce FIFO first-in first-out data processing and organization method into the hexadecimal to ASCII code module.

[0015] Another object of the present invention is to provide a temperature detection system module division system, the system implements the temperature detection system module division method, the system comprises: Functional requirement definition unit, used to define the functional requirement information in the interaction between the host computer and FPGA; The peripheral device hardware system construction unit is used to construct a block diagram of the hardware system with added peripheral devices, and determine the peripheral device information required in addition to the FPGA according to the functional requirements; the peripheral devices include computers, digital tubes, temperature sensors, and buzzers; The interface conversion module hardware unit designs the interface conversion module based on adding the peripheral device hardware system, and obtains the hardware system designed after adding the interface conversion module; The register parsing module hardware unit is used to design the instruction system according to the designed hardware system after adding the interface conversion module; and obtain the hardware system after adding the register parsing module; A register configuration unit, used for configuring peripheral device registers based on a hardware system to which a register parsing module is added; The corresponding module adjustment and improvement unit is used to adjust and improve the design of the module according to the hardware system configured by the peripheral device register, and obtain the hardware system after the module adjustment and improvement; The rate matching unit is used to design the rate matching of the hardware system after module adjustment and improvement, and is used in temperature detection projects.

[0016] In combination with all the above-mentioned technical solutions, the beneficial effects possessed by the present invention are as follows: the present invention proposes an intelligent temperature detection system based on FPGA, and provides a module division method, which can display the current temperature value in real time and can alarm according to the set threshold. The present invention provides a module division method for a temperature detection system, which involves interface transmission, instruction parsing, and peripheral control. An interface conversion module is provided, and the interface timing of the peripheral device is converted into a universal interface timing, or the universal interface timing is converted into the interface timing of the peripheral device, so that other modules inside the FPGA no longer need to care about the timing of the peripheral interface. Modular design can improve the readability of the code, make the design ideas clearer, facilitate the division of labor and independent testing of large-scale designs, and help maintain and reuse design files. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure; Figure 1 is a flow chart of a method for dividing modules of a temperature detection system provided by an embodiment of the present invention; Figure 2 It is a block diagram of the hardware system structure of adding peripheral devices provided by an embodiment of the present invention; Figure 3 This is the hardware system structure diagram after adding the interface conversion module; Figure 4 The block diagram of the hardware system structure with the register parsing module added; Figure 5 To adjust and improve the hardware system block diagram for the corresponding modules. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0019] Embodiment 1: The method for dividing the temperature detection system modules provided by the embodiment of the present invention includes: S1, defines the functional requirements information in the interaction between the host computer and FPGA; The host computer sends a series of different functional instructions to the FPGA. After receiving the instructions, the FPGA executes the operations corresponding to each instruction. At the same time, the temperature value collected by the temperature sensor DS18B20 is displayed in real time on the digital tube and transmitted to the host computer. The host computer is required to send commands to set the upper and lower limits of the alarm temperature. When the temperature value exceeds the upper or lower limit, the buzzer starts to sound. You can send commands to turn off or turn on the digital tube display.

[0020] The functional requirements include: The host computer sends instructions to the FPGA (turn on and off the digital tube display, turn on and off the buzzer, reset the temperature sensor, turn on the temperature conversion, read the converted temperature value, and set the upper and lower limits of the alarm temperature); Read and write DS18B20; Digital tube display; Digital tube display switch control; Calculate temperature value; Send the calculated temperature value to the host computer; Set the upper and lower temperature limits; Buzzer switch control.

[0021] S2, build a block diagram of the hardware system structure of adding peripheral devices, and determine the peripheral device information required in addition to FPGA according to the functional requirements; the peripheral devices include computers, digital tubes, temperature sensors, and buzzers; A total of four peripheral devices are required: computer, digital tube, temperature sensor DS18B20, buzzer. The hardware system structure diagram is as follows Figure 2 shown.

[0022] S3, designing an interface conversion module based on adding a peripheral device hardware system, and obtaining a hardware system designed after adding the interface conversion module; The communication between the host computer and FPGA involves both sending and receiving. Since the speed at which the computer sends commands to the FPGA is slower than the speed at which the FPGA sends back temperature values ​​to the computer, the speed of the communication interface between the host computer and the FPGA depends on the speed at which the FPGA sends back temperature values ​​to the computer. It takes 750ms for the temperature sensor DS18B20 to convert a collected temperature value. Therefore, if the communication interface rate between the FPGA and the host computer is greater than 750ms, data will not be lost. Therefore, the use of the serial port as the communication interface between the host computer and the FPGA is sufficient to meet the requirements. The serial port uses a serial port interface module; Furthermore, the following interface modules are also involved, including: Digital tube interface module, used to complete the output of digital tube position selection and segment selection; Single bus 1bit interface module, used to convert DS18B20 single bus protocol into 1bit and perform 1bit data transmission; Buzzer interface module, used to enable the buzzer switch; The hardware system structure diagram after adding the interface conversion module is as follows: Figure 3 shown.

[0023] S4, designing an instruction system according to the hardware system designed after adding the interface conversion module; obtaining the hardware system added with the register parsing module; The present invention relates to an instruction system. The host computer needs to send instructions to the FPGA to configure the temperature sensor, the upper and lower limits of the temperature alarm, and at the same time, send instructions to control the digital tube display to turn off and the buzzer to turn on. Therefore, after adding the interface conversion module, the hardware system of the design needs to add a "register analysis module", as follows Figure 4 The hardware system diagram with the register parsing module added is shown in the figure.

[0024] S5, based on the hardware system with the register parsing module added, configure the peripheral device registers; In the present invention, the temperature sensor DS18B20 needs to configure the internal registers, but the present invention does not adopt the MDY template method (the method of reading the configuration register table to configure the DS18B20), but sends the configuration command through the host computer, and parses the configuration register value through the register parsing module to configure the temperature sensor DS18B20.

[0025] S6, adjusting and improving the design of the module according to the hardware system configured by the peripheral device register, and obtaining the hardware system after the module adjustment and improvement; The received data is the ASCII code sent by the host computer. In order to facilitate the FPGA to parse the instructions, the ASCII code needs to be decoded and converted into the corresponding hexadecimal. Therefore, an ASCII code to 8-bit hexadecimal module is required; Furthermore, it is necessary to detect the packet header of the received packet, and retain the packet that meets the correct packet header conditions, otherwise discard the packet. Therefore, a packet header detection module is needed to filter the valid packets received; Furthermore, after passing through the register parsing module, the instruction will be parsed out and may be sent to the temperature sensor DS18B20, the digital tube display switch control module, the digital tube segment selection interface module, and the buzzer control interface module according to the instruction function requirements; Furthermore, the register parsing module sends 8-bit data, which cannot be sent directly to DS18B20 (DS18B20 only receives single bit), so an 8-bit to 1-bit conversion module is required between the register parsing module and the single bus conversion interface module; Furthermore, the temperature alarm function needs to determine whether the real-time temperature is greater than the upper limit or less than the lower limit. Therefore, a real-time temperature value comparison and judgment module is required; Furthermore, the collected temperature data is transmitted to the FPGA through the single-bit interface conversion module as single-bit data. In order to facilitate the FPGA to process the data later, 1 bit needs to be converted to 8 bits. Therefore, a 1-bit to 8-bit module is needed; the 8-bit temperature data needs to be calculated and processed, so a data processing module is needed; Furthermore, the host computer only displays data in ASCII format. In order to display the temperature value on the host computer, the 8-bit temperature value needs to be converted into ASCII code, so an 8-bit hexadecimal data conversion module is required; Furthermore, the result after data processing is hexadecimal, while the digital tube displays BCD code. In order to display the correct data on the digital tube, a hexadecimal to BCD code module is required.

[0026] After adjusting and improving the corresponding modules, the hardware system block diagram is as follows Figure 5 shown.

[0027] S7, after adjusting and improving the module, the hardware system is designed for rate matching, which is used in temperature detection engineering; (1) First consider whether a handshake signal is required on the interface that communicates with peripheral devices; (2) The communication with the temperature sensor DS18B20 is done by parsing the operation instructions for DS18B20 through the register parsing module and sending them to the 8-bit to 1-bit module. Therefore, it is necessary to consider whether DS18B20 can respond to the operation instructions at all times. (3) The rate of the serial port interface module is lower than the rate at which the FPGA writes the temperature sensor DS18B20. According to the manual, it takes 63us to write 1 bit of data and 504us to write 8 bits, which is less than the 833us time it takes for the serial port to send an 8-bit instruction to the FPGA. Therefore, there is no need to consider the cache FIFO problem on the serial port receiving data path. In the single-bus 1-bit interface module, since the writing timing rate of DS18B20 is much lower than the internal read and write frequency of the FPGA, it is necessary to inform the 8-bit to 1-bit module to wait for each 1-bit data to be written, and to send new 1-bit data after the timing meets the timing requirements for sending 1 bit. Therefore, a handshake signal needs to be set between the single-bit interface conversion module and the 8-bit to 1-bit module.

[0028] (4) Consider the serial port sending end. Since the serial port sending module needs time to convert the parallel to the serial code, the serial port sending module needs to tell the upstream hexadecimal to ASCII code module to wait. Therefore, a handshake signal needs to be set between the serial port sending module and the hexadecimal to ASCII code module. Since the serial port sending module needs to wait for the serial to parallel conversion, the hexadecimal to ASCII code module also needs to cache the data sent by the control module. Therefore, the hexadecimal to ASCII code module needs to introduce a FIFO (First Input First Output) data processing and organization method.

[0029] In the embodiment 2, in step S6, in the 8-bit to 1-bit module timing conversion, the conversion method includes: 1. Assume that any temperature single bus line of the input 8-bit to 1-bit module The length of the data packet is , then the The segmenter is divided into index bits Information Bit The two parts are: (1) Let index number be The width of the sub-buffer is , then the total width of the buffer satisfies: (2) In the formula, is the total width of the buffer; Define entry into each sub-buffer The number of vectors , let the length be of The statistical probability of occurrence is , input 8bit to 1bit module The expected length is ,but satisfy: (3) In the formula, is the statistical probability, , is the initial length of the message, The length is of The specific number of data bits entering the buffer, is the total width of the buffer, The total length of the buffer.

[0030] Ways to increase the transmission rate: Communication register analysis module buffer storage and transmitted super packets , are just input 8bit to 1bit module In block information; The data is implicit in the super data packet In the inherent order, to increase the transmission rate of communication; then the transmission rate It is expressed as: (4) In the formula, is the expected length.

[0031] 2. The 8-bit data sent by the register parsing module is converted into 1-bit through the 8-bit to 1-bit module. To ensure communication at all times, the conversion method includes: The register parsing module periodically sends the length information of each sub-byte data block after dynamic adjustment of the buffer area to the single bus 1bit interface module so that the single bus 1bit interface module can complete the implicit information The recovery of the data transmission overhead is called feedback data overhead, which is recorded as ; Each transmission is used for the single bus 1bit interface module to complete the implicit information The recovered feedback data is valid at least until the next sub-buffer dynamic adjustment. The resulting decreased communication efficiency is expressed as: (5) In the formula, Feedback data overhead bits for each column sub-buffer, is the communication time, is the effective height of the buffer area, is the total width of the buffer; The feedback data is transmitted in differential form. The maximum value of the difference between the binary values ​​of the sub-buffers in the same column after the current dynamic adjustment and the previous adjustment is used as the number of bits of overhead for each sub-buffer in the current adjustment. After multiple adjustments, Then it decreases and finally stabilizes.

[0032] 3. The 8-bit data sent by the register parsing module is converted to 1-bit by the 8-bit to 1-bit module. To avoid communication delay, the communication delay generally includes the delay of processing the original data ( Divide into time, The time for entering the corresponding position of the memory for storage), queuing delay (also known as waiting delay, the time for the sub-byte data block in the buffer to wait for it to be sent out from the buffer), sending delay (the time from the formation of the super data packet to be sent to the time of sending) and transmission delay (the time for the super data packet to be transmitted on the channel). Due to the delay in processing the original data, the time spent on the sending delay and the transmission delay can be basically determined, and these processing times can be carried out simultaneously with the data transmission. Therefore, the waiting delay is mainly considered this time, and other delays are not considered in the present invention. The conversion method further includes: Assume that the transmission rate of the super data packet on the channel is , the transmission time of each data packet in the channel is , then: (6) In the formula, It is a super data packet; Get the maximum delay of the buffer byte data block waiting for: (7) In the formula, is the transmission time of each data packet in the channel, The maximum buffer height after the cache area is dynamically adjusted; Because the buffer stores a large amount of data bit information, and each data has a delay in transmission on the channel, the data bit information has a waiting time in the buffer. The delay of information from the register analysis module to the single bus 1bit interface module will affect the communication quality. Therefore, in order to ensure the communication quality, the communication delay must be controlled within a certain range. Considering the communication efficiency and transmission rate, the communication delay is required to be kept within a certain range. Within, there are: (8) In the formula, The primary delay for waiting for a byte data block in the buffer; Since the cache stores a large amount of temperature data, in order to make full use of the cache resources and improve the information transmission rate, the cache needs to be dynamically adjusted to balance the cache temperature. This puts forward requirements on the storage capacity in the memory. The required storage capacity is called storage overhead, which is recorded as ; Storage overhead The value of is related to the memory capacity and communication delay, and is: (9) The temperature sensor data representing different source nodes and destination nodes are transmitted through the same routing node path at the physical layer. The packet header will carry synchronization and other related information so that the data information can be processed synchronously at the same routing node to increase the transmission rate; when the data enters the cache area for storage, only In part of which The packet header information (including synchronization information bits) will be removed; and the super data packet is encapsulated by adding a packet synchronization signal, a start flag, a check unit, and an end flag to the reassembled byte data block after buffer equalization.

[0033] Although the flag bits added during the encapsulation process of the data packet increase the overhead of the reassembled data in the channel, this overhead is much less than the large amount of synchronization information, packet header information, and As for the bit overhead of the related information, the impact on the communication efficiency is negligible, so this overhead is not considered in the present invention.

[0034] The effective buffer height after dynamic adjustment of the buffer area Whether it is appropriate or not greatly affects the overall communication efficiency of both parties. Comprehensively consider the main factors affecting communication efficiency, quantitatively analyze the communication overhead and communication delay, and plan a solution with the minimum communication overhead, the best communication delay, and the best communication efficiency. , Maximum delay and storage overhead The relationship between , defines the utility function of communication efficiency , the optimization objective function is expressed as: (10) In the formula, For communication efficiency; The effective buffer height after dynamic adjustment of the buffer area Whether it affects the overall communication efficiency of both parties.

[0035] According to equation (4), to make the communication efficiency Maximize, As small as possible. From a practical communication perspective, The size depends on the input 8bit to 1bit module The specific situation. And 8bit to 1bit module input The diversity of types and the uncertainty of occurrence probability are determined by the objective data entering the 8-bit to 1-bit module, and can only passively adapt to their characteristics. Therefore, it is impossible to use it in a single bus 1-bit interface module. Minimize further. But you can choose a smaller The situation where short data packets change dynamically is suitable for using the solution recommended by the present invention. For example, the temperature data transmitted by the temperature sensor network is often a data packet with a very short length.

[0036] According to equation (10), to maximize the utility function value, the utility function system must have Minimize. From equation (5), we can see that to achieve Minimization requires the effective buffer height of the cache area , that is, the minimum height of each sub-buffer area must be maximized.

[0037] The present invention solves the problem of uneven distribution of load data of different lengths in sub-buffers. It is proposed to use a segmenter to divide each WL into a CW block and an IW block; divide the memory into multiple buffers and number them; and the IW selector searches the corresponding sub-buffer according to the value of IW, and stores the CW load byte data block corresponding to its IW information in the selected sub-buffer. The information finally transmitted is only the data related to the CW block, and this process effectively improves the transmission rate. The temperature balance method dynamically adjusts the sub-buffer to cache as many CWs as possible to obtain a higher transmission rate gain.

[0038] The present invention utilizes the special position and width characteristics of the sub-buffer area to realize the transmission In The storage and transmission of information can alleviate the problem of limited communication resources in actual communication; the storage width of the sub-buffer area is adjusted by using the subdividable characteristics of byte data blocks to achieve the problem of balancing the load data of different lengths in the buffer area. Therefore, the proposed data communication scheme can reduce the waste of communication resources and greatly improve communication efficiency.

[0039] It can be understood that 1bit to 8bit can be converted using the above reverse engineering.

[0040] Embodiment 3, the embodiment of the present invention provides a temperature detection system module division system, including: Functional requirement definition unit, used to define the functional requirement information in the interaction between the host computer and FPGA; The peripheral device hardware system construction unit is used to construct the block diagram of the hardware system with added peripheral devices, and determine the peripheral device information required in addition to the FPGA according to the functional requirements; the peripheral devices include computers, digital tubes, temperature sensors, and buzzers; An interface conversion module hardware unit, used to obtain a designed hardware system after adding the interface conversion module; The register parsing module hardware unit is used to design the instruction system according to the designed hardware system after adding the interface conversion module; and obtain the hardware system after adding the register parsing module; A register configuration unit, used for configuring peripheral device registers based on a hardware system to which a register parsing module is added; The corresponding module adjustment and improvement unit is used to adjust and improve the design of the module according to the hardware system configured by the peripheral device register; and obtain the hardware system after the corresponding module adjustment and improvement; The rate matching unit is used to adjust and improve the corresponding modules and then design the rate matching of the hardware system for temperature detection engineering.

[0041] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for dividing modules of a temperature detection system, characterized in that: The method converts the interface timing of the peripheral device into the universal interface timing, or converts the universal interface timing into the peripheral device interface timing through the design of interface transmission, instruction parsing, peripheral control, and interface conversion modules, so that the internal module of the FPGA no longer pays attention to the timing of the peripheral interface, and completes the division of multiple modules in temperature detection; specifically, the following steps are included: S1, defines the functional requirements information in the interaction between the host computer and FPGA; S2, build a block diagram of the hardware system structure of adding peripheral devices, and determine the peripheral device information required in addition to FPGA according to the functional requirements; the peripheral devices include computers, digital tubes, temperature sensors, and buzzers; S3, designing an interface conversion module based on adding a peripheral device hardware system, and obtaining a hardware system designed after adding the interface conversion module; S4, designing an instruction system according to the hardware system designed after adding the interface conversion module; obtaining the hardware system added with the register parsing module; S5, based on the hardware system with the register parsing module added, configure the peripheral device registers; S6, adjusting and improving the design of the module according to the hardware system configured by the peripheral device register, and obtaining the hardware system after the module adjustment and improvement; S7, after adjusting and improving the module, the hardware system is designed for rate matching and used in temperature detection engineering.

2. The method for dividing the temperature detection system modules according to claim 1, characterized in that: In step S1, the functional requirement information in the interaction between the host computer and the FPGA is defined, including: the host computer sends instructions to the FPGA, wherein the instructions include: switching digital tube display data, buzzer switch control, resetting the temperature sensor, turning on temperature conversion, reading the converted temperature value, setting the upper and lower limits of the alarm temperature; reading and writing the temperature sensor, digital tube display and switch control, calculating the temperature value and sending the calculated temperature value to the host computer; setting the upper and lower limits of the temperature.

3. The method for dividing the temperature detection system modules according to claim 1, characterized in that: In step S3, the interface conversion module includes: Serial port interface module in the communication between the host computer and FPGA; Digital tube interface module, used to complete the output of digital tube position selection and segment selection; The single bus 1bit interface module is used to convert the temperature sensor single bus protocol into 1bit and perform 1bit data transmission; Buzzer interface module, used to enable the buzzer switch; The host computer sends instructions to the FPGA to configure the temperature sensor, configure the upper and lower limits of the temperature alarm, and send instructions to control the digital tube display to turn off and the buzzer to turn on and off. A register parsing module is added to the FPGA; the register parsing module parses the configuration register value and then configures the temperature sensor.

4. The method for dividing the temperature detection system modules according to claim 1, characterized in that: In step S6, the module is adjusted and the design is improved, including: The ASCII code sent by the host computer is converted into the corresponding hexadecimal through the ASCII code to 8-bit hexadecimal module FPGA; The packet header detection module detects the packet header of the received packet converted into the corresponding hexadecimal format, and retains the packet that meets the correct packet header conditions, otherwise the packet is discarded, thus completing the filtering of the received valid packet; After the package is tested, the instructions are parsed by the register parsing module and sent to the temperature sensor, digital tube display switch control module, digital tube interface module and buzzer interface module respectively according to the instruction function requirements; The 8-bit data sent by the register parsing module is converted to 1-bit by the 8-bit to 1-bit module and then sent to the single bus conversion interface module, and then to the temperature sensor; The real-time temperature comparison module determines whether the real-time temperature is greater than the upper limit or less than the lower limit, and issues a temperature alarm. The 1-bit data transmitted by the temperature sensor to the FPGA through the single bus conversion interface module is converted into 8-bit data through the data processing module; The 8-bit temperature value converted by the data processing module is converted into ASCII code through the 8-bit hexadecimal data conversion module, and the ASCII code format data is sent to the host computer through the serial port sending module; The hexadecimal code after data processing is converted into BCD code by the hexadecimal to BCD code module and sent to the digital tube interface module.

5. The method for dividing the temperature detection system modules according to claim 4, characterized in that: The 8-bit data sent from the register parsing module is converted to 1-bit through the 8-bit to 1-bit module. To ensure the transmission rate, the conversion method includes: Assume that any temperature single bus line of the input 8-bit to 1-bit module The length of the data packet is , then the The segmenter is divided into index bits Information Bit The two parts are: （1） Let index number be The width of the sub-buffer is , then the total width of the buffer satisfies: （2） In the formula, is the total width of the buffer; Define entry into each sub-buffer The number of vectors , let the length be of The statistical probability of occurrence is , input 8bit to 1bit module The expected length is ,but satisfy: （3） In the formula, is the statistical probability, , is the initial length of the message, The length is of The specific number of data bits entering the buffer, is the total width of the buffer, The total length of the buffer.

6. The method for dividing the temperature detection system modules according to claim 5, characterized in that: Ways to increase the transmission rate: Communication register analysis module buffer storage and transmitted super packets , are just input 8bit to 1bit module In block information; The data is implicit in the super data packet In the inherent order, to increase the transmission rate of communication; then the transmission rate It is expressed as: （4） In the formula, is the expected length.

7. The method for dividing the temperature detection system modules according to claim 4, characterized in that: The 8-bit data sent from the register parsing module is converted into 1-bit through the 8-bit to 1-bit module. To ensure communication at all times, the conversion method includes: The register parsing module periodically sends the length information of each sub-byte data block after dynamic adjustment of the buffer area to the single bus 1bit interface module so that the single bus 1bit interface module can complete the implicit information The recovery of the data transmission overhead is called feedback data overhead, which is recorded as ; Each transmission is used for the single bus 1bit interface module to complete the implicit information The recovered feedback data is valid at least until the next sub-buffer dynamic adjustment. The resulting decreased communication efficiency is expressed as: （5） In the formula, Feedback data overhead bits for each column sub-buffer, is the communication time, is the effective height of the buffer area, is the total width of the buffer; The feedback data is transmitted in differential form. The maximum value of the difference between the binary values ​​of the sub-buffers in the same column after the current dynamic adjustment and the previous adjustment is used as the number of bits of overhead for each sub-buffer in the current adjustment. After multiple adjustments, Then it decreases and eventually stabilizes.

8. The method for dividing the temperature detection system modules according to claim 4, characterized in that: The 8-bit data sent from the register parsing module is converted into 1-bit by the 8-bit to 1-bit conversion module. To avoid communication delay, the conversion method further includes: Assume that the transmission rate of the super data packet on the channel is , the transmission time of each data packet in the channel is , then: （6） In the formula, It is a super data packet; Get the maximum delay of the buffer byte data block waiting for: （7） In the formula, is the transmission time of each data packet in the channel, The maximum buffer height after the cache area is dynamically adjusted; Considering the communication efficiency and transmission rate comprehensively, the communication delay is kept at Within, there are: （8） In the formula, The primary delay for waiting for a byte data block in the buffer; In order to make full use of the cache resources and improve the information transmission rate, the storage capacity in the memory is the storage overhead, which is recorded as ; Storage overhead The value of is related to the memory capacity and communication delay, and is: （9） Quantitatively analyze the communication overhead and communication delay, and plan a solution with the minimum communication overhead, the best communication delay, and the best communication efficiency; according to the transmission rate , Maximum delay and storage overhead The relationship between , defines the utility function of communication efficiency , the optimization objective function is expressed as: （10） In the formula, For communication efficiency; The effective buffer height after dynamic adjustment of the buffer area Whether it affects the overall communication efficiency of both parties.

9. The method for dividing the temperature detection system modules according to claim 1, characterized in that: In step S7, the rate matching design is performed on the hardware system after the module adjustment and improvement, including: (1) Determine whether handshake signals are required on the interface for communicating with peripheral devices; (2) Determine whether the temperature sensor can always respond to operation instructions; (3) Set a handshake signal between the single bus bit interface conversion module and the 8-bit to 1-bit module; (4) Set a handshake signal between the serial port sending module and the hexadecimal to ASCII code module; introduce FIFO first-in first-out data processing and organization method into the hexadecimal to ASCII code module.

10. A temperature detection system module division system, characterized in that: The system implements the temperature detection system module division method according to any one of claims 1 to 9, and the system comprises: Functional requirement definition unit, used to define the functional requirement information in the interaction between the host computer and FPGA; The peripheral device hardware system construction unit is used to construct a block diagram of the hardware system with added peripheral devices, and determine the peripheral device information required in addition to the FPGA according to the functional requirements; the peripheral devices include computers, digital tubes, temperature sensors, and buzzers; The interface conversion module hardware unit designs the interface conversion module based on adding the peripheral device hardware system, and obtains the hardware system designed after adding the interface conversion module; The register parsing module hardware unit is used to design the instruction system according to the designed hardware system after adding the interface conversion module; and obtain the hardware system after adding the register parsing module; A register configuration unit, used for configuring peripheral device registers based on a hardware system to which a register parsing module is added; The corresponding module adjustment and improvement unit is used to adjust and improve the design of the module according to the hardware system configured by the peripheral device register, and obtain the hardware system after the module adjustment and improvement; The rate matching unit is used to design the rate matching of the hardware system after module adjustment and improvement, and is used in temperature detection projects.

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