Logic online upgrading method and system based on UATR-to-JTAG logic core

Abstract

The invention provides a logic online upgrading method and system based on a UATR-to-JTAG logic core, and relates to the technical field of embedded computer application, and the method comprises the steps that a processor obtains data needing to be upgraded through an external network; transmitting the acquired data needing to be upgraded to a UART to JTAG core through a serial port; the UART to JTAG core realizes protocol conversion from UART data to JTAG, and simulates a JTAG protocol to realize logic online upgrade. According to the method, the upgrading mode of the FPGA in the product is optimized, and the labor cost and the time cost of product maintenance are reduced.

Description

Technical Field

[0001] The invention relates to the technical field of embedded computer application, and in particular provides a logic online upgrade method and system based on UATR to JTAG logic core. Background Art

[0002] UART (Universal Asynchronous Receiver / Transmitter) is a serial communication protocol used to transmit data between external or internal resources of a computer. UART uses two signals for communication: one for data transmission (TX: send) and the other for receiving data (RX: receive).

[0003] JTAG (Joint Test Action Group) is an international standard test protocol, mainly used for internal chip testing and system simulation and debugging. The JTAG interface usually includes several key signal lines, test clock input (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO).

[0004] Programmable logic is an indispensable and important software in embedded computer products. Its main function is to provide specific logic functions for embedded computer products. For the circuit design of computer products, it can reduce the development cycle, provide high flexibility and reusability, high performance, economic benefits, etc., and provide strong support and solutions for various application scenarios.

[0005] However, the solidification of programmable logic relies on a more complex development environment and expensive debugging equipment. Taking the JYXSIP25-256 programmable logic chip as an example, it supports standard debugging interfaces (such as Figure 3 ). The debugging environment is attached. Figure 2 , which includes an industrial computer with Xilinx software environment and a Xilinx emulator. In the debugging of JYXSIP25-256, the user uses the debugging host to connect to the product programmable logic chip through the emulator. Only after the programmable logic chip is connected can the programmable logic program be solidified.

[0006] Such a process faces two main problems. First, it relies on Xilinx simulators and proprietary debugging environments. Second, a large amount of human resources is required if the programmable logic of delivered batch products needs to be updated and maintained. Summary of the invention

[0007] The purpose of this application is to provide a logic online upgrade method based on UATR to JTAG logic core to address the problems existing in the prior art.

[0008] In order to achieve the above object, the present invention adopts the following technical solution: a logic online upgrade method based on UATR to JTAG logic core, the method comprising:

[0009] The processor obtains the data that needs to be updated through the external network;

[0010] The acquired data to be upgraded is transferred to the UART to JTAG core through the serial port;

[0011] The UART to JTAG core realizes the conversion of UART data to JTAG protocol and simulates the JTAG protocol to realize the online upgrade of logic.

[0012] The logic online upgrade method based on the UART to JTAG logic core provided by the present invention also has such a technical feature that the UART to JTAG core implements the protocol conversion from UART data to JTAG, including:

[0013] Step 1: The core UART receives the communication serial port handshake request and forwards the information to the core ACK;

[0014] Step 2: The core ACK compares the handshake information. If they are consistent, it sends a confirmation reply to the core UART and enables the core FIFO. If they are inconsistent, it is ignored.

[0015] Step 3: The core UART sends the confirmation reply information to the communication serial port;

[0016] Step 4: The communication serial port receives the confirmation reply information and starts sending the upgrade information to the core UART;

[0017] Step 5: The core UART receives the upgrade information and sends the upgrade information to the core FIFO for buffering;

[0018] Step 6: Perform a cache upgrade every 32 Bytes of data, and send the upgrade information from the core FIFO to the core JTAG for upgrade;

[0019] Step 7: The upgrade information is sent from the core FIFO to the core JTAG, the buffer area is cleared, and steps 5 to 7 are repeated until the data transfer is completed.

[0020] Another object of the present invention is to provide a logic online upgrade system based on a UATR to JTAG logic core, the system being used to implement the method described in any one of claims 1 to 2, comprising: a processor communicating with an external network, an FPGA configured with a UATR to JTAG logic core, and a communication module for implementing communication between the processor and the FPGA.

[0021] The logic online upgrade system provided by the present invention also has such technical characteristics that the UATR to JTAG logic core includes a serial communication function sub-core UART, a serial handshake protocol sub-core ACK, a cache function sub-core FIFO and an interface protocol sub-core JTAG.

[0022] The logic online upgrade system provided by the present invention also has such a technical feature that the interface protocol sub-core JTAG is used to realize the switching of multiple states, thereby realizing the simulation of JTAG protocol data including:

[0023] The platform sends the logic object code binary file that needs to be updated to the processor through the external network;

[0024] After the processor receives the logic object code file, it sends it to the FPGA chip through the serial port that communicates with the logic;

[0025] The UATR-to-JTAG logic core running in the FPGA chip, after receiving the target code, transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface, thus completing the update of the logic target code.

[0026] The logic online upgrade system provided by the present invention also has such a technical feature that the processor provides an external communication network and a communication serial port for the FPGA chip. During communication, the serial port driver baud rate is set to 115200, 1KB of data is sent, and a response from the logic U2J core is waited. If there is no response within 60ms, it is judged as a timeout.

[0027] The logic online upgrade system provided by the present invention also has such a technical feature that the FPGA connects its own JTAG interface to its own 3.3V IO BANK, and when not in the online upgrade state, the JTAG pin is set to a high impedance state.

[0028] Beneficial Effects

[0029] The logic online upgrade method based on UATR to JTAG logic core provided by the present invention optimizes the upgrade mode of FPGA in the product and reduces the manpower cost and time cost of product maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 A schematic diagram of a topological architecture provided by an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram for burning the logic target code during initial debugging;

[0033] Figure 3 This is a schematic diagram of the U2J logic core topology. DETAILED DESCRIPTION

[0034] The present application is further described in detail below in conjunction with the accompanying drawings and examples, but it should be noted that these implementation methods are not limitations of the present application, and equivalent changes or substitutions in functions, methods, or structures made by ordinary technicians in the field based on these implementation methods are all within the scope of protection of the present application.

[0035] In the description of the embodiments of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the creation of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the creation of the present application.

[0036] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the invention of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0037] The terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention of this application can be understood by specific circumstances.

[0038] like Figure 1-3 As shown, the embodiment of the present application provides a method for online upgrading of logic based on UATR to JTAG logic core, the method comprising:

[0039] The processor obtains the data that needs to be updated through the external network;

[0040] The acquired data to be upgraded is transferred to the UART to JTAG core through the serial port;

[0041] The UART to JTAG core realizes the conversion of UART data to JTAG protocol and simulates the JTAG protocol to realize the online upgrade of logic.

[0042] In some embodiments, the UART to JTAG core implements the protocol conversion from UART data to JTAG, including:

[0043] Step 1: The core UART receives the communication serial port handshake request and forwards the information to the core ACK;

[0044] Step 2: The core ACK compares the handshake information. If they are consistent, it sends a confirmation reply to the core UART and enables the core FIFO. If they are inconsistent, it is ignored.

[0045] Step 3: The core UART sends the confirmation reply information to the communication serial port;

[0046] Step 4: The communication serial port receives the confirmation reply information and starts sending the upgrade information to the core UART;

[0047] Step 5: The core UART receives the upgrade information and sends the upgrade information to the core FIFO for buffering;

[0048] Step 6: Perform a cache upgrade every 32 Bytes of data, and send the upgrade information from the core FIFO to the core JTAG for upgrade;

[0049] Step 7: The upgrade information is sent from the core FIFO to the core JTAG, the buffer area is cleared, and steps 5 to 7 are repeated until the data transfer is completed.

[0050] In some embodiments, a logic online upgrade system based on a UATR-to-JTAG logic core is provided, and the system is used to implement the method described in any one of claims 1-2, including: a processor communicating with an external network, an FPGA configured with a UATR-to-JTAG logic core, and a communication module for implementing communication between the processor and the FPGA.

[0051] In some embodiments, the UATR to JTAG logic core includes a serial port communication function sub-core UART, a serial port handshake protocol sub-core ACK, a cache function sub-core FIFO and an interface protocol sub-core JTAG.

[0052] In some embodiments, the interface protocol sub-core JTAG is used to implement switching of multiple states, thereby simulating JTAG protocol data including:

[0053] The platform sends the logic object code binary file that needs to be updated to the processor through the external network;

[0054] After the processor receives the logic object code file, it sends it to the FPGA chip through the serial port that communicates with the logic;

[0055] The UATR-to-JTAG logic core running in the FPGA chip, after receiving the target code, transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface, thus completing the update of the logic target code.

[0056] In some embodiments, the processor provides an external communication network and a communication serial port for the FPGA chip. During communication, the serial port driver baud rate is set to 115200, 1KB of data is sent, and the logic U2J core waits for a response. If there is no response within 60ms, it is judged as a timeout.

[0057] In some embodiments, the FPGA connects its own JTAG interface to its own 3.3V IO BANK, and when not in the online upgrade state, the JTAG pin is set to a high impedance state.

[0058] In some embodiments, one FT-2000 / 4 processor, one JYXSIP25-256 programmable control logic chip and Ethernet are used as the hardware design architecture of the external network.

[0059] For the first debugging, the debugger needs to use the debugging environment of the programmable logic on the PC to connect to the emulator, and establish a link communication between the debugging environment and the FPGA chip through the emulator, so as to realize the burning of the control logic target code.

[0060] After the product is delivered, the logical target code can be updated by the initial debugging method or by online upgrading. The method provided in the above embodiment can provide a fast and stable online upgrading mechanism. The specific steps are as follows:

[0061] Step 1: The external platform sends the logic target code to be updated to the FT2000 / 4 processor via Ethernet;

[0062] Step 2: After receiving the data, the FT2000 / 4 processor sends the data to JYXSIP25-256 through the communication serial port with JYXSIP25-256.

[0063] Step 3: After receiving the target code, the UATR-to-JTAG logic core running in the JYXSIP25-256 chip transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface, thus completing the update of the logic target code.

[0064] The above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application. The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and variations can be made without departing from the technical principles of the present application, and these improvements and variations should also be regarded as the protection scope of the present application.

Claims

1. A method for online upgrading of logic based on UATR to JTAG logic core, characterized in that: The method comprises: The processor obtains the data that needs to be updated through the external network; The acquired data to be upgraded is transferred to the UART to JTAG core through the serial port; The UART to JTAG core realizes the conversion of UART data to JTAG protocol and simulates the JTAG protocol to realize the online upgrade of logic.

2. The method for online upgrading of logic based on UATR to JTAG logic core according to claim 1, characterized in that: The UART to JTAG core implements the protocol conversion from UART data to JTAG including: Step 1: The core UART receives the communication serial port handshake request and forwards the information to the core ACK; Step 2: The core ACK compares the handshake information. If they are consistent, it sends a confirmation reply to the core UART and enables the core FIFO. If they are inconsistent, it is ignored. Step 3: The core UART sends the confirmation reply information to the communication serial port; Step 4: The communication serial port receives the confirmation reply information and starts sending the upgrade information to the core UART; Step 5: The core UART receives the upgrade information and sends the upgrade information to the core FIFO for buffering; Step 6: Perform a cache upgrade every 32 Bytes of data, and send the upgrade information from the core FIFO to the core JTAG for upgrade; Step 7: The upgrade information is sent from the core FIFO to the core JTAG, the buffer area is cleared, and steps 5 to 7 are repeated until the data transfer is completed.

3. A logic online upgrade system based on UATR to JTAG logic core, characterized in that: The system is used to implement the method according to any one of claims 1-2, comprising: a processor communicating with an external network, an FPGA configured with a UATR to JTAG logic core, and a communication module for implementing communication between the processor and the FPGA.

4. The logic online upgrade system according to claim 3, characterized in that: The UATR-to-JTAG logic core comprises a serial port communication function sub-core UART, a serial port handshake protocol sub-core ACK, a cache function sub-core FIFO and an interface protocol sub-core JTAG.

5. The logic online upgrade system according to claim 3, characterized in that: The interface protocol sub-core JTAG is used to implement the switching of multiple states, thereby simulating JTAG protocol data including: The platform sends the logic object code binary file that needs to be updated to the processor through the external network; After the processor receives the logic object code file, it sends it to the FPGA chip through the serial port that communicates with the logic; The UATR-to-JTAG logic core running in the FPGA chip, after receiving the target code, transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface, thus completing the update of the logic target code.

6. The logic online upgrade system according to claim 3, characterized in that: The processor provides an external communication network and a communication serial port for the FPGA chip. During communication, the serial port driver baud rate is set to 115200, 1KB of data is sent, and the logic U2J core is waiting for a response. If there is no response within 60ms, it is judged as a timeout.

7. The logic online upgrade system according to claim 3, characterized in that: The FPGA connects its JTAG interface to its own 3.3V IO BANK. When not in online upgrade state, the JTAG pin is set to high impedance state.

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