Method and device for optimizing memory stack conflict during local register access

Abstract

The invention relates to the technical field of chips, and provides a method and a device for optimizing memory stack conflicts during access to a local register. The method comprises the steps that M arithmetic logic groups are set, the maximum number of threads capable of being accessed by a register in parallel is N, the number of concurrent threads of each arithmetic logic group is increased to N from N / M, and the number of pipelines connected with each arithmetic logic group and an instruction module is increased to N; therefore, the total number of the threads concurrently accessing the registers in each clock period is increased to K, K = M * N, the number of the concurrent threads in each clock period is increased to K from original N, and the requirement that the number of the concurrent threads and the registers form a many-to-few mapping relation is met; the instruction module receives the access requests of the K threads and plans the issuing time of the access requests of the K threads, so that the number of the access requests issued in each clock period reaches the maximum issuing number. According to the method and the device, the access requests of the threads are issued in a smaller number of clock cycles as much as possible, and the instruction performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method and device for optimizing storage body conflicts when accessing a local register. Background Art

[0002] When accessing local registers, such as when the mov instruction accesses the local registers of the graphics processing unit (GPU), since the local registers are divided into multiple banks, these banks can be accessed simultaneously, but the number of accesses is affected by the number of banks, so the throughput is also related to the number of banks. When multiple threads access multiple banks, there is often a bank conflict. A bank conflict means that when at least two threads access the same bank, there will be an access conflict, so it is usually divided into multiple accesses, thereby increasing the access time.

[0003] In the prior art, the architecture for executing corresponding instructions usually includes an alu group, an instruction module and a corresponding local register. N pipelines are connected between the instruction module and the local register, where n is the number of storage bodies. Correspondingly, n / m pipelines are connected between each alu group and the instruction module, where m is the number of alu groups, thereby forming an m-group n to n mapping. In this implementation, multiple threads need to be divided into multiple groups, each group contains n threads, and the access requests of these n threads are issued in parallel by m alu groups. Only after the access requests of one group of threads are processed can the access requests of the next group of threads be processed. This results in that whenever there is a storage body conflict between multiple access requests of a group of threads, the number of clock cycles required to issue all access requests will increase linearly with the number of access requests with storage body conflicts, ultimately resulting in too long a time required to complete a single instruction, affecting the performance of the instruction.

[0004] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in the field of this technology. Summary of the invention

[0005] The technical problem to be solved by the present invention is that in the prior art, whenever there is a storage conflict between multiple access requests in a group of threads, the number of clock cycles required to issue all access requests will increase linearly with the number of access requests with storage conflicts, ultimately resulting in too long a time required to complete a single instruction, affecting the performance of the instruction.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a method for optimizing storage conflicts when accessing a local register, wherein M operation logic groups are set, the number of threads contained in each operation logic group is expanded to N, and the number of pipelines connected between each operation logic group and an instruction module is expanded to N, so that the M operation logic groups can issue access requests of K threads in parallel; wherein K is the maximum number of threads that can concurrently access the local register, and N=K / M; the method comprises:

[0008] M operation logic groups send K threads' access requests to the instruction module in parallel;

[0009] The instruction module receives the access requests of the K threads, and performs storage bank conflict detection on the access requests of the K threads together;

[0010] According to the result of the memory bank conflict detection, the issuing time of the access requests of the K threads is planned so that the number of the access requests issued in each clock cycle reaches the maximum number that can be issued.

[0011] Preferably, the planning of the issuing time of the access requests of the K threads according to the result of the memory bank conflict detection specifically includes:

[0012] When there is no storage bank conflict between the access request of the first thread and the access requests of each current cycle thread, the first thread is used as the current cycle thread, until the number of current cycle threads reaches the maximum number that can be issued, and the access requests of all current cycle threads are issued in the current clock cycle;

[0013] Otherwise, the access request of the first thread is reserved and sent in a subsequent clock cycle.

[0014] Preferably, the planning of the issuing time of the access requests of the K threads according to the result of the memory bank conflict detection further includes:

[0015] The clock cycle for issuing the access request of each thread is determined in sequence according to the priority of the threads from high to low.

[0016] Preferably, each operation logic group processes N threads, wherein the threads processed by the i-th operation logic group include: m×N+(i-1)×N / M+1 to m×N+i×N / M threads, m∈{0, 1, ..., M}.

[0017] Preferably, N is the number of storage bodies, that is, the number of threads contained in each operation logic group is expanded to be consistent with the number of storage bodies, and the number of pipelines connected between each operation logic group and the instruction module is expanded to be consistent with the number of storage bodies, M=K / N.

[0018] Preferably, the M operation logic groups send the access requests of K threads in parallel, specifically including:

[0019] M operation logic groups issue access requests in parallel; wherein each operation logic group issues access requests of N threads.

[0020] Preferably, when there are 128 threads that need to access local registers and the number of storage bodies is 32, 4 operation logic groups are set, the number of threads contained in each operation logic group is expanded to 32, and the number of pipelines connected between each operation logic group and the instruction module is expanded to 32;

[0021] Four operation logic groups issue access requests of 128 threads in parallel;

[0022] The instruction module receives the access requests of the 128 threads, and performs storage bank conflict detection on the access requests of the 128 threads together;

[0023] According to the result of the memory bank conflict detection, the issuing time of the access requests of the 128 threads is planned so that the number of the access requests issued in each clock cycle reaches the maximum number that can be issued.

[0024] Preferably, the access request is generated according to an instruction, and the instruction includes one or more of a MOV instruction, a DMA instruction or an AP instruction.

[0025] Preferably, the maximum number that can be sent is the number of storage bodies, or the maximum number of access requests without conflicts between storage bodies.

[0026] In a second aspect, the present invention provides a device for optimizing storage bank conflicts when accessing a local register, comprising M operation logic groups and an instruction module;

[0027] The number of pipelines connected between each operation logic group and the instruction module is N; wherein N = K / M, K is the number of threads that need to access the local register;

[0028] M operation logic groups are used to send access requests of K threads to the instruction module in parallel;

[0029] The instruction module is used to receive the access requests of the K threads, and perform storage body conflict detection on the access requests of the K threads together; and according to the results of the storage body conflict detection, plan the issuance time of the access requests of the K threads so that the number of access requests issued in each clock cycle reaches the maximum number that can be issued; so as to use the access requests to realize access to the storage body in the local register.

[0030] The present invention sends the access requests of K threads to the instruction module together, so that the instruction module can perform common storage conflict detection and clock cycle scheduling for the K threads, thereby avoiding the thread waiting caused by the grouped sending of the thread access requests, which leads to the increase of instruction execution time. And by maximizing the number of sent access requests in each clock cycle, the thread access requests are sent in as few clock cycles as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a schematic diagram of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0034] Figure 3 is a schematic diagram of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0036] Figure 5 It is a flow chart of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0037] Figure 6 is a schematic diagram of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0038] Figure 7 It is a flow chart of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0039] Figure 8 is a schematic diagram of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0040] Fig. 9 is a schematic diagram of a method for optimizing storage bank conflicts when accessing a local register provided by an embodiment of the present invention;

[0041] Fig.10 It is a schematic diagram of the architecture of a device for optimizing memory bank conflicts when accessing a local register provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner, that is, although they may be carried in the embodiments or examples of the above terms due to reasons such as the order and position of appearance, it is not limited to that they can be carried in combination by one embodiment or example.

[0044] In the description of the present invention, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "multiple" is two or more. In addition, for example, the same type of nouns may be described as two independent individuals by adding "A" and "B" at the end. In this case, the corresponding features defined as "A" and "B" are only used to distinguish the same type of individuals for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0045] When describing some embodiments, the expressions "coupling", "coupling" and "connection" and their derivatives may be used. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupling" may be used to indicate that two or more components are in direct physical or electrical contact. However, the terms "connection" or "coupling" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other, such as "optical path coupling", "wireless connection", etc. The embodiments disclosed herein are not necessarily limited to the contents of the present invention.

[0046] In the description of the present invention, the expression "A and / or B" (where A and B are used to formally represent specific characteristic contents) will be involved, and the corresponding expressions include the following three combinations: only A, only B, and a combination of A and B.

[0047] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0048] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0049] In the prior art, whenever there is a storage conflict between multiple access requests in a group of threads, the number of clock cycles required to issue all access requests will increase linearly with the number of access requests with storage conflicts, ultimately resulting in too long a time to complete a single instruction, affecting instruction performance.

[0050] In order to make the purpose, technical solution and advantages of the present invention more clear, an existing architecture in which 128 threads access 32 storage banks under a MOV instruction is briefly described as an example. Figure 1 As shown, four operation logic groups are set, each operation logic group is connected to the instruction module through 8 pipelines, and the instruction module is connected to the local register through 32 pipelines.

[0051] Assume that the storage banks that 128 threads need to access are as follows Figure 2 As shown, thread 8 and thread 9 both need to access storage body 9, thread 43 and thread 44 both need to access storage body 12, thread 79 and thread 80 both need to access storage body 16, and thread 115 and thread 116 both need to access storage body 20.

[0052] like Figure 3As shown, the data is scheduled and parsed from the task scheduling module, and then sent to the task controller. After decoding, ICTRL will send the corresponding mov instruction to the data handling module. At this time, the mov instruction contains 128 threads divided into 4 groups, each group contains 32 threads, and is sent to 4 operation logic groups on average. Each operation logic group will eventually process the operation of 32 threads, and each group of each operation logic group processes 8 threads. Therefore, the execution rate of the mov instruction is 32 / cycle. The task scheduling module is also referred to as the SCHED module in subsequent embodiments, the task controller is also referred to as the ICTRL module in subsequent embodiments, and the data handling module is also referred to as the MOV module in subsequent embodiments.

[0053] Each operation logic group issues access requests from 8 threads in parallel, so that the instruction module receives access requests from 32 threads in parallel at a time. Figure 2 As shown, threads 0 to 31 are group 0, threads 32 to 63 are group 1, threads 64 to 95 are group 2, and threads 96 to 127 are group 3. The access requests of each group of threads are issued in batches, as shown in Figure 2 As shown in FIG. 1 , the access requests of threads 0 to 31 of group 0 are sent to the instruction module in the first clock cycle. However, since threads 8 and 9 access the same storage body, there is a storage body conflict. The instruction module will delay the access request of thread 8 or thread 9 to the next clock cycle (i.e., the second clock cycle) for sending. As a result, the access request processing of group 0 requires two clock cycles. After the access request processing of group 0 is completed, the access request processing of group 1 is performed. Therefore, in the presence of Figure 2 In the case of memory bank conflict shown, it takes a total of 8 clock cycles to complete the access request processing of 128 threads (ie, execute one instruction).

[0054] In order to shorten the execution time of instructions and improve execution efficiency, an embodiment of the present invention provides a method for optimizing memory bank conflicts when accessing local registers, such as Figure 4 As shown, M operation logic groups are set, the number of threads contained in each operation logic group is expanded to N, and the number of pipelines connected between each operation logic group and the instruction module is expanded to N, so that the M operation logic groups can issue access requests of K threads in parallel; wherein K is the maximum number of threads that can concurrently access the local register, N = K / M, in actual use, the maximum number of threads that can concurrently access the local register is the number of storage bodies in the local register; as shown Figure 5 As shown, the method includes:

[0055] In step 201, M operation logic groups send access requests of K threads to the instruction module in parallel; wherein, the M operation logic groups send access requests of K threads in parallel, specifically including: M operation logic groups send access requests in parallel; wherein, each operation logic group sends access requests of N threads. Since each operation logic group can process N threads, and each operation logic group is connected to the instruction module with N pipelines, one operation logic group can send N access requests to the instruction module in parallel, and M operation logic groups can send N×M (i.e., K) access requests to the instruction module in parallel, so that the access requests of all threads that need to access the local register are sent to the instruction module together.

[0056] In step 202, the instruction module receives the access requests of the K threads, and performs storage conflict detection on the access requests of the K threads together; the storage conflict detection on the access requests of the K threads together is to detect whether multiple threads need to access the same storage body.

[0057] In step 203, according to the result of the memory bank conflict detection, the time for issuing the access requests of the K threads is planned so that the number of access requests issued in each clock cycle reaches the maximum number that can be issued. Among them, the access request in step 201 is issued to the instruction module by the operation logic group, so that the instruction module performs memory bank conflict detection and clock cycle planning according to each access request, and step 203 is that the instruction module issues the received access request to the local register in the corresponding clock cycle, thereby realizing access to the memory bank. The maximum number that can be issued is the number of memory banks, or the maximum number of access requests without memory bank conflicts between each other.

[0058] It can be understood that the changes made in this embodiment are: the number of threads contained in each operation logic group is expanded from Q in the original solution to N, and the expansion method is that each operation logic group processes M combinations, M = N / Q. And the number of pipelines connected between each operation logic group and the instruction module is expanded to N, so that M operation logic groups can issue access requests of K threads in parallel; where K is the maximum number of threads that can access local registers in parallel, N = Q × M, and the processed thread bundle set is K = N × M. The original solution can only perform N thread conflict detection, while the present invention can perform K thread conflict detection at the same time, which expands the number of detection threads.

[0059] by Figure 6For example, in the first clock cycle, the number of threads waiting to access the local register is large enough, so a thread that needs to access the storage body can be selected for each storage body, and the access requests of these threads are issued. After multiple clock cycles, some access requests have been issued, and the number of remaining unissued access requests is relatively small. Some storage bodies no longer have corresponding access requests. At this time, the maximum number that can be issued is used as the basis for issuance, such as Figure 6 As shown in the 4th and 5th clock cycles in Figure 6 It only takes 5 clock cycles to issue access requests to all threads, that is, to complete an instruction. Figure 2 This method reduces 3 clock cycles.

[0060] This embodiment sends the access requests of K threads to the instruction module together, so that the instruction module can perform common storage conflict detection and clock cycle scheduling for the K threads, so as to avoid the thread waiting caused by the grouped sending of the thread access requests, which leads to the increase of instruction execution time. And by maximizing the number of sent access requests in each clock cycle, the thread access requests are sent in as few clock cycles as possible.

[0061] In actual use, there are multiple implementation methods for planning the time of issuing the access requests of the K threads. Three specific implementation methods are given as examples below:

[0062] The first implementation method is to plan the time for issuing the access requests of the K threads according to the result of the memory bank conflict detection, such as Figure 7 As shown, specifically including:

[0063] In step 301, when there is no storage body conflict between the access request of the first thread and the access request of each current cycle thread, the first thread is used as the current cycle thread until the number of current cycle threads reaches the maximum number that can be issued, and the access requests of all current cycle threads are issued in the current clock cycle; wherein, the first current cycle thread is determined by technical personnel in this field according to needs.

[0064] In step 302, otherwise, the access request of the first thread is reserved and sent in a subsequent clock cycle.

[0065] It should be noted here that the first thread refers to a thread waiting for an access request to be issued, the current clock cycle refers to a clock cycle for determining which access requests to issue, and the current cycle thread refers to the current clock cycle. For different clock cycles for executing a single instruction, the corresponding current cycle thread is also different.

[0066] Here still Figure 6 For example, in the first clock cycle, a person skilled in the art determines thread 0 as the first current cycle thread according to the needs, and then compares another thread with thread 0. If there is no storage body conflict between the other thread and thread 0, the other thread is issued as the second current cycle thread in the first clock cycle, otherwise, it is reserved for comparison in subsequent clock cycles. If the other thread is thread 1, and there is no storage body conflict between thread 1 and thread 0, thread 1 becomes the second current cycle thread, that is, the access request of thread 1 is issued in the first clock cycle, and subsequent threads need to be compared with thread 0 and thread 1 until the number of threads in the current cycle reaches the number of storage bodies, or all threads are compared, and then enter the thread selection of the second clock cycle; if the other thread is thread 32, and there is a storage body conflict between thread 32 and thread 0, thread 32 is not issued in the first clock cycle, but waits for the subsequent clock cycle to make a judgment.

[0067] In the actual implementation process, the detection of storage conflicts for the access requests of K threads together can also be performed in step 301, that is, when executing step 301, it is determined whether there is a storage conflict between the first thread and each current cycle thread, and then it is determined whether the first thread is issued in the current clock cycle according to the storage conflict result.

[0068] The second implementation method is to find multiple threads that have memory bank conflicts (i.e., need to access the same memory bank), and arrange the threads closely in order of clock cycles. For example, assume that among all threads, 4 threads need to access memory bank 0. These 4 threads are thread 0, thread 32, thread 64, and thread 96. The access requests are issued in order of thread request priority from high to low, i.e., from 0 to 128. Therefore, according to the request priority, the access request of thread 0 is issued in the first clock cycle, the access request of thread 32 is issued in the second clock cycle, the access request of thread 64 is issued in the third clock cycle, and the access request of thread 96 is issued in the fourth clock cycle. Arrange all threads that need to access local registers in this way, and finally obtain the threads issued in each clock cycle.

[0069] Since the access requests of K threads are sent to the instruction module together, when the instruction module sends the access request to the local register, the access order of each operation logic group to the local register may be disrupted, thereby affecting the subsequent write rate. In order to solve this problem, under the first implementation method mentioned above, there is also a preferred implementation method, that is, according to the result of the memory conflict detection, the sending time of the access request of the K threads is planned, and it also includes: according to the order of the thread priority from high to low, the clock cycle for sending the access request of each thread is determined in turn. Under this implementation method, it can be ensured that the access request of the thread with high priority is sent first.

[0070] For the second implementation, when the threads are closely arranged in sequence according to the clock cycles, threads with high priorities are preferentially arranged in the earlier clock cycles.

[0071] In actual use, technicians in this field will label each thread. The smaller the thread number, the higher the priority. When each thread bundle K threads are sent to M operation logic groups, each operation logic group needs to process N threads, and each operation logic group can only process Q threads per clock cycle. Therefore, each operation logic group needs to perform m consecutive operations to expand to N threads, m=N / Q, wherein the threads processed by the i-th operation logic group include: m×N+(i-1)×Q+1 to m×N+i×Q threads, m∈{0, 1,…, N / Q}, the j-th thread represents a thread with a priority ranking of j, and the larger the j value, the lower the priority; wherein, the m×N+1-th thread to the m×N-th thread are also referred to as the number of threads for the m-th operation (also called thread group, with Q×M number of threads processed each time, i.e., N). In actual use, each thread and each operation logic group is usually numbered starting from 0. At this time, operation logic group i processes threads m×N+i×Q to threads m×N+(i+1)×Q-1. For example, when M=4, N=32, and K=128, threads 0 to 7, threads 32 to 39, threads 64 to 71, and threads 96 to 103 are processed by operation logic group 0; threads 8 to 15, threads 40 to 47, threads 72 to 79, and threads 104 to 111 are processed by operation logic group 1; threads 16 to 23, threads 48 to 55, threads 80 to 87, and threads 112 to 119 are processed by operation logic group 2; threads 24 to 31, threads 56 to 63, threads 88 to 95, and threads 120 to 127 are processed by operation logic group 3.

[0072] In one embodiment, N is the number of storage bodies, that is, the number of threads contained in each operation logic group is expanded to be consistent with the number of storage bodies, and the number of pipelines connected between each operation logic group and the instruction module is expanded to be consistent with the number of storage bodies, M=K / N.

[0073] For example, when there are 128 threads that need to access local registers and the number of storage bodies is 32, 4 operation logic groups are set, the number of threads contained in each operation logic group is expanded to 32, and the number of pipelines connected between each operation logic group and the instruction module is expanded to 32; the 4 operation logic groups issue access requests of 128 threads in parallel; the instruction module receives the access requests of the 128 threads, and performs storage body conflict detection on the access requests of the 128 threads together; according to the result of the storage body conflict detection, the issuance time of the access requests of the 128 threads is planned so that the number of access requests issued in each clock cycle reaches the maximum number that can be issued.

[0074] In actual application scenarios, the access request is generated based on instructions. There are multiple types of instructions, and all instructions that require multi-threaded access to registers are applicable. For example, in an optional implementation, the instructions include one or more of MOV instructions (also called data transfer instructions), DMA instructions (also called direct storage instructions), or AP instructions (also called atomic instructions). This embodiment is presented using the MOV instruction as an example.

[0075] The present invention is based on the method described above, combined with specific application scenarios, and uses technical descriptions in related scenarios to illustrate the implementation process of the present invention in the characteristic scenarios.

[0076] This embodiment takes the case where 128 threads access 32 banks under the optimization of the mov instruction as an example of the application scenario.

[0077] In the prior art, when the mov instruction accesses the local memory of the GPU, since the local memory is divided into multiple banks, these banks can be accessed simultaneously, but the number of accesses is affected by the number of banks, so the throughput is also related to the number of banks. When multiple threads access multiple banks, there is often a bank conflict. Bank conflict means that when at least two threads access the same bank, it will be split into multiple accesses, thereby increasing the access time.

[0078] This embodiment aims to optimize the conflict situation when 128 threads access 32 banks. The framework of our current model is as follows: Figure 3As shown: data is scheduled and parsed from the SCHED module, and then sent to the ICTRL module. After decoding, ICTRL sends the corresponding mov instruction to the MOV module. At this time, the mov instruction contains 128 threads divided into 4 groups, each group contains 32 threads, and is sent to 4 operation logic groups on average. Each operation logic group will eventually process the operation of 32 threads, and each group of each operation logic group processes 8 threads. Therefore, the execution rate of the mov instruction is 32 / cycle.

[0079] In the prior art, each operation unit group includes 8 threads, and there are 4 operation unit groups in total, that is, only 32 threads can be processed, and the local memory includes 32 banks in total, which can accept a maximum of 32 thread data.

[0080] The access of each operation logic group's thread to local memory is as follows Figure 2 As shown, bank conflict is involved. The four groups will perform bank conflict detection in turn, and each group of threads can only access the next group of threads after all the threads have completed the access. If there are two threads in each group of threads accessing the local memory and they access the same bank, then this group of threads needs two cycles to complete the access. Therefore, each single mov instruction 128 threads needs 8 cycles to complete the access.

[0081] When 128 threads are divided into 4 groups to access local memory, each group has a priority, which leads to sparse requests for local memory during some time between groups, thus affecting the overall performance. Based on this, a method is proposed to use 128 threads to perform bank conflict detection simultaneously to improve the utilization rate of accessing local memory under a single instruction. The specific method is as follows: Figure 4 As shown, the number of threads in each operation logic group is expanded to 32, so that a total of 128 threads can access simultaneously. Each operation logic group is expanded from 8 threads to 32 threads. In order not to increase the number of internal ALUs, the valid data of 4 clock cycles is combined into 1 clock cycle through the timing combination logic, as shown in Figure 8 shown.

[0082] Among them, each operation logic group requests 32 threads, and the four operation logic groups form 128 threads to access registers. However, when accessing the register bank, the thread with a lower number always has a higher priority, that is, thread 0 has the highest access priority and thread 127 has the lowest priority. Therefore, the thread groups of each operation logic group need to be arranged in the order of 0 to 127 when performing conflict detection. Because the mov execution rate is 32, this can satisfy the relatively consistent access priorities of the four operation logic groups, which will not affect the subsequent write rate. Fig. 9 shown.

[0083] Since the number of local memory banks is 32, a 128-to-32 mapping relationship is formed. Compared with the previous four groups of 32-to-32 mappings, access requests can be issued faster, resulting in the following: Figure 6 The new access request is shown.

[0084] from Figure 6 From the latest mapping shown, it only takes 5 cycles for 128 threads to access 32 banks, which is about 60% less than the previous 8 cycles. If the mov instructions of the entire test case are issued quickly enough and in parallel, at least one mov instruction can be issued in every 5 cycles, and enough threads can be processed in parallel in the pipeline, then the overall performance of the corresponding mov access to local memory will be improved to the ideal situation. The specific improvement depends on the number of cycles required after the two bank conflicts. However, as long as there are enough mov instructions, the conflict in accessing local memory is serious, and the conflict points of the two thread groups are not on the same bank, there will be a certain performance improvement.

[0085] Based on the above method for optimizing memory bank conflicts when accessing local registers, this embodiment further provides a device for optimizing memory bank conflicts when accessing local registers, such as Figure 4 As shown, it includes M operation logic groups and instruction modules; the number of pipelines connected between each operation logic group and the instruction module is N; where N = K / M, K is the number of threads that need to access local registers; the M operation logic groups are used to send access requests of K threads to the instruction module in parallel.

[0086] The instruction module is used to receive the access requests of the K threads, and perform storage body conflict detection on the access requests of the K threads together; and according to the results of the storage body conflict detection, plan the issuance time of the access requests of the K threads so that the number of access requests issued in each clock cycle reaches the maximum number that can be issued; so as to use the access requests to realize access to the storage body in the local register.

[0087] In an optional implementation, M is 4, N is 32, and K is 128.

[0088] The step of planning the issuing time of the access requests of the K threads according to the result of the memory bank conflict detection specifically includes:

[0089] In order of thread numbers from small to large, determine in which clock cycle the access request of the thread is issued. Specifically: when the corresponding thread has a storage body conflict with each current cycle thread of the current clock cycle, the thread is retained until the subsequent clock cycle for issuance. Otherwise, the thread is issued in the current clock cycle as the current cycle thread, and the thread also participates in the judgment of whether the access requests of other subsequent threads can be issued in the current clock cycle as the current clock cycle.

[0090] like Fig.10 , is a schematic diagram of the architecture of a device for optimizing memory bank conflicts when accessing a local register according to an embodiment of the present invention. The device for optimizing memory bank conflicts when accessing a local register according to this embodiment includes one or more processors 21 and a memory 22. Fig.10 A processor 21 is taken as an example.

[0091] The processor 21 and the memory 22 may be connected via a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0092] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer executable programs, such as the method for optimizing storage bank conflicts when accessing local registers in Example 1. The processor 21 executes the method for optimizing storage bank conflicts when accessing local registers by running the non-volatile software programs and instructions stored in the memory 22.

[0093] The memory 22 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 22 may optionally include a memory remotely arranged relative to the processor 21, and these remote memories may be connected to the processor 21 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0094] The program instructions / modules are stored in the memory 22, and when executed by the one or more processors 21, the method for optimizing memory bank conflicts when accessing local registers is performed.

[0095] It is worth noting that the information interaction, execution process, etc. between the modules and units within the above-mentioned devices and systems are based on the same concept as the processing method embodiment of the present invention. The specific contents can be found in the description of the method embodiment of the present invention and will not be repeated here.

[0096] A person skilled in the art may understand that all or part of the steps in the various methods of the embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing memory bank conflicts when accessing local registers, characterized in that: M operation logic groups are set, the number of threads contained in each operation logic group is expanded to N, and the number of pipelines connected between each operation logic group and the instruction module is expanded to N, so that the M operation logic groups can issue access requests of K threads in parallel; wherein K is the maximum number of threads that can concurrently access the local register, and N=K / M; the method includes: M operation logic groups send K threads' access requests to the instruction module in parallel; The instruction module receives the access requests of the K threads, and performs storage bank conflict detection on the access requests of the K threads together; According to the result of the memory bank conflict detection, the issuing time of the access requests of the K threads is planned so that the number of the access requests issued in each clock cycle reaches the maximum number that can be issued.

2. The method for optimizing memory bank conflicts when accessing local registers according to claim 1, characterized in that: The planning of the issuing time of the access requests of the K threads according to the result of the memory bank conflict detection includes: When there is no storage bank conflict between the access request of the first thread and the access requests of each current cycle thread, the first thread is used as the current cycle thread, until the number of current cycle threads reaches the maximum number that can be issued, and the access requests of all current cycle threads are issued in the current clock cycle; Otherwise, the access request of the first thread is reserved and sent in a subsequent clock cycle.

3. The method for optimizing memory bank conflicts when accessing local registers according to claim 2, characterized in that: The step of planning the issuing time of the access requests of the K threads according to the result of the memory bank conflict detection further includes: The clock cycle for issuing the access request of each thread is determined in sequence according to the priority of the threads from high to low.

4. The method for optimizing memory bank conflicts when accessing local registers according to claim 3, characterized in that: Each operation logic group processes N threads, wherein the threads processed by the i-th operation logic group include: m×N+(i-1)×N / M+1 to m×N+i×N / M threads, m∈{0, 1, . . . , M}.

5. The method for optimizing memory bank conflicts when accessing local registers according to claim 1, characterized in that: N is the number of storage bodies, that is, the number of threads contained in each operation logic group is expanded to be consistent with the number of storage bodies, and the number of pipelines connected between each operation logic group and the instruction module is expanded to be consistent with the number of storage bodies, M=K / N.

6. The method for optimizing memory bank conflicts when accessing local registers according to claim 1, characterized in that: The M operation logic groups send the access requests of the K threads in parallel, including: M operation logic groups issue access requests in parallel; wherein each operation logic group issues access requests of N threads.

7. The method for optimizing memory bank conflicts when accessing local registers according to claim 1, characterized in that: When there are 128 threads that need to access local registers and the number of storage banks is 32, 4 operation logic groups are set, the number of threads contained in each operation logic group is expanded to 32, and the number of pipelines connected between each operation logic group and the instruction module is expanded to 32; Four operation logic groups issue access requests of 128 threads in parallel; The instruction module receives the access requests of the 128 threads, and performs storage bank conflict detection on the access requests of the 128 threads together; According to the result of the memory bank conflict detection, the issuing time of the access requests of the 128 threads is planned so that the number of the access requests issued in each clock cycle reaches the maximum number that can be issued.

8. The method for optimizing memory bank conflicts when accessing local registers according to claim 1, characterized in that: The access request is generated according to an instruction, and the instruction includes one or more of a MOV instruction, a DMA instruction or an AP instruction.

9. The method for optimizing memory bank conflicts when accessing local registers according to claim 1, characterized in that: The maximum number that can be sent is the number of storage bodies, or the maximum number of access requests without conflicts between storage bodies.

10. A device for optimizing memory bank conflicts when accessing a local register, characterized in that: It includes M operation logic groups and instruction modules; The number of pipelines connected between each operation logic group and the instruction module is N; wherein N = K / M, K is the number of threads that need to access the local register; M operation logic groups are used to send access requests of K threads to the instruction module in parallel; The instruction module is used to receive the access requests of the K threads, and perform storage body conflict detection on the access requests of the K threads together; and according to the results of the storage body conflict detection, plan the issuance time of the access requests of the K threads so that the number of access requests issued in each clock cycle reaches the maximum number that can be issued; so as to use the access requests to realize access to the storage body in the local register.

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