Data processing method and system

Abstract

The invention discloses a data processing method and system. The system comprises an execution node, an accelerator and a management node, the management node is used for generating scheduling information for a plurality of sub-tasks included in the calculation task, and the scheduling information comprises information of a first sub-task executed by the execution node and information of a second sub-task executed by the accelerator; the information of the first subtask and the information of the second subtask are sent to the execution node; the execution node executes the first subtask according to the information of the first subtask and sends the information of the second subtask to the accelerator; and the accelerator is used for executing the second subtask according to the information of the second subtask. The scheme can be used for providing a flexible computing power acceleration architecture so as to improve the computing power processing efficiency of the whole system.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data processing method and system. Background Art

[0002] At present, big data / databases have become the mainstream business scenarios in various industries (such as finance, Internet, operators, etc.). With the continuous expansion of actual data scale and the emergence of complex data analysis / query needs, higher requirements are placed on the computing acceleration capabilities of business systems. The efficiency of traditional data analysis acceleration frameworks based on pure software can no longer meet business demands.

[0003] Although the current design proposes that hardware accelerators can be introduced into the business system to achieve computing power acceleration with the help of some computing capabilities provided by the hardware accelerators, there is no solution for effective management and scheduling of accelerators.

[0004] Therefore, how to flexibly manage and schedule the computing resources of business systems remains an important issue that needs to be solved urgently. Summary of the invention

[0005] The embodiments of the present application provide a data processing method and system for flexibly managing and scheduling the computing resources of the system, thereby improving the computing processing efficiency of the entire system.

[0006] In a first aspect, an embodiment of the present application provides a data processing system, which may include: an execution node, an accelerator, and a management node; the management node is used to generate scheduling information for multiple subtasks included in a computing task, the scheduling information including information about a first subtask executed by the execution node and information about a second subtask executed by the accelerator; the management node is used to send information about the first subtask and information about the second subtask to the execution node; the execution node is used to execute the first subtask according to the information about the first subtask, and send information about the second subtask to the accelerator; the accelerator is used to execute the second subtask according to the information about the second subtask.

[0007] Through the above scheme, accelerators can be added to the data processing system to support different computing acceleration capabilities. At the same time, the management node can flexibly schedule the required execution nodes and / or accelerators for the computing tasks, so as to realize pipeline acceleration processing of computing tasks through a combination of software and hardware, thereby improving the computing acceleration effect and reducing the consumption of computing resources.

[0008] In one possible design, the management node is also used to obtain resource information of the execution node and the accelerator, and the management node is used to generate the scheduling information for the multiple subtasks included in the computing task based on the resource information of the execution node and the accelerator.

[0009] It should be understood that in the embodiment of the present application, the resource information of the execution node and the accelerator may include information on the computing capabilities supported by the execution node and the accelerator, for example, the execution node and / or the accelerator may be implemented as at least one of the following computing hardware: central processing unit CPU, graphics processing unit GPU, data processing unit DPU, neural network processor NPU. Alternatively, the resource information of the execution node and the accelerator may include information on the operators supported by the execution node and the accelerator, for example, the execution node and / or the accelerator may support at least one of the following operators: sorting (Sort) operator, filtering (Filter) operator, aggregation (Agg) operator, scanning (Scan) operator, projection (Proj) operator, k-nearestneighbor (KNN) operator, Top-K operator, approximate nearest neighbor (Approximate Nearest Neighbor, ANN) operator. In an optional embodiment, the execution node and / or the accelerator may also support other types of advanced operators, such as omnivector (OmniVector) operator, omniJit (OmniJit) operator, OmniSheild operator, etc. In specific implementation, the system can open the expansion of basic operators or high-efficiency operators to meet different needs, which will not be elaborated here.

[0010] Through the above scheme, the management node can act as a decision maker in the data processing system and perform unified scheduling for computing tasks through the acquired resource information, so as to utilize the different computing power resources provided by the accelerator and realize pipeline processing of computing tasks.

[0011] In one possible design, the data processing system may include at least one accelerator, and the management node is further used to obtain resource usage information of the at least one accelerator, and the management node is used to generate information of a second subtask executed by the accelerator based on the resource usage information of the at least one accelerator. In this way, the management node can dynamically schedule available accelerators for computing tasks based on the usage of computing resources of different accelerators, and achieve load balancing of the data processing system as much as possible. At the same time, it is also possible to reuse different accelerators, to reduce resource usage, improve the interactivity and scalability of the accelerators, and expand the application scope of the data processing system.

[0012] In one possible design, the accelerator supports multiple computing modules, each computing module is used to execute a type of subtask.

[0013] In one possible design, the management node is further used to obtain resource usage information of multiple computing modules of the accelerator, and the management node is used to generate information of a second subtask executed by the accelerator based on the resource usage information of the multiple computing modules of the accelerator.

[0014] In a possible design, before sending the information of the second subtask to the accelerator, the execution node is further configured to start a computing module corresponding to the second subtask in the accelerator according to the information of the second subtask.

[0015] In one possible design, each computing module in the accelerator includes a switch, and the execution node starts the computing module corresponding to the second subtask by turning on the switch of the computing module corresponding to the second subtask.

[0016] In one possible design, the execution node is further used to obtain resource information and / or resource usage information of the accelerator, and the execution node is used to send the resource information and / or resource usage information of the accelerator to the management node.

[0017] In one possible design, the execution node includes any of the following types: a computing node, a computing node cache layer, and a storage node.

[0018] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to a data processing system, wherein the data processing system may include an execution node, an accelerator, and a management node. The method may include: the management node generates scheduling information for multiple subtasks included in a computing task, the scheduling information including information about a first subtask executed by the execution node and information about a second subtask executed by the accelerator; the information about the first subtask and the information about the second subtask are sent to the execution node; the execution node executes the first subtask according to the information about the first subtask, and sends the information about the second subtask to the accelerator; the accelerator is used to execute the second subtask according to the information about the second subtask.

[0019] In one possible design, the method further includes: the management node obtaining resource information of the execution node and the accelerator, and generating the scheduling information for the multiple subtasks included in the computing task based on the resource information of the execution node and the accelerator.

[0020] In one possible design, the data processing system includes at least one accelerator, and the method further includes: the management node obtains resource usage information of the at least one accelerator; the management node generates scheduling information for multiple subtasks included in the computing task, including: the management node generates information of a second subtask executed by the accelerator based on the resource usage information of the at least one accelerator.

[0021] In one possible design, the accelerator supports multiple computing modules, each computing module is used to execute a type of subtask.

[0022] In one possible design, the method may also include: the management node obtains resource usage information of multiple computing modules of the accelerator; the management node generates scheduling information for multiple subtasks included in the computing task, including: the management node generates information of a second subtask executed by the accelerator based on the resource usage information of the multiple computing modules of the accelerator.

[0023] In one possible design, before the execution node sends the information of the second subtask to the accelerator, the method further includes: the execution node starting a computing module corresponding to the second subtask in the accelerator according to the information of the second subtask.

[0024] In one possible design, each computing module in the accelerator includes a switch, and the execution node starts the computing module corresponding to the second subtask in the accelerator, including: starting the computing module corresponding to the second subtask by turning on the switch of the computing module corresponding to the second subtask.

[0025] In one possible design, the method further includes: the execution node obtaining resource information and / or resource usage information of the accelerator; and the execution node sending the resource information and / or resource usage information of the accelerator to the management node.

[0026] In one possible design, the execution node may include any of the following types: a computing node, a computing node cache layer, and a storage node.

[0027] In the third aspect, the embodiment of the present application further provides a computing device, which has the function of implementing the management node or execution node in the method example of the second aspect above. The beneficial effects can be found in the description of the first aspect and will not be repeated here. The functions can be implemented by hardware or by executing corresponding software through hardware. The hardware or software includes one or more modules corresponding to the above functions. In one possible design, the structure of the device includes an acquisition module, a backup module, and optionally, a processing module. These modules can execute the corresponding functions of the execution node / management node in the method example of the second aspect above. Please refer to the detailed description in the method example for details, which will not be repeated here.

[0028] In a fourth aspect, an embodiment of the present application further provides a computing device, the device comprising a processor and a power supply circuit, the power supply circuit being used to power the processor, the processor executing program instructions in the memory to execute the method executed by the execution node or management node provided in the second aspect or any possible implementation of the second aspect. The memory is coupled to the processor, and stores program instructions and data necessary for executing data processing.

[0029] In a fifth aspect, an embodiment of the present application further provides a computing device, the computing device includes a processor and a memory, and may also include a communication interface, the processor executes program instructions in the memory to execute the method executed by the execution node in the above second aspect or any possible implementation of the second aspect, or executes the method executed by the management node in the above second aspect or any possible implementation of the second aspect. The memory is coupled to the processor, and stores program instructions and data necessary for executing the data backup process. The communication interface is used to communicate with other devices.

[0030] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, and when the computer-readable storage medium is executed by a computing device, the computing device executes the method executed by the execution node in the aforementioned second aspect or any possible implementation of the second aspect, or the method executed by the management node in the aforementioned second aspect or any possible implementation of the second aspect. The storage medium stores a program. The storage medium includes but is not limited to volatile memory, such as random access memory, non-volatile memory, such as flash memory, hard disk drive (HDD), solid state drive (SSD).

[0031] In a seventh aspect, an embodiment of the present application provides a computing device program product, the computing device program product includes computer instructions, and when executed by a computing device, the computing device executes the method executed in the aforementioned second aspect or any possible implementation of the second aspect. The computer program product can be a software installation package, and when it is necessary to use the method provided in the aforementioned second aspect or any possible implementation of the second aspect, the computer program product can be downloaded and executed on a computing device.

[0032] In an eighth aspect, an embodiment of the present application further provides a chip, which is used to implement the method executed by the host in the above-mentioned second aspect or each possible implementation manner of the second aspect by executing a software program.

[0033] Based on the implementations provided in the above aspects, the embodiments of the present application can be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of a scenario architecture applicable to an embodiment of the present application is shown;

[0035] Figure 2 A functional schematic diagram of a management node in an embodiment of the present application is shown;

[0036] Figure 3 A schematic diagram of the architecture of a data processing system according to an embodiment of the present application is shown;

[0037] Figure 4 A schematic diagram showing the structure of multiple computing modules of an accelerator according to an embodiment of the present application is shown;

[0038] Figure 5a A schematic diagram showing the principle of a data acceleration processing method is shown;

[0039] Figure 5b A schematic diagram showing the principle of another data acceleration processing method is shown;

[0040] Figure 6 A schematic diagram showing a flow chart of a data processing method according to an embodiment of the present application is shown;

[0041] Figure 7a A topological structure of an embodiment of the present application is shown;

[0042] Figure 7b Another topological structure of an embodiment of the present application is shown;

[0043] Figure 8 A schematic diagram of load scheduling in an embodiment of the present application is shown;

[0044] Fig. 9A schematic diagram of the structure of a communication device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0045] The embodiments of the present application provide a data processing method and system for providing a flexible computing power acceleration architecture to improve the computing power processing efficiency of the entire system. Among them, the method and the device are based on the same technical concept. Since the principles of solving problems by the method and the device are similar, the implementation of the device and the method can refer to each other, and the repeated parts will not be repeated. In addition, in each embodiment of the present application, if there is no special explanation and logical conflict, the terms and / or descriptions between the various embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form a new embodiment according to their inherent logical relationship.

[0046] It should be noted that in the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0047] Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the priority or importance of multiple objects. For example, the first device and the second device are only used to distinguish different electronic devices, rather than indicating the difference in priority or importance of the two devices.

[0048] Figure 1 The schematic diagram of the scene architecture applicable to the embodiment of the present application is shown. The architecture is only an exemplary description and only provides components related to the embodiment of the present application. Figure 1 This is not a specific limitation on the application of this application. Figure 1 As shown, the data processing system may include an execution node 10 , an accelerator 20 , and a management node 30 .

[0049] Figure 1On the left side is the user device, which can be a virtual machine or a physical machine. The physical machine can be an ordinary computer 101a, a tablet computer 101b, a smart phone 101c, etc., which is not limited in the embodiments of the present application. An application (application, APP) (or tool) for implementing functions such as data query and analysis / processing can be deployed on the user device. The APP may include but is not limited to at least one of the following: Hive, Spark, Flink, openLooKeng, openGauss or VectorDatabase. The user can trigger a computing task by operating the APP. The user device can send the computing task to the data processing system through the network 150 to request the data processing system to process the computing task based on its own computing resources or storage resources, etc., which can support data-intensive scenarios such as big data, database analysis, and artificial intelligence (AI) reasoning, and achieve the purpose of computing power acceleration, thereby improving the computing density and computing power processing efficiency of the entire system.

[0050] As the decision maker of the data processing system, the management node 30 can be a hardware device, such as a server, a laptop, a desktop computer, etc., or a software device, such as a set of software programs running on the hardware device. The management node 30 can be used to obtain resource information of the execution node 10 and / or the accelerator 20, know the computing power that different execution nodes or accelerators can provide, and uniformly manage and schedule the computing resources of the data processing system.

[0051] Exemplarily, the execution node 10 can be implemented as any of the following types: a computing node, a computing node cache layer, and a storage node. The computing node or the computing node cache layer can be implemented as, but not limited to, any of the following types of infrastructure: a CPU, a data processing unit (DPU), a co-processor, a graphics processing unit (GPU), a processor in memory (PIM, processing-in-memory, also known as in-memory computing or in-memory computing), a field programmable gate array (FPGA), a smart solid-state drive (smart SSD), various domain-specific architectures (DSA), application-specific integrated circuits (ASIC), virtual computing devices (Virtual Computing) or other types of processor engines (expressed as xPU, where x represents unknown).

[0052] A storage node can be a hardware device or a virtual machine. Hardware devices such as storage servers and storage arrays are usually used to store data persistently, including but not limited to serial hard disks (such as Serial Advanced Technology Attachment hard disk, SATA) or solid state disks (Solid State Disk or Solid State Drive, SSD), etc. The storage node can be a centralized storage node or a distributed storage node. The storage node can provide but is not limited to: Hadoop Distributed File System (Hadoop Distributed File System, HDFS), Object Storage Service (Object Storage Service, OBS), Ceph distributed storage system, or Simple Storage Service (S3).

[0053] The computing power type supported by the accelerator 20 may be the same as that of the execution node, or may be different from that of the execution node. Figure 2As shown, the operator types supported by the accelerator 20 include but are not limited to at least one of the following basic operators: sort (Sort) operator (for example, represented by S), filter (Filter) operator (for example, represented by F), aggregation (Agg) operator (for example, represented by A), scan (Scan) operator, projection (Proj) operator, k-nearest neighbor analysis (k-NearestNeighbor, KNN) operator (for example, represented by K), Top-K operator (for example, represented by T), approximate nearest neighbor (Approximate Nearest Neighbor, ANN) operator. In an optional embodiment, the computing power resources of the execution node 10 and / or the accelerator 20 may also include other types of advanced operators, such as omnivector (OmniVector) operator, omniJit (OmniJit) operator, OmniSheild operator, etc. It should be understood that this is an example of the operator types supported by the execution node 10 and / or the accelerator 20, rather than any limitation. In specific implementation, the system can open the types of basic operators or high-efficiency operators for expansion to meet the different computing power requirements of different user devices. For example, the accelerator can be implemented as the DPU or FPGA introduced above, supporting the above-mentioned operators F, A, S, K, T, etc.

[0054] In the embodiment of the present application, the data processing system can provide a unified software and hardware interface (or a unified interface specification), support abstraction into a general atomic interface based on industry standard models, algorithms, etc., and can support virtualized computing power hardware or storage hardware, shielding the differences caused by different underlying hardware (including computing power hardware or storage hardware), so that developers can quickly build applications and services to build the data processing system described above. At the same time, it supports deployment in multiple forms (such as bare metal servers (or bare metal), virtual machines, containers, lightweight containers, serverless, etc.) without users having to pay attention to the underlying hardware.

[0055] The management node 30 may obtain and record the resource information of the execution node 10 and the accelerator 20. The management node 30 may also receive a computing task from a user device, and generate scheduling information for multiple subtasks included in the computing task according to the resource information of the execution node and the accelerator. The management node 30 may send the scheduling information to the execution node 10. Accordingly, the execution node 10 may receive the scheduling information from the management node 30, and may execute the corresponding task according to the scheduling information.

[0056] In a possible implementation, some subtasks in the computing task can be executed by the execution node 10, and another part of the subtasks can be executed by the accelerator 20. For the convenience of distinction, the embodiment of the present application can refer to the computing task that is a subtask executed by the execution node among multiple subtasks as the first subtask, and the computing task that is a subtask executed by the accelerator among multiple subtasks as the second subtask. The scheduling information from the management node may include information about the first subtask executed by the execution node and information about the second subtask executed by the accelerator. After receiving the scheduling information from the management node, the execution node can execute the first subtask according to the information of the first subtask, and send the information of the second subtask to the associated accelerator, and the accelerator can execute the second subtask according to the information of the second subtask.

[0057] In specific implementation, the data processing system can be built according to the business. Figure 1 The execution node shown can be implemented as any of the following types: a computing node, a computing node cache layer, and a storage node. Taking the implementation of the execution node as a computing node as an example, the computing node can be a hardware device or a virtual machine, such as a server, a laptop, etc. The computing node can be used to receive scheduling information from the management node, and execute the first subtask according to the information of the first subtask included in the scheduling information, and specifically can be used to perform operations such as data calculation and processing in the first subtask. Taking the implementation of the execution node as a storage node as an example, the storage node can be a hardware device or a virtual machine, such as a storage server, a storage array, etc., which are usually used to store data persistently. The storage node can be used to receive scheduling information from the management node, and execute the first subtask according to the information of the first subtask included in the scheduling information, and specifically can be used to perform operations such as data calculation and processing in the first subtask.

[0058] The accelerator 20 can be deployed on the execution node 10, or it can be deployed independently of the execution node 10. The accelerator 20 can be used to execute at least one subtask of the computing task, such as executing the second subtask, to help the execution node 10 achieve computing power acceleration. When the management node performs scheduling, at least one accelerator may also perform operations such as data calculation and processing in the second subtask in the computing task. The above-mentioned "association" refers to the execution node and the accelerator being used to execute different subtasks of the same computing task based on task association, and does not constitute a limitation on the product form or deployment method of the execution node and accelerator. In specific implementation, the accelerator can be deployed on the same chip or device as the execution node 10, or it can be deployed independently of the execution node 10. Figure 1The connection line between the execution node 10 and the accelerator 20 or the connection line between the management node 30 and the execution node 10 only schematically represents the communication interaction between the execution node 10, the accelerator 20 or the management node 30, and does not constitute a limitation on the product form or deployment method of the three.

[0059] It should be noted that Figure 1 The number of execution nodes, accelerators, and management nodes shown is not limited. The functions of the nodes described above are only examples. For example, in addition to generating scheduling information for computing tasks, the management node 30 can also Figure 2 As shown, the scheduling information is optimized by the optimizer, and at the same time, the computing resources of each execution node or accelerator can be monitored, operated, maintained, and alarmed to implement load perception and equipment management, etc., and adaptively according to the actual needs of the computing tasks and the status of each computing hardware to achieve unified management and scheduling of computing resources, storage resources, network resources, and security resources, etc., configure the interconnection within / between accelerators, so that data only flows through the accelerator once to complete the data processing flow, the acceleration range is wider, and the system performance is improved. The embodiments of the present application are not limited to this.

[0060] In the embodiment of the present application, the accelerator for providing the computing power acceleration function can be independently deployed on the storage node side, or the computing node cache layer side, or at least one of the computing node side. The management node can schedule the accelerator for operations such as data calculation and processing that need to be performed on the storage node side, or the computing node cache layer side, or at least one of the computing node side according to each subtask of the computing task, and use the computing power resources provided by the accelerator to implement a pipelined computing power acceleration processing flow to maximize the performance of each side.

[0061] Below Figure 1 The data processing system shown is implemented as Figure 3 Taking the deployment architecture shown as an example, the data processing solution of the embodiment of the present application is introduced in detail.

[0062] 1. Management node 30:

[0063] like Figure 3 As shown, the management node 30 may include a processor 31 , a memory 32 , a network card 33 and a bus 34 . The processor 31 , the memory 32 , and the network card 33 are connected via a bus 34 .

[0064] The processor 31 can receive the data from the user device ( Figure 3The processor 31 may be a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, artificial intelligence chips, chips on chips, graphics processing units (GPU), etc. It should be noted that Figure 3 Only one processor is shown in the figure. In actual applications, the number of processors of the management node may be multiple, wherein one processor may have one or more processor cores. The embodiment of the present application does not limit the number of processors of the management node and the number of processor cores.

[0065] The memory 32 can be used to store computer instructions and data, such as the computer instructions and data required for the memory to store the data processing method provided in the present application. The memory can include a volatile memory, such as a random access memory (RAM), a dynamic random access memory (DRAM), etc. It can also be a non-volatile memory, such as a storage-class memory (SCM), etc., or a combination of a volatile memory and a non-volatile memory.

[0066] The network card 33 can be used to communicate with the execution node. For example, the management node 30 sends scheduling information to the computing node through the network card 33, or the management node sends scheduling information to the storage node through the network card 33, or the management node sends scheduling information to the computing node cache layer through the network card 33.

[0067] In addition to the data bus, the bus 34 may also include a power bus, an address bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, various buses are labeled as bus 34 in the figure. The bus 34 may be a Peripheral Component Interconnect Express (PCIe) bus, a double data rate (DDR) bus, a serial advanced technology attachment (SATA) bus, a serial attached SCSI (SAS) bus, a controller area network (CAN) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc., and the present application does not limit this.

[0068] In a possible implementation, the processor 31 can obtain resource information of the execution node and the accelerator, and generate scheduling information for multiple subtasks included in the computing task based on the resource information of the execution node and the accelerator. For specific resource types, please refer to the relevant introduction in the previous text, which will not be repeated here. Among them, the resource information of the execution node can be sent by the execution node to the management node, and the resource information of the accelerator can be obtained by the execution node from the accelerator node and sent to the management node. The management node can receive resource information from the execution node through the network card, and can store the received resource information in the memory 32. It should be understood that in the specific implementation, different execution nodes or accelerators can be pre-registered with the management node to inform the management node of their own resource information. When the resource information of the execution node or the accelerator changes, the execution node can also send updated resource information to the management node, and the embodiment of the present application does not limit the acquisition time of this resource information.

[0069] In another possible implementation, the data processing system may include at least one accelerator, and the processor 31 may obtain resource usage information of at least one accelerator, which may be used to describe the usage status of the relevant resources of the accelerator, such as busy or idle, normal use or damaged, etc. The processor 31 may generate information about the second subtask performed by the accelerator based on the resource usage information of at least one accelerator. For example, the processor 31 may schedule an available accelerator for a computing task, and execute the information about the second subtask of the computing task through the accelerator. Alternatively, the processor 31 may perform cross-accelerator scheduling for the computing task, and execute the information about the second subtask of the computing task through at least one accelerator in collaboration.

[0070] In another possible implementation, any accelerator may support multiple computing modules, each of which is used to execute a type of subtask. The processor 31 may also obtain resource usage information of multiple computing modules of different accelerators, and generate information of the second subtask executed by the accelerator according to the resource usage information of multiple computing modules of different accelerators.

[0071] like Figure 4 As shown, represented by R0-R15 Figure 3 Taking the multiple computing modules supported by any accelerator as an example, each computing module can be used to perform a type of subtask, for example, R0 and R9 can be used to perform the task of the KNN operator, R1 and R10 can be used to perform the task of the TOPK operator, R2, R11 and R12 can be used to perform the task of the scanning operator, R3, R4 and R13 can be used to perform the task of the filtering operator, R5 and R14 can be used to perform the task of the aggregation operator, R6 and R15 can be used to perform the task of the sorting operator, and R7 and R8 can be used to perform the task of the ANN operator. The processor 31 can obtain the operator types supported by different computing modules of the accelerator, and analyze whether the accelerator can still be scheduled for use in combination with the occupancy of different computing modules. For example, if the subtasks of the computing task include the tasks of the KNN operator that need to be executed by the accelerator, and R0 of a certain accelerator is occupied but R9 is not occupied, the processor 31 can schedule R9 of the accelerator to the computing task. If all computing modules of a certain accelerator for executing the task of the KNN operator are occupied, the processor 31 needs to schedule other accelerators capable of executing the task of the KNN operator for the computing task when generating scheduling information for the computing task.

[0072] It should be understood that in the embodiment of the present application, different computing modules of each accelerator can achieve interconnection and communication through an intra-chip interconnection technology, and the intra-chip interconnection technology may include but is not limited to NOC, ShareMem or Crossbar interconnection technology. Figure 4Only some of the bidirectional arrows are used to indicate that different computing modules can communicate with each other through the intra-chip interconnection technology, which does not constitute a limitation. The computing modules that are not shown with bidirectional arrows can also communicate with each other based on the intra-chip interconnection technology. For example, R0 and R5, R1 and R4, R1 and R6, R2 and R5, etc. can communicate with each other through the intra-chip interconnection technology. Other computing modules are similar and will not be repeated here.

[0073] Similarly, the resource usage information of the accelerator may also be obtained by the execution node from the accelerator node and sent to the management node. The management node may receive and record the resource usage information from the execution node through the network card. Alternatively, since the management node may perform unified management and scheduling for different execution nodes or accelerators, the processor 31 may also synchronously record the resource scheduling results after generating scheduling information for the computing task to monitor the resource usage of different accelerators. The embodiment of the present application does not limit the method for obtaining the resource usage information of the accelerator.

[0074] The processor 31 may send the generated scheduling information to the execution node through the network card 33 .

[0075] 2. Compute nodes:

[0076] A computing node may be an example of an execution node as described above. Figure 3 As shown, similar to the management node, the computing node may include a processor, memory, network card and bus, and the computing node may realize communication and interconnection with the accelerator, management node or storage node through the network card and network interconnection technology. The functional implementation details of the specific components of the computing node can be found in the above introduction to the management node, which will not be repeated here.

[0077] The CPU represents the processor of the computing node. After receiving the scheduling information from the management node, the CPU of the computing node can cooperate with the associated accelerator to perform computing tasks in the following two ways. As shown below:

[0078] Method (1):

[0079] like Figure 5a As shown, the CPU receives the scheduling information from the management node, and obtains the information of the first subtask and the information of the second subtask by analyzing the scheduling information.

[0080] For the first subtask that needs to be performed by the computing node, the CPU can perform the first subtask according to the information of the first subtask. For the second subtask that needs to be performed by the accelerator, the CPU can send the information of the second subtask to the accelerator on the one hand. On the other hand, the CPU can also read the required target data from the target storage medium to the memory of the computing node in a P2P manner. The accelerator itself can have a memory (not shown in the figure), and after receiving the information of the second subtask, the accelerator can store the information of the second subtask in the memory of the accelerator. The corresponding computing module of the accelerator can perform the second subtask according to the information of the second subtask. For example, the corresponding computing module of the accelerator can read the target data from the memory of the computing node, and sequentially execute pipeline processing processes including but not limited to decryption, decompression, decoding, filtering, evaluation, sorting / aggregation according to the information of the second subtask.

[0081] Among them, the information of the second subtask may include the execution order of each second subtask. Before sending the information of the second subtask to the accelerator, the CPU of the computing node may start the computing module corresponding to the second subtask in the accelerator according to the information of the second subtask. In one possible implementation, the CPU of the computing node may send an enable signal to the computing module of the accelerator used to execute the second subtask to start the computing module corresponding to the second subtask in the accelerator. In another possible implementation, each computing module of the accelerator may include a switch, and the CPU of the computing node may start the computing module corresponding to the second subtask by turning on the switch of the computing module corresponding to the second subtask. The specific implementation of the startup method of the computing module is not limited in the embodiment of the present application.

[0082] After startup, the first computing module that performs the second subtask can obtain the target data from the memory of the computing node and perform the corresponding second subtask, such as decryption. After the task of the first computing module that performs the second subtask is completed, the computing module sends the data processing result to the second computing module that performs the second subtask through the intra-chip interconnection technology, triggering the second computing module that performs the second subtask to perform the corresponding second subtask, such as decompression. After the task of the second computing module that performs the second subtask is completed, the computing module sends the data processing result to the third computing module that performs the second subtask through the intra-chip interconnection technology, triggering the third computing module that performs the second subtask to perform the corresponding second subtask, such as decoding, and so on, until the second subtask in the accelerator is completed.

[0083] After the acceleration process completes the second subtask, the accelerator can provide the data processing results to the memory of the computing node. The CPU can obtain the data processing results from the memory and feed them back to the user device. During this processing process, the accelerator can provide a pipelined acceleration processing method for the computing node. The CPU does not need to frequently interact with the memory of the computing node, which can reduce the CPU resource usage and greatly improve the computing power processing efficiency of the computing node. Method (2):

[0084] The accelerator can also have disk reading capability, such as Figure 5b As shown, the CPU receives the scheduling information from the management node, and obtains the information of the first subtask and the information of the second subtask by analyzing the scheduling information.

[0085] For the first subtask that needs to be executed by the computing node, the CPU may execute the first subtask according to information of the first subtask.

[0086] For the second subtask that needs to be executed by the accelerator, the CPU can send the information of the second subtask to the accelerator. The accelerator itself can have a memory (not shown in the figure). After receiving the information of the second subtask, the accelerator can store the information of the second subtask in the memory of the accelerator. The corresponding computing module of the accelerator can execute the second subtask according to the information of the second subtask. For example, the corresponding computing module of the accelerator can read the target data from the target storage medium into the memory of the accelerator, and sequentially execute pipeline processing processes including but not limited to decryption, decompression, decoding, filtering, evaluation, sorting / aggregation, etc. according to the information of the second subtask.

[0087] Among them, the information of the second subtask may include the execution order of each second subtask. Before sending the information of the second subtask to the accelerator, the CPU of the computing node may start the computing module corresponding to the second subtask in the accelerator according to the information of the second subtask. In one possible implementation, the CPU of the computing node may send an enable signal to the computing module of the accelerator used to execute the second subtask to start the computing module corresponding to the second subtask in the accelerator. In another possible implementation, each computing module of the accelerator may include a switch, and the CPU of the computing node may start the computing module corresponding to the second subtask by turning on the switch of the computing module corresponding to the second subtask. The specific implementation of the startup method of the computing module is not limited in the embodiment of the present application.

[0088] After startup, the first computing module that performs the second subtask can obtain the target data from the memory of the computing node and perform the corresponding second subtask, such as decryption. After the task of the first computing module that performs the second subtask is completed, the computing module sends the data processing result to the second computing module that performs the second subtask through the intra-chip interconnection technology, triggering the second computing module that performs the second subtask to perform the corresponding second subtask, such as decompression. After the task of the second computing module that performs the second subtask is completed, the computing module sends the data processing result to the third computing module that performs the second subtask through the intra-chip interconnection technology, triggering the third computing module that performs the second subtask to perform the corresponding second subtask, such as decoding, and so on, until the second subtask in the accelerator is completed.

[0089] After the acceleration process completes the second subtask, the accelerator can provide the data processing results to the memory of the computing node. The CPU can obtain the data processing results from the memory and feed them back to the user device. During this processing process, the accelerator can provide a pipelined acceleration processing method for the computing node. The CPU does not need to frequently interact with the memory of the computing node, which can reduce the occupation of CPU resources and greatly improve the computing power processing efficiency of the computing node.

[0090] It is worth noting that Figure 5a and Figure 5b The dotted box in the figure only indicates the type of data processing operation that may be involved in the second subtask, and does not constitute a limitation on the type of operators involved in a pipeline processing involved in the second subtask.

[0091] Understandably, Figure 3 The execution unit (executor) and the different processing flows implemented by it are only schematic illustrations of a pipelined processing process and are not any limitation. For example, the execution unit 1 may include using at least one computing module of the accelerator to perform scanning operations and filtering operations on the data obtained through the network. Or the execution unit 2 may include using at least one computing module of the accelerator to shuffle and sort the acquired data. Or, the execution unit 3 may include using at least one computing module of the accelerator to sort and aggregate the input data. Or, the execution unit 4 may include performing a nested loop join (NLJ) query on the input data access instruction (for example, represented as input 1 and input 2). The execution unit may provide the processing result or the final data obtained after the acceleration processing is completed to the memory of the computing node, and the CPU may obtain the processing result or the final data from the memory to complete the processing flow for the data access request.

[0092] 3. Compute node cache layer:

[0093] The computing node cache layer is a temporary storage of the computing node. The computing node can temporarily store hot data with a high access frequency in the cache layer to reduce the access frequency of the storage medium. In the embodiment of the present application, the computing node cache layer can be used as an example of the execution node introduced above. For computing tasks that need to be executed in the computing node cache layer, the management node can also schedule the second subtask in the computing task to the accelerator to realize the computing power acceleration processing of the cache layer.

[0094] When implementing, Figure 3 As shown, after receiving the scheduling information from the management node, the computing node cache layer obtains the information of the first subtask executed by the computing node cache layer and the information of the second subtask executed by the accelerator by analyzing the scheduling information. The computing node cache layer can execute the first subtask according to the information of the first subtask, and send the information of the second subtask to the accelerator. The accelerator can store the information of the second subtask in its own memory. The corresponding computing module of the accelerator can execute the second subtask according to the information of the second subtask. For example, the corresponding computing module of the accelerator can read the target data from the target storage medium (such as SSD) into the memory of the accelerator, and sequentially execute the pipeline processing flow including but not limited to scanning, filtering, and projection according to the information of the second subtask.

[0095] Among them, similar to the above description, the information of the second subtask may include the execution order of each second subtask. Before sending the information of the second subtask to the accelerator, the computing node cache layer may start the computing module corresponding to the second subtask in the accelerator according to the information of the second subtask. In one possible implementation, the computing node cache layer may send an enable signal to the computing module of the accelerator used to execute the second subtask to start the computing module corresponding to the second subtask in the accelerator. In another possible implementation, each computing module of the accelerator may include a switch, and the computing node cache layer may start the computing module corresponding to the second subtask by turning on the switch of the computing module corresponding to the second subtask. The specific implementation of the startup method of the computing module is not limited in the embodiment of the present application.

[0096] After startup, the first computing module that performs the second subtask can obtain target data from the target storage medium and perform the corresponding second subtask, such as scanning. After the task of the first computing module that performs the second subtask is completed, the computing module sends the data processing result to the second computing module that performs the second subtask through the intra-chip interconnection technology, triggering the second computing module that performs the second subtask to perform the corresponding second subtask, such as filtering. After the task of the second computing module that performs the second subtask is completed, the computing module sends the data processing result to the third computing module that performs the second subtask through the intra-chip interconnection technology, triggering the third computing module that performs the second subtask to perform the corresponding second subtask, such as projection, until the second subtask in the accelerator is completed.

[0097] After the acceleration process completes the second subtask, the accelerator can provide the data processing results to the computing node cache layer. The computing node cache layer can feed back the data processing results to the user device. During this processing process, the accelerator can provide a pipelined acceleration processing method for the computing node cache layer, which can reduce the occupation of cache layer resources and improve the computing power processing efficiency of the computing node cache layer.

[0098] It can be understood that in specific applications, the computing node cache layer can receive scheduling information from the management node through the processor of the computing node. For example, the management node sends scheduling information to the computing node, and the processor of the computing node sends the scheduling information to the computing node cache layer. It will not be repeated here.

[0099] 4. Storage Node:

[0100] The storage node can be an example of the execution node described above. Figure 3 As shown, the storage node may be a distributed storage node, which may provide but is not limited to: HDFS, OBS, Ceph distributed storage system, or S3. The storage node may communicate and interconnect with the accelerator, management node, or computing node through network interconnection technology.

[0101] The storage node may include a CPU / DPU, etc. The CPU / DPU, etc. may receive scheduling information from the management node, and obtain information about the first subtask and the second subtask by analyzing the scheduling information. For the first subtask that needs to be executed by the CPU / DPU, etc., the CPU / DPU may execute the first subtask based on the information of the first subtask. For the second subtask that needs to be executed by the accelerator, the CPU / DPU may send the information of the second subtask to the accelerator to complete the data parsing, filtering, aggregation and other operations required for the storage-side near data processing (Neighbor Discovery Protocol, NDP) calculation using at least one operator provided by the accelerator. In high-density storage scenarios, computing power unloading services can also be provided to filter out most of the invalid data through data filtering, scanning and pre-aggregation, which helps to solve the bottleneck of network IO.

[0102] Among them, similar to the above description, the information of the second subtask may include the execution order of each second subtask. Before sending the information of the second subtask to the accelerator, the storage node may start the computing module corresponding to the second subtask in the accelerator according to the information of the second subtask. In one possible implementation, the storage node may send an enable signal to the computing module of the accelerator used to execute the second subtask to start the computing module corresponding to the second subtask in the accelerator. In another possible implementation, each computing module of the accelerator may include a switch, and the storage node may start the computing module corresponding to the second subtask by turning on the switch of the computing module corresponding to the second subtask. The specific implementation of the startup method of the computing module is not limited in the embodiment of the present application.

[0103] After startup, the first computing module that executes the second subtask can obtain the target data from the target storage medium (such as SSD or SATA) and execute the corresponding second subtask, such as parsing. After the task of the first computing module that executes the second subtask is completed, the computing module sends the data processing result to the second computing module that executes the second subtask through the intra-chip interconnection technology, triggering the second computing module that executes the second subtask to execute the corresponding second subtask, such as filtering. After the task of the second computing module that executes the second subtask is completed, the computing module sends the data processing result to the third computing module that executes the second subtask through the intra-chip interconnection technology, triggering the third computing module that executes the second subtask to execute the corresponding second subtask, such as aggregation, until the second subtask in the accelerator is completed.

[0104] After the acceleration process completes the second subtask, the accelerator can provide the data processing results to the storage node. The CPU / DPU of the storage node can feed back the data processing results to the user device. During this processing process, the accelerator can provide a pipelined acceleration processing method for the storage node, which can reduce the occupancy of the storage node's resources and improve the computing power processing efficiency of the storage node.

[0105] It should be understood that the above combination Figure 3 The deployment architecture described is only an example of a storage-computing separation architecture and does not constitute a limitation on the architecture of the embodiments of the present application. In other embodiments, Figure 3 The computing nodes and storage nodes shown in the figure can be deployed as a storage-computing integrated architecture. For example, the computing nodes and storage nodes are deployed on the same server. The data processing scheme of the embodiment of the present application is also applicable to the storage-computing integrated architecture. The implementation details are similar to those in the embodiment of the present application. Figure 3 The storage and computing separation architecture introduced is the same. Please refer to the relevant introduction in the previous article and will not be repeated here.

[0106] based on Figure 1 and Figure 3 The architecture shown in the figure, the embodiment of the present application provides a data processing method, which can be implemented by the management node introduced above in collaboration with the execution node and the accelerator, and the execution node can be implemented as any one of the computing node, computing node cache layer, and storage node introduced above. Among them, the accelerator may include multiple computing modules, each computing module is used to execute a type of subtask, and the type of the subtask may include but is not limited to the computing power task corresponding to the basic operator described above or the computing power task corresponding to the advanced operator.

[0107] like Figure 6 As shown, the method may include the following steps:

[0108] S610: The management node generates scheduling information for multiple subtasks included in the computing task.

[0109] In the embodiment of the present application, the scheduling information may include information about the first subtask executed by the execution node and information about the second subtask executed by the accelerator.

[0110] Take the execution plan of the SQL statement as an example. Figure 7aAs shown, different symbols are used to represent different operators. An execution plan may include a single computing power acceleration processing pipeline composed of at least one operator. For example, the operator tasks involved in execution plan 1 are abstracted as pipeline ①, the operator tasks involved in execution plan 2 are abstracted as pipeline ②, and the operator tasks involved in execution plan 3 are abstracted as pipeline ③. The management node can generate scheduling information for any one of execution plan 1, execution plan 2, or execution plan 3 based on the resource information of different execution nodes and accelerators of the data processing system, so as to utilize the computing power of the computing module of the available accelerator to execute the operations involved in any one of the execution plan 1, execution plan 2, or execution plan 3.

[0111] Or, if Figure 7b As shown, different symbols are used to represent different operators, and the execution plan of the SQL statement can have a tree-like topology structure. At least one operator included in the execution plan can also be abstracted according to the tree-like topology structure to include several sub-pipelines, such as a pipeline topology structure. The management node can schedule available computing resources for multiple subtasks involved in the pipeline topology structure according to resource information of different execution nodes and accelerators of the data processing system, so as to utilize the computing power of the computing module of the available accelerator to achieve the purpose of computing power acceleration.

[0112] It is worth noting that the management node can also obtain the resource usage information of the at least one accelerator, and generate information about the second subtask executed by the accelerator based on the resource usage information of the at least one accelerator. Alternatively, for multiple computing modules of the accelerator, the management node can also obtain the resource usage information of the multiple computing modules, and generate information about the second subtask executed by the accelerator based on the resource usage information of the multiple computing modules of the accelerator. In the scheduling process shown in 7a and 7b, the capabilities supported by the computing modules of at least one accelerator included in the data processing system can be divided into at least one resource queue according to type, and each resource queue can provide the same type of computing power to execute the same type of tasks, such as Figure 8 shown.

[0113] When implementing S610, the management node can determine the target resource queue according to the type of different tasks, and according to the load of the target resource queue, provide the computing modules available in the target resource queue to the corresponding tasks for use, so as to implement a pipelined processing flow. That is, the management node can perform scheduling within the same accelerator or between different accelerators, which is not limited in the embodiments of the present application.

[0114] S620: The management node sends the information of the first subtask and the information of the second subtask to the execution node. Accordingly, the execution node may receive the information of the first subtask and the information of the second subtask from the management node.

[0115] S630: The execution node executes the first subtask according to the information of the first subtask. The first subtask may include but is not limited to the tasks of the basic operators or advanced operators described above. Figure 2-Figure 5b The relevant description will not be repeated here.

[0116] S640: The execution node may send the information of the second subtask to the accelerator. The dashed box represents the accelerator, which only indicates that the execution node is associated with the accelerator, and does not limit the product form or deployment method of the accelerator.

[0117] S650: The accelerator executes the second subtask according to the information of the second subtask. The second subtask may include but is not limited to the tasks of the basic operators or advanced operators described above. Figure 2-Figure 5b The relevant description will not be repeated here.

[0118] Understandably, Figure 6 It is only an example illustration of the steps involved in the embodiments of the present application and is not a limitation. In an optional implementation, the execution node may first execute the pre-operation processing flow involved in S640-S650, and then execute S630. For example, the data processing system supports a computing power acceleration processing flow that combines software and hardware. During specific implementation, when the management node implements S610, it can be combined with the optimizer to optimize the scheduling information. After implementing S620, the accelerator may first execute S640-S650, and perform the pre-operations involved in the task in sequence based on the available computing modules. S630 is then executed by the execution node, for example, continuing to process based on the pre-operation results. The processing results or final data obtained after the execution node completes the processing can be provided directly or indirectly to the user device to complete the processing flow for the computing task from the user device.

[0119] In the above method, a pipeline accelerator architecture can be built according to business needs. In this architecture, the computing task is abstracted into a pipeline processing flow by the management node, and the tasks implemented by basic operators or advanced operators such as sorting, aggregation, filtering, and aggregation are supported based on the operator granularity. At least one accelerator is implemented to maximize the reduction of data movement between the memory of the accelerator and the execution node in the data processing flow, improve the computing density, reduce the ping-pong access caused by data movement, and improve data processing efficiency. At the same time, the management node supports optimizing the scheduling information in combination with the optimizer, so that at least one accelerator can perform pre-processing, pre-aggregation, pre-sorting and other pre-operations involved in the computing task, and supports the software to continue to further process the process based on the pre-operation results, that is, the software and hardware combined processing process. The solution can also support flexible configuration of the pipeline processing flow based on business needs or computing power load, support linkage within the accelerator and between multiple accelerators, and support the reuse of multiple accelerators, which can reduce resource usage, improve the interactivity and scalability of the accelerator, and have a wider range of application scenarios.

[0120] Based on the same inventive concept as the method embodiment, the embodiment of the present application also provides a communication device for executing the method executed by the management node or the execution node in the above embodiment. The relevant features can be found in the above method embodiment and will not be repeated here.

[0121] For example Fig. 9 As shown, the communication device 900 can be applied to a management node, and the device may include: a generation unit 901, used to generate scheduling information for multiple subtasks included in a computing task, the scheduling information including information about a first subtask executed by the execution node and information about a second subtask executed by the accelerator; a transceiver unit 902, used to send information about the first subtask and information about the second subtask to the execution node. Accordingly, the execution node can execute the first subtask according to the information about the first subtask, and send the information about the second subtask to the accelerator. The accelerator can be used to execute the second subtask according to the information about the second subtask. For specific implementation methods, please refer to the method steps implemented by the management node, execution node or accelerator in the above method embodiment, which will not be repeated here.

[0122] It should be understood that the division of the units in the above device is only a division of logical functions, and in actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. In addition, the units in the device can be implemented in the form of a processor calling software; for example, the device includes a processor, the processor is connected to a memory, and instructions are stored in the memory. The processor calls the instructions stored in the memory to implement any of the above methods or realize the functions of the units of the device, wherein the processor is, for example, a general-purpose processor, such as a central processing unit (CPU) or a microprocessor, and the memory is a memory inside the device or a memory outside the device. Alternatively, the units in the device can be implemented in the form of hardware circuits, and the functions of some or all of the units can be realized by designing the hardware circuits, and the hardware circuits can be understood as one or more processors; for example, in one implementation, the hardware circuit is an application-specific integrated circuit (ASIC), and the functions of some or all of the above units are realized by designing the logical relationship of the components in the circuit; for another example, in another implementation, the hardware circuit can be realized by a programmable logic device (PLD), taking a field programmable gate array (FPGA) as an example, which can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured by a configuration file, so as to realize the functions of some or all of the above units. All units of the above devices can be realized in the form of a processor calling software, or in the form of a hardware circuit, or in part by a processor calling software, and the rest by a hardware circuit.

[0123] In the embodiment of the present application, the processor is a circuit with signal processing capability. In one implementation, the processor may be a circuit with instruction reading and running capability, such as a CPU, a microprocessor, a graphics processing unit (GPU) (which may be understood as a microprocessor), or a digital signal processor (DSP), etc.; in another implementation, the processor may implement certain functions through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit may be fixed or reconfigurable, such as a hardware circuit implemented by an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the hardware circuit configuration may be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. In addition, it may also be a hardware circuit designed for artificial intelligence, which may be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a data processing unit (DPU), etc.

[0124] It can be seen that each unit in the above device can be one or more processors (or processing circuits) configured to implement the above method, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0125] In addition, all or part of the units in the above device can be integrated together, or can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a system-on-a-chip (SOC). The SOC may include at least one processor for implementing any of the above methods or implementing the functions of each unit of the device. The type of the at least one processor may be different, for example, including a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, etc.

[0126] The present application also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the computer executes the above-mentioned related method steps to implement the method executed by the management node in the above-mentioned embodiment. Figure 6 The description of the relevant steps will not be repeated here.

[0127] The present application also provides a computer program product. When the computer program product is run on a computer, the computer executes the above-mentioned related steps to implement the method performed by the management node in the above-mentioned embodiment. Figure 6 The description of the relevant steps will not be repeated here.

[0128] In addition, an embodiment of the present application further provides a device, which may be a chip, a component or a module, and the device may include a connected processor and a memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor may execute the computer-executable instructions stored in the memory, so that the chip executes the method executed by the management node in the above-mentioned method embodiments, see Figure 6 The description of the relevant steps will not be repeated here.

[0129] Among them, the communication device, computer storage medium, computer program product or chip provided in the embodiments of the present application are all used to execute the methods corresponding to the management nodes provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above and will not be repeated here.

[0130] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0131] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0132] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0133] In addition, each functional unit (or module) in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0134] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0135] Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

[0136] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, data center, etc. that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

[0137] The various illustrative logic units and circuits described in the embodiments of the present application can be implemented or operated by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or the design of any combination of the above functions. The general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any traditional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration to implement.

[0138] The steps of the method or algorithm described in the embodiments of the present application can be directly embedded in the software unit executed by the hardware, the processor, or a combination of the two. The software unit can be stored in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM or other storage media of any form in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Alternatively, the storage medium can also be integrated into the processor. The processor and the storage medium can be arranged in an ASIC.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0140] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, a person skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data processing system, characterized in that: The system includes an execution node, an accelerator, and a management node; The management node is used to generate scheduling information for a plurality of subtasks included in the computing task, wherein the scheduling information includes information of a first subtask executed by the execution node and information of a second subtask executed by the accelerator; The management node is used to send information about the first subtask and information about the second subtask to the execution node; The execution node is used to execute the first subtask according to the information of the first subtask, and send the information of the second subtask to the accelerator; The accelerator is used to execute the second subtask according to the information of the second subtask.

2. The system according to claim 1, characterized in that The management node is further used to obtain resource information of the execution node and the accelerator, and the management node is used to generate the scheduling information for the multiple subtasks included in the computing task according to the resource information of the execution node and the accelerator.

3. The system according to claim 1, characterized in that The data processing system includes at least one accelerator, the management node is further used to obtain resource usage information of the at least one accelerator, and the management node is used to generate information of a second subtask executed by the accelerator according to the resource usage information of the at least one accelerator.

4. The system according to any one of claims 1 to 3, characterized in that: The accelerator supports multiple computing modules, each computing module is used to execute a type of subtask.

5. The system according to claim 4, characterized in that The management node is further used to obtain resource usage information of the multiple computing modules of the accelerator, and the management node is used to generate information of the second subtask executed by the accelerator according to the resource usage information of the multiple computing modules of the accelerator.

6. The system according to claim 4 or 5, characterized in that: Before sending the information of the second subtask to the accelerator, the execution node is further configured to start a computing module corresponding to the second subtask in the accelerator according to the information of the second subtask.

7. The system according to claim 6, characterized in that Each computing module in the accelerator includes a switch, and the execution node starts the computing module corresponding to the second subtask by turning on the switch of the computing module corresponding to the second subtask.

8. The system according to any one of claims 1 to 7, characterized in that: The execution node is further used to obtain resource information and / or resource usage information of the accelerator, and the execution node is used to send the resource information and / or resource usage information of the accelerator to the management node.

9. The system according to any one of claims 1 to 8, characterized in that: The execution node includes any of the following types: Compute nodes, compute node cache layer, and storage nodes.

10. A data processing method, characterized in that: Applied to a data processing system, the data processing system includes an execution node, an accelerator, and a management node, the method includes: The management node generates scheduling information for a plurality of subtasks included in the computing task, wherein the scheduling information includes information of a first subtask executed by the execution node and information of a second subtask executed by the accelerator; and sends the information of the first subtask and the information of the second subtask to the execution node; The execution node executes the first subtask according to the information of the first subtask, and sends the information of the second subtask to the accelerator; The accelerator executes the second subtask according to the information of the second subtask.

11. The method according to claim 10, characterized in that The method further comprises: The management node obtains resource information of the execution node and the accelerator, and generates the scheduling information for a plurality of subtasks included in the computing task according to the resource information of the execution node and the accelerator.

12. The method according to claim 10, characterized in that The data processing system includes at least one accelerator, and the method further includes: The management node obtains resource usage information of the at least one accelerator; The management node generates scheduling information for a plurality of subtasks included in the computing task, including: The management node generates information of a second subtask executed by the accelerator according to the resource usage information of the at least one accelerator.

13. The method according to any one of claims 10 to 12, characterized in that: The accelerator supports multiple computing modules, each computing module is used to execute a type of subtask.

14. The method according to claim 13, characterized in that The method further comprises: The management node obtains resource usage information of multiple computing modules of the accelerator; The management node generates scheduling information for a plurality of subtasks included in the computing task, including: The management node generates information of a second subtask executed by the accelerator according to resource usage information of multiple computing modules of the accelerator.

15. The method according to claim 13 or 14, characterized in that Before the execution node sends the information of the second subtask to the accelerator, the method further includes: The execution node starts a computing module corresponding to the second subtask in the accelerator according to the information of the second subtask.

16. The method according to claim 15, characterized in that Each computing module in the accelerator includes a switch, and the execution node starts the computing module corresponding to the second subtask in the accelerator, including: The computing module corresponding to the second subtask is started by turning on a switch of the computing module corresponding to the second subtask.

17. The method according to any one of claims 10 to 16, characterized in that The method further comprises: The execution node obtains resource information and / or resource usage information of the accelerator; The execution node sends the resource information and / or resource usage information of the accelerator to the management node.

18. The method according to any one of claims 10 to 17, characterized in that: The execution node includes any of the following types: Compute nodes, compute node cache layer, and storage nodes.

19. A computing device, characterized in that The computing device includes a processor and a memory; The processor is configured to execute instructions stored in the memory, so that the computing device executes the method executed by the execution node according to any one of claims 10 to 18.

20. A computer-readable storage medium, characterized in that: When the computer-readable storage medium is executed by a computing device, the computing device executes the method executed by the execution node according to any one of claims 10 to 18.

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