Cache device and operation method thereof, processor, equipment and medium

Abstract

The invention discloses a cache device, an operation method of the cache device, a processor, equipment and a medium. The cache device comprises a plurality of cache spaces, and the plurality of cache spaces comprise a first cache space which is distributed according to a page table item cache rule and is used for caching page table items; the operation method for the cache device comprises the following steps: receiving a first cache request; an operation object responding to the first cache request comprises the first page table item, and the first page table item is written into the first cache space according to the page table item cache rule. According to the operation method of the cache device, page table access missing of the processor due to cache flushing can be avoided, and the memory access performance of the processor is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a cache device, a method for operating the cache device, a processor, a device, and a medium. Background Art

[0002] With the development of technologies such as cloud computing and big data and the growing demand for memory capacity, various large-capacity memory technologies are also constantly developing. Since the processor needs to translate the virtual address into a physical address through the corresponding page table entry before accessing the memory resources to achieve memory access, therefore, quickly accessing the target page table entry is very important for quickly accessing memory resources. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an operating method for a cache device, wherein the cache device includes multiple cache spaces, and the multiple cache spaces include a first cache space allocated for caching page table entries according to a page table entry cache rule. The operating method of the cache device includes receiving a first cache request; in response to the first cache request, an operation object includes a first page table entry, and writing the first page table entry into the first cache space according to the page table entry cache rule.

[0004] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, the multiple cache spaces also include a second cache space for caching data items; the operating method of the cache device also includes: receiving a second cache request; in response to the second cache request, the operation object of which is the first processed data, writing the first processed data into the second cache space.

[0005] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, it also includes: receiving a second cache request; in response to the operation object of the second cache request being the first processed data and the first cache space including a free cache line, writing the first processed data into the first cache space.

[0006] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, the cache device is configured as a first-level cache, a second-level cache, or a third-level cache for a processor.

[0007] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, the cache device is a set-associative mapping, and the multiple cache spaces are respectively multiple cache groups or multiple cache ways of the cache device, and the first cache space includes part of the cache groups or part of the cache ways of the cache device.

[0008] For example, in the operating method of the cache device provided by at least some embodiments of the present disclosure, the page table entry cache rule is read from the configuration register.

[0009] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, the page table entry cache rules are written into the configuration register.

[0010] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, writing page table entry cache rules in the configuration register includes: writing page table entry cache rules in response to monitoring information of a processor including the cache device or monitoring information of the cache device itself; or, writing page table entry cache rules by a user of the processor including the cache device.

[0011] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, a user of a processor including the cache device writes page table entry cache rules, including: the user analyzes the microarchitecture state information of the processor through a hardware counter, and provides the analysis results for adjusting the page table entry cache rules.

[0012] For example, in the operating method of the cache device provided by at least some embodiments of the present disclosure, the page table entry cache rule is determined by the page table mask in the configuration register.

[0013] For example, in the operating method of the cache device provided in at least some embodiments of the present disclosure, the page table mask includes multiple bits, and the multiple bits correspond to multiple cache spaces respectively. When each of the multiple bits is a first value, it indicates that the corresponding cache space is allocated for caching page table entries, and when each of the multiple bits is a second value, it indicates that the corresponding cache space is allocated not for caching page table entries.

[0014] At least one embodiment of the present disclosure also provides a cache device, which includes multiple cache spaces and a cache controller. The cache controller is configured to determine a first cache space for caching page table entries among the multiple cache spaces according to a page table entry cache rule, and in response to a received first cache request, an operation object includes a first page table entry, and the first page table entry is written into the first cache space according to the page table entry cache rule.

[0015] At least one embodiment of the present disclosure further provides a processor, which includes the cache device provided by any embodiment of the present disclosure and a configuration register, wherein the configuration register is configured to store page table entry cache rules.

[0016] For example, in a processor provided in at least some embodiments of the present disclosure, the processor includes multiple hardware threads or multiple processor cores, and the page table entry cache rule includes setting multiple page table entry cache sub-rules for the multiple hardware threads or the multiple processor cores respectively.

[0017] For example, in the processor provided by at least some embodiments of the present disclosure, the page table entry cache rule sets the object page table entry cache sub-rule of the object hardware thread among the multiple hardware threads through multiple service type identifiers corresponding to the multiple hardware threads respectively.

[0018] For example, the processor provided in at least some embodiments of the present disclosure further includes a monitoring module, which is configured to dynamically monitor the page table cache miss rate or the data cache miss rate of the cache device and provide monitoring results for adjusting the page table entry cache rules.

[0019] At least some embodiments of the present disclosure further provide an electronic device, comprising the cache device provided by any embodiment of the present disclosure or the processor provided by any embodiment of the present disclosure.

[0020] At least some embodiments of the present disclosure also provide a non-temporary storage medium that non-temporarily stores computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processor, the operating method of the cache device provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0022] Figure 1 A flowchart of a processor reading data is shown;

[0023] Figure 2 A schematic diagram of an address translation process through a page table is shown;

[0024] Figure 3 A flowchart showing an operating method of a cache device provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 4 A schematic diagram showing a group-associative organization form and addressing mode of a cache device provided by at least one embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of a multi-level cache operation based on cache ways provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 6 A schematic diagram of an operation of a multi-level cache by cache group provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 7 A schematic diagram of an operation based on a service type identifier provided by at least one embodiment of the present disclosure is shown;

[0029] Figure 8 An operation flow chart of a cache device provided by at least one embodiment of the present disclosure is shown;

[0030] Fig. 9 A schematic diagram of writing a page table entry cache rule provided by at least one embodiment of the present disclosure is shown;

[0031] Fig.10 A schematic diagram of writing a page table entry cache rule provided by at least one embodiment of the present disclosure is shown;

[0032] Fig.11 A block diagram of a cache device provided by at least one embodiment of the present disclosure is shown;

[0033] Fig.12 A block diagram of a processor provided by at least one embodiment of the present disclosure is shown;

[0034] Fig.13 A schematic diagram showing the structure of an electronic device provided by at least one embodiment of the present disclosure; and

[0035] Fig.14 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0039] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0040] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0041] With the development of emerging industry technologies, the demand for memory capacity of various applications is increasing. To access large-capacity memory, modern computer systems (such as LINUX) use page tables to manage memory. For example, every time an application accesses a page, the processor will first look for the page table (Page Table Entry, PTE) after receiving the access request to translate the virtual address of the access request into the actual physical address in the memory.

[0042] Figure 1 FIG. 1 shows a flow chart of a processor reading data. Figure 1 As shown, the process of the processor reading data includes the following steps S01 to S07. It should be noted that the processor here can also be replaced by other processing devices or units with information processing capabilities. For example, for a multi-core processor, the processor here can also be replaced by one of the processor cores.

[0043] Step S01: The processor (or processor core) outputs the virtual address of the target data or instruction of the access request to the address translator 101 (e.g., address translation pipeline), and the address translator 101 translates the virtual address into a physical address. Then, the processor determines whether the target data or instruction of the access request is in the first level cache (e.g., L1 Cache). The access request can be a read request for data or instructions. For example, the address translator 101 stores a page table for address translation.

[0044] Step S02: If the target data or instruction of the access request exists in the first-level cache, the target data or instruction of the access request is taken out from the first-level cache, and the target data or instruction of the access request is sent to the processor through the following step S07.

[0045] Step S03: If the target data or instruction of the access request does not exist in the first-level cache, a storage item is requested from the miss address cache (MAB) 102, and the storage item is allocated to the access request.

[0046] Step S04: the miss address cache 102 requests the target data or instruction of the access request from the cache at the next level (eg, the second level cache, L2 Cache) based on the storage item.

[0047] Step S05: The next level cache obtains the target data or instruction of the access request, and returns the target data or instruction of the access request to the miss address cache.

[0048] like Figure 1 As shown, in the case where the target data or instruction of the access request is stored in the second-level cache, the second-level cache obtains the target data or instruction of the access request from the second-level cache. In the case where the target data or instruction of the access request is not stored in the second-level cache, the second-level cache can obtain the target data or instruction of the access request from the memory located at the next level of the second-level cache. For example, the memory located at the next level of the second-level cache can be a third-level cache (L3Cache), a fourth-level cache (e.g., the last level cache, Last Level Cache) or a memory (e.g., DRAM), etc.

[0049] Step S06: the miss address cache 102 writes the target data or instruction of the access request into the first level cache.

[0050] Step S07: The first-level cache provides the target data or instruction of the access request to the processor for further processing by the processor.

[0051] Since there are many types of data that need to be processed by the processor in the access request, however, the cache (such as the first-level or second-level cache mentioned above) may only save the data that the processor has recently accessed. Therefore, when the amount of data access is large in a short period of time, the data previously in the cache will be kicked out (flushed out) of the cache due to the size of the cache, causing some data originally cached in the cache processor to need to obtain data from the memory (such as DRAM memory), which reduces the access performance of the processor. Therefore, a cache allocation technology is proposed.

[0052] For example, the cache space of the first-level cache or the second-level cache may be divided. For example, the corresponding cache space may be divided on the first-level cache or the second-level cache for multiple data types that may be accessed by the access request. For example, the first cache space in the first-level cache stores data, and the second cache space in the first-level cache stores instructions. In this way, after the physical address of the access request is determined according to the address translator 101 (for example, after the above step S01), the first cache space or the second cache space on the first-level cache may be correspondingly selected based on whether the access request is to read data or read instructions (for example, the target data or instruction of the access request in the above step S02 exists in the first-level cache).

[0053] For example, when the processor includes multiple processing cores or multiple processing threads, the first-level cache or the second-level cache may also be divided into different cache spaces corresponding to different processing cores or different processing threads.

[0054] The above cache allocation technology can improve some data that does not need to be kicked out of the cache processor to a certain extent, and can avoid some data being replaced by a large number of short-term accesses to a certain extent. Figure 1 In the processor data reading process of the above steps S01-S07, the processor needs to first use the address translator 101 to translate the virtual address into a physical address through the page table, and then use the physical address to find the target data or instruction in the first-level cache or the second-level cache to achieve the purpose of accessing the target data.

[0055] Therefore, if the address translator 101 fails to hit the target during address translation, even if some data can be prevented from being replaced, the overall processing efficiency of the processor for access requests cannot be improved. In particular, when facing an application that requires a large memory capacity, the address translator 101 is limited by the storage space and cannot manage the large memory capacity required by the application well.

[0056] Aiming at the problem of address translation in the above page table, a multi-level page table index translation method is proposed, which supports a larger address space in a limited storage space by means of a multi-level page table.

[0057] For example, the page table (Page Table Entry, PTE) is multi-level, and each level of the page table can be regarded as a conversion from a "virtual address" to a "physical address", except that the "virtual address" here is a bit field subset of the virtual address to be converted. Except for the last level of the page table PTE, which directly points to the physical page, the "physical address" in other levels of page tables all points to the starting address of the corresponding next level of page table.

[0058] Figure 2 A schematic diagram of an address translation process through a page table, showing the address translation process of a four-level page table.

[0059] like Figure 2As shown, a virtual address is divided into several segments, for example, respectively represented as EXT, OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, OFFSET_lvl1, and OFFSET_pg. In this example, the high-order virtual address segment EXT is not used. The virtual address segments OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, and OFFSET_lvl1 respectively represent the offset values ​​of the four-level page table, that is, the virtual address segment OFFSET_lvl4 represents the offset value of the fourth-level page table, the virtual address segment OFFSET_lvl3 represents the offset value of the third-level page table, the virtual address segment OFFSET_lvl2 represents the offset value of the second-level page table, and the virtual address segment OFFSET_lvl1 represents the offset value of the first-level page table. The initial address of the highest-level page table (that is, the fourth-level page table) is stored in the architecture register REG_pt, and its content is set by the operating system and cannot be changed by the application. In the second-level page table, the third-level page table, and the fourth-level page table, the page table entry of each level of the page table stores the starting address of the next level of the page table. The first-level page table entry (Page Table Entry, PTE) stores the high bits of the physical address of the corresponding memory page, which is combined with the virtual address offset (OFFSET_pg) to obtain the physical address corresponding to the virtual address. Therefore, by obtaining the starting address of the next level of the page table step by step in this way, the first-level page table entry (PTE) can be obtained in the end, and the corresponding physical address can be further obtained, realizing the translation from virtual address to physical address.

[0060] Although using more page table levels in a limited space can support a larger memory address space, this will slow down the translation process from virtual addresses to physical addresses and reduce processor performance.

[0061] For example, the size of a conventional PTE is 8 bytes, and the conventional page size is 4KB (also called memory page). The ratio of the PTE size to the page size is 1:512. For a 32MB cache, it can store 4M (megabytes) of PET, and the corresponding data is up to 16GB. Assuming that the hotspot access memory of the application accounts for 20% of the total memory, once the memory required by the program is greater than 80GB (80GB*20%=16GB), the 4M page table data cannot manage all the memory.

[0062] Moreover, if the amount of data accessed by hot spots is too large, at least two misses will occur each time the application accesses memory, one is the page table access miss, and the other is the data cache miss, resulting in a second miss of the access request, which seriously degrades the processor's memory access performance.

[0063] In response to the above problems, at least one embodiment of the present disclosure provides an operating method for a cache device, wherein the cache device includes multiple cache spaces, and the multiple cache spaces include a first cache space allocated for caching page table entries according to page table entry cache rules. The operating method includes: receiving a first cache request; in response to the first cache request, an operation object includes a first page table entry, and the first page table entry is written into the first cache space according to the page table entry cache rules.

[0064] In the operating method of the cache device of the above-mentioned embodiment of the present disclosure, since the page table entries are written into the first cache space according to the page table entry cache rules, the page table entries are cached separately from other data types, so that the page table entries can have an independent cache space; and since an independent cache space is set up, protection is formed for the page table entries stored in the cache device, and even in the case of a large amount of data access, the page table entries will not be flushed out of the cache by the data, so that when the processor processes an access request, there will be no cache miss of the page table, which improves the efficiency of translating virtual addresses into physical addresses, thereby improving the memory access performance of the processor.

[0065] Various embodiments of the present disclosure will be described below with reference to specific examples.

[0066] Figure 3 A flowchart of an operating method of a cache device provided by at least one embodiment of the present disclosure is shown.

[0067] like Figure 3 As shown, in some embodiments of the present disclosure, the operating method of the cache device includes steps S30 and S31.

[0068] Step S30: receiving a first cache request.

[0069] Step S31: In response to the first cache request, the operation object includes a first page table entry, and the first page table entry is written into the first cache space according to the page table entry cache rule.

[0070] The above-mentioned cache device includes multiple cache spaces, and the multiple cache spaces include a first cache space allocated for caching page table entries according to the page table entry cache rule. The first cache space can be any cache space among the multiple cache spaces, and the multiple cache spaces are multiple equal or unequal cache spaces divided in the cache device. In the above description, "first cache request" refers to a cache request as a description object, for example, it can be a read request or a write request, etc.; "first page table entry" refers to a page table entry as a description object, and the operation object of its cache request corresponds to a read request or a write request, which can be an object to be read or an object to be written.

[0071] The cache device is composed of multiple cache groups (Sets), each cache group includes multiple cache lines (Cache Lines), and a cache line is a basic unit of cache. For example, the cache device is a set-associative cache. In a set-associative cache, a cache group (Set) can be divided into multiple cache ways (Ways), each way can independently store different data blocks, and multiple cache ways allow more flexibility to store data within the same cache group, thereby reducing cache conflicts and improving cache efficiency.

[0072] For example, the cache device may be a storage array composed of a random access memory (RAM). For example, the random access memory array includes a tag array and a data array, which are respectively used to store information such as tags and data information in the access address of the stored object (such as data or instructions). For example, the tag array and the data array may also be referred to as a data RAM array and a tag RAM array, respectively. For example, the random access memory may be a static random access memory (SRAM), and the data array may also be a data SRAM array.

[0073] In an embodiment of the present disclosure, the page table entry cache rule is a rule for selecting a first cache space for caching page table entries from a plurality of cache spaces.

[0074] For example, the page table entry cache rules can be set for different processor cores of the processor, or can be set for different threads of the processor. For example, different page table entry cache rules are set for different characteristics of applications running on different processor cores or different threads of the processor. For example, a separate page table entry cache rule can be set for each processor core or each thread, which can increase the flexibility of cache partitioning. For example, the first cache request can be determined according to the access request issued by the processor.

[0075] For example, the cache operation object requested by the first cache request is a page table entry, and the first page table entry may be any page table entry among all page table entries.

[0076] In some embodiments of the present disclosure, the cache device in the cache device operating method is configured as a first-level cache, a second-level cache, or a third-level cache for a processor.

[0077] The processor may include multiple processor cores, and the multiple processor cores have a shared cache and each has a dedicated cache. For example, the dedicated cache of each processor core may include a first-level cache (L1 Cache) or a second-level cache (L2Cache). For example, each processor core has a different first-level cache and a different second-level cache. For example, the shared cache of the multiple processor cores may include a third-level cache (L3Cache).

[0078] The first level cache (hereinafter also referred to as L1) is used to store the most frequently used data and instructions. The L1 capacity is usually small, for example, the L1 capacity is tens of KB, but the access speed is very fast. For example, L1 uses static RAM (SRAM).

[0079] The second level cache (hereinafter referred to as L2) is used to store more data and instructions to provide more backup when the L1 cache misses. The L2 capacity is usually larger than the L1, for example, the L2 capacity is between 256KB and several MB, and the L2 access speed is faster but slower than the L1 cache.

[0080] The third level cache (hereinafter referred to as L3) is used to enable multiple processor cores to share the same cache, which helps to reduce the data transmission latency between processor cores. The capacity of L3 cache is usually much larger than L1 and L2 cache, and the access speed of L3 is slower than L1 and L2.

[0081] For example, the first cache space may be divided into one or more of a first-level cache, a second-level cache, or a third-level cache.

[0082] For example, part of the capacity of the first-level cache, the second-level cache, or the third-level cache is used as the first cache space for caching page table entries.

[0083] For example, the size of a page table entry is 8 bytes, and the size of a page (also called a memory page) is 4 KB.

[0084] For example, if the capacity of the first cache space on L1 is 64KB, L1 can store 64KB / 8Bytes=8K (thousand) page table entries, and can cover a maximum memory size of 8K*4KB=32MB.

[0085] For example, if the capacity of the first cache space on L2 is 1MB, L2 can store 1MB / 8B=128K (thousand) page table entries, and can cover a maximum memory size of 128K*4KB=512MB.

[0086] For example, if the capacity of the first cache space on L3 is 32MB, L3 can store 32MB / 8B=4M (megabytes) of page table entries, and can cover a maximum of 4M*4KB=16GB of memory.

[0087] For example, the first cache space can be divided evenly on the first-level cache, the second-level cache or the third-level cache to implement page table coverage of memory spaces of different sizes, so that the page table can translate physical addresses of memory spaces of different sizes.

[0088] It should be noted that although the above embodiments are described using the first-level cache, the second-level cache and the third-level cache as examples, in some necessary cases, the cache device may further include a fourth-level cache or a fifth-level cache, etc. The fourth-level cache or the fifth-level cache may be set inside the processor or outside the processor. The present disclosure does not limit the number and setting location of the cache.

[0089] In some embodiments of the present disclosure, the cache device is a multi-level cache. For example, the cache device may include a first-level cache and a second-level cache or a first-level cache, a second-level cache, and a third-level cache.

[0090] In some embodiments of the present disclosure, the cache device in the cache device operation method is a set-associative mapping, for example, the multiple cache spaces are respectively multiple cache groups or multiple cache ways of the cache device, and the first cache space includes part of the cache groups or part of the cache ways of the cache device.

[0091] For example, at least one or more of the first level cache, the second level cache, and the third level cache are set associative maps.

[0092] Figure 4 A schematic diagram showing a group-associative organization form and addressing method of a cache device provided by at least one embodiment of the present disclosure is shown.

[0093] like Figure 4 As shown, the cache device can be organized into a cache group (Set). A column of cache lines constitutes a way (Way), multiple cache lines at the same position in multiple columns of cache lines constitute a group, and the cache device includes multiple cache groups. The location (Set, Way, Byte) of the accessed data or the accessed instruction in the cache device is obtained by reading the access address of the access request. Each access address may include:

[0094] (a) An index part (Index), which is used to select a cache set (Set) in the cache device. All cache lines in the same set are selected by the index.

[0095] (b) The tag part (Tag) is used to select a specific cache line in a cache set (Set). The tag of the physical address is compared with the tag of each cache line. If they match, it is a cache hit (Cache Hit), thereby selecting this cache line. Otherwise, it is a cache miss (Cache Miss).

[0096] (c) The offset part (Offset) is used to select the corresponding address in the cache line, which indicates that the access address is the first byte (Byte) in the cache line, and the corresponding data or instruction is read from the position of this byte.

[0097] For example, when accessing a target page table entry cached in a cache device, the cache group where the target page table entry is located can be determined by the index portion in the access address, and the cache line where the target page table entry is located can be determined by the tag portion in the cache group. For example, if there is a cache miss in the first-level cache, the second-level cache is searched; if there is a cache miss in the second-level cache, the third-level cache is searched, and so on.

[0098] Figure 5 A schematic diagram of a multi-level cache operation according to cache ways provided by at least one embodiment of the present disclosure is shown. Figure 6 A schematic diagram of multi-level cache operations by cache group provided by at least one embodiment of the present disclosure is shown.

[0099] For example, the page table entry cache rule includes a plurality of page table entry cache sub-rules respectively set for a plurality of hardware threads or a plurality of processor cores. For example, the processor includes a plurality of hardware threads, and the page table entry cache rule includes a plurality of page table entry cache sub-rules respectively corresponding to the plurality of hardware threads. For example, the processor includes a plurality of processor cores, and the page table entry cache rule includes a plurality of page table entry cache sub-rules respectively corresponding to the plurality of processor cores.

[0100] For example, the page table entry cache rules of the corresponding cache levels can be configured for the first-level cache, the second-level cache, and the third-level cache, respectively, wherein the first-level cache is configured with the first-level page table entry cache rules, the second-level cache is configured with the second-level page table entry cache rules, and the third-level cache is configured with the third-level page table entry cache rules. For example, the first-level page table entry cache rules, the second-level page table entry cache rules, and the third-level page table entry cache rules can respectively include multiple page table entry cache sub-rules set according to multiple hardware threads or multiple processor cores.

[0101] like Figure 5 As shown, processor core 10 and processor core 11 are included. For example, corresponding page table entry cache sub-rules can be set for processor core 10 and processor core 11 in the first-level page table entry cache rule, the second-level page table entry cache rule, and the third-level page table entry cache rule, respectively.

[0102] For example, processor core 10 is a multi-threaded processor core, for example, multiple hardware threads include thread 0 and thread 1; processor core 11 is a multi-threaded processor core, including thread 2 and thread 3. Thread 0, thread 1, thread 2, and thread 3 may be threads provided according to the Simultaneous Multi-Threading (SMT) technology, that is, hardware threads (different from software threads in an operating system running on the processor). For example, in the SMT mode, multiple threads of the same type among thread 0, thread 1, thread 2, and thread 3 are allowed to share resources (such as cache, execution unit, etc.) within the corresponding processor core, so that multiple threads of the same type can be executed in parallel, thereby improving the efficiency and performance of the processor.

[0103] For example, the first-level page table item cache rule may include multiple first-level page table item cache sub-rules, the second-level page table item cache rule may include multiple second-level page table item cache sub-rules, and the third-level page table item cache rule may include multiple third-level page table item cache sub-rules. For example, for different hardware threads of the processor, each hardware thread may have its own page table item cache rule corresponding to the corresponding cache level. For example, in the first-level page table item cache rule, the second-level page table item cache rule, and the third-level page table item cache rule, thread 1, thread 2, thread 3, and thread 4 respectively have their own page table item cache sub-rules in the page table item cache rule of the corresponding cache level.

[0104] like Figure 5 As shown, taking thread 0 as an example, a first-level page table entry cache sub-rule 4001 is configured in the first-level cache L1; a second-level page table entry cache sub-rule 4002 is configured in the second-level cache L2; and a third-level page table entry cache sub-rule 4003 is configured in the third-level cache L3.

[0105] For each level of cache in the multi-level cache, the page table entry cache rule can determine the available cache ways in each level of cache in the multi-level cache according to the cache ways. For example, according to the division of the cache ways of each level of cache, the page table entry cache rule of each level is set accordingly.

[0106] For example, the first-level cache 3001 is divided into 8 cache ways way0 to way7, and the first-level page table entry cache sub-rule 4001 includes 8 cache way selection rules corresponding to each cache way of the first-level cache 3001, which are used to determine the available status of way0 to way7 respectively; the second-level cache 3002 is divided into 16 cache ways way0 to way15, and the second-level page table entry cache sub-rule 4002 is set to 16 cache ways way0 to way15, and the second-level page table entry cache sub-rule 4002 includes 8 cache way selection rules corresponding to each cache way of the first-level cache 3001, which are used to determine the available status of way0 to way7 respectively; The 16 cache way selection rules corresponding to each cache way of cache 3002 are used to respectively determine the available status of way0~way15; the third-level cache 3003 is divided into 16 cache ways way0~way15, and the third-level page table entry cache sub-rule 4003 is set to 16 cache ways way0~way15. The third-level page table entry cache sub-rule 4003 includes 16 cache way selection rules corresponding to each cache way of the third-level cache 3003, which are used to respectively determine the available status of way0~way15.

[0107] For example, for thread 0, the first-level page table entry cache sub-rule 4001 determines that way0~way2 of the first-level cache 3001 are available cache ways; the second-level page table entry cache sub-rule 4002 determines that way0~way4 of the second-level cache 3002 are available cache ways; and the third-level page table entry cache sub-rule 4003 determines that way0~way7 of the third-level cache 3003 are available cache ways.

[0108] like Figure 6 As shown, for different threads of the processor, the page table entry cache rule can determine the available cache groups in each level of the multi-level cache according to the cache group. For example, according to the division of the cache groups of each level of cache, the page table entry cache rule of each level is set accordingly. For example, the page table entry cache rule can also be customized to correspond to the available states of different cache groups. For example, the first-level cache 3001 is divided into 4 cache groups set0 to set3, and the first 4 bits in the first-level page table entry cache sub-rule 4001 are used to respectively determine the available states of set0 to set3; the second-level cache 3002 is divided into 4 cache groups set0 to set3, and the first 4 bits in the second-level page table entry cache sub-rule 4002 are used to respectively determine the available states of set0 to set3; the third-level cache 3003 is divided into n+1 cache groups set0 to setn, where n is a positive integer, and the first n+1 bits in the third-level page table entry cache sub-rule 4003 are used to respectively determine the available states of set0 to set3.

[0109] It should be noted that each cache set may include multiple cache ways. When a cache set is determined to be an available cache set, it indicates that all cache ways included in the cache set are available cache ways.

[0110] For example, for thread 0, the first-level page table entry cache sub-rule 4001 determines that set0~set1 of the first-level cache 3001 is an available cache group; the second-level page table entry cache sub-rule 4002 determines that set0 of the second-level cache 3002 is an available cache group; the third-level page table entry cache sub-rule 4003 determines that set0 of the third-level cache 3003 is an available cache group.

[0111] It should be noted that although the above Figure 5 and Figure 6 The specific number of cache ways and cache groups is used as an example for explanation, but it does not mean that the number of cache ways and cache groups of each level of cache in the cache device is limited. In addition, although the above description is only based on thread 0, threads 1, 2, and 3 also have corresponding page table entry cache sub-rules in the first-level page table entry cache sub-rule, the second-level page table entry cache sub-rule, and the third-level page table entry cache sub-rule, respectively, and the available state of the cache way or cache group can be determined in the same way as thread 0.

[0112] For example, the operation object in response to the first cache request includes a first page table entry. For example, taking the operation object as one of the cache lines that includes the page table entry, when the cache device needs to write a new cache line that includes the page table entry, it can determine the cache way or cache group into which the page table entry can be written by checking the page table entry cache rules corresponding to the current cache device, and then determine the cache way or cache group in an available state from these cache ways or cache groups, and then further determine the old cache line that can be replaced from the available cache ways or cache groups, and then replace the old cache line with the new cache line that includes the page table entry, so that the new cache line that includes the page table entry can be inserted into the cache way or cache group in an available state that was last selected above.

[0113] In some embodiments of the present disclosure, in the operation method of the cache device, the page table entry cache rule is determined by the page table mask (Page Table Mask) in the configuration register.

[0114] In some embodiments of the present disclosure, in the operating method of the cache device, the page table mask includes multiple bits, and the multiple bits correspond to multiple cache spaces respectively. When each of the multiple bits is a first value, it indicates that the corresponding cache space is allocated for caching page table entries, and when each of the multiple bits is a second value, it indicates that the corresponding cache space is allocated not for caching page table entries.

[0115] For example, in Figure 5 and Figure 6 For example, the gray part may represent that the corresponding bit of the page table mask is the first value, and the white part may represent that the corresponding bit of the page table mask is the second value. For example, the first value may be set to 1, and the second value may be set to 0.

[0116] It should be noted that the specific setting values ​​of the first value and the second value can be numbers, symbols or letters. The embodiments of the present disclosure do not limit the specific setting values ​​of the first value and the second value, as long as they can distinguish and determine the available status cache way or cache group that can be used to cache page table entries.

[0117] Figure 7 A schematic diagram of an operation of a page table entry cache line based on a service type identifier provided by at least one embodiment of the present disclosure is shown;

[0118] like Figure 7 As shown, different hardware threads can determine corresponding page table entry cache rules based on corresponding service type markers. For example, multiple service type markers (Classes of Service) include CLOS 0, CLOS1~CLOS n, and n is a positive integer. For example, the page table entry cache rules corresponding to each service type marker are different. For example, when the cache device is a multi-level cache, a service type marker can include page table entry cache rules for each level of cache in the multi-level cache. For example, for thread 0, the page table entry cache sub-rules of thread 0 in the corresponding caches at each level can be determined based on the configured service type marker CLOS 0. For example, the service type marker CLOS 0 corresponds to the first-level page table entry cache sub-rule 4001 of the first-level cache L1, the second-level page table entry cache sub-rule 4002 of the second-level cache L2, and the third-level page table entry cache sub-rule 4003 of the third-level cache L3.

[0119] For example, each CLOS may include at least one mask register (MASK register for short) for controlling cache allocation according to a policy.

[0120] It should be noted that, although the above description is only based on thread 0 as an example, thread 1, thread 2, and thread 3 can also determine the page table entry cache sub-rules of their respective threads in the corresponding cache levels based on the configured service type identifier. For example, thread 0, thread 1, thread 2, and thread 3 can be configured with different service type identifiers, for example, at least two threads among thread 0, thread 1, thread 2, and thread 3 can have the same service type identifier.

[0121] For example, if thread 1, thread 2, and thread 3 are not configured with a service type identifier, the first cache space of the cache page table entry is selected according to the default configuration. For example, under the default configuration, any cache space in the plurality of cache spaces may be selected as the first cache space.

[0122] In some embodiments of the present disclosure, the operating method of the cache device further includes a second cache space for caching data items in the multiple cache spaces, and the operating method of the cache device further includes steps S40 and S41.

[0123] Step S40: receiving a second cache request.

[0124] Step S41: in response to the second cache request, the operation object of which is the first processed data, the first processed data is written into the second cache space.

[0125] For example, the second cache request may be determined based on an access request issued by a processor. For example, the operation object of the second cache request is data, and the first processing data may be any processing data among all processing data. In the above description, "the second cache request" refers to a cache request as a description object other than the "first cache request", for example, it may be a read request or a write request, and "the first processing data" refers to the processing data as a description object, and the operation object of the cache request corresponds to a read request or a write request, which may be an object to be read or an object to be written.

[0126] For example, after receiving an access request, responding to the access request includes both accessing the page table entry and accessing the processed data, and the page table entry and the processed data can be cached separately. For example, a first cache request is initiated to the cache device for the page table entry, and a second cache request is initiated to the cache device for the processed data. For example, the first cache request and the second cache request can be responded to by the cache device at the same time, or they can be responded to by the cache device separately.

[0127] It should be noted that the second cache space can be determined in any manner. For example, the second cache space can be configured as any cache space in the cache device. For example, the second cache space can also overlap with part of the cache space of the first cache space. For example, different processor cores or different threads can be configured with corresponding cache ways or cache groups for caching processing data as the second cache space. For example, different processor cores or different threads are configured with processing data cache rules, and the second cache space of the corresponding processor core or the corresponding thread can be determined by the processing data cache rules. For example, the processing data cache rules can be configured in the same manner as the above-mentioned page table entry cache rules, and the present disclosure will not be repeated here.

[0128] When the operation object is processing data, the processing data is written into the second cache space according to the second cache request, so that the caching of the processing data and the caching of the page table entries are processed separately in the cache device, thereby isolating the cache operation.

[0129] For example, the second cache space may be any cache space except the first cache space.

[0130] By storing the processing data in a cache space different from the page table entries, the page table entries and the processing data are cache isolated, and there will be no cache conflict between the page table entries and the processing data, which will cause the page table entries in the cache to be flushed when an application that occupies a large amount of memory accesses a large amount of processing data. As a result, as many page table entries as possible are saved in the cache device, thereby speeding up the process of the processor performing virtual address translation, reducing the occurrence of secondary cache misses (one page table entry miss and one processing data miss) when the processor is processing, and improving the processor's memory access performance.

[0131] In some embodiments of the present disclosure, the operating method of the cache device also includes steps S50 and S51.

[0132] Step S50: receiving a second cache request.

[0133] Step S51: in response to the operation object of the second cache request being the first processed data and the first cache space including a free cache line, writing the first processed data into the first cache space.

[0134] For example, when the first cache space of the cache page table entry includes a free cache line, the first processed data may be written into the free cache line in the first cache space, so that the cache space of the cache device can be fully utilized.

[0135] In some embodiments of the present disclosure, the operating method of the cache device further includes step S32.

[0136] Step S32: Read the page table entry cache rule from the configuration register.

[0137] The page table entry cache rule can be stored in a configuration register, and the page table entry cache rule can be read from the configuration register. For example, a page table mask representing the page table entry cache rule is stored in the configuration register. For example, the number of bits of the configuration register can be selected according to the number of cache ways or cache groups divided by the cache device, for example, for a cache device with 8 cache ways, an 8-bit register is selected; for example, for a cache device with 16 cache ways, a 16-bit register is selected.

[0138] Figure 8 An operation flow chart of a cache device provided by at least one embodiment of the present disclosure is shown.

[0139] like Figure 8As shown, an example of operating a cache device according to cache ways is given, which can determine whether the operation object of the new cache line written by the cache request includes a page table entry. If so, an available cache way can be selected according to the page table mask, and the old cache line that can be replaced can be found from the cache way; if not, it means that the page table entry is not included, which may be for processing data, and the replaceable cache line can be selected from all cache ways.

[0140] Afterwards, the new cache line replaces the old cache line, thereby completing the operation on the cache device according to the cache request.

[0141] In some embodiments of the present disclosure, the operating method of the cache device further includes step S33.

[0142] Step S33: writing the page table entry cache rules into the configuration register.

[0143] For example, a fixed page table entry cache rule may be pre-written into the configuration register when the configuration is performed, or the page table entry cache rule may be dynamically updated according to the situation of the cache device.

[0144] In some embodiments of the present disclosure, step S33 in the operating method of the cache device also includes step S330 or step S331.

[0145] Step S330: writing a page table entry cache rule in response to monitoring information of a processor including the cache device or monitoring information of the cache device itself.

[0146] For example, a monitoring module can be set inside the processor, which can monitor at least one processor core or at least one thread in the processor to obtain monitoring information related to cache hits and misses in the cache device, thereby determining or adjusting the page table entry cache rules to write the page table entry cache rules.

[0147] Alternatively, the monitoring module can monitor the cache device itself. For example, the monitoring module can dynamically monitor indicators such as the page table cache miss rate and / or the data cache miss rate in the cache device, analyze the monitoring information, and write the determined or adjusted page table entry cache rules.

[0148] The page table cache miss rate reflects the cache miss situation of the page table entry in the page table in the cache device, and the data cache miss rate reflects the cache miss situation of the processed data in the cache device.

[0149] For example, the page table entry cache rule may be written into the configuration register in the form of a page table mask. For example, the page table entry cache rule may be written by adjusting a digital bit in the configuration register according to monitoring information.

[0150] Fig. 9A schematic diagram of writing page table entry cache rules provided by at least one embodiment of the present disclosure is shown.

[0151] For example, a monitoring module 5001 is provided in the processor core 10. The monitoring module 5001 obtains monitoring information by monitoring the processor core 10 or the cache device (for example, the first-level cache 3001, the second-level cache 3002, and the third-level cache 3003), and writes page table entry cache rules, such as a page table mask, based on the monitoring information.

[0152] For example, if the page table entry cache miss rate of access from thread 0 in the cache device is high, the size of the first cache space of thread 0 in the cache device may be adjusted.

[0153] For example, if the application has a large amount of hot data, and the page table cache miss rate and data cache miss rate from each thread are both high (i.e., secondary cache misses occur frequently in the cache device), then the first cache space used by each thread to cache page table entries can be adjusted to all cache spaces to ensure that when the processor processes an access request, it can hit the cache at least once (i.e., hit the page table entry).

[0154] It should be noted that the above-mentioned method of adjusting the page table entry cache rules through the hardware monitoring module is only an example, and the present disclosure does not limit the method of adjusting the page table entry cache rules.

[0155] Step S331: A page table entry cache rule is written by a user for a processor including a cache device.

[0156] For example, a user may adjust the page table entry cache rule by software. For example, the "user" may be a thread or process running in a processor.

[0157] In some embodiments of the present disclosure, step S331 in the operating method of the cache device also includes step S3310.

[0158] Step S3310: The user analyzes the micro-architecture state information of the processor through a hardware counter, and provides the analysis result for adjusting the page table entry cache rule.

[0159] Fig.10 A schematic diagram of writing page table entry cache rules provided by at least one embodiment of the present disclosure is shown.

[0160] like Fig.10 As shown, the microarchitecture state information of the processor can be analyzed through the hardware counter, so that the user can determine or adjust the page table entry cache rules through software, thereby writing the page table entry cache rules.

[0161] For example, a hardware counter (Performance Monitoring Counters, PMC) is a programmable register on the processor that is used to monitor and count specific hardware events (such as microarchitecture status information). The hardware counter can pass the monitored and counted specific hardware events to the software (such as a monitoring client) so that the user can determine or adjust the page table entry cache rules and write the page table entry cache rules through software.

[0162] For example, the micro-architecture state information of the processor may include the path of the instruction pipeline, the number of instruction cycles, the instruction scheduling status, the number of instructions executed or the number of cache misses, etc. For example, the user can configure through software which micro-architecture state information the hardware counter needs to analyze.

[0163] It should be noted that the embodiments of the present disclosure do not limit which microarchitecture state information the hardware counter monitors and analyzes. The analysis of the microarchitecture state information by the hardware counter may include counting the total number, counting the state over a period of time, or calculating the proportion of a certain situation, etc. The present disclosure does not limit the analysis method of the hardware counter.

[0164] At least one embodiment of the present disclosure also provides a cache device, which includes multiple cache spaces and a cache controller. The cache controller is configured to determine a first cache space for caching page table entries among the multiple cache spaces according to a page table entry cache rule, and in response to a received first cache request, an operation object includes a first page table entry, and the first page table entry is written into the first cache space according to the page table entry cache rule.

[0165] Fig.11 A block diagram of a cache device provided by at least one embodiment of the present disclosure is shown.

[0166] The cache device 300 includes a plurality of cache spaces and a cache controller 310 . For example, the plurality of cache spaces may include cache spaces 1 to n, where n is a positive integer.

[0167] For example, the cache controller 310 is configured to determine a first cache space for caching page table entries among multiple cache spaces according to a page table entry cache rule, and in response to an operation object of a received first cache request including a first page table entry, write the first page table entry into the first cache space according to the page table entry cache rule.

[0168] For example, the cache controller 310 is further configured to determine a second cache space for caching processed data among the multiple cache spaces, and in response to the operation object of the second cache request being the first processed data, write the first processed data into the second cache space.

[0169] For example, the cache controller 310 is further configured to receive a second cache request; in response to the second cache request operating on the first processed data and the first cache space including a free cache line, write the first processed data into the first cache space.

[0170] In some embodiments of the present disclosure, the cache device is configured as a first level cache, a second level cache, or a third level cache for a processor.

[0171] In some embodiments of the present disclosure, the cache device is a set-associative mapping, the multiple cache spaces are multiple cache groups or multiple cache ways of the cache device, and the first cache space includes part of the cache groups or part of the cache ways of the cache device.

[0172] For example, the cache controller 310 is further configured to read the page table entry cache rule from the configuration register. For example, the cache controller 310 is further configured to write the page table entry cache rule into the configuration register.

[0173] The cache controller 310 is also configured to write the page table entry cache rules in response to monitoring information for the processor including the cache device or monitoring information for the cache device itself; or, the page table entry cache rules are written by a user of the processor including the cache device.

[0174] The cache controller 310 is also configured to analyze the micro-architecture state information of the processor through the hardware counters, and provide the analysis results for adjusting the page table entry cache rules.

[0175] In some embodiments of the present disclosure, the page table entry caching rules are determined by a page table mask in a configuration register.

[0176] In some embodiments of the present disclosure, the page table mask includes multiple bits, and the multiple bits correspond to multiple cache spaces respectively. When each of the multiple bits is a first value, it indicates that the corresponding cache space is allocated for caching page table entries. When each of the multiple bits is a second value, it indicates that the corresponding cache space is allocated not for caching page table entries.

[0177] The technical effect of the cache device of the above embodiment of the present disclosure is the same as the technical effect of the operating method of the above cache device, and thus will not be described in detail.

[0178] At least one embodiment of the present disclosure further provides a processor, which includes the cache device and a configuration register provided by any embodiment of the present disclosure, and the configuration register is configured to store page table entry cache rules.

[0179] Fig.12 A block diagram of a processor provided by at least one embodiment of the present disclosure is shown.

[0180] The processor 100 includes a cache device 300 and a configuration register 400 .

[0181] Configuration register 400 is configured to store page table entry cache rules.

[0182] In some embodiments of the present disclosure, the processor includes multiple hardware threads or multiple processor cores, and the page table entry cache rule includes setting multiple page table entry cache sub-rules for the multiple hardware threads or the multiple processor cores respectively.

[0183] In some embodiments of the present disclosure, the page table entry cache rule sets an object page table entry cache sub-rule of an object hardware thread among the multiple hardware threads through multiple service type identifiers corresponding to the multiple hardware threads respectively.

[0184] In some embodiments of the present disclosure, the processor 100 further includes a monitoring module 5001, which is configured to dynamically monitor a page table cache miss rate or a data cache miss rate of the cache device 300, and provide monitoring results for adjusting page table entry cache rules.

[0185] The technical effect of the processor in the above embodiment of the present disclosure is the same as the technical effect of the above cache device, so it will not be repeated.

[0186] At least one embodiment of the present disclosure further provides an electronic device, wherein the electronic device includes the cache device described in at least one of the above embodiments or the processor described in at least one of the above embodiments.

[0187] Fig.13 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0188] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.13 The electronic device 1000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0189] For example, refer to Fig.13In some examples, the electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 into a random access memory (RAM) 1003. For example, the processing device 1001 can be used as a processor in an embodiment of the present disclosure. In the RAM 1003, various programs and data required for the operation of the computer system are also stored. The processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other via an Internet 1004. An input / output (I / O) interface 1005 is also connected to the Internet 1004.

[0190] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. Removable media 1011, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1010 as needed, so that the computer program read therefrom can be installed into the storage device 1008 as needed. Although Fig.13 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0191] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0192] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be a combination of operating devices and hardware of any cache device, and the embodiments of the present disclosure are not limited to this.

[0193] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer executable instructions. For example, when the computer executable instructions are executed by a processor, the operating method of the cache device provided by at least one embodiment of the present disclosure is implemented.

[0194] Fig.14 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Fig.14 As shown, the non-transitory storage medium 900 can non-transitorily store computer executable instructions 910, and the computer executable instructions 910, when executed by a computer, implement the operating method of the cache device provided by any embodiment of the present disclosure.

[0195] There are a few points to note about this disclosure:

[0196] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0197] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0198] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An operating method of a cache device, the cache device comprising a plurality of cache spaces, the plurality of cache spaces comprising a first cache space allocated for caching page table entries according to a page table entry cache rule, the operating method comprising: receiving a first cache request; In response to the first cache request, the operation object includes a first page table entry, and the first page table entry is written into the first cache space according to the page table entry cache rule.

2. The operating method according to claim 1, wherein: The plurality of cache spaces also include a second cache space for caching data items; The operation method also includes: receiving a second cache request; In response to the operation object of the second cache request being the first processed data, the first processed data is written into the second cache space.

3. The operating method according to claim 1, further comprising: receiving a second cache request; In response to the operation object of the second cache request being the first processed data and the first cache space including a free cache line, the first processed data is written into the first cache space.

4. The operating method according to claim 1, wherein: The cache device is configured as a first level cache, a second level cache or a third level cache for a processor.

5. The operating method according to claim 1, wherein: The cache device is a set associative mapping, The plurality of cache spaces are respectively a plurality of cache groups or a plurality of cache ways of the cache device, and the first cache space includes a portion of cache groups or a portion of cache ways of the cache device.

6. The operating method according to any one of claims 1 to 5, further comprising: The page table entry cache rule is read from a configuration register.

7. The operating method according to claim 6, further comprising: The page table entry cache rule is written into the configuration register.

8. The operating method according to claim 7, wherein: Writing the page table entry cache rule into the configuration register includes: writing the page table entry cache rule in response to monitoring information of a processor including the cache device or monitoring information of the cache device itself; or, The page table entry caching rules are written by a user of a processor including the caching device.

9. The operating method according to claim 8, wherein: The step of writing the page table entry cache rule by a user of a processor including the cache device comprises: The user analyzes the micro-architecture state information of the processor through a hardware counter, and provides an analysis result for adjusting the page table entry cache rule.

10. The operating method according to claim 7, wherein: The page table entry caching rule is determined by the page table mask in the configuration register.

11. The operating method according to claim 10, wherein: The page table mask includes multiple bits, each of which corresponds to the multiple cache spaces. When each of the multiple bits is a first value, it indicates that the corresponding cache space is allocated for caching page table entries. When each of the multiple bits is a second value, it indicates that the corresponding cache space is allocated not for caching page table entries.

12. A cache device, comprising: Multiple cache spaces; A cache controller is configured to determine a first cache space for caching page table entries among the multiple cache spaces according to a page table entry cache rule, and in response to a first cache request received, wherein the operation object includes a first page table entry, write the first page table entry into the first cache space according to the page table entry cache rule.

13. A processor, comprising: The cache device according to claim 12; A configuration register is configured to store the page table entry cache rule.

14. The processor of claim 13, wherein: The processor includes multiple hardware threads or multiple processor cores, and the page table entry cache rule includes setting multiple page table entry cache sub-rules for the multiple hardware threads or the multiple processor cores respectively.

15. The processor of claim 14, wherein: The page table entry cache rule sets a target page table entry cache sub-rule of a target hardware thread among the multiple hardware threads through the multiple service type identifiers respectively corresponding to the multiple hardware threads.

16. The processor of claim 15, further comprising: The monitoring module is configured to dynamically monitor the page table cache miss rate or the data cache miss rate of the cache device and provide monitoring results for adjusting the page table entry cache rules.

17. An electronic device comprising the cache device according to claim 12 or comprising the processor according to any one of claims 13-16.

18. A non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein: When the computer executable instructions are executed by at least one processor, the operating method of the cache device according to any one of claims 1-11 is implemented.

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