Satellite-borne heterogeneous computing system

Abstract

The satellite-borne heterogeneous computing system comprises a CPU (central processing unit) module, an FPGA (field programmable gate array) module and an NPU (network processing unit) module, the CPU module is used for receiving instructions and telemetering polling of a satellite service computer, reading load scientific data received by the FPGA module, providing installation and operation environments for various types of universal application programs, and scheduling and controlling the NPU module; the FPGA module is used for providing external interface expansion, receiving load scientific data and sending the load scientific data to the CPU module, and is also used for providing a logic control function comprising SPI FLASH triple modular redundancy logic and barking reset; and the NPU module is used for performing high-performance calculation and providing a high-computing-power environment for the system. The system has high flexibility, reliability and universality, and can operate various computing software and neural network algorithms; the power consumption is low, and strict requirements of a satellite platform on power consumption can be met. And a plurality of systems are interconnected to form a distributed computing system, so that the performance is extremely high.

Description

Technical Field

[0001] The present invention belongs to the field of space integrated electronic systems and satellite-borne high-performance computing technology, and in particular relates to a satellite-borne heterogeneous computing system. Background Art

[0002] In traditional spacecraft, due to the lack of high-performance computing platforms that can survive the harsh space environment and meet the requirements of low size, weight, power consumption and cost, it is not feasible to perform a lot of on-orbit processing. Most of the data generated by spacecraft sensors is usually transmitted to ground stations for processing. However, on the one hand, the data transmission rate between the satellite and the ground cannot keep up with the rate at which increasingly complex sensors generate data, and on the other hand, various space missions have many and high requirements for on-orbit autonomy. By improving on-orbit processing capabilities, the amount of data that must be transmitted can be reduced and more autonomous spacecraft operations can be achieved.

[0003] At present, satellite data processing systems usually use highly reliable CPUs, DSPs or FPGAs for on-orbit data processing. Although they have good processing effects on specific tasks, the overall system performance is not high, the versatility and scalability are poor, the power consumption is high, the interconnection function is weak, and the artificial neural network algorithm cannot be deployed quickly and efficiently. There is an urgent need to develop a satellite-borne computing system. Summary of the invention

[0004] The purpose of the present invention is to overcome the defects of the prior art and propose a satellite-borne heterogeneous computing system.

[0005] In view of this, the present invention proposes a satellite-borne heterogeneous computing system, characterized in that the system comprises: a CPU module, an FPGA module and an NPU module; wherein,

[0006] The CPU module is used to receive instructions and telemetry polling from the satellite computer, to read the payload science data received by the FPGA module, to provide an installation and operating environment for various types of general-purpose applications, and to schedule and control the NPU module;

[0007] The FPGA module is used to provide external interface expansion, receive payload scientific data, and send it to the CPU module through the internal bus. It is also used to provide logic control functions including SPI FLASH triple-mode redundant logic and dog barking reset;

[0008] The NPU module is used to perform high-performance computing and provide a high-computing environment for the system.

[0009] Preferably, the system also includes a DDR4 SDRAM memory required for the operation of the CPU module, an SPI FLASH memory for storing BIOS, and an eMMC and a solid-state storage SSD for storing an operating system and application programs.

[0010] Preferably, the data bus of the DDR4 SDRAM memory is 72 bits, including 8 check bits, and the data is corrected and checked when the CPU module accesses the DDR4 SDRAM;

[0011] The SPI FLASH memory is configured with a triple-module redundancy function, the BIOS is stored in three independent SPI FLASH chips, the CPU module reads the three SPI FLASH chips at the same time, and the FPGA module performs a three-to-two operation on the data of the three SPI FLASH chips, and outputs the correct data to the CPU;

[0012] The eMMC and solid-state storage SSD are used to store the Linux operating system and various application programs and library functions, wherein two copies of the operating system are stored in the eMMC and three copies of the operating system are stored in the solid-state storage SSD.

[0013] Preferably, each operating system kernel stored in the eMMC or solid-state storage SSD has three copies. When the CPU module starts, it reads the three operating system kernels in sequence and compares two out of three, and then writes the compared data into the memory.

[0014] Preferably, the CPU module reads three operating system kernels in sequence when starting up, including:

[0015] After the CPU module is powered on, it first reads the first operating system from the eMMC. During operation, if the first dog barking reset occurs, the second operating system in the eMMC is started. If the second dog barking reset occurs, the first operating system in the solid-state storage SSD is started, and so on until the third operating system stored in the SSD is read.

[0016] Preferably, the processing process of the CPU module specifically includes:

[0017] When receiving the NPU power-on command from the satellite computer, control the NPU module to power on, load the NPU driver and dynamic library, and configure the NPU;

[0018] When receiving the NPU power-off instruction from the satellite computer, the NPU module is powered off. If the power-off operation fails, the satellite computer powers off the NPU module through direct instructions.

[0019] Preferably, the processing process of the CPU module also includes: performing operation monitoring, telemetry monitoring and current monitoring on the NPU module, and resetting or powering off the NPU module if an abnormality occurs.

[0020] Preferably, the satellite platform provides a secondary power supply for the system; the satellite service computer communicates with the CPU module via the CAN bus, the payload sends payload scientific data to the FPGA module via the LVDS interface or the RS422 interface, and sends the processed results to the satellite service computer via the CAN bus.

[0021] Preferably, the CPU module adopts the Loongson processor LS2K2000, and is connected and communicated with the NPU module via PCIe3.0. The CPU module and the NPU module are independent of each other in hardware, and the NPU module is independently powered on and off.

[0022] Preferably, the system is interconnected with other devices via Gigabit Ethernet to form a network, and a plurality of the systems are interconnected via the network to form a distributed computing system.

[0023] Compared with the prior art, the advantages of the present invention are:

[0024] The NPU module in the present invention can be powered on and off independently according to performance requirements, which improves the flexibility and reliability of the system; multiple onboard heterogeneous computing systems are interconnected through Gigabit Ethernet to form a distributed computing system with extremely high performance; the system is versatile and can run various computing software and neural network algorithms; the system has the characteristics of low power consumption and can adapt to the strict requirements of satellite platforms on power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the composition of the onboard heterogeneous computing system of the present invention;

[0026] Figure 2 It is an internal and external connection diagram of the onboard heterogeneous computing system of the present invention. DETAILED DESCRIPTION

[0027] The present invention proposes a spaceborne heterogeneous computing system, which includes: a CPU module, an FPGA module and an NPU module; wherein:

[0028] The CPU module is used to receive instructions and telemetry polling from the satellite computer through the CAN and RS422 buses, to read the payload science data received by the FPGA, to provide an installation and operating environment for various types of general-purpose applications (APPs), and to schedule and control the NPU;

[0029] The FPGA module is used for external interface expansion, receiving payload scientific data sent through RS422 and LVDS interfaces, and read by the CPU through the internal bus, and is also used for SPI FLASH triple-mode redundant logic and dog barking reset and other logic control functions;

[0030] The NPU module is used for high-performance computing, providing a high-computing environment for the system, and can efficiently run artificial intelligence algorithms such as neural networks.

[0031] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0032] Example

[0033] The present invention D provides a spaceborne heterogeneous computing system, the composition principle diagram of which is as follows Figure 1 As shown, the system includes a CPU module, an FPGA module and an NPU module.

[0034] The CPU module receives instructions and telemetry polling from the satellite computer through the CAN and RS422 buses, is used to read the payload science data received by the FPGA, provides an installation and operating environment for various types of general-purpose applications (APPs), and is also used to schedule and control the NPU;

[0035] The FPGA module performs external interface expansion, receives payload science data sent through RS422 and LVDS interfaces, and is read by the CPU through the internal bus. It is also used for SPI FLASH triple-mode redundant logic and dog barking reset and other logic control functions;

[0036] The NPU module is used for high-performance computing, providing a high-computing power environment for the system, and can efficiently run artificial intelligence algorithms such as neural networks.

[0037] In one embodiment, the CPU uses the Loongson high-performance processor LS2K2000, which has the characteristics of high performance and low power consumption. It is connected and communicated with the NPU through PCIe3.0. The CPU module and the NPU module are independent of each other in hardware, and the NPU module can be powered on and off independently.

[0038] The CPU program runs in the DDR4 SDRAM memory, where the data bus is 72 bits, including 8 check bits. The CPU can perform one-check and two-check on the data when accessing the DDR4 SDRAM;

[0039] The SPI FLASH memory is configured with triple-mode redundancy. The BIOS is stored in three independent SPI FLASH chips. The CPU reads the three SPI FLASH chips at the same time. The FPGA performs a three-out-of-two operation on the data of the three SPI FLASH chips and outputs the correct data to the CPU.

[0040] eMMC and solid-state storage SSD are mainly used to store the Linux operating system and various application programs and library functions. Two operating systems are stored in the eMMC and three operating systems are stored in the SSD.

[0041] The system has three copies of each operating system kernel stored in the eMMC and SSD. When the CPU starts, it reads the three operating system kernels in sequence and compares them two out of three, and then writes the compared data to the memory.

[0042] After the CPU is powered on, it first reads the first operating system from the eMMC. During operation, if the first dog barking reset occurs, the second operating system in the eMMC is started. If the second dog barking reset occurs, the first operating system in the SSD is started, and so on until the third operating system stored in the SSD is read.

[0043] The satellite platform provides secondary power for the system; the satellite computer communicates with the CPU module via the CAN bus, the payload sends payload data to the FPGA module via the LVDS interface or RS422 interface, and sends the processed results to the satellite computer via the CAN bus. Figure 2 Shown is the system internal and external connection diagram.

[0044] The system can be interconnected with other devices through Gigabit Ethernet to form a network. Multiple onboard heterogeneous computing systems can be interconnected through the network to form a more powerful distributed computing system.

[0045] When the CPU module receives the NPU power-on command from the satellite computer, it controls the NPU module to power on, loads the NPU driver and dynamic library, and configures the NPU;

[0046] When the CPU module receives the NPU power-off instruction from the satellite computer, it powers off the NPU module. If the power-off operation fails, the satellite computer powers off the NPU module through direct instructions.

[0047] The CPU module performs operation monitoring, telemetry monitoring, and current monitoring on the NPU module. If an abnormality occurs, the NPU module is reset or powered off.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A spaceborne heterogeneous computing system, characterized in that: The system includes: a CPU module, an FPGA module and an NPU module; wherein, The CPU module is used to receive instructions and telemetry polling from the satellite computer, to read the payload science data received by the FPGA module, to provide an installation and operating environment for various types of general-purpose applications, and to schedule and control the NPU module; The FPGA module is used to provide external interface expansion, receive payload scientific data, and send it to the CPU module through the internal bus. It is also used to provide logic control functions including SPI FLASH triple-mode redundant logic and dog barking reset; The NPU module is used to perform high-performance computing and provide a high-computing environment for the system.

2. The onboard heterogeneous computing system according to claim 1, characterized in that: The system also includes a DDR4 SDRAM memory required for the operation of the CPU module, an SPI FLASH memory for storing BIOS, and an eMMC and a solid-state memory SSD for storing an operating system and application programs.

3. The onboard heterogeneous computing system according to claim 2, characterized in that: The data bus of the DDR4 SDRAM memory is 72 bits, including 8 check bits, and the data is corrected and checked when the CPU module accesses the DDR4 SDRAM; The SPIFLASH memory is configured with a triple-module redundancy function, the BIOS is stored in three independent SPIFLASH chips, the CPU module reads the three SPIFLASH chips at the same time, the FPGA module performs a three-to-two operation on the data of the three SPIFLASH chips, and outputs the correct data to the CPU; The eMMC and solid-state storage SSD are used to store the Linux operating system and various application programs and library functions, wherein two copies of the operating system are stored in the eMMC and three copies of the operating system are stored in the solid-state storage SSD.

4. The onboard heterogeneous computing system according to claim 3, characterized in that: Each operating system kernel stored in the eMMC or solid-state storage SSD has three copies. When the CPU module starts, it reads the three operating system kernels in sequence and compares them two out of three, and then writes the compared data into the memory.

5. The onboard heterogeneous computing system according to claim 4, characterized in that: When the CPU module starts, it reads three operating system kernels in sequence, including: After the CPU module is powered on, it first reads the first operating system from the eMMC. During operation, if the first dog barking reset occurs, the second operating system in the eMMC is started. If the second dog barking reset occurs, the first operating system in the solid-state storage SSD is started, and so on until the third operating system stored in the SSD is read.

6. The onboard heterogeneous computing system according to claim 1, characterized in that: The processing process of the CPU module specifically includes: When receiving the NPU power-on command from the satellite computer, it controls the NPU module to power on, loads the NPU driver and dynamic library, and configures the NPU; When receiving the NPU power-off instruction from the satellite computer, the NPU module is powered off. If the power-off operation fails, the satellite computer powers off the NPU module through direct instructions.

7. The onboard heterogeneous computing system according to claim 6, characterized in that: The processing process of the CPU module also includes: operation monitoring, telemetry monitoring and current monitoring of the NPU module. If an abnormality occurs, the NPU module is reset or powered off.

8. The onboard heterogeneous computing system according to claim 1, characterized in that: The satellite platform provides secondary power for the system; the satellite computer communicates with the CPU module via the CAN bus, the payload sends payload scientific data to the FPGA module via the LVDS interface or the RS422 interface, and sends the processed results to the satellite computer via the CAN bus.

9. The onboard heterogeneous computing system according to claim 1, characterized in that: The CPU module adopts the Loongson processor LS2K2000, and is connected and communicated with the NPU module via PCIe3.

0. The CPU module and the NPU module are independent of each other in hardware, and the NPU module is independently powered on and off.

10. The onboard heterogeneous computing system according to claim 1, characterized in that: The system is interconnected with other devices via Gigabit Ethernet to form a network, and multiple systems are interconnected via the network to form a distributed computing system.

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