Matrix transposition method, transposition module and chip

Abstract

A matrix transposing method, transposing module and chip, the transposing module comprises a first storage space, a second storage space and N acceleration units, the first storage space stores a first matrix, the first matrix corresponds to a first block array composed of M rows * N columns of blocks, the N acceleration units correspond to N block columns respectively, and the N acceleration units correspond to N block columns respectively. The method comprises the steps that the ith acceleration unit determines the line number j of a block to be read and position information of a transposed block based on i, M and the reading frequency of the ith acceleration unit; reading a first block from the ith block column; carrying out transposition on the first sub-block to obtain a second sub-block; and storing the second block into the second storage space based on the position information.

Description

Technical Field

[0001] The embodiments of the present specification belong to the field of computer technology, and in particular, relate to a matrix transposition method, a transposition module, and a chip. Background Art

[0002] As people's awareness of data security and privacy protection continues to increase, privacy computing, as a new type of secure computing model, is gradually becoming one of the mainstream methods for data processing and analysis. Privacy computing achieves data privacy and security protection by directly calculating encrypted or anonymous data without exposing the original data, and has broad application prospects. At present, privacy computing technology has been widely used in artificial intelligence, finance, medical and other fields, becoming an important supporting technology for the future digital society. Homomorphic encryption is one of the common mainstream technologies in the field of privacy computing. It can perform various common computing operations in an encrypted state while ensuring the correctness of the results and the privacy of the data. Homomorphic encryption technology has been widely used in cloud computing, data privacy protection, secure multi-party computing and other scenarios. It is one of the important technical means to protect privacy data and achieve secure computing.

[0003] A fully homomorphic encryption (FHE) accelerator chip is a hardware device designed specifically to accelerate fully homomorphic encryption operations. The FHE accelerator chip improves the efficiency of fully homomorphic encryption operations by implementing specific mathematical operations at the hardware level.

[0004] FHE acceleration chips are mainly used to accelerate number theoretic transform (NTT) and automorphism operations. NTT and Automorphism operations involve a lot of transposition processing. In order to achieve efficient FHE acceleration, high-performance transposition processing must be achieved. In the existing transposition scheme, the matrix to be transposed is divided into multiple blocks, and multiple processing elements (PE) process different blocks in parallel to achieve the effect of accelerating the transposition. However, in this scheme, multiple computing units are required to process synchronously. If there is a lack of synchronization between the acceleration units, it will cause data misalignment between the blocks, making the final transposition result wrong.

[0005] For example, in Figure 1 In the transposition scheme shown, the rows of the EG×EG matrix are distributed among the Lane groups in a cyclic manner, the matrix is ​​partitioned into multiple G×G blocks, and the transposition is decomposed into two steps: transposing the (EG / G)×(EG / G) block matrix; and transposing all G×G blocks. Figure 1The process of transposing a 4×4 matrix (EG=4) through G=2 Lane groups (i.e., Lane group 0 and Lane group 1) is shown. Wherein, Lane group 0 and Lane group 1 are, for example, two computing units, and the 4×4 matrix is ​​divided into multiple 2×2 blocks for processing. Figure 1 Steps in As shown, Lane group 0 is responsible for row 0 of all 2×2 blocks, and Lane group 1 is responsible for row 1 of all 2×2 blocks. In step ①: Each Lane group performs a local transposition on the four 1×2 sub-blocks it holds, for example, Lane group 0 swaps 2, 3 with 8, 9, and Lane group 1 swaps 6, 7 with 12, 13. In step ②: Lane group 0 and Lane group 1 follow a fixed pattern to move elements between Lane groups, specifically, group i sends the elements in the jth column of all 1×2 sub-blocks it holds to group j. The scheme uses a fixed permutation network between Lane groups to achieve this.

[0006] In the above scheme, when Lane group0 and Lane group1 are processed by processing unit A and processing unit B respectively, if processing units A and B are not processed synchronously, the output of step ① will be misaligned. For example, the original {0,1,8,9} and {4,5,12,13} aligned outputs become {0,1,8,9} and {6,7,14,15} aligned outputs to the fixed arrangement network, resulting in the transposed result of step ② changing from the correct {0,4,8,12} and {1,5,9,13} to the incorrect {0,6,8,14} and {1,7,9,15}. Summary of the invention

[0007] The object of the present invention is to provide a matrix transposition method to improve the correctness of matrix transposition.

[0008] In a first aspect, the present specification provides a matrix transposition method, which is performed by a transposition module, wherein the transposition module includes a first storage space, a second storage space, and N acceleration units, wherein the first storage space stores a first matrix, the first matrix corresponds to a first block array consisting of M rows×N columns of blocks, and the N acceleration units correspond to the N block columns respectively, and the method includes:

[0009] The i-th acceleration unit determines, based on i, M, and the number of times the i-th acceleration unit reads the i-th block column in the first block array, the number of rows j of the blocks to be read in the i-th block column and the position information of the transposed blocks corresponding to the blocks to be read in the second block array, wherein the second block array corresponds to a second matrix, and the second matrix is ​​the transposed matrix of the first matrix;

[0010] The i-th acceleration unit reads the first block from the i-th block column based on the row number j of the to-be-read blocks;

[0011] The i-th acceleration unit transposes the first block to obtain a second block;

[0012] The i-th acceleration unit stores the second block in the second storage space based on the position information.

[0013] A second aspect of the present specification provides a transposition module, comprising a first storage space, a second storage space and N acceleration units, wherein the first storage space stores a first matrix, the first matrix corresponds to a first block array consisting of M rows×N columns of blocks, the N acceleration units correspond to the N block columns respectively,

[0014] The i-th acceleration unit corresponding to the i-th block column of the first block array is used to perform the following operations:

[0015] Based on i, M, and the number of times the i-th acceleration unit reads the i-th block column in the first block array, determine the number of rows j of the blocks to be read in the i-th block column and the position information of the transposed blocks corresponding to the blocks to be read in the second block array, wherein the second block array corresponds to a second matrix, and the second matrix is ​​the transposed matrix of the first matrix;

[0016] Based on the row number j of the blocks to be read, read the first block from the i-th block column;

[0017] Transposing the first block to obtain a second block;

[0018] Based on the location information, the second block is stored in the second storage space.

[0019] A third aspect of this specification provides a chip, comprising a computing unit and a transposition module as described in the second aspect, wherein the computing unit is used to store the first matrix in the first storage space and instruct the transposition module to perform transposition processing on the first matrix.

[0020] The matrix transposition scheme in the embodiments of this specification determines the write-back address of each block after different computing units transpose the blocks they process, so as to store the transposed blocks in the correct location based on the write-back address. This scheme does not rely on synchronous processing between computing units, thereby improving the correctness of the transposition processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 is a process schematic diagram of a transposition method in an embodiment;

[0023] Figure 2 This is a flow chart of a matrix transposition method in an embodiment of this specification;

[0024] Figure 3 to Figure 8 Schematic diagram of the process of transposing a matrix in an embodiment of this specification;

[0025] Fig. 9 is a flow chart of a matrix transposition method based on a systolic array in an embodiment of this specification;

[0026] Fig.10 is a schematic diagram of a systolic array in an embodiment of this specification;

[0027] Fig.11 A schematic diagram of a process of storing a first block in a systolic array in an embodiment of this specification;

[0028] Fig.12 A schematic diagram of a process of outputting data from a systolic array to a second storage space in an embodiment of this specification;

[0029] Fig.13 is a schematic diagram of a systolic array in another embodiment of the present specification;

[0030] Fig.14 is a structural schematic diagram of a transposition module used in, for example, an FHE chip in another embodiment of this specification;

[0031] Fig.15 It is a schematic diagram of the structure of the MIN network in the embodiment of this specification. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this specification.

[0033] Matrix transpose is a matrix operation that interchanges the rows and columns of a matrix. Specifically, assume

[0034] matrix then the transpose matrix of matrix A

[0035] Regarding the problems existing in the existing matrix transpose schemes mentioned above, the embodiments of this specification provide a matrix transpose scheme. After different computing units transpose the respective blocks they process, they determine the write-back addresses of each block, and based on these write-back addresses, store the transposed blocks in the correct positions. This scheme does not rely on the synchronization processing between computing units and improves the robustness of the transpose processing.

[0036] Figure 2 is a flowchart of a matrix transpose method in the embodiments of this specification, Figure 2 The method shown can be executed by a transpose module in an FHE chip. The transpose module may include a first storage space, a second storage space, and N acceleration units.

[0037] The first storage space stores the matrix M1 to be transposed. The matrix M1 can be divided into a first block array composed of M rows × N column blocks. Each block can be a K×K square matrix or a non-square matrix. The N acceleration units correspond to N block columns in the first block array respectively. Among them, the following relationship may exist between M and N: M = N. In this case, the array composed of multiple blocks is a square matrix, such as the array shown on the left; M < N. In this case, the array composed of multiple blocks is, for example, as shown in Figure 3 shown on the left; M > N. In this case, the array composed of multiple blocks is, for example, as shown in Figure 4 , Figure 5 or Figure 6 shown on the left; M > N. In this case, the array composed of multiple blocks is, for example, as shown in Figure 7 or Figure 8 shown on the left. Among them, Figure 3 to Figure 8 is a schematic diagram of the process of transposing a matrix in the embodiments of this specification, Figure 3 to Figure 8 each small cell in represents a block in the block array.

[0038] Figure 2 The method shown includes the i-th acceleration unit corresponding to the i-th block column of the first block array performing the following steps:

[0039] In step S201, based on i, M, and the number of times the i-th acceleration unit reads the i-th block column, determine the number of rows j of the block to be read in the i-th block column and the position information of the transposed block corresponding to this block in the second block array. Among them, the second block array corresponds to the matrix M2, and the matrix M2 is the transpose matrix of the matrix M1;

[0040] In step S203, based on the row number j of the block to be read, the first block is read from the i-th block column;

[0041] In step S205, the first block is transposed to obtain a second block;

[0042] In step S207, based on the position information, the second block is stored in the second storage space.

[0043] The N acceleration units may correspond to N computing units, specifically, each acceleration unit may include a computing unit. The N computing units may be, for example, computing units in different computing cores. Since each computing core has its own independent instruction control unit, the instructions of different computing cores are issued asynchronously, that is, different computing cores will not issue an instruction at the same time. Using the N computing units to execute the matrix transposition scheme in the prior art may cause errors in the transposition result as described in the background technology.

[0044] In the embodiment of this specification, each of the N acceleration units independently processes the corresponding block column, and the correctness of the processing result does not depend on whether the processing of different acceleration units is synchronized.<N、M> N three cases respectively describe the processing process of the i-th acceleration unit as examples. It can be understood that the processing process of each acceleration unit in the N acceleration units is the same as the processing process of the i-th acceleration unit.

[0045] 1. In the case of M=N, the matrix M1 is divided into an N×N block array, that is, each block column includes N rows of blocks. Figure 3 As shown in the left array, the matrix M1 is divided into an 8×8 block array, with a total of 8 block columns, each of which includes 8 rows of blocks, where Figure 3 The numbers on the left side of the array on the left represent the row number of the block, and the numbers on the top of the array represent the column number of the block.

[0046] First, in step S201, the i-th acceleration unit determines the number of rows j of the block to be read and the position information of the transposed block based on i, M and the number of times the i-th acceleration unit reads the i-th block column.

[0047] In addition to the computing unit, each acceleration unit may also include a register for storing the value of the number of reads rt. The register may initially store a value "0" to indicate that the value of the number of reads is initially 0.

[0048] When the i-th acceleration unit reads a block for the first time (i.e., the number of reads is 0), it can read the i-th row of blocks from the i-th block column, i.e., start reading from the blocks on the diagonal of the block array. After each block is processed, the number of reads rt is increased by one, and the row number j of the next block to be read is determined according to the following formula (1):

[0049]

[0050] Specifically, assuming Figure 3 The number of columns of the block array on the left side is 0 to 7, and the number of rows is 0 to 7, then the identifiers of the N acceleration units are the 0th acceleration unit to the 7th acceleration unit. When the second acceleration unit corresponding to the second block column reads the number of times rt=0, it can be determined that the number of rows of the block to be read is 2, that is, the block to be read is block 18. After the i-th acceleration unit completes the processing of a block, the reading number rt is increased by 1. For example, after the second acceleration unit completes the processing of block 18, it adds 1 to the value stored in its corresponding register, so that rt=1. At this time, the second acceleration unit determines that the number of rows of blocks to be read j is 2+rt=2+1=3, that is, the block to be read is block 26. After the second acceleration unit completes the processing of block 26, it updates the value of rt to 2, then the second acceleration unit can determine that the number of rows of blocks to be read is 2+rt=2+2=4. The same process is repeated until rt is updated to Mi=8-2=6. When rt is updated to 6, the second computing unit determines that the number of blocks to be read is 2+rt-8=0, that is, the block to be read is block 2 of the 2nd column and the 0th row. After rt is updated to 7 and the reading of the blocks of the 1st row is completed, the second computing unit determines that the reading of all blocks of the 2nd column is completed.

[0051] The i-th acceleration unit may determine the position information of the transposed block (the second block) corresponding to the block to be read (the first block) in the matrix M2.

[0052] The position information may include the number of rows k and the number of columns t of the block array of the second block in the matrix M2. According to the above matrix transposition rule, since the block array in the matrix M1 is a square matrix, the block array in the matrix M2 is also a square matrix, and the number of rows k of the second block is equal to the number of columns i of the first block, and the number of columns t of the second block is equal to the number of rows j of the first block.

[0053] In step S203, the i-th acceleration unit reads the first block from the j-th row of the i-th block column.

[0054] The first storage space may include N first sub-spaces, and each column of blocks in the above-mentioned first block array is stored in a corresponding first sub-space. The i-th acceleration unit is connected to the read / write interface of the i-th first sub-space. The i-th acceleration unit can address in the first sub-space based on i, so as to read the data in the j-th row of the i-th block column.

[0055] In step S205, the read first block is transposed to obtain a second block.

[0056] The i-th acceleration unit can use the existing matrix transposition method to transpose the first block. Since the i-th acceleration unit itself performs the transposition of the first block and there is no problem of asynchronous instruction issuance by different acceleration units, there will be no problem of obtaining an incorrect transposed result. As Figure 3 shown on the right, the second block can be represented as the transpose of the first block. For example, the transposed block corresponding to block 18 is represented as 18 T , and the transposed block corresponding to block 26 is represented as 26 T and so on.

[0057] In step S207, the i-th acceleration unit stores the second block into the second storage space based on the position information of the second block.

[0058] For example, the second storage space may include N second sub-spaces, and each second sub-space is used to store a column of blocks in the second block array. After the i-th acceleration unit determines the number of rows k and the number of columns t of the second block as described above, it can provide the second block to the t-th second sub-space and instruct the t-th second sub-space to store the second block in the k-th row.

[0059] Second, in the case of M < N, in one example, as Figure 4 shown by the matrix M1 on the left, the block array corresponding to the matrix M1 can be divided into two horizontally arranged block square matrices with M×M block square matrices as units, and each acceleration unit can perform transposition processing based on its corresponding block square matrix. In another example, in the case where the matrix M1 cannot be exactly divided into an integer number of block square matrices, referring to Figure 5 the matrix M1 shown on the left, after filling two blank block columns in the matrix M1, the filled block array can be divided into two block square matrices, and each acceleration unit can similarly perform transposition processing based on its corresponding block square matrix. The following takes the Figure 4 shown processing process as an example for description. It can be understood that in the Figure 5 shown processing process, each acceleration unit processes in a manner similar to the Figure 4 shown process.

[0060] First, in step S201, the i-th acceleration unit determines the number of rows j of the block to be read, and the position information of the corresponding transposed block in the second block array, based on i, M, and the number of times the i-th acceleration unit reads the i-th block column.

[0061] When the i-th acceleration unit reads a block for the first time (i.e., the number of reads is 0), referring to Figure 4 , in the case of the block square matrix on the left side of the i-th column corresponding to the i-th acceleration unit in matrix M1, the i-th row block can be read from the i-th block column, that is, starting from the block on the diagonal of the block square matrix; in the case of the block square matrix on the right side of the i-th column corresponding to the i-th acceleration unit in matrix M1, the number of columns s in the block square matrix corresponding to the i-th column can be determined first, and then the s-th row block can be read from the i-th block column. After each block is processed, the read count rt is incremented by one, and the number of rows j of the next block to be read is determined based on the read count rt and the row number i or s.

[0062] Therefore, the i-th acceleration unit can determine the number of rows j of the block to be read based on the following formula (2):

[0063]

[0064] Wherein, the parameter s in formula (2) is the number of columns of the i-th column in its corresponding block square matrix, that is, s = i mod M. It can be understood that formula (1) is a special case of formula (2) when i < M.

[0065] Specifically, referring to Figure 4 , assuming Figure 4 the number of columns of the left block array in is 0 to 7 columns, and the number of rows is 0 to 3 rows, then the identifiers of the N acceleration units are the 0th acceleration unit to the 7th acceleration unit, and this block array can be divided into two 4-row × 4-column block square matrices. According to formula (2), when i = 2 < M = 4, the above two formulas in formula (2) are applicable. When the read count rt = 0 of the 2nd acceleration unit, the number of rows of the block to be read can be determined to be 2, that is, the block to be read is block 34. When rt is updated to 2, the 2nd acceleration unit determines that the number of rows j of the block to be read is 2 + rt - 4 = 0, that is, the block to be read is the block at the 2nd column and 0th row, block 2.

[0066] When i = 6 > 4, the following two formulas in formula (2) are applicable. For i = 6, s = 6 mod 4 = 2. When rt = 0 for the 6th acceleration unit, the number of rows j of the block to be read can be determined to be 2, and the block to be read is Figure 4The block 38 on the diagonal of the block array on the right side in the middle matrix M1. When rt = 2 for the 6th acceleration unit, the number of rows j of the block to be read can be determined as s + rt - M = 2 + 2 - 4 = 0, and the block to be read is the block 6 in the 6th column and the 0th row.

[0067] The i-th acceleration unit also determines the position information of the transposed block (the second block) corresponding to the block to be read (the first block) in the second block array. The second block array is as Figure 4 shown by the block array on the right side, which is a block array obtained by partitioning the matrix M2 into blocks.

[0068] The position information may include the number of rows k and the number of columns t of the second block in the second block array. Among them, the number of rows k of the second block is equal to the number of columns i of the first block in the first block array, and the number of columns t of the second block is equal to the number of rows j of the first block in the first block array.

[0069] Specifically, for the block 34 to be read, it can be determined that the number of rows k = i = 2 and the number of columns t = j = 2 of its transposed block 34 T ; for the block 2 to be read, it can be determined that the number of rows k = i = 2 and the number of columns t = j = 0 of its transposed block 2 T .

[0070] After that, the i-th acceleration unit reads the first block from the j-th row of the i-th block column, transposes the read first block to obtain the second block, and stores the second block in the second storage space according to the number of rows k and the number of columns t.

[0071] In Figure 4 and Figure 5 During the transposition process shown, the columns of the second blocks corresponding to the first blocks calculated by different acceleration units among the N acceleration units are the same columns. For example, the 2nd acceleration unit and the 5th acceleration unit may simultaneously calculate the transposed block 17 of the block 17 T corresponding to the 1st block column in the second block array, and the transposed block 21 of the block 21 T corresponding to the 1st block column in the second block array. When the second storage space is divided into 4 vertical sub-spaces (i.e., the 0th sub-space to the 3rd sub-space) for storing each block column, it is possible that the 1st sub-space of the second storage space needs to store the transposed block 17 T and the transposed block 21 T simultaneously, resulting in an extension of the storage time.

[0072] Therefore, referring to Figure 6 , the N acceleration units can respectively transpose two block square matrices in the matrix M1, so that Figure 6The second block array corresponding to the matrix M3 shown on the right is stored in the second storage space. In this case, the columns of the transposed blocks calculated by each acceleration unit do not overlap with each other, thereby avoiding the above-mentioned problem of prolonged storage time. Figure 4 and Figure 6 , Figure 6 The matrix M3 in the figure is equivalent to horizontally expanding the matrix M2. After reading the matrix M3 from the transposition module, the computing device can splice the two block matrices of the second block array corresponding to the matrix M3 into the following: Figure 4 , thereby obtaining the transposed matrix M2 of the matrix M1. Alternatively, when the transposition module outputs the matrix data, it can output the rows of each block matrix in the order of the two block matrixes, for example, first sequentially output the rows of the block matrix on the left side of the second block array, then sequentially output the rows of the block matrix on the right side of the second block array, and arrange the sequentially output rows of the blocks as Figure 4 The block array corresponding to the matrix M2 in the matrix M1 can be obtained to obtain the transposed matrix M2 of the matrix M1.

[0073] for Figure 6 In the process shown, specifically, the i-th acceleration unit can still determine the number of rows j of the block to be read based on the above formula (2), and determine the position information of the transposed block corresponding to the block in the second block array. The position information may include the number of rows k and the number of columns t of the second block in the second block array. The number of rows k of the second block is equal to the number of columns i mod M of the first block, and the number of columns t of the second block is equal to j+(i / / M)*M, where “ / / ” indicates integer division. Specifically, for the block 34 to be read, its transposed block 34 can be determined. T The number of rows k is i mod 4 = 2, and the number of columns t is t = 2 + 0 = 2; for the block 37 to be read, its transposed block 37 can be determined T The number of rows k=5mod4=1, and the number of columns t is t=2+4=6.

[0074] Afterwards, the i-th acceleration unit can read the first block from the j-th row of the i-th block column of the first block array, transpose the read first block to obtain the second block, and store the second block in the second storage space according to the number of rows k and columns t of the second block.

[0075] 3. In the case of M>N, if Figure 7 As shown in the matrix M1 on the left, the block array corresponding to the matrix M1 can be divided into two vertically arranged block arrays in units of M×M block arrays, and each acceleration unit can perform transposition processing based on the first block array starting from the 0th row.

[0076] First, in step S201, the ith acceleration unit determines the number of rows j of the block to be read and the position information of the corresponding transposed block in the second block array based on i, M and the number of times the ith acceleration unit reads the ith block column.

[0077] When the i-th acceleration unit reads a block for the first time (i.e., the number of reads is 0), it can read the i-th row of blocks from the i-th block column, i.e., start reading from the blocks on the diagonal of the first block matrix in the matrix M1. After each block is processed, the number of reads rt is increased by one, and the number of rows j of the next block to be read is determined according to the following formula (3):

[0078]

[0079] Specifically, assuming Figure 7 The number of columns of the block array on the left side is 0 to 3, and the number of rows is 0 to 7, then the identifiers of the N acceleration units are the 0th acceleration unit to the 3rd acceleration unit. When the second acceleration unit corresponding to the second block column reads the number of times rt=0, it can be determined that the number of rows of the block to be read is 2, that is, the block to be read is block 34. After the i-th acceleration unit completes the processing of a block, the reading number rt is increased by 1. For example, after the second acceleration unit completes the processing of block 34, it adds 1 to the value stored in its corresponding register, so that rt=1. At this time, the second acceleration unit determines that the number of rows of blocks to be read is 2+rt=2+1=3, that is, the block to be read is block 50. After the second acceleration unit completes the processing of block 50, it updates the value of rt to 2, then the second acceleration unit can determine that the number of rows of blocks to be read is 2+rt=2+2=4, that is, the block to be read is block 54. The same process is repeated until rt is updated to Mi=8-2=6. When rt is updated to 6, the second computing unit determines that the number of blocks to be read is 2+rt-8=0, that is, the block to be read is block 2 of the 2nd column and the 0th row. After rt is updated to 7 and the reading of the blocks of the 1st row is completed, the second computing unit determines that the reading of all blocks of the 2nd column is completed.

[0080] The i-th acceleration unit also determines the position information of the second block in the second block array corresponding to the matrix M2. The position information may include the number of rows k and the number of columns t of the second block in the second block array. According to the above matrix transposition rule, the number of rows k of the second block is equal to the number of columns i of the first block, and the number of columns t of the second block is equal to the number of rows j of the first block.

[0081] Afterwards, the i-th acceleration unit may read the first block from the j-th row of the i-th block column of the first block array, transpose the read first block to obtain the second block, and store the second block in the second storage space.

[0082] exist Figure 7 In the transposition process shown, the i-th acceleration unit needs to store two columns of blocks (eg, the i-th column and the (i+M)-th column) in the second block array into two subspaces in the second storage space, which prolongs the time of the transposition process.

[0083] For this purpose, refer to Figure 8 , before being stored in the first storage space, the lower block matrix of the matrix M1 may be placed on the right side of the upper block matrix to obtain a matrix M4 including 4 rows×8 columns of blocks, and then the matrix M4 may be stored in the first storage space. In another embodiment, the matrix M1 may be directly stored in the first storage space, wherein, in the first storage space, the upper four columns of the matrix M1 and the upper four columns of the matrix M1 are stored in 8 first subspaces, respectively, which is equivalent to providing a 4-row×8-column block array.

[0084] In this case, you can Figure 6 The same process as shown is used to transpose the left block matrix and the right block matrix in the first block array corresponding to the matrix M4, respectively, to obtain Figure 8 The transposed matrix M2 shown in .

[0085] In the above scheme, the N acceleration units corresponding to the N block columns of the first block array independently process the blocks in the i-th column based on the column number i, the number of reads of the acceleration unit and the number of rows of the first block array to transpose the matrix M1 to obtain the matrix M2. In this scheme, the N acceleration units do not need to process synchronously, which improves the robustness of the transposition processing.

[0086] Fig. 9 Flow chart of a matrix transposition method based on a systolic array in an embodiment of this specification. Fig. 9 The method shown can be performed by a transposition module in a FHE chip, for example. The transposition module may include a first storage space and a second storage space, wherein the first storage space is used to store the matrix to be transposed (or the first block array), and the second storage space is used to store the transposed matrix (or the second block array). The matrix M1 to be transposed is, for example, a matrix of size E*F. The following description takes the example of a square matrix of 128*128 as the matrix M1. It can be understood that the processing process for non-square matrices can refer to the processing of square matrices described below. The matrix M1 can be divided into a plurality of blocks, each of which is, for example, of a size of 16*16, so that the matrix M1 can be divided into 8*8 blocks.

[0087] The transposition module may also include a systolic array, which includes, for example, 16*16 storage locations, each of which includes one or more bytes of storage space for storing an element in a block, so that a block in the matrix can be transposed. In the case where the above-mentioned block is not a square matrix, the storage location included in the systolic array can be set according to the size of the block, or the pulse array can be set as a square matrix to be suitable for blocks of different sizes.

[0088] Each storage location in the systolic array includes at least one input port and two output ports for systolic data in the row direction and the column direction of the array, respectively.

[0089] Fig.10 is a schematic diagram of a systolic array in an embodiment of this specification, such as Fig.10 As shown, the systolic array includes, for example, 16*16 registers (RF) as multiple storage locations, and the systolic array also includes a logic circuit ( Fig.10 The two numbers in each register represent the row and column number of the register in the systolic array, for example, "0,1" means that the register is located at row 0 and column 1 in the array. Each register in rows 0 to 14 includes two input ports and two output ports.

[0090] For example, for the register marked with "0,0" (hereinafter referred to as RF 0,0 ), the arrow on the left is an input port for inputting data from outside the systolic array, and the arrow on the right is an output port for outputting the data stored in the register to a register on the right (i.e., RF 0,1 ), the arrow on the lower side is an input port for registers on the lower side (i.e. RF 1,0 ) input data, and the arrow on the upper side is an output port for outputting the stored data to the outside of the systolic array. For the convenience of description, the arrow on the left side of the register is referred to as the first input port, the arrow on the right side of the register is referred to as the first output port, the arrow on the lower side of the register is referred to as the second input port, and the arrow on the upper side of the register is referred to as the second output port. The first input port of each register in the 0th column of the systolic array constitutes the input port (input) of the systolic array, and the second output port of each register in the 0th row constitutes the output port (output) of the systolic array.

[0091] For RF 1,1 , the first input port on its left side, is used to read the register on its left side (i.e. RF 1,0 ) input data, and the second output port on the upper side is used to send data to the register on the upper side (i.e. RF 0,1) output data, the first output port and the second input port have the same function as RF 0,0 same.

[0092] Each register in the 15th row includes a first input port, a first output port, and a second output port. The three ports have the same functions as the ports at the same positions of the registers in other rows of the same column, and are not described in detail here.

[0093] The register may include a trigger and a gate circuit, wherein the trigger includes the first input port, the first output port, the second input port and the second output port, and the gate circuit is used to store data. The trigger can read and output data under the trigger of the clock signal. By controlling the trigger signal input to each register in the systolic array, the pulsation of data between registers can be achieved.

[0094] refer to Fig. 9 First, in step S901, based on the pulsation of the systolic array in the row direction, each row of data of the first block is stored row by row in a column of storage locations in the systolic array.

[0095] The first block may be a block of q rows and p columns. In the transposition module, the data in the first block may be stored in the systolic array through the following steps: p data in the i-th row of the first block are read from the first storage space; for the data stored in the storage positions from the 0th column to the i-1th column in the systolic array, starting from the i-1th column storage position, the data in the first p storage positions of each column are sequentially moved and stored in the first p storage positions of the next column; and the p data in the i-th row are respectively stored in the first p storage positions in the 0th column of the systolic array.

[0096] The above steps are described in detail below by taking the first block as a square matrix as an example. It can be understood that for the case where the first block is a non-square matrix, it can be processed similarly with reference to the description below.

[0097] Assume that the first block to be transposed in the matrix M1 is a 16*16 square matrix as shown below:

[0098]

[0099] A logic circuit is pre-set in the systolic array to enable each register in the systolic array to read data through the first input port in the 1st clock cycle to the 16th clock cycle and to read data through its second input port in the 17th clock cycle to the 32nd clock cycle.

[0100] Fig.11 Schematic diagram of a process of storing a first block in a systolic array in an embodiment of the present specification.

[0101] refer to Fig.11 In the top systolic array, the transposition module first reads the data in the first row of the first block from the first storage space. By triggering the register in the first column in the first clock cycle, according to the timing of the logic circuit, the registers in the first column obtain data from the outside of the systolic array through the first input port, thereby storing the data (i.e., 10, 20, 30…, 40, 50, 60) in the registers in the 0th column of the systolic array.

[0102] refer to Fig.11 In the middle systolic array, the transposition module first triggers the registers in the first column in the second clock cycle, so that each register in the first column reads the data stored therein from each register in the zero column through its first input port, i.e., 10, 20, 30…, 40, 50, 60, and stores them in each register in the first column respectively, and then triggers the registers in the zero column, so that each register in the zero column obtains each data in the second row of the first block (i.e., 11, 21, 31…, 41, 51, 61).

[0103] That is, the pulsation in the row direction (ie, left-right direction) of the systolic array is realized through the above operation, so that each row of data in the first block can be stored in a column of storage locations in the systolic array by analogy.

[0104] refer to Fig.11 In the systolic array at the bottom, the transposition module first triggers the registers in the 15th column at the 16th clock cycle, so that the registers in the 15th column read the data stored therein from the registers in the 14th column through their first input ports, i.e., 10, 20, 30…, 40, 50, 60, and store them in the registers in the 15th column respectively; then the registers in the 14th column are triggered, so that the registers in the 14th column read the data stored therein from the registers in the 13th column through their first input ports, i.e., 11, 21, 31…, 41, 51, 61, and store them in the registers in the 14th column respectively; and so on, until the registers in the 0th column are triggered, so that the registers in the 0th column obtain the data in the 16th row of the first block, i.e., 15, 25, 35…, 45, 55, 65.

[0105] That is, through 16 clock cycles, all elements of the first block are stored in the systolic array.

[0106] In step S903, based on the systolic array's systolic in the column direction, the data stored in each row of storage locations in the systolic array are stored as row data in the second storage space.

[0107] In the case where the first block is a block of q rows and p columns, the transposition module can store the data in the systolic array into the second storage space through the following steps: read q data of the 0th row in the systolic array, and store the read q data as row data in the second storage space according to the positions of the read q data in the transposed block; and for each row after the 0th row in the systolic array, starting from the 1st row, sequentially move the data in the first q storage positions in each row to the first q storage positions of the previous row and store them.

[0108] Fig.12 Schematic diagram of the process of outputting data from the systolic array to the second storage space in the embodiment of this specification.

[0109] refer to Fig.12 In the systolic array at the bottom, the transposition module first outputs the data in each storage position of the 0th row at the 17th clock cycle, and stores each data in the form of row data in the 1st row of the position corresponding to the first block. Assume that in the continuous addresses of the 1st row of the transposed block for storing the first block in the second storage space, the data of the lower column number in the row is stored in the high address, and the data of the higher column number in the row is stored in the low address, so that the data of the 1st row of the transposed block stored in the second storage space can be stored in the higher address of the 1st row in the second storage space, and the data of the lower column number in the register of the 0th row in the systolic array can be stored in the lower address of the 1st row in the second storage space, so that the data of the 1st row of the transposed block stored in the second storage space is 10, 11, 12, ..., 13, 14, 15. After that, in the systolic array, each register in row 0 is triggered to read data from the register in row 1 through its second input port and store it in each register in row 0, and then each register in row 1 is triggered to read data from the register in row 2 through its second input port and store it in each register in row 1. This is repeated until each register in row 14 is triggered to read data from the register in row 15 through its second input port and store it in each register in row 14. Each register in row 15 can eliminate the stored data after the register in row 14 outputs the data, so that Fig.12 The systolic array in the middle.

[0110] refer to Fig.12In the systolic array in the middle, in the 18th clock cycle, the transposition module first outputs the data in each storage position of the 0th row, and stores each data in the form of row data in the 2nd row of the position corresponding to the first block. Referring to the description above, after this storage, the 2nd row data of the transposed block stored in the second storage space is 20, 21, 22, ..., 23, 24, 25. After that, the systolic array sequentially triggers rows 0 to 13 to read and store data from the next row through its second input port, so that Fig.12 The systolic array shown at top.

[0111] That is, through Fig.12 The operation shown realizes the pulsation in the column direction (i.e., the up and down direction) of the systolic array. By analogy, all the data stored in the systolic array can be stored in the position corresponding to the first block in the second storage space, and the transposed matrix of the first block is stored in the position, that is:

[0112]

[0113]

[0114] Fig.13 FIG. 1 is a schematic diagram of a systolic array in another embodiment of the present specification. Fig.13 As shown, the transposition module may include structures and Fig.10 The systolic array A1 and the systolic array A2 are the same as the systolic array shown. The input of the systolic array A1 and the systolic array A2 can be connected to the first storage space, so that the blocks can be read from the first storage space. At the same time, the output of the systolic array A1 and the systolic array A2 can be connected to the second storage space, so that the transposed blocks can be stored in the second storage space. Under this structure, after the data of the first block are stored in the systolic array A1 from the 1st clock cycle to the 16th clock cycle as described above, in the 17th clock cycle to the 32nd clock cycle, while the transposed blocks of the first block are stored from the systolic array A1 to the second storage space, the data of the second block in the matrix M1 can be stored in the systolic array A2 in the same manner as the first block is stored above. In the 33rd clock cycle to the 48th clock cycle, while the transposed blocks of the second block are stored from the systolic array A2 to the second storage space, the data of the third block in the matrix M1 can be stored in the systolic array A1. Therefore, multiple blocks in the matrix M1 can be processed in a pipeline manner, thereby improving the efficiency of matrix transposition.

[0115] Fig.14 FIG. 1 is a schematic diagram of a transposition module used in, for example, an FHE chip in another embodiment of the present specification. Fig.14As shown, the transposition module may include a first on-chip storage, N acceleration units Ac0 to Ac N-1 , MIN network, and second on-chip storage. Each acceleration unit Ac i The computing unit PE may be included i and transposition unit Tr i , where the computing unit PE i Used to calculate the read position and write position of the i-th column block in the first on-chip storage. i Used to perform transposition processing on the i-th column block in the first on-chip storage.

[0116] The following will refer to Fig.14 The structure of the transpose module shown describes the process of transposing a matrix.

[0117] When the computing unit PE in the FHE chip is performing, for example, an NTT operation, when it is necessary to perform a transposition operation on the matrix M1, the matrix M1 can be stored in the N first subspaces stored on the first chip, and a transposition instruction can be sent to the transposition module, where the transposition instruction is used to instruct the matrix M1 stored in the first on-chip storage to be transposed.

[0118] Specifically, as described above, the matrix M1 is, for example, an E*E matrix (e.g., 128*128), and the matrix M1 can be divided into a plurality of blocks by a block size of K*K (e.g., 16*16). Fig. 9 The numbers 1, 2, 3, etc. in each block in the matrix M1 are used to represent the block number of the block. Through such division, the matrix M1 includes 8 column blocks and 8 row blocks. It can be understood that although the matrix M1 is described as a square matrix here, as described above, the matrix to be transposed is not limited to a square matrix, as long as it can be divided into an integer number of blocks.

[0119] The first on-chip storage and the second on-chip storage can be implemented as, for example, a static random access memory (SRAM), a random access memory (RAM), etc. For the matrix size of the matrix M1, the first on-chip storage can be divided into 8 first subspaces, each of which includes a read-write interface. The computing unit PE can store the 8 column blocks in the 8 first subspaces respectively. The first on-chip storage can address each block stored in the first subspace according to the block number through the read-write interface of each first subspace. For example, Fig.14As shown, the 0th column of blocks is stored in the 0th first subspace, including block 0, block 8, block 16, block 24, block 32, block 40, block 48 and block 56, and these blocks can be addressed through the read-write interface of the 0th first subspace, so they can be read separately.

[0120] Understandable, although Fig.14 It is shown that each block is stored in the first on-chip storage in the form of an array, specifically, a column of blocks is stored in the form of a column, which is merely illustrative and is not used to limit the specific form of the matrix stored in the first on-chip storage. For example, the first on-chip storage can store each column of blocks in the matrix M1 in the form of a logical column (rather than a physical column). In addition, this specification is not limited to storing a column of blocks in each first subspace. For example, the matrix M1 can be divided into N block groups, and a block group is stored in each first subspace, and each first subspace can address each block in the block group.

[0121] After performing the above storage, the computing unit PE may send a transposition instruction for the matrix M1 to each computing unit PE. i The transposition instruction includes, for example, information indicating the matrix M1 stored in the first on-chip storage. i It can be connected to a first subspace and used to read the blocks from the first subspace to which it is connected. Specifically, each computing unit PE i A hardware connection is established with a read / write interface of a first subspace of the first on-chip storage. i After receiving the transposition instruction, the number of rows of the block to be read may be calculated according to the total number of rows of the block array corresponding to the matrix M1 and the number of reading times rt.

[0122] Specifically, in the first round of transposition, each computing unit PE i It can be determined that each block on the diagonal line in the read block array, that is, 0, 9, 18, 27, 36, 45, 54, 63, can be read through 8 computing units PE i The 8 blocks are transposed in parallel. The reason for determining the block number to be read in this way is that the second on-chip storage includes 8 second subspaces similar to the first on-chip storage, each second subspace includes a read-write interface, and each second subspace can be used to store a column of transposed blocks in the transposed matrix. The blocks on the diagonal of the block array in the matrix M1 are not on the same row, so after transposition, the transposed blocks corresponding to each block will not be located in the same column, so that the 8 transposed blocks corresponding to the 8 blocks can be stored in parallel in the second on-chip storage.

[0123] Each transposition unit Tr i Including Fig.10 Alternatively, each transposition unit may include a systolic array as shown. Fig.13 The systolic array A1 and the systolic array A2 are shown for pipelined transposition processing of each block in a storage subspace.

[0124] Each computing unit PE i Respectively with the transposition unit Tr i Connect the hardware. Each computing unit PE i After determining the number of block rows to be read, a row of data in the block corresponding to the block number is read row by row through the read-write interface of the first subspace to which it is connected, and the row of data is stored row by row in a column of storage locations in the systolic array based on the pulsation of the systolic array in the row direction, similar to the description of step S901 above.

[0125] Each computing unit PE i As described above, the position of the transposed block corresponding to the block in the transposed matrix is ​​determined, and the position includes, for example, the block column number t and the block row number k in the second block array corresponding to the transposed block in the matrix M2. i The first block read, the number of rows k and the number of columns t of the corresponding transposed block can be sent to the transposition unit Tr connected thereto. i After receiving the above data, the transposition unit may store the number of rows k and the number of columns t in a specific register, and transpose the first block to obtain a second block.

[0126] Each transposition unit Tr i The transposition units are respectively connected to the input ports of the MIN network (hereinafter referred to as MIN), and each transposition unit can input the data stored in each row storage position in the systolic array (i.e., the row data of the second block) to the input port of the MIN row by row, and can also input the number of rows and columns of the second block to the input port of the MIN. The output port of the MIN is connected to each second subspace of the second storage space.

[0127] For example, the computing unit PE1 reads the block 17 from the first slice according to the calculated number of rows of blocks to be read j=2, and determines the corresponding transposed block 17 T The number of columns t = 2, the number of rows k = 1 (shown in the figure as the write-back block number), the number of columns t ( Fig.13 The number of rows k is sent to the transposition unit Tr1, and the transposition unit Tr1 transposes the block 17 to obtain its transposed block 17. T , transpose block 17 T , column number t and row number k are transmitted to the MIN network.

[0128] Fig.15It is a schematic diagram of the structure of the MIN network in the embodiment of this specification.

[0129] like Fig.15 As shown, each of the above transposition units Tr i It may include 2 output ports for connecting to the MIN, and the N=8 transposition units may include 2*8=16 output ports for connecting to the MIN. Different output ports have different output addresses. Usually, the output addresses can be assigned to the 16 output ports using a bit sequence of length 4 starting from 1 according to the arrangement order of the 8 transposition units. Each second subspace S in the second on-chip storage 2i May include 2 input ports for connecting to MIN, N=8 second subspaces S 2i It may include 2*8=16 input ports for connecting to the MIN, different input ports have different input addresses, and the input addresses can usually be allocated to the 16 input ports using a bit sequence of length 4 starting from 1 according to the arrangement order of the 8 second calculation units.

[0130] MIN may include at least one of the networks such as Benes Network, Omega Network, Baseline Network, Butterfly Network, etc.

[0131] MIN may include N*M switching units divided into M levels, such as level 0 to level M-1; for any level in the M levels, the number of switching units belonging to that level in MIN is N. Depending on the network type of MIN, the number of levels M may be different. The value of the number of transposition units N is 2 k-1 In the case of: For Omega Network, Baseline Network, Butterfly Network and other types of networks, the value of M is k; for Benes Network, the value of M is 2k-1.

[0132] For MIN N=8, a bit sequence of length 4 can be used to represent the input addresses of the 16 input ports of the 8 switching units belonging to the same level, and a bit sequence of length 4 can be used to represent the output addresses of the 16 output ports of the 8 switching units belonging to the same level.

[0133] Depending on the type of MIN, two output ports belonging to the same transposition unit may be connected to the same switching unit belonging to the first level in the MIN, or may be connected to different switching units belonging to the first level in the MIN. Two input ports belonging to the same second subspace are connected to the same switching unit belonging to the second level in the MIN, while input ports belonging to different second calculation units are connected to different switching units belonging to the second level in the MIN. The first level and the second level are the highest level and the lowest level in the m levels, in other words, the first level is 0 and the second level is m-1, or the first level is m-1 and the second level is 0.

[0134] Refer to the above Fig.12 By setting the connection between the systolic array and the input port of the MIN to connect the registers with higher column numbers of the systolic array to the higher-order data lines of the input port of the MIN and connect the registers with lower column numbers of the systolic array to the lower-order data lines of the input port of the MIN, a row of data in the systolic array transmitted from the systolic array to the input port of the MIN can be the transposed blocked row data.

[0135] Specifically, taking the transposition unit Tr2 as an example, in the first round of transposition, the transposition unit Tr2 transposes the block 18, thereby converting the transposed block 18 row by row. T The transposition unit Tr2 can select any one of its two output addresses (for example, 0101) to send the transposed block 18. T Each row of data and block 18 T At the same time, the transposition unit Tr2 can be based on the transposition block 18 T The column number determines the transposition block 18 T Each row of data and row number is sent to the second subspace S corresponding to the second column 22 , the transposition unit Tr2 can select the second subspace S 22 Any input address (e.g. 0100) is used as the destination address for receiving data. Then, the transposition unit Tr2 can transpose the block 18 row by row. T The row data, row number and destination address 0100 are sent to the address "1010" in level 0 in the MIN connected to its output address "0101".

[0136] MIN can be divided into blocks 18 according to the destination address. T Each row of data and the row number of block 18 are routed.

[0137] The switching unit may be a functional switching unit including two input ports and two output ports. In the following, the input port with a larger input address included in the same switching unit is described as a high-address input port, and the input port with a smaller input address is described as a low-address input port; similarly, the output port with a larger output address is described as a high-address output port, and the output port with a smaller output address is described as a low-address output port. The switching unit includes two working modes, which are here referred to as pass-through and crossover.

[0138] When the working mode of the switching unit is pass-through, the high-address input port and the high-address output port are connected, and the low-address input port and the low-address output port are connected. In this case, the switching data entering the switching unit through the high-address input port is output from the high-address output port of the switching unit; the switching data entering the switching unit through the low-address input port is output from the low-address output port of the switching unit.

[0139] When the working mode of the switching unit is crossover, the high-address input port and the low-address output port are connected, and the low-address input port and the high-address output port are connected. In this case, the switching data entering the switching unit through the high-address input port is output from the low-address output port of the switching unit; the switching data entering the switching unit through the low-address input port is output from the high-address output port of the switching unit.

[0140] When a transposition unit inputs data to the MIN through the output address of the bit sequence s3s2s1s0 and specifies the destination address as the bit sequence d3d2d1d0, the switching unit in the MIN can route the switching data only according to the bit sequence d3d2d1d0, or can route the switching data according to the bit sequence s3s2s1s0 and the bit sequence d3d2d1d0.

[0141] When MIN routes the exchanged data according to the destination address, that is, the switching unit in MIN only routes the data according to the bit sequence d3d2d1d0: for the switching unit belonging to any level q, the output port can be determined according to the length of the bit sequence. For example, when the length of the bit sequence is 4, the output port can be determined according to the d in the bit sequence d3d2d1d0. 4-1-qDetermine the output port, that is, select the 4-qth bit from the bit sequence d3d2d1d0 in order from low to high to determine the output port; specifically: when the value of the 4-qth bit is 0, the switching data is output from the low address output port, and when the value of the 4-qth bit is 1, the switching data is output from the high address output port. In this way, the switching unit belonging to level 0 needs to use d3 in the bit sequence d3d2d1d0 to determine the output port, the switching unit belonging to level 1 needs to use d2 in the bit sequence d3d2d1d0 to determine the output port, the switching unit belonging to level 2 needs to use d1 in the bit sequence d3d2d1d0 to determine the output port, and the switching unit belonging to level 3 needs to use d1 in the bit sequence d3d2d1d0 to determine the output port. More specifically, when d 4-1-q When the value of d is 0, the switching unit can select a certain working mode between pass-through and crossover to ensure that the switching data is output from the low address output port; when d 4-1-q When the value is 1, the switching unit can select a certain working mode between pass-through and crossover to ensure that the switching data is output from the high-address output port.

[0142] Specifically, as described above, the transposition unit Tr2 determines that the destination address of the data is 0100, and after sending the data to the address "1010" in level 0, the reference Fig.15 As shown, the switching unit belonging to level 0 selects the 4th bit in 0100 to determine the working mode. Since the 4th bit is 0, the switching unit belonging to level 0 outputs data from its low address output port (i.e., 1010); based on a similar principle, the switching unit belonging to level 1 outputs data from its high address output port (i.e., 0101), the switching unit belonging to level 2 outputs data from its low address output port (i.e., 1010), and the switching unit belonging to level 3 outputs data from its low address output port (i.e., 0100), so that the data reaches S from the input port with an input address of 0100. 22 .

[0143] In another embodiment, when the MIN performs routing transmission on the exchanged data according to the connection relationship, that is, when the switching unit in the MIN implements routing transmission on the exchanged data according to the bit sequence s3s2s1s0 and the bit sequence d3d2d1d0: the switching unit can perform routing transmission on the exchanged data in the same space through x=s dCalculate the target sequence, where s is the value of the bit sequence s3s2s1s0, d is the value of the bit sequence d3d2d1d0 and x is the value of the target bit sequence. Here, the target bit sequence is denoted by x3x2x1x0. For a switching unit belonging to any level q, the working mode can be determined according to the length of the bit sequence. For example, when the length of the bit sequence is 4, the x in the bit sequence x3x2x1x0 can be used. 4-1-q Determine the output port, that is, select the 4-qth bit from the bit sequence x3x2x1x0 in order from low to high to determine the working mode; specifically: when the value of the 4-qth bit is 0, the working mode selects pass-through, and when the value of the 4-qth bit is 1, the working mode selects crossover. In this way, the switching unit belonging to level 0 needs to use x3 in the bit sequence x3x2x1x0 to determine the working mode, the switching unit belonging to level 1 needs to use x2 in the bit sequence x3x2x1x0 to determine the working mode, the switching unit belonging to level 2 needs to use x1 in the bit sequence x3x2x1x0 to determine the working mode, and the switching unit belonging to level 3 needs to use x1 in the bit sequence x3x2x1x0 to determine the working mode.

[0144] After the MIN network routes the data including each row of transposed block data and its corresponding row number to each second subspace row by row, each second subspace stores the transposed block in the corresponding row.

[0145] After the first round of transposition operation is completed as described above, the second round of transposition operation can be started in the transposition module.

[0146] As mentioned above, it is assumed that each transposition unit includes Fig.13 In the structure shown, for 16*16 blocks, each computing unit can store each target block in the first round of transposition operation into the systolic array A1 of the corresponding transposition unit from the 1st clock cycle to the 16th clock cycle. After starting the first round of transposition operation, each computing unit can add 1 to the value of the number of reads stored in the register of each acceleration unit, and then determine the next block number to be read based on the value of the number of reads and the number of block columns i corresponding to the acceleration unit. And each target block in the second round of transposition operation can be stored in the systolic array A2 of the corresponding transposition unit from the 17th clock cycle to the 32nd clock cycle.

[0147] For example, when the value of the counter of the computing unit PE0 is 1, the number of rows of the block to be read can be calculated as 0+1=2. Therefore, the computing unit PE0 can store the block 8 in the systolic array A2 of the transposition unit Tr0 from the 17th clock cycle to the 32nd clock cycle to transpose the block 8. Similarly, the other computing units can store the blocks 17, 26, 35, 44, 53, 62 and 7 in the systolic array A2 of each transposition unit from the 17th clock cycle to the 32nd clock cycle to transpose in parallel.

[0148] At the same time, each computing unit also determines the number of columns and rows of the transposed blocks corresponding to each block, and transmits the number of columns and rows of each block and the transposed blocks to each transposition unit.

[0149] After transposing the blocks, each transposition unit obtains a transposed block, and determines the destination address of the MIN corresponding to the transposed block according to the number of columns of the transposed block, and sends the data, destination address and number of rows of the transposed block to the MIN through its input address, thereby performing inter-block transposition on each transposed block.

[0150] Specifically, taking the transposition unit Tr2 as an example, in the second round of transposition, the transposition unit Tr2 transposes the block 26. The transposition unit Tr2 can select any one of its two output addresses (for example, 0100) to transmit the transposed block 26. T Each row of data and transposed block 26 T At the same time, the transposition unit Tr2 can be based on the transposition block 26 T The number of columns of the corresponding transposed block column (i.e., the 3rd column) determines the transposed block 26 T The row data and row number of each row are sent to the second subspace S corresponding to the third column 23 , the transposition unit Tr2 can select the second subspace S 23 Any input address (such as 0110) is used as the destination address for receiving data. Then, refer to Fig.15 , the transposition unit Tr2 can transpose the block 26 T The data of each row, the number of rows and the destination address 0110 are sent to the address "1000" in the level 0 of the MIN connected to its output address "0100". The switching units at all levels in the MIN can route the data according to the destination address 0110 similarly to the above, thereby converting the transposed block 26 T Each row of data and the number of rows in block 26 are sent to the second subspace S 23 .

[0151] The transposition module can store the transposed matrix of the matrix M1 in the second on-chip storage through multiple rounds of transposition operations similar to the above process. For a 128*128 matrix M1, the transposition module can complete the transposition of the matrix M1 through 128 clock cycles.

[0152] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0153] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0154] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a server system. Of course, the present application does not exclude that with the development of computer technology in the future, the computer that implements the functions of the above embodiments may be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0155] Although one or more embodiments of the present specification provide method operation steps as described in the embodiments or flow charts, more or less operation steps may be included based on conventional or non-creative means. The order of steps listed in the embodiments is only one way of executing the order of many steps, and does not represent the only execution order. When the device or terminal product in practice is executed, it can be executed in sequence or in parallel according to the method shown in the embodiments or the drawings (for example, a parallel processor or a multi-threaded processing environment, or even a distributed data processing environment). The term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, product or equipment. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or equipment including the elements. For example, if the words first, second, etc. are used to represent the name, they do not represent any specific order.

[0156] For the convenience of description, the above devices are described in various modules according to their functions. Of course, when implementing one or more of the present specification, the functions of each module can be implemented in the same or more software and / or hardware, or the module implementing the same function can be implemented by a combination of multiple sub-modules or sub-units, etc. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0157] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0158] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0159] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0160] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0161] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0162] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage, graphene storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0163] It should be understood by those skilled in the art that one or more embodiments of the present specification may be provided as a method, system or computer program product. Therefore, one or more embodiments of the present specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, one or more embodiments of the present specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0164] One or more embodiments of the present specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of the present specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0165] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. In the description of this specification, the description of the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0166] The above description is only an example of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. For those skilled in the art, one or more embodiments of the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims.

Claims

1. A matrix transposition method, performed by a transposition module, the transposition module comprising a first storage space, a second storage space and N acceleration units, the first storage space storing a first matrix, the first matrix corresponding to a first block array consisting of M rows×N columns of blocks, the N acceleration units corresponding to the N block columns respectively, the method comprising: The i-th acceleration unit determines, based on i, M, and the number of times the i-th acceleration unit reads the i-th block column in the first block array, the number of rows j of the blocks to be read in the i-th block column and the position information of the transposed blocks corresponding to the blocks to be read in the second block array, wherein the second block array corresponds to a second matrix, and the second matrix is ​​the transposed matrix of the first matrix; The i-th acceleration unit reads the first block from the i-th block column based on the row number j of the to-be-read blocks; The i-th acceleration unit transposes the first block to obtain a second block; The i-th acceleration unit stores the second block in the second storage space based on the position information.

2. According to the method of claim 1, M is less than N, the second block array includes M rows×N columns of blocks, and the position information includes the number of rows k and columns t of the second block in the second block array.

3. The method according to claim 2, wherein the i-th acceleration unit determines the number j of rows of blocks to be read in the i-th block column based on the i, the M, and the number of times the i-th acceleration unit reads the i-th block column in the first block array, comprising: The i-th acceleration unit divides the first block array into M-row×M-column block arrays, and determines the number of rows j based on the number of columns of the i-th block column in its corresponding first block array and the number of reads.

4. According to the method of claim 3, the first block matrix includes filled block columns.

5. According to the method of claim 3, the number of rows k corresponding to the transposed block is the number of columns of the i-th column of the block in the first block array in its corresponding first block matrix.

6. The method according to claim 2, wherein the number of columns of the first matrix is ​​greater than the number of rows, and the method further comprises: After storing the second block array in the second storage space, the second storage space divides the second block array into M-row×M-column block matrixes to obtain multiple second block matrixes, and provides the second matrix based on the multiple second block matrixes.

7. According to the method of claim 2, the number of rows of the first matrix is ​​greater than the number of columns, and the method further includes: the first storage space divides the first matrix according to a preset block size to obtain a third block array; the first storage space divides the third block array into a block matrix of M rows × M columns, and obtains the first block array based on the divided third block array.

8. The method according to claim 2, wherein the transposition module comprises a multi-stage switching network MIN, the MIN is connected to the N acceleration units, the second storage space comprises N second subspaces arranged in sequence, each second subspace comprises a read-write interface for storing a column of blocks of the second block array, The i-th acceleration unit stores the second block in the second storage space based on the position information, including: The i-th acceleration unit sends the second block, the row number k, and the target address corresponding to the target read / write interface corresponding to the column number t to the MIN; The MIN transmits the second block and the row number k to the read / write interface of the t-th second subspace based on the target address; The second subspace stores the second block in the kth row of the tth column of the second block array based on the k.

9. The method according to claim 1, wherein: The i-th acceleration unit includes a register, and the value stored in the register is used to indicate the number of reads. The method also includes: the i-th acceleration unit reads the value of the number of reads from the register, and adds 1 to the value stored in the register.

10. The method according to claim 1, wherein each of the acceleration units comprises a first computing unit and a storage array, and the i-th acceleration unit transposing the first block comprises: The first computing unit in the i-th acceleration unit stores each row of data of the first block stored in the first storage space into a column of storage locations in the first storage array row by row based on the pulsation of data in the row direction by the storage array in the i-th acceleration unit; The storage array in the i-th acceleration unit outputs the data stored in each row of storage locations in the first storage array as the row data of the second block by pulsating the data in the column direction.

11. A transposition module, comprising a first storage space, a second storage space and N acceleration units, wherein the first storage space stores a first matrix, the first matrix corresponds to a first block array consisting of M rows×N columns of blocks, the N acceleration units correspond to the N block columns respectively, The i-th acceleration unit corresponding to the i-th block column of the first block array is used to perform the following operations: Based on i, M, and the number of times the i-th acceleration unit reads the i-th block column in the first block array, determine the number of rows j of the blocks to be read in the i-th block column and the position information of the transposed blocks corresponding to the blocks to be read in the second block array, wherein the second block array corresponds to a second matrix, and the second matrix is ​​the transposed matrix of the first matrix; Based on the row number j of the blocks to be read, read the first block from the i-th block column; Transposing the first block to obtain a second block; Based on the location information, the second block is stored in the second storage space.

12. A chip, comprising a computing unit and the transposition module according to claim 11, wherein the computing unit is used to store the first matrix in the first storage space and instruct the transposition module to perform transposition processing on the first matrix.

Images