An FPGA single event upset detection system and method

Abstract

The application discloses an FPGA single event upset detection system and method, and relates to the field of FPGA testing.The system comprises a host computer, a test mainboard and a test subboard.The test subboard comprises an FPGA to be tested.The test mainboard configures an original code stream file sent by the host computer to the FPGA to be tested, and successively increases the same fluence to perform a single event irradiation test on the FPGA to be tested for multiple test periods, and reads back a read-back code stream file of each test period.The host computer compares the read-back code stream file of the current test period with a read-back code stream file of the last test period, determines the occurrence position of single event upset in the current test period, accumulates the number of single event upsets of each occurrence position, and obtains the total number of single event upsets under the total fluence of the current test period.The application solves the problems that the occurrence position of single event upset cannot be detected and the multiple single event upsets of the same circuit unit cannot be detected.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of Field Programmable Gate Array (FPGA) testing, in particular to an FPGA single event upset detection system and method. BACKGROUND

[0002] With the development of integrated circuit technology, the application of FPGA in the field of aerospace puts forward higher requirements for reliability. Therefore, reliability has gradually become an important problem that needs to be considered equally with performance when designing FPGA. Especially in the space environment, FPGA is easily affected by single event effects, which can cause the content of the logic unit in the FPGA to flip and lock, resulting in FPGA failure. Before designing a fault-tolerant FPGA, in-depth single event effect sensitivity analysis is needed, especially the behavior characteristics of FPGA when single event effects occur. The detection of single event upset is an important technology for evaluating the reliability of FPGA, so the research and design of the single event upset detection tool are of great significance.

[0003] A related single event upset detection method is to read the configuration file from the FPGA and compare it with the original configuration file, and transmit the number of errors to the host computer through the serial port for analysis. The main shortcomings of this method are: in the single event upset test, only the number of flips can be obtained, the specific flip position cannot be known, and it is difficult to target the FPGA for single event hardening; at the same time, the single event upset of each circuit unit can only be recorded at most once, and the case of more than twice flip of the same circuit unit cannot be recorded, resulting in the most sensitive area of single event upset being ignored in radiation hardening. SUMMARY

[0004] The purpose of the present application is to provide an FPGA single event upset detection system and method, which solves the problems of being unable to detect the position of single event upset and being unable to detect the case of multiple single event upsets of the same circuit unit.

[0005] To achieve the above-mentioned purpose, the present application provides the following solutions:

[0006] In a first aspect, the present application provides an FPGA single event upset detection system, which comprises a host computer, a test board and a test sub-board; the test sub-board comprises a to-be-tested FPGA; the host computer is connected with the test board; the test board is connected with the to-be-tested FPGA;

[0007] The host computer is configured to:

[0008] send an original code stream file to the test board;

[0009] The test board is configured to:

[0010] configuring the original code stream file to the to-be-tested FPGA;

[0011] reading back the code stream file of the to-be-tested FPGA in each test period under single event upset test, to obtain a read-back code stream file of each test period; the single event upset test is a test of performing single event upset on the to-be-tested FPGA by increasing the same fluence step by step from the first test period to the last test period; the total fluence of the last test period reaches a rated total fluence;

[0012] sending the read-back code stream file of each test period to the host computer;

[0013] The host computer is further configured to:

[0014] compare the read-back code stream file of the current test period with the read-back code stream file of the last test period, determine the occurrence position of single event upset in the current test period, and accumulate the number of single event upsets at each occurrence position, to obtain the total number of single event upsets under the total fluence of the current test period.

[0015] Optionally, for reading back the code stream file of the to-be-tested FPGA in each test period under single event upset test, to obtain a read-back code stream file of each test period, the test board is specifically configured to:

[0016] for any test period under single event upset test, reading back the triple modular redundancy code stream of the current test period by using a triple modular redundancy structure; the triple modular redundancy code stream comprises a first code stream file, a second code stream file and a third code stream file of the to-be-tested FPGA;

[0017] determining the read-back code stream file of the current test period by using a majority voter according to the triple modular redundancy code stream of the current test period.

[0018] Optionally, the test board is further configured to:

[0019] for any test period under single event upset test, determining the number of single event transients by using a source determinator according to the triple modular redundancy code stream of the current test period.

[0020] Optionally, the test board comprises a processing FPGA and a memory; the processing FPGA is connected with the host computer, the memory and the to-be-tested FPGA respectively;

[0021] The processing FPGA is configured to:

[0022] send the original code stream file to the memory;

[0023] The memory is configured to:

[0024] buffering the original bitstream file;

[0025] the processing FPGA is further configured to:

[0026] configure the memory-buffered original bitstream file to the FPGA under test;

[0027] read back the bitstream file of the FPGA under test in each test cycle under the single event upset test to obtain a read-back bitstream file of each test cycle;

[0028] the memory is further configured to:

[0029] buffer the read-back bitstream file of each test cycle;

[0030] the processing FPGA is further configured to:

[0031] send the memory-buffered read-back bitstream file of each test cycle to the host computer.

[0032] Optionally, the processing FPGA comprises a data control module, an Ethernet interface and a SelectMap interface.

[0033] The data control module is connected with the memory, the data control module is connected with the host computer through the Ethernet interface, and the data control module is connected with the FPGA under test through the SelectMap interface.

[0034] The Ethernet interface is configured to:

[0035] send the original bitstream file to the data control module;

[0036] The data control module is configured to:

[0037] send the original bitstream file to the memory;

[0038] configure the memory-buffered original bitstream file to the FPGA under test through the SelectMap interface;

[0039] read back the bitstream file of the FPGA under test in each test cycle through the SelectMap interface under the single event upset test to obtain a read-back bitstream file of each test cycle;

[0040] send the memory-buffered read-back bitstream file of each test cycle to the host computer through the Ethernet interface.

[0041] Optionally, the processing FPGA further comprises a serial port.

[0042] The data control module is connected with the host computer through the serial port;

[0043] The serial port is used to send control instructions to the host computer; the control instructions include: code stream input instruction, code stream configuration instruction, code stream read-back instruction and memory reading instruction;

[0044] The host computer is used to:

[0045] When the code stream input instruction is received, the Ethernet interface is controlled to send the original code stream file to the data control module and buffer in the memory;

[0046] When the code stream configuration instruction is received, the original code stream file buffered in the memory is controlled to be configured to the FPGA under test through the SelectMap interface;

[0047] When the code stream read-back instruction is received, the SelectMap interface is controlled to read back the code stream file of the FPGA under test in the current test cycle, obtain the read-back code stream file in the current test cycle, and buffer in the memory;

[0048] When the memory reading instruction is received, the Ethernet interface is controlled to obtain the read-back code stream file in the current test cycle buffered in the memory.

[0049] Optionally, the source judging device is an AND gate.

[0050] In a second aspect, the application provides an FPGA single event upset detection method, which is used in the FPGA single event upset detection system and includes the following steps:

[0051] Obtaining an original code stream file;

[0052] Configuring the original code stream file to the FPGA under test;

[0053] Under the single event upset test, reading back the code stream file of the FPGA under test in each test cycle to obtain the read-back code stream file in each test cycle; the single event upset test is a test in which the same fluence is increased from the first test cycle to the last test cycle to irradiate the FPGA under test; the total fluence in the last test cycle reaches the rated total fluence;

[0054] Sending the read-back code stream file in each test cycle to the host computer;

[0055] The host computer compares the read-back code stream file of the current test cycle with the read-back code stream file of the last test cycle, determines the occurrence position of the single event upset in the current test cycle, and accumulates the number of single event upsets at each occurrence position to obtain the total number of single event upsets under the total fluence of the current test cycle.

[0056] Optionally, under the single event upset test, the code stream file of the to-be-tested FPGA in each test cycle is read back to obtain a read-back code stream file of each test cycle, and the read-back code stream file of each test cycle specifically includes:

[0057] Under the single event upset test, for any test cycle, the triple modular redundancy code stream of the current test cycle is read back by using a triple modular redundancy structure; the triple modular redundancy code stream includes a first code stream file, a second code stream file and a third code stream file of the to-be-tested FPGA.

[0058] According to the triple modular redundancy code stream of the current test cycle, a majority voter is used to determine the read-back code stream file of the current test cycle.

[0059] Optionally, after the triple modular redundancy code stream of the current test cycle is obtained, the FPGA single event upset detection method further includes:

[0060] According to the triple modular redundancy code stream of the current test cycle, a source determinator is used to determine the number of single event transients.

[0061] According to the specific embodiments provided in the present application, the present application has the following technical effects:

[0062] The present application provides an FPGA single event upset detection system and method, which includes a host computer, a test backplane and a test subboard; the test subboard includes a to-be-tested FPGA; the test backplane reads back a read-back code stream file of each test cycle by using an incremental detection method; and the host computer compares the read-back code stream file of the current test cycle with the read-back code stream file of the last test cycle, which can not only determine the occurrence position of the single event upset in the current test cycle, but also obtain the total number of single event upsets under the total fluence of the current test cycle, thereby solving the problems of being unable to detect the occurrence position of the single event upset and being unable to detect the multiple single event upsets of the same circuit unit. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0064] Figure 1A structure schematic diagram of an FPGA single event upset detection system provided by an embodiment of the present application is shown in the figure;

[0065] Figure 2 A principle diagram of a three-module redundancy structure provided by an embodiment of the present application is shown in the figure;

[0066] Figure 3 A flow schematic diagram of an FPGA single event upset detection method provided by another embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be apparently and completely described below with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0068] In order to make the above objects, features and advantages of the present application more obvious and understandable, the present application will be further described in detail below with the accompanying drawings and specific embodiments.

[0069] Referring to Figure 1 , the embodiment of the present application provides an FPGA single event upset detection system, which comprises a host computer, a test backboard and a test subboard. The test subboard comprises a to-be-tested FPGA. The host computer is connected with the test backboard. The test backboard is connected with the to-be-tested FPGA.

[0070] The host computer is configured to send an original code stream file to the test backboard. The original code stream file is a binary file format FPGA configuration file.

[0071] The test backboard is configured to configure the original code stream file to the to-be-tested FPGA. Under a single event upset test, a code stream file of the to-be-tested FPGA in each test period is read back to obtain a read-back code stream file in each test period. The single event upset test is a test in which the to-be-tested FPGA is subjected to single event upset by gradually increasing the same fluence from the first test period to the last test period. The read-back code stream file in each test period is sent to the host computer. The total fluence of the first test period is an initial total fluence, the total fluence of the last test period reaches a rated total fluence, the fluence is increased by the same amount each time, the total fluence is cumulatively increased each time from the initial total fluence until the rated total fluence is reached. For example, in a single event upset test with a rated total fluence of 10 7 , the read-back code stream file obtained by reading back immediately after configuration is the read-back code stream file in the first test period, and the total fluence is increased by 10% (i.e. 10 6read back once until the total fluence reaches the rated total fluence 10 7 Wherein, the read back means that the FPGA under test sends its configuration file to the receiving end of the test board.

[0072] The host computer is further configured to compare the read back code stream file of the current test cycle with the read back code stream file of the last test cycle, determine the occurrence positions of single event upsets in the current test cycle, and accumulate the number of single event upsets at each occurrence position to obtain the total number of single event upsets under the total fluence of the current test cycle. The host computer can be a computer that sends operation commands to the test board and performs post-analysis on data.

[0073] In this embodiment, the host computer is placed in a test monitoring room and is used for test setting, test process control and test result processing; the test board and the test sub-board are placed in an irradiation test room.

[0074] In this embodiment, the complete read back code stream file is sent to the host computer to obtain the occurrence positions of all single event upsets, solving the problem that the single event upset test cannot obtain accurate occurrence positions; an incremental detection method is adopted, i.e., the read back code stream file of each test cycle is compared with the read back code stream file of the last test cycle instead of being compared with the original code stream file, solving the problem that the single event upset of the same circuit unit can only be detected once, i.e., the condition that the single event upset of the same circuit unit can be detected multiple times is realized.

[0075] In one exemplary embodiment, for reading back the code stream file of the FPGA under test in each test cycle under the single event upset test to obtain the read back code stream file of each test cycle, the test board is specifically configured to: under the single event upset test, for any test cycle, read back the triple modular redundancy code stream of the current test cycle using a triple modular redundancy (TMR) structure; the triple modular redundancy code stream includes a first code stream file, a second code stream file and a third code stream file of the FPGA under test. According to the triple modular redundancy code stream of the current test cycle, a majority voter is used to determine the read back code stream file of the current test cycle. The schematic diagram of the triple modular redundancy structure is shown in Figure 2 .

[0076] Wherein, the triple modular redundancy is a common single event effect mitigation method. Three completely identical redundant calculation paths are used, and when there is no fault, all redundant units should have the same output. The output of each redundant unit is compared with other redundant units through a majority voter. If the output of one of the redundant units is inconsistent with the other two redundant units, the majority voter will still produce a correct output.

[0077] In an exemplary embodiment, due to the related FPGA single event upset detection mode, the periodic code stream back reading is performed in the irradiation environment, and it is unable to confirm whether the error in the back reading code stream originates from the single event upset of the device or the single event transient in the code stream reading process. Therefore, still referring to Figure 2 The test board in the embodiment is also used for: under the single event upset test, for any test period, determining the number of single event transients according to the triple modular redundancy code stream of the current test period by using a source determinator. The source determinator can be an AND gate.

[0078] The embodiment separates the error introduced by the dynamic back reading in the single event test, and further improves the accuracy of the single event test by comparing the data after redundancy (i.e., the triple modular redundancy code stream). Meanwhile, by comparing the results of each path in the triple modular redundancy code stream, the single event transient phenomenon in the back reading process can be analyzed.

[0079] In an exemplary embodiment, still referring to Figure 1 The test board comprises a processing FPGA and a memory. The processing FPGA is connected with the host computer, the memory and the FPGA under test respectively.

[0080] The processing FPGA is used for sending the original code stream file to the memory.

[0081] The memory is used for buffering the original code stream file.

[0082] The processing FPGA is also used for configuring the original code stream file buffered by the memory to the FPGA under test. Under the single event upset test, the code stream file of the FPGA under test in each test period is back read to obtain the back reading code stream file in each test period.

[0083] The memory is also used for buffering the back reading code stream file in each test period.

[0084] The processing FPGA is also used for sending the back reading code stream file in each test period buffered by the memory to the host computer.

[0085] In the embodiment, the memory can be a double data rate synchronous dynamic random access memory (DDR).

[0086] In an exemplary embodiment, due to the insufficient transmission rate of the serial port, the configuration and back reading of a large-scale FPGA will take more than one minute, and the real-time performance and accuracy of the detection result cannot be guaranteed. Therefore, still referring to Figure 1The processing FPGA includes a data control module, an Ethernet interface and a SelectMap interface. The data control module is connected with the memory. The data control module is connected with the host computer through the Ethernet interface. The data control module is connected with the to-be-tested FPGA through the SelectMap interface. The SelectMap interface is an interface for configuring the FPGA through input and output pins.

[0087] The Ethernet interface is used for sending the original code stream file to the data control module.

[0088] The data control module is used for sending the original code stream file to the memory. The original code stream file cached in the memory is configured to the to-be-tested FPGA through the SelectMap interface. Under the single event upset test, the code stream file of the to-be-tested FPGA in each test period is read back through the SelectMap interface, and the read-back code stream file in each test period is obtained. The read-back code stream file in each test period cached in the memory is sent to the host computer through the Ethernet interface.

[0089] In the embodiment, before the single event upset test, the data control module sends the initial code stream file received by the Ethernet interface to the memory, and then reads the stored initial code stream file from the memory and sends the initial code stream file to the SelectMap interface for configuration. During the single event upset test, the data control module regularly carries the code stream file read back from the to-be-tested FPGA and input to the SelectMap interface to the memory, reads the stored read-back code stream file from the memory, and sends the read-back code stream file to the Ethernet interface. The host computer compares the read-back code stream file of the last test period with the read-back code stream file, and calculates the accurate occurrence position of the single event upset in each test period. In the embodiment, the Ethernet interface is used for transmitting the code stream file, which can greatly reduce the transmission time, provides a hardware basis for redundant data transmission, and improves the real-time performance and accuracy of the single event upset detection.

[0090] In one exemplary embodiment, still referring to Figure 1 , the processing FPGA further includes a serial port. The data control module is connected with the host computer through the serial port.

[0091] The serial port is used for sending a control instruction to the host computer. The control instruction includes a code stream input instruction, a code stream configuration instruction, a code stream read-back instruction and a memory reading instruction.

[0092] The host computer is configured to: when receiving the code stream input instruction, control the Ethernet interface to send the original code stream file to the data control module and cache the original code stream file in the memory; when receiving the code stream configuration instruction, control the original code stream file cached in the memory to be configured to the to-be-tested FPGA through the SelectMap interface; when receiving the code stream back-reading instruction, control the SelectMap interface to back-read the code stream file of the to-be-tested FPGA in the current test cycle, obtain a back-reading code stream file in the current test cycle, and cache the back-reading code stream file in the memory; and when receiving the memory reading instruction, control the Ethernet interface to obtain the back-reading code stream file in the current test cycle cached in the memory.

[0093] In the embodiment, the host computer and the test board transmit data through the serial port and the Ethernet interface, and the test board and the test sub-board transmit data through an FPGA mezzanine card (FMC) interface.

[0094] In actual application, a specific implementation process of the FPGA single event upset detection system in the above embodiment of the application can be described as follows: (1) the host computer sends an original code stream file to the memory through the Ethernet interface for caching; (2) the original code stream file cached in step (1) is configured to the to-be-tested FPGA through the SelectMap interface; (3) a single event upset source is turned on to perform single event upset on the to-be-tested FPGA and start the single event upset test; (4) after a predetermined time, three code stream files (i.e. three-mode redundant code streams) of the to-be-tested FPGA are back-read from the SelectMap interface to the memory in a timely manner by using a three-mode redundant structure; (5) the host computer receives the three-mode redundant code streams cached in step (4); (6) the three-mode redundant code streams in step (4) are compared to analyze single event transient errors in the path, record the number of dynamic back-reading single event transients, and calculate the back-reading code stream file by using a majority voter and cache the back-reading code stream file in the memory, and the back-reading code stream file is sent from the memory to the host computer through the Ethernet; (7) the host computer compares the back-reading code stream file in the current test cycle in step (6) with the back-reading code stream file in the last test cycle bit by bit to obtain the occurrence position of the single event upset in the current test cycle, wherein, if the current test cycle is the first test cycle, the back-reading code stream file in the current test cycle is compared with the original code stream file to obtain the occurrence position of the single event upset in the current test cycle; (8) the number of single event upsets at each position is accumulated to obtain the total number of single event upsets under the total fluence in the current test cycle; (9) steps (4) to (8) are repeated until the total fluence of the single event upset reaches a rated total fluence.

[0095] The above embodiment of the present application provides a system for obtaining the accurate position of FPGA single event upset, detecting multiple single event upsets, distinguishing the error source of single event effect, improving the real-time performance and accuracy of single event upset detection, and achieving incremental detection of FPGA single event upset and transient.

[0096] Another embodiment of the present application further provides a FPGA single event upset detection method for the FPGA single event upset detection system.

[0097] Referring to Figure 3 , the FPGA single event upset detection method comprises the following steps.

[0098] Step 301: obtaining an original code stream file.

[0099] Step 302: configuring the original code stream file to a to-be-tested FPGA.

[0100] Step 303: under a single event upset test, reading back the code stream file of the to-be-tested FPGA in each test period to obtain a read-back code stream file of each test period.

[0101] The single event upset test is a test of increasing the same fluence of the to-be-tested FPGA by single event irradiation from the first test period to the last test period; and the total fluence of the last test period reaches the rated total fluence.

[0102] Step 304: sending the read-back code stream file of each test period to the host computer.

[0103] Step 305: the host computer compares the read-back code stream file of the current test period with the read-back code stream file of the last test period, determines the occurrence position of single event upset in the current test period, and accumulates the number of single event upsets at each occurrence position to obtain the total number of single event upsets under the total fluence of the current test period.

[0104] In an exemplary embodiment, step 303 specifically comprises: under the single event upset test, for any test period, reading back the triple modular redundancy code stream of the current test period by using the triple modular redundancy structure.

[0105] The triple modular redundancy code stream comprises a first code stream file, a second code stream file and a third code stream file of the to-be-tested FPGA.

[0106] According to the triple modular redundancy code stream of the current test cycle, a majority voter is used to determine the read-back code stream file of the current test cycle.

[0107] In an exemplary embodiment, after obtaining the triple modular redundancy code stream of the current test cycle, the FPGA single event upset detection method further comprises: according to the triple modular redundancy code stream of the current test cycle, using a source determinator to determine the number of single event transients.

[0108] Embodiments of the present application aim to solve the problems that the accurate position of FPGA single event upset cannot be obtained, at most one single event upset can be detected in the same circuit unit, the source of single event upset is unknown, and the real-time and accuracy of single event upset detection are poor, and propose a FPGA single event upset detection method which can be described in detail as follows:

[0109] (1) a code stream input instruction is sent through a serial port, and the original code stream file is sent to a memory for storage through an Ethernet interface; (2) a code stream configuration instruction is sent through a serial port, and the original code stream file in the memory is configured to the FPGA under test through a SelectMap interface; (3) a single event upset number counter is established for each bit of the code stream file on the host computer, and the initial value is set to 0; (4) a single event irradiation source is turned on, and the FPGA under test is irradiated by single events; (5) a triple modular redundancy code stream read-back instruction is sent through a serial port at a fixed time interval (for example, every 1 second), and the code stream file of the FPGA under test after irradiation is read back to the memory for storage through a SelectMap interface; (6) a memory reading instruction is sent through a serial port, and the code stream file obtained by read-back in step (5) is obtained from the memory through an Ethernet interface; (7) the triple modular redundancy code stream is read back using a triple modular redundancy structure, the triple modular redundancy code stream is compared using a majority voter, and the number of single event transients in the three paths is calculated and recorded through an AND gate, and the result of the majority voter is taken as the read-back code stream file; (8) the read-back code stream file of the current test cycle in step (7) and the read-back code stream file of the last test cycle are compared bit by bit, and all different bits are marked, which are the positions of single event upset in the current test cycle; (9) the single event upset number counter established in step (3) is accumulated, and the counters of all single event upset positions in step (8) are incremented by 1, and the counters of the remaining positions remain unchanged; (10) steps (5) to (9) are repeated until the total dose reaches the rated value; (11) according to the inherent format of the code stream file, the bit with a non-zero single event upset number counter is determined to correspond to the circuit unit number in the FPGA under test, and the accurate position of the upset in the FPGA under test is determined.

[0110] Any technical features in the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described above, however, it should be understood that the application encompasses all possible combinations of the technical features described above.

[0111] The principles and implementation manners of the present application are described herein by using specific examples, and the above embodiments are only used to help understand the method of the present application and its core idea; meanwhile, according to the idea of the present application, the specific implementation manners and application scopes will be changed by those skilled in the art. In conclusion, the content of the present specification should not be understood as a limitation of the present application.

Claims

1. An FPGA single event upset detection system, characterized in that: The FPGA single event upset detection system includes: a host computer, a test baseboard and a test daughter board; the test daughter board includes: an FPGA to be tested; the host computer is connected to the test baseboard; the test baseboard is connected to the FPGA to be tested; The host computer is used for: Sending the original code stream file to the test board; The test base plate is used for: Configuring the original code stream file on the FPGA to be tested; Under the single event upset test, the code stream file of the FPGA under test is read back in each test cycle to obtain the readback code stream file of each test cycle; the single event upset test is a test in which the FPGA under test is subjected to single particle irradiation by successively increasing the same fluence from the first test cycle to the last test cycle; the total fluence of the last test cycle reaches the rated total fluence; Send the readback code stream file of each test cycle to the host computer; The host computer is also used for: The readback code stream file of the current test cycle is compared with the readback code stream file of the previous test cycle to determine the occurrence location of the single-event upset in the current test cycle. The number of single-event upsets at each occurrence location is accumulated to obtain the total number of single-event upsets under the total dose of the current test cycle.

2. The FPGA single event upset detection system according to claim 1, characterized in that: In terms of reading back the code stream file of the FPGA under test in each test cycle under a single event upset test to obtain the readback code stream file of each test cycle, the test baseboard is specifically used to: Under the single event upset test, for any test cycle, a triple modular redundant structure is used to read back the triple modular redundant code stream of the current test cycle; the triple modular redundant code stream includes: the first code stream file, the second code stream file, and the third code stream file of the FPGA to be tested; According to the triple modular redundant code stream of the current test cycle, a majority voter is used to determine the readback code stream file of the current test cycle.

3. The FPGA single event upset detection system according to claim 2, characterized in that: The test base plate is also used for: In the single event upset test, for any test cycle, the source determiner is used to determine the number of single event transients based on the triple modular redundant code stream of the current test cycle.

4. The FPGA single event upset detection system according to claim 1, characterized in that: The test baseboard includes: a processing FPGA and a memory; the processing FPGA is connected to the host computer, the memory and the FPGA to be tested respectively; The processing FPGA is used to: Sending the original code stream file to the memory; The memory is used for: caching the original code stream file; The processing FPGA is also used for: Configuring the original code stream file cached in the memory to the FPGA to be tested; Under the single event upset test, read back the bit stream file of the FPGA under test in each test cycle to obtain the readback bit stream file of each test cycle; The memory is further used for: Cache the readback code stream file of each test cycle; The processing FPGA is also used for: The readback code stream file of each test cycle cached in the memory is sent to the host computer.

5. The FPGA single event upset detection system according to claim 4, characterized in that: The processing FPGA includes: a data control module, an Ethernet interface and a SelectMap interface; The data control module is connected to the memory; the data control module is connected to the host computer through the Ethernet interface; the data control module is connected to the FPGA to be tested through the SelectMap interface; The Ethernet interface is used for: Sending the original code stream file to the data control module; The data control module is used for: Sending the original code stream file to the memory; Configuring the original code stream file cached in the memory to the FPGA to be tested through the SelectMap interface; Under the single event upset test, the code stream file of the FPGA to be tested is read back through the SelectMap interface in each test cycle to obtain the readback code stream file of each test cycle; The readback code stream file of each test cycle cached in the memory is sent to the host computer through the Ethernet interface.

6. The FPGA single event upset detection system according to claim 5, characterized in that: The processing FPGA also includes: a serial port; The data control module is connected to the host computer via the serial port; The serial port is used to send control instructions to the host computer; the control instructions include: code stream input instructions, code stream configuration instructions, code stream read back instructions and memory read instructions; The host computer is used for: When receiving the code stream input instruction, controlling the Ethernet interface to send the original code stream file to the data control module and buffering it in the memory; When receiving the code stream configuration instruction, controlling the original code stream file cached in the memory to be configured on the FPGA to be tested through the SelectMap interface; When the code stream readback instruction is received, the SelectMap interface is controlled to read back the code stream file of the FPGA to be tested in the current test cycle, obtain the readback code stream file of the current test cycle, and cache it in the memory; When the memory read instruction is received, the Ethernet interface is controlled to obtain the readback code stream file of the current test cycle cached in the memory.

7. The FPGA single event upset detection system according to claim 3, characterized in that: The source determiner is an AND gate.

8. A FPGA single event upset detection method, characterized in that: The FPGA single-event upset detection method is used in the FPGA single-event upset detection system according to any one of claims 1 to 7, and the FPGA single-event upset detection method includes: Get the original stream file; Configuring the original code stream file on the FPGA to be tested; Under the single event upset test, the code stream file of the FPGA under test is read back in each test cycle to obtain the readback code stream file of each test cycle; the single event upset test is a test in which the FPGA under test is subjected to single particle irradiation by successively increasing the same fluence from the first test cycle to the last test cycle; the total fluence of the last test cycle reaches the rated total fluence; Send the readback code stream file of each test cycle to the host computer; The host computer compares the readback code stream file of the current test cycle with the readback code stream file of the previous test cycle, determines the occurrence location of the single-event upset in the current test cycle, and accumulates the number of single-event upsets at each occurrence location to obtain the total number of single-event upsets under the total dose of the current test cycle.

9. The FPGA single event upset detection method according to claim 8, characterized in that: Under the single event upset test, the code stream file of the FPGA under test is read back in each test cycle to obtain the readback code stream file of each test cycle, specifically including: Under the single event upset test, for any test cycle, a triple modular redundant structure is used to read back the triple modular redundant code stream of the current test cycle; the triple modular redundant code stream includes: the first code stream file, the second code stream file, and the third code stream file of the FPGA to be tested; According to the triple modular redundant code stream of the current test cycle, a majority voter is used to determine the readback code stream file of the current test cycle.

10. The FPGA single event upset detection method according to claim 9, characterized in that: After obtaining the triple-modular redundant code stream of the current test cycle, the FPGA single-event upset detection method further includes: According to the triple modular redundant code stream of the current test cycle, a source determiner is used to determine the number of single-particle transients.

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