Power semiconductor device simulation method under high and low temperature cycle condition

Abstract

The invention discloses a power semiconductor device simulation method under a high and low temperature cycle condition, which comprises the following steps of: obtaining structure parameters and material parameters of a power semiconductor device, constructing a cellular three-dimensional model, constructing a semiconductor device whole and cellular composite model on the basis, and performing grid division to obtain a power semiconductor device whole and cellular composite model; and adding a temperature load into the composite model for analogue simulation, and analyzing and evaluating a simulation result. According to the method, the coupling relation between the overall model of the semiconductor device and the cellular model is established, different dimension dimensions between the overall model of the semiconductor device and the cellular model are integrated, the interaction between different dimension models is effectively considered, and the real performance of the semiconductor device in high and low temperature circulation can be comprehensively revealed.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a simulation method for optimizing the performance of power semiconductor devices under high and low temperature cycle conditions. Background Art

[0002] In modern power electronic equipment, power semiconductor devices play a vital role and are widely used in aerospace and other fields. The performance stability and reliability of these devices under high and low temperature cycling conditions have always been a hot topic of research. Long-term high and low temperature cycling will cause repeated alternation of thermal expansion and contraction of the internal materials of the device, resulting in uneven stress distribution, which in turn causes device performance degradation, malfunction and failure. The performance stability and reliability of power semiconductor devices under high and low temperature cycling conditions is a major challenge that needs to be solved urgently.

[0003] At present, the research on the high and low temperature cycle performance of power semiconductor devices mainly relies on two methods: experiments and simulations. The experimental method can provide an intuitive understanding of its electrical degradation, but the test cycle is long, and it is difficult to understand the reasons for the degradation of the device at the microscopic level. The simulation method predicts the performance changes of the device under different working environments through simulation, and has strong flexibility and scalability. High and low temperature simulation research focuses on using unit cell models to simulate the high and low temperature cycles of power semiconductor devices, which is limited to the microscopic level. Although the unit cell model used can partially evaluate the performance and stress response of local materials during high and low temperature cycle simulation, this method has significant limitations and cannot fully reflect and predict the influence of complex interactions between multiple cells in a complex structure, as well as the coupling of different size scales under extreme temperature changes. In addition, the unit cell model has not fully considered the thermodynamic and mechanical interaction effects between cells and other structural materials of the device. Summary of the invention

[0004] In order to solve the limitations of single-cell model simulation in high and low temperature cycle performance research, the present invention provides a simulation method for power semiconductor devices under high and low temperature cycle conditions. Through the overall semiconductor device and cellular composite model, a coupling relationship between the overall model and the cellular model is established, which can comprehensively consider each layer of materials and their interaction effects.

[0005] To achieve the above object, the technical solution proposed by the present invention is: a method for simulating a power semiconductor device under high and low temperature cycle conditions, comprising the following steps: A method for simulating a power semiconductor device under high and low temperature cycle conditions comprises the following steps: S1 obtains structural parameters and material parameters of power semiconductor devices; S2 builds a cellular three-dimensional model; S3 builds the overall and cellular composite model of the semiconductor device and performs mesh division; S4 adds temperature load and performs simulation; S5 analyzes and evaluates the simulation results.

[0006] Specifically, in step S1, the structural parameters and material parameters of the power semiconductor device include the overall structure of the semiconductor device, the unit cell structure, the material composition of each layer structure, the elastic modulus, Poisson's ratio, thermal conductivity, and density of the material.

[0007] Specifically, in step S3, the connection between the macroscopic structure of the semiconductor device and the microscopic structure of the cell is established by modeling the semiconductor device as a whole.

[0008] Specifically, the grid is divided using an adaptive grid division method, and the microscopic part of the cell and other parts of the overall device are divided into different grid qualities.

[0009] Specifically, the mesh quality of the microscopic part of the cell is higher than the mesh quality of other parts of the overall device.

[0010] Improving the mesh quality of the microscopic part of the cell can ensure higher mesh accuracy in key areas and areas of high stress concentration, capture subtle stress changes, and improve simulation accuracy; coarse mesh division (i.e., mesh quality is lower than that of the microscopic part of the cell) is used for other parts of the overall device, which can reduce computational complexity and time cost, and is conducive to completing multiple iterations and optimization analysis in a shorter time.

[0011] Specifically, the mesh quality of the cellular model is not less than 0.832.

[0012] Furthermore, the step S4 is specifically as follows: S41 imports the semiconductor device as a whole and the cell composite model into the finite element software; S42 inputs corresponding physical properties according to the material characteristics and mechanical behaviors of each structural layer of the cellular model and the cellular model in the composite model, and assigns materials to different structures that meet the model; S43 inputs the interface contact conditions and interactions between different structural layers; S44 performs fixed constraints on the bottom of the device; S45 adds temperature cycle loads to the composite model and applies thermal boundary conditions; S46 obtains the temperature and stress distribution of materials in different structural layers of the cell and analyzes the stress state of each layer of the structure.

[0013] Specifically, in step 42, the input physical properties include elastic modulus, Poisson's ratio, thermal conductivity, and density.

[0014] By inputting corresponding elastic modulus, Poisson's ratio, thermal conductivity, material density and other properties according to the material properties and mechanical behaviors of different structural layers, and meshing the composite model, it can be ensured that the response of each layer of material in the composite model can accurately reflect the actual mechanical behavior of each layer of the semiconductor device.

[0015] Through the interface contact conditions and interactions between different structural layers, the overall device model can accurately simulate the mechanical and thermodynamic behaviors under actual working conditions during the analysis process, thereby improving the accuracy and reliability of the simulation results.

[0016] Specifically, in step S45, the temperature cycle load condition is -40°C~125°C, and the cycle is repeated five times, and the thermal boundary condition is applied to set the convection coefficient to 10w / mm 2 , the added temperature load simulates the temperature changes that semiconductor devices experience during operation.

[0017] Furthermore, in step S5, the evaluation of the simulation results includes: calculating the thermal distribution of each structure and cellular model of the semiconductor device caused by temperature changes, and evaluating the stress distribution, evolution trend and potential failure risk of each structural layer under the action of temperature cycling.

[0018] Beneficial effects of the present invention: 1. By establishing the coupling relationship between the overall model of semiconductor devices and the cellular model, the different dimensions between the overall semiconductor device and the cellular model are integrated, and the interaction between models of different dimensions is effectively considered, which can fully reveal the true performance of semiconductor devices in high and low temperature cycles. This comprehensive analysis can significantly improve the understanding of the device performance degradation mechanism and provide a solid theoretical basis for the design of more reliable and efficient power semiconductor devices; 2. Through simulation of the coupling of the overall model of semiconductor devices and the cellular model, the reliability assessment capability of power semiconductor devices in extreme temperature environments can be significantly improved, the thermal stress distribution and material performance changes caused by temperature cycles can be accurately predicted, and the risks that may lead to failures can be identified in advance, thereby providing important guidance for engineers in the design stage, effectively reducing the probability of device failure and improving the safety and stability of the overall system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. For those skilled in the art, other drawings can be obtained based on the drawings without paying creative work.

[0020] Figure 1 This is a flow chart of a power semiconductor simulation method under high and low temperature cycle conditions of the present invention; Figure 2 A schematic diagram of a cell structure according to an embodiment of the present invention; Figure 3 The stress distribution curve of each layer of the unit cell model of the embodiment of the present invention; Figure 4 It is a schematic diagram of an optimized cellular model in the overall semiconductor device and cellular composite model according to an embodiment of the present invention; Figure 5 A schematic diagram of a composite model of a semiconductor device as a whole and a cell according to an embodiment of the present invention; Figure 6 This is the stress distribution curve of the composite model under high and low temperature cycle conditions in the embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The present invention provides an embodiment to verify the accuracy of the technical solution through specific experiments. like Figure 1 As shown, the flowchart of the power semiconductor simulation method under high and low temperature cycle conditions of the present invention comprises the following steps: S1 obtains structural parameters and material parameters of power semiconductor devices; S2 builds a cellular three-dimensional model; S3 builds the overall and cellular composite model of the semiconductor device and performs mesh division; S4 adds temperature load for simulation; S5 analyzes and evaluates the simulation results.

[0023] By constructing the coupling relationship between the overall model of semiconductor devices and the cellular model, comprehensive simulation is carried out to comprehensively analyze the actual performance of semiconductor devices in high and low temperature cycles.

[0024] In this implementation of the present invention, through experiments, the comparative effect of single semiconductor cell model analysis and device overall model analysis is given, and the following is the specific implementation process.

[0025] First, a unit cell three-dimensional model is constructed and high and low temperature simulations are performed to obtain the simulation results of the unit cell three-dimensional model.

[0026] In this embodiment, the semiconductor device used is an enhancement mode p-type gate GaN HEMT device, such as Figure 2 As shown, the cell structure of the enhanced p-type gate GaN HEMT device is analyzed. Figure 2 (a) is a schematic diagram of the unit cell structure. By collecting the material data and structural data of the semiconductor device, a three-dimensional structure diagram is constructed based on the unit cell structure of the device. Its H1 is 11μm, H2 is 260μm, and the height includes a 1μm thick Si substrate, a 2.2μm GaN buffer layer, and a 15nm AlGaN layer. Figure 2 (b) is a diagram of the unit cell structure for simulation, and the three-dimensional structure is imported into the finite element software to construct the unit cell structure for simulation.

[0027] In finite element software, the assignment of materials to different structures of a unit cell requires input of corresponding physical properties, including elastic modulus, Poisson's ratio, thermal conductivity, density, etc., based on the material characteristics and mechanical behavior of each structural layer, to ensure that the response of each layer of material can reflect its actual performance. In addition, the interface contact conditions and interactions between the layers are also considered, so that the entire unit cell model can accurately simulate the mechanical and thermal behavior under actual working conditions during the analysis process, thereby improving the accuracy and reliability of the simulation results.

[0028] For the established unit cell model, an adaptive meshing method is used to ensure higher mesh accuracy in key areas and areas of high stress concentration. After the meshing is completed, the generated mesh is quality checked and the mesh quality requirement is not less than 0.832.

[0029] Set high and low temperature cycle loads and thermal boundary conditions. The temperature cycle conditions are set to -40℃~125℃. A total of five cycles are performed. The convection coefficient of the thermal boundary conditions is set to 10w / mm 2 , to simulate the actual temperature changes experienced by the device during operation, and ensure that the loading process can truly reflect the thermal environment changes of the device in actual applications. At the same time, necessary constraints are imposed on the mechanical module to ensure the static balance and dynamic stability of the model. In this embodiment, when applying constraints, the actual movement and fixing method of the device should be taken into account to simulate the actual working state, so the bottom of the cell is fixed.

[0030] like Figure 3 As shown in the figure, finite element solution is performed after simulation to obtain the temperature and stress distribution of each layer of material, and the stress state of each layer of structure is analyzed to generate the stress curve of each layer of the unit cell model to reflect the changes in stress and temperature of each layer. Figure 3 (a) to (c) are curves showing the temperature and stress changes of AlGaN, Si, and GaN over time. Figure 3(d) is the curve of the comprehensive change of stress of AlGaN, Si and GaN layers over time, showing that for the unit cell model structure, the stress of the AlGaN layer is the largest.

[0031] Since the analysis of a single cell does not fully consider the macroscopic effect of the entire device, the influence of this factor on the stress behavior in the actual working environment cannot be ignored. Therefore, this method has certain limitations in predicting the stress of a single cell structure. To overcome this deficiency, the present invention combines the overall device model with the cell model to form a composite model.

[0032] The simulation process of the overall composite model of semiconductor devices is as follows: Figure 4 and 5 As shown in the figure, based on the unit cell model, the cell region of the device is optimized, the cell sub-model is equivalent, and the overall model of the semiconductor device is modeled to build the connection between the macro and micro. Figure 5 (a) is the overall device modeling diagram. Figure 5 (b) is the cell area modeling diagram of the overall device.

[0033] After the semiconductor device is modeled as a whole, the adaptive meshing method is used for meshing. For the cell area, the mesh is refined to ensure that subtle stress changes can be captured in key areas and improve the accuracy of the simulation. For other parts of the overall device, coarse meshing can be used to reduce computational complexity and time cost, which helps to complete multiple iterations and optimization analysis in a shorter time.

[0034] The composite model was tested under the same temperature cycle load conditions as the unit cell model. Temperature cycle loads and thermal boundary conditions were added. The temperature cycle conditions were set to -40℃~125℃ for five cycles. The convection coefficient of the thermal boundary conditions was set to 10w / mm 2 , ensuring that the simulation process can reflect the impact of temperature changes on the device and cellular structure, while fixing constraints on the bottom of the device.

[0035] After simulating the composite model, the finite element solution is performed, and based on the solution results, post-processing is performed to evaluate the stress distribution, evolution trend and potential failure risk of each layer under the action of temperature cycling.

[0036] like Figure 6 As shown, the simulated stress curve of the composite model under high and low temperature cycle conditions, Figure 6(a) is the stress distribution curve of different layers of the cell module, showing the stress distribution of the Si layer, AlGaN layer and GaN layer in the optimized cell. The overall trend of the figure shows that the internal stress of the material shows a periodic change pattern over time. Among them, the stress of the AlGaN layer is the largest, with a maximum stress of about 160Mpa, which is 12.5% ​​optimized compared with the result obtained by the single cell model. The stress of the GaN layer is about 148Mpa, which is 15.5% optimized compared with the result obtained by the single cell model. The stress of the Si layer is about 88Mpa, which is 9% optimized compared with the result obtained by the single cell model. Therefore, when using the device and cell composite model, the comprehensive consideration of the relationship between multiple cells and the effect of the wiring layer on the cell shows a significant optimization effect.

[0037] Further analysis shows that the simulation results of the composite model also reveal the stress distribution of the solder layer and the bonding wire, thus providing more comprehensive data support for the reliability assessment of the device. Figure 6 (b) is the stress curve of the solder layer and the bonding wire, showing the stress distribution and accumulated strain of the solder layer. This curve not only reveals the stress distribution of the solder layer during temperature cycling, but also helps identify the failure risks that may be caused by accumulated strain, providing a basis for subsequent device design and material selection.

[0038] Through the analysis of the above composite model simulation results, we can fully understand the thermodynamic behavior of the device level and the cell level under high and low temperature cycle conditions, and provide data support for improving the reliability and performance optimization of power semiconductor devices.

[0039] Although the preferred implementation cases of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms of specific changes without departing from the scope of protection of the invention spirit and claims, which all fall within the scope of protection of the present invention.

Claims

1. A method for simulating power semiconductor devices under high and low temperature cycle conditions, characterized in that: The following steps are involved: S1 obtains structural parameters and material parameters of power semiconductor devices; S2 builds a cellular three-dimensional model; S3 builds the overall and cellular composite model of the semiconductor device and performs mesh division; S4 adds temperature load and performs simulation; S5 analyzes and evaluates the simulation results.

2. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 1, characterized in that: In the step S1, the structural parameters and material parameters of the power semiconductor device include the overall structure of the semiconductor device, the unit cell structure, the material composition of each layer structure, the elastic modulus, Poisson's ratio, thermal conductivity, and density of the material.

3. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 1, characterized in that: In the step S3, the connection between the macroscopic structure of the semiconductor device and the microscopic structure of the cell is established by modeling the semiconductor device as a whole.

4. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 3, characterized in that: The grid is divided by an adaptive grid division method, and the microscopic part of the cell and other parts of the overall device are divided into different grid qualities.

5. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 4, characterized in that: The mesh quality of the microscopic part of the cell is higher than the mesh quality of other parts of the overall device.

6. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 5, characterized in that: The mesh quality of the cellular model is not less than 0.

832.

7. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 1, characterized in that: The step S4 is specifically as follows: S41 imports the semiconductor device as a whole and the cell composite model into the finite element software; S42 inputs corresponding physical properties according to the material characteristics and mechanical behaviors of each structural layer of the cellular model and the cellular model in the composite model, and assigns materials to different structures that meet the model; S43 inputs the interface contact conditions and interactions between different structural layers; S44 performs fixed constraints on the bottom of the device; S45 adds a temperature cycle load to the composite model and applies a convection thermal boundary condition to the outside of the device; S46 obtains the temperature and stress distribution of materials in different structural layers of the cell and analyzes the stress state of each layer of the structure.

8. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 5, characterized in that: In step 42, the input physical properties include elastic modulus, Poisson's ratio, thermal conductivity, and density.

9. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 5, characterized in that: In step S45, the added temperature cycle condition is -40°C to 125°C, and the convection coefficient is set to 10w / mm2 for the thermal boundary condition of convection applied to the outside of the device. 2 , temperature load simulates the temperature changes experienced by semiconductor devices during operation.

10. The method for simulating power semiconductor devices under high and low temperature cycle conditions according to claim 1, characterized in that: In step S5, the evaluation of the simulation results includes: calculating the thermal distribution of each structure and cellular model of the semiconductor device caused by temperature changes, and evaluating the stress distribution, evolution trend and potential failure risk of each structural layer under the action of temperature cycles.

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