Power-off protection circuit of Flash memory chip, Flash memory chip and Flash memory

Abstract

The invention relates to the technical field of data storage, and discloses a power-off protection circuit of a Flash storage chip, the Flash storage chip and a Flash memory. The power-off protection circuit comprises an energy storage circuit, a phase inverter and a discharge path, the energy storage circuit is connected with a power supply and the phase inverter, and the energy storage circuit is configured to generate an internal power supply to supply power to the phase inverter under the condition that the power supply is powered off; the phase inverter is connected with the discharge path, and the phase inverter is configured to output a high-level signal to the discharge path under the condition that the internal power supply provided by the energy storage circuit is used for supplying power; and the discharge path is configured to discharge the Flash storage chip under the condition that the high-level signal is received. According to the Flash memory chip, the energy storage circuit and the phase inverter are utilized, under the condition that the power supply is powered off abnormally, the internal power supply is generated through the energy storage circuit, power is supplied to the phase inverter, the phase inverter outputs a high-level signal to conduct a discharge path, and internal high voltage is discharged, so that the stability of the Flash memory chip is improved, and the problem of wrong erasing and writing is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and for example, to a power-off protection circuit of a Flash storage chip, a Flash storage chip, and a Flash memory. Background Art

[0002] Flash memory, also known as flash memory, combines the advantages of ROM (Read Only Memory) and RAM (Random Access Memory). It not only has the performance of electronic erasability and programmability, but also can read data quickly.

[0003] In the related art, when the Flash memory is being erased using high voltage (about 10V-12V), if the power supply of the chip in which it is located is abnormally cut off, the high voltage inside the Flash memory cannot be discharged according to the normal timing, which will affect the life of the device and cause the Flash memory to be erased incorrectly.

[0004] Combination Figure 1 As shown in the figure, the power supply signal is represented by "power supply VDD", and the internal high voltage signal during the flash memory erasing is represented by "HV". Under normal circumstances, the power supply is stable during the flash memory erasing. At the beginning of the erasing, HV is boosted from 0V to 10V. During the erasing stabilization period, HV maintains a high voltage of 10V. At the end of the erasing, the discharge control signal DISCTRL changes from 0 to VDD, and the discharge is normally discharged through the discharge path, and HV is reduced from 10V to 0V.

[0005] Combination Figure 2 As shown in the figure, the power supply VDD suddenly loses power when the Flash memory is still in the process of erasing and writing. In this abnormal situation, points ① and ② are the same as the normal situation, and the difference is at point ③. Because the power supply VDD suddenly loses power at point ③, and DISCTRL is a VDD power supply signal, the discharge control signal DISCTRL is always 0 at this time and will not become VDD. The discharge path cannot be opened normally, and HV cannot be discharged normally to 0V. At this time, the problem of affecting the life of the device and the problem of incorrect erasure of the Flash memory arises. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a power-off protection circuit of a Flash memory chip, a Flash memory chip and a Flash memory, so as to solve the problem that the life of the device is affected and the Flash memory is accidentally erased when the power supply VDD suddenly fails abnormally.

[0008] In some embodiments, a power-off protection circuit for a Flash memory chip is provided, comprising an energy storage circuit, an inverter, and a discharge path, wherein: the energy storage circuit is connected to a power supply and an inverter, and the energy storage circuit is configured to generate an internal power supply to power the inverter when the power supply is cut off; the inverter is connected to the discharge path, and the inverter is configured to output a high-level signal to the discharge path when the internal power supply provided by the energy storage circuit is used; and the discharge path is configured to discharge the Flash memory chip when a high-level signal is received.

[0009] Optionally, the energy storage circuit includes: a resistor, a first end of the resistor is connected to a power supply; a capacitor, a first end of the capacitor is connected to a second end of the resistor, and the second end of the capacitor is grounded; a unidirectional conductive element, connected in parallel with the resistor, and when the unidirectional conductive element is in a conductive state, connected in series with the capacitor to form a charging path.

[0010] Optionally, the unidirectional conductive element includes a MOS tube, a source of the MOS tube is connected to the inverter, and a gate and a drain of the MOS tube are connected to a power source.

[0011] Optionally, the unidirectional conductive element includes a diode, and the diode conducts in a direction from the power supply to the capacitor.

[0012] Optionally, the discharge duration of the energy storage circuit is determined according to the resistance and the capacitance; wherein the resistance value of the resistance is greater than or equal to 2 MΩ, and the capacitance value is greater than or equal to 2 pF.

[0013] Optionally, the inverter includes: a PMOS tube, the source of the PMOS tube is connected to the output end of the energy storage circuit, the gate of the PMOS tube is connected to the power supply, and the drain of the PMOS tube is connected to the control signal end of the discharge path; a first NMOS tube, the drain of the first NMOS tube is connected to the drain of the PMOS tube and the control signal end of the discharge path, the gate of the first NMOS tube is connected to the power supply, and the source of the first NMOS tube is grounded.

[0014] Optionally, the discharge path includes a second NMOS tube, or multiple second NMOS tubes connected in series; wherein the first end of the discharge path is connected to the internal high-voltage output end of the Flash memory, the second end of the discharge path is grounded, and the control signal end of the discharge path is set at the second NMOS tube on the ground side.

[0015] Optionally, the number of the second NMOS transistors in the discharge path is determined according to a discharge target of the Flash memory.

[0016] In some embodiments, a Flash memory chip is provided, including: a power-off protection circuit of the Flash memory chip as described in any of the above embodiments.

[0017] Optionally, the Flash storage chip further includes: a high voltage generating circuit, wherein a high voltage output end of the high voltage generating circuit is connected to a first end of the discharge path, and a second end of the discharge path is grounded.

[0018] In some embodiments, a Flash memory is provided, comprising: a memory body; and a Flash memory chip as described in any of the above embodiments, disposed in the memory body.

[0019] The power-off protection circuit of the Flash storage chip, the Flash storage chip, and the Flash memory provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The power-off protection circuit of the Flash memory chip provided by the present disclosure includes an energy storage circuit, an inverter and a discharge path. The energy storage circuit is connected to a power supply and an inverter. The inverter is connected to the discharge path. The discharge path.

[0021] The power-off protection circuit disclosed in the present invention can store energy and electricity when the power supply is in a normal state, the energy storage circuit can store energy, the output signal of the inverter is a low-level signal, and the discharge path is in an open circuit state. However, when the power supply is in an abnormal power failure, the energy storage circuit generates an internal power supply to supply power to the inverter, the output signal of the inverter is converted into a high-level signal, and the high-level signal is output to the discharge path. The first end of the discharge path is connected to the high-voltage output end of the internal circuit of the chip, and the second end of the discharge path is grounded. When the discharge path receives a high-level signal, the discharge path is turned on to discharge the Flash storage chip.

[0022] The power-off protection circuit disclosed in the present invention uses an energy storage circuit and an inverter. When the power supply of the Flash memory chip is abnormally powered off, the internal power supply is generated by the energy storage circuit to supply power to the inverter, ensuring that the Flash memory chip can be discharged smoothly at the moment of power off, avoiding voltage fluctuations and current mutations caused by sudden power off, thereby reducing damage to the internal components of the Flash memory chip and extending the service life of the device. The inverter can output a high-level signal after power off, and discharge the internal high voltage of the Flash memory chip during the erasing and writing period through the discharge path, thereby improving the data stability of the Flash memory chip during the power off process and effectively avoiding the problem of mistaken erasure. In this way, by providing a power-off protection circuit, the reliability of the Flash memory chip in an abnormal power supply environment is enhanced.

[0023] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0025] Figure 1 It is a schematic diagram of the signal state when the power supply of the Flash memory is in a normal state in the prior art;

[0026] Figure 2 It is a schematic diagram of the signal state when the power supply of the Flash memory is in an abnormal power-off state in the prior art;

[0027] Figure 3 It is a structural schematic diagram of a power-off protection circuit of a Flash storage chip provided by an embodiment of the present disclosure;

[0028] Figure 4 It is a structural schematic diagram of a power-off protection circuit of a Flash storage chip provided in yet another embodiment of the present disclosure;

[0029] Figure 5 It is a schematic diagram of signal states when the power supply of the Flash storage chip provided by the embodiment of the present disclosure is in an abnormal power-off state.

[0030] Reference numerals:

[0031] 100 power-off protection circuit;

[0032] 110 energy storage circuit; 112 resistor; 114 capacitor; 116 unidirectional conductive element;

[0033] 120 inverter; 122 PMOS tube; 124 first NMOS tube;

[0034] 130 is a discharge path; 132 is a second NMOS tube. DETAILED DESCRIPTION

[0035] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and protection circuits can be simplified for display.

[0036] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0037] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated protection circuits, elements or components to have specific directions, or to be constructed and operated in specific directions. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure may be understood according to specific circumstances.

[0038] In addition, the terms "set", "connect", and "fix" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two protection circuits, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0039] Unless otherwise stated, the term "plurality" means two or more.

[0040] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0041] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0043] In some embodiments, in combination Figure 3 and Figure 4As shown, a power-off protection circuit 100 for a Flash memory chip is provided, comprising a storage circuit 110, an inverter 120 and a discharge path 130, wherein: the storage circuit 110 is connected to a power supply and the inverter 120, and the storage circuit 110 is configured to generate an internal power supply to power the inverter 120 when the power supply is cut off; the inverter 120 is connected to the discharge path 130, and the inverter 120 is configured to output a high-level signal to the discharge path 130 when the internal power supply provided by the storage circuit 110 is used for power supply; and the discharge path 130 is configured to discharge the Flash memory chip when a high-level signal is received.

[0044] The power-off protection circuit 100 of the Flash memory chip provided by the present disclosure includes a storage circuit 110, an inverter 120 and a discharge path 130. The storage circuit 110 is connected to a power source and an inverter 120. The inverter 120 is connected to the discharge path 130. The discharge path 130 is connected to the Flash memory.

[0045] In the power-off protection circuit 100 disclosed in the present invention, when the power supply is in a normal state, the energy storage circuit 110 can store energy, the output signal of the inverter 120 is a low-level signal, and the discharge path 130 is in an open circuit state. However, when the power supply is in an abnormal power failure, the energy storage circuit 110 generates an internal power supply to power the inverter 120, the output signal of the inverter 120 is converted into a high-level signal, and the high-level signal is output to the discharge path 130. The first terminal of the discharge path 130 is connected to the high-voltage output terminal of the internal circuit of the chip, and the second terminal of the discharge path 130 is grounded. When the discharge path 130 receives a high-level signal, the discharge path 130 is turned on to discharge the Flash storage chip.

[0046] By adopting the power-off protection circuit 100 disclosed in the present invention, using the energy storage circuit 110 and the inverter 120, when the power supply of the Flash memory chip is abnormally powered off, the internal power supply is generated by the energy storage circuit 110 to supply power to the inverter 120, ensuring that the Flash memory chip can be discharged smoothly at the moment of power off, avoiding voltage fluctuations and current mutations caused by sudden power off, thereby reducing damage to the internal components of the Flash memory chip and extending the service life of the device. In addition, the inverter 120 can output a high-level signal after power off, and discharge the internal high voltage of the Flash memory chip during the erasing and writing period through the discharge path 130, thereby improving the data stability of the Flash memory chip during the power off process and effectively avoiding the problem of erroneous erasure. In this way, by providing the power-off protection circuit 100, the reliability of the Flash memory chip in an abnormal power supply environment is enhanced.

[0047] Optionally, combined Figure 3 and Figure 4As shown, the energy storage circuit 110 includes: a resistor 112, a capacitor 114 and a unidirectional conductive member 116. The first end of the resistor 112 is connected to a power source. The first end of the capacitor 114 is connected to the second end of the resistor 112, and the second end of the capacitor 114 is grounded. The unidirectional conductive member 116 is connected in parallel with the resistor 112. When the unidirectional conductive member 116 is in a conducting state, it is connected in series with the capacitor 114 to form a charging path.

[0048] In this embodiment, when the power supply is in a normal state, the capacitor 114 can store electricity and energy. When the power supply voltage drops briefly, the capacitor 114 can temporarily provide energy to prevent the Flash memory from malfunctioning due to insufficient voltage, so as to smooth the instantaneous fluctuation of the power supply. Further, by setting a one-way conductive member 116 in parallel with the resistor 112, the one-way conductive member 116 can be used to increase the charging speed of the capacitor 114 when the power supply is in a normal state. And the one-way conductive member 116 is used to prevent the capacitor 114 from reversely discharging when the power supply is cut off, thereby protecting the power supply line from the influence of reverse current. The energy storage circuit 110 provided by the present disclosure, when the power supply is normally supplied, the capacitor 114 is charged through the resistor 112 and the one-way conductive member 116 to prepare for power failure. In the case of a sudden power failure of the power supply, the capacitor 114 has stored a certain amount of electrical energy, and can provide a short working voltage for the Flash memory by discharging. In this way, by preventing the influence of power fluctuations and sudden power failures on the Flash memory, the stress of the device is reduced, thereby extending the service life of the Flash memory.

[0049] Optionally, combined Figure 3 As shown, the unidirectional conductive element 116 includes a MOS transistor, the source of the MOS transistor is connected to the inverter 120, and the gate and drain of the MOS transistor 122 are connected to the power supply.

[0050] In this embodiment, the unidirectional conductive element 116 of the energy storage circuit 110 adopts a MOS tube, and the gate of the MOS tube can be used to receive the control signal of the power supply to realize the precise control of the conduction and cutoff of the MOS tube. When the power supply is normal, the MOS tube remains on, allowing the capacitor 114 to charge. When the power supply is cut off, the MOS tube is quickly cut off to protect the energy in the capacitor 114 from being consumed in reverse. In addition, by controlling the cutoff of the MOS tube, the capacitor 114 provides a short discharge process for the Flash memory through the inverter 120, ensuring that the Flash memory can complete the data storage operation and avoid data loss or damage. Since the MOS tube can quickly cut off the power supply, the impact of power supply fluctuations on the Flash memory is reduced, thereby reducing the risk of mis-erasing caused by unstable power supply. In addition, when the power supply is working normally, the on-resistance 112 of the MOS tube is low, which reduces the power consumption from the power supply to the energy storage capacitor 114, helps to reduce the power consumption of the entire system, and improves the charging speed of the capacitor 114.

[0051] Optionally, combined Figure 3 As shown, the unidirectional conductive element 116 is a P-type MOS tube or an N-type MOS tube.

[0052] Optionally, combined Figure 4 As shown, the unidirectional conductive element 116 includes a diode, and the diode conducts from the power supply to the capacitor 114 .

[0053] In this embodiment, the unidirectional conductive element 116 of the energy storage circuit 110 is a diode, which has a small forward voltage drop. When the power supply is normal, the low power consumption of the diode helps to reduce the power consumption of the entire system and can increase the charging speed of the capacitor 114. In addition, the diode only allows the current to be conducted in one direction. When the power supply is suddenly cut off, the diode can prevent the current from flowing to the power supply, while allowing the capacitor 114 to provide the necessary discharge process for the Flash memory, thereby reducing the risk of accidental erasure of the Flash memory.

[0054] Optionally, the discharge duration of the energy storage circuit 110 is determined according to the resistor 112 and the capacitor 114 .

[0055] In this embodiment, by selecting a resistor 112 and a capacitor 114 with specific resistance values ​​and capacitance 114 values, the duration of the discharge process can be controlled. In the RC circuit formed by the resistor 112 and the capacitor 114, the discharge time constant τ determines the time required for the capacitor 114 to discharge to 1 / e (about 37%) of its initial voltage. And τ = R × C, where R is the resistance value of the resistor 112 and C is the capacitance 114 value of the capacitor 114. In this way, by adjusting the values ​​of R and C, the requirements of different Flash memories for the duration of discharge can be met.

[0056] Optionally, the resistance value of the resistor 112 is greater than or equal to 2 MΩ, and the value of the capacitor 114 is greater than or equal to 2 pF.

[0057] In this embodiment, the resistance value of the resistor 112 is greater than or equal to 2MΩ, and the value of the capacitor 114 is greater than or equal to 2pF. By setting larger values ​​of the resistor 112 and the capacitor 114, it is helpful to maintain a relatively stable power supply voltage during the discharge process, and to provide a sufficiently long discharge time to ensure that after the power is cut off, the Flash memory has enough time to complete data preservation or other necessary operations to prevent data loss. However, due to the limitation of the volume of the Flash memory, an overly large resistor 112 or capacitor 114 occupies a large space. Therefore, the selection of the resistor 112 and the capacitor 114 should not only consider the discharge duration, but also be comprehensively selected in combination with the volume of the Flash memory, and should not be too large or too small.

[0058] Optionally, combined Figure 3 and Figure 4 As shown, the inverter 120 includes: a PMOS transistor 122 and a first NMOS transistor 124, the source of the PMOS transistor 122 is connected to the output end of the energy storage circuit 110, the gate of the PMOS transistor 122 is connected to the power supply, and the drain of the PMOS transistor 122 is connected to the control signal end of the discharge path 130. The drain of the first NMOS transistor 124 is connected to the drain of the PMOS transistor 122 and the control signal end of the discharge path 130, the gate of the first NMOS transistor 124 is connected to the power supply, and the source of the first NMOS transistor 124 is grounded.

[0059] In this embodiment, the gate of the PMOS tube 122 and the gate of the first NMOS tube 124 are connected to the control signal PORb corresponding to the flag signal of the power supply, and the drain of the first NMOS tube 124 and the drain of the PMOS tube 122 are connected to the control signal end of the discharge path 130, which is used to send a control signal NEWDISCTRL to the discharge path 130. Wherein, when the power supply is in a normal state, the control signal PORb input by the inverter 120 outputs a high-level signal, the PMOS tube 122 in the inverter 120 is turned on, and the first NMOS tube 124 is turned off, the control signal NEWDISCTRL output by the inverter 120 is a low-level signal, and the discharge path 130 is in an open circuit state and is not turned on, which ensures that unnecessary discharge does not occur in the Flash memory during normal operation, thereby protecting the data in the memory. When the power supply is in a power-off state, the control signal PORb input to the inverter 120 outputs a low-level signal, the PMOS tube 122 in the inverter 120 is turned off, and the NMOS tube is turned on, the control signal NEWDISCTL output by the inverter 120 is a high-level signal, and the discharge path 130 is in a conducting state, so that the internal high-voltage output end of the Flash memory is quickly discharged to the ground through the discharge path 130, thereby preventing the internal charge accumulation caused by power failure, and avoiding data damage or memory damage.

[0060] Optionally, the discharge path 130 includes a second NMOS tube 132, or a plurality of second NMOS tubes 132 connected in series; wherein a first end of the discharge path 130 is connected to an internal high-voltage output end of the Flash memory, a second end of the discharge path 130 is grounded, and a control signal end of the discharge path 130 is arranged at the second NMOS tube 132 on the ground side.

[0061] In this embodiment, the MOS transistor can be turned on quickly under the control signal, providing a low impedance path, so that the internal high-voltage output terminal of the Flash memory can be quickly discharged to the ground. In this way, the discharge path 130 provided by the present disclosure is used to quickly discharge the internal high-voltage output terminal of the Flash memory to the ground when the power is off by providing a second NMOS transistor 132 or a plurality of second NMOS transistors 132 connected in series, so as to protect the memory from damage.

[0062] In some embodiments, the discharge path 130 includes a second NMOS transistor 132 .

[0063] In some embodiments, in combination Figure 3 and Figure 4 As shown, the discharge path 130 includes a plurality of second NMOS transistors 132 connected in series.

[0064] Optionally, the number of the second NMOS transistors 132 in the discharge path 130 is determined according to a discharge target of the Flash memory.

[0065] In this embodiment, the number of NMOS tubes in the discharge path 130 can be adjusted according to the discharge speed and discharge amount that the Flash memory needs to achieve. According to the specific discharge target of the Flash memory, a suitable number of NMOS tubes is selected to achieve more accurate discharge control. In addition, an appropriate number of NMOS tubes can reduce unnecessary energy consumption. Too many NMOS tubes may cause more energy to be consumed during the discharge process, while an appropriate number of NMOS tubes can maintain low energy consumption while meeting the discharge requirements.

[0066] In some embodiments, in combination Figure 4 As shown, taking the unidirectional conductive element 116 as an N-type MOS tube, the discharge path 130 includes three second NMOS tubes 132 connected in series as an example, the three second NMOS tubes 132 connected in series are NM23, NM22 and NM21. Figure 5As shown, the power signal is represented by "power supply VDD", the energy storage circuit 110 generates an internal power supply represented by "internal VDDIN", and the internal power supply VDDIN supplies power to the inverter 120 to maintain the generation of the NEWDISCTL signal. The internal high voltage signal during the erasing of the Flash memory is represented by "HV". Under normal circumstances, the power supply is stable during the erasing of the Flash memory. At the beginning of the erasing, HV is boosted from 0V to 10V at ①, and during the stable erasing period, HV maintains a high voltage of 10V at ②. When the erasing action of the Flash memory is not yet completed, the power supply VDD suddenly loses power abnormally. In this abnormal situation, points ① and ② are no different from the normal power supply situation. During the erasing and writing process, the power supply VDD suddenly loses power at ③, and the control signal PORb corresponding to the input of the inverter 120 and the power status flag signal is converted from a high level signal to a low level signal, and the control signal NEWDISCTL output by the corresponding inverter 120 is converted from a low level to a high level signal, and the NM23, NM22 and NM21 of the discharge path 130 are normally opened, so that HV is normally discharged from the high voltage of 10V to 0V. At this time, the device life problem and the problem of incorrect erasure of the Flash memory are avoided. The power-off protection circuit 100 provided by the present disclosure has a simple control timing and is easy to use, thereby enhancing the reliability of the Flash memory at a very small cost.

[0067] In some embodiments, a Flash memory chip is provided, including: the power-off protection circuit 100 of the Flash memory chip as described in any of the above embodiments.

[0068] The Flash memory chip provided in the embodiment of the present disclosure includes the power-off protection circuit 100 of the Flash memory chip described in any of the above embodiments. The power-off protection circuit 100 is arranged inside the Flash memory chip. The power-off protection circuit 100 of the Flash memory chip provided in the present disclosure includes an energy storage circuit 110, an inverter 120 and a discharge path 130. The energy storage circuit 110 is connected to the power supply and the inverter 120. The inverter 120 is connected to the discharge path 130. The discharge path 130 is connected to the internal high-voltage output terminal of the Flash memory chip. By setting the power-off protection circuit 100, when the power supply is in a normal state, the energy storage circuit 110 can store energy and electricity, the output signal of the inverter 120 is a low-level signal, and the discharge path 130 is in an open circuit state. However, when the power supply is in an abnormal power failure, the energy storage circuit 110 generates an internal power supply to power the inverter 120, and the output signal of the inverter 120 is converted into a high-level signal, and a high-level signal is output to the discharge path 130. When the discharge path 130 receives a high level signal, the path is turned on to discharge the Flash memory chip.

[0069] The Flash memory chip provided by the embodiment of the present disclosure adopts the power-off protection circuit 100 of the present disclosure, utilizes the energy storage circuit 110 and the inverter 120, and when the power supply of the Flash memory chip is abnormally powered off, the internal power is generated by the energy storage circuit 110 to supply power to the inverter 120, thereby ensuring that the Flash memory chip can discharge smoothly at the moment of power off, avoiding voltage fluctuations and current mutations caused by sudden power off, thereby reducing damage to the internal components of the Flash memory chip and extending the service life of the device. In addition, the inverter 120 can output a high-level signal after power off, and discharge the internal high voltage of the Flash memory chip during the erasing and writing period through the discharge path 130, thereby improving the data stability of the Flash memory chip during the power off process and effectively avoiding the problem of erroneous erasure. In this way, by providing the power-off protection circuit 100, the reliability of the Flash memory in an abnormal power supply environment is enhanced.

[0070] Furthermore, by integrating the power-off protection circuit 100 into the Flash memory chip, a compact design is achieved, the need for external components is reduced, and the volume and complexity of the overall system are reduced. The power-off protection circuit 100 integrated into the Flash memory chip can be uniformly tested and calibrated during the production process, thereby improving manufacturing efficiency and quality control.

[0071] Optionally, combined Figure 3 and Figure 4 As shown, the Flash memory chip further includes: a high voltage generating circuit, a high voltage output terminal HV of the high voltage generating circuit is connected to a first end of the discharge path 130, and a second end of the discharge path 130 is grounded.

[0072] In this embodiment, the output terminal HV of the high voltage generating circuit is connected to the first end of the discharge path 130. When the power is off, the internal high voltage can be quickly reduced through the discharge path 130 to protect the Flash memory chip from damage caused by excessive voltage.

[0073] In some embodiments, a Flash memory is provided, comprising: a memory body; and a Flash memory chip as described in any of the above embodiments, disposed in the memory body.

[0074] The Flash memory provided by the embodiment of the present disclosure includes a memory body and a Flash memory chip described in any of the above embodiments. By integrating a Flash memory chip with a power-off protection circuit 100 in the memory body, the power-off protection circuit 100 ensures that when the power is off, the internal power is generated by the energy storage circuit 110 to power the inverter 120, ensuring that the Flash memory can be discharged smoothly at the moment of power off, avoiding voltage fluctuations and current mutations caused by sudden power off, thereby reducing damage to the internal components of the Flash memory and extending the service life of the device. And the inverter 120 can output a high-level signal after power off, and discharge the internal high voltage during the erasing and writing of the Flash memory through the discharge path 130, thereby improving the data stability of the Flash memory during the power-off process and effectively avoiding the problem of erroneous erasure. In this way, the Flash memory enhances the reliability of the Flash memory in an abnormal power supply environment by setting the power-off protection circuit 100 described in any of the above embodiments.

[0075] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A power-off protection circuit for a Flash memory chip, characterized in that: It includes a storage circuit, an inverter and a discharge path, wherein: The energy storage circuit is connected to the power supply and the inverter, and the energy storage circuit is configured to generate an internal power supply to power the inverter when the power supply is cut off; The inverter is connected to the discharge path, and the inverter is configured to output a high level signal to the discharge path when powered by an internal power supply provided by the energy storage circuit; The discharge path is configured to discharge the Flash memory chip when a high level signal is received.

2. The power-off protection circuit according to claim 1, characterized in that: The energy storage circuit includes: a resistor, wherein a first end of the resistor is connected to a power source; A capacitor, wherein a first end of the capacitor is connected to a second end of the resistor, and a second end of the capacitor is grounded; The unidirectional conductive component is connected in parallel with the resistor. When the unidirectional conductive component is in the on state, it is connected in series with the capacitor to form a charging path.

3. The power-off protection circuit according to claim 2, characterized in that: The unidirectional conductive element includes a MOS tube, the source of the MOS tube is connected to the inverter, and the gate and drain of the MOS tube are connected to the power supply; or, The unidirectional conductive element includes a diode, and the diode conducts from the power supply to the capacitor.

4. The power-off protection circuit according to claim 2, characterized in that: The duration of the discharge of the energy storage circuit is determined by the resistance and capacitance; The resistance value of the resistor is greater than or equal to 2 MΩ, and the value of the capacitor is greater than or equal to 2 pF.

5. The power-off protection circuit according to any one of claims 1 to 3, characterized in that the inverter include: A PMOS tube, wherein the source of the PMOS tube is connected to the output end of the energy storage circuit, the gate of the PMOS tube is connected to the power supply, and the drain of the PMOS tube is connected to the control signal end of the discharge path; The first NMOS tube has a drain connected to the drain of the PMOS tube and a control signal end of the discharge path, a gate connected to a power source, and a source connected to ground.

6. The power-off protection circuit according to any one of claims 1 to 3, characterized in that: The discharge path includes a second NMOS tube, or a plurality of second NMOS tubes connected in series; The first end of the discharge path is connected to the internal high voltage output end of the Flash memory, the second end of the discharge path is grounded, and the control signal end of the discharge path is arranged at the second NMOS tube on the ground side.

7. The power-off protection circuit according to claim 6, characterized in that: The number of the second NMOS transistors in the discharge path is determined according to the discharge target of the Flash memory.

8. A Flash storage chip, characterized in that: include: A power-off protection circuit for a Flash memory chip as claimed in any one of claims 1 to 7.

9. The Flash storage chip according to claim 8, characterized in that: Also includes: A high voltage generating circuit, wherein a high voltage output end of the high voltage generating circuit is connected to a first end of a discharge path, and a second end of the discharge path is grounded.

10. A Flash memory, characterized in that: include: Memory body; as well as The Flash memory chip as described in claim 8 or 9 is arranged in the memory body.

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