Memory control unit and memory control method

Abstract

The invention provides a control unit of a memory and a control method of the memory. The control unit comprises a first input stage, a second input stage, a first output stage and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processed signal. The second output stage is connected to the second input stage and configured to generate a second processed signal. If the first signal and the second signal are the same, the first processed signal and the second processed signal are different.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. patent application No. 18 / 379,819 (i.e., the priority date is "October 13, 2023"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a control unit of a memory and a control method of the memory, and more particularly to a control unit having at least one input stage and at least one output stage. Background Art

[0004] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) uses a data strobe signal to synchronize data transmission between a transmitter and a receiver. However, in some cases, the data strobe signal may not comply with the JEDEC standard, resulting in DDR SDRAM failure.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the invention

[0006] An embodiment of the present disclosure provides a control unit of a memory, comprising a first input stage, a second input stage, a first output stage and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processing signal. The second output stage is connected to the second input stage and configured to generate a second processing signal. If the first signal is the same as the second signal, the first processing signal is different from the second processing signal.

[0007] Another embodiment of the present disclosure provides a control unit of a memory, comprising a first input stage and a first output stage. The first input stage comprises a first input terminal configured to receive a first signal and a second input terminal configured to receive a second signal. The first output stage is connected to the first input stage and comprises an output terminal configured to generate a first processed signal. If the first signal and the second signal are the same, the first input stage is open circuited to separate the first processed signal from the first signal.

[0008] Another embodiment of the present disclosure provides a control method for a memory, comprising receiving a first signal and a second signal through a first input stage; receiving the first signal and the second signal through a second input stage; generating a first processing signal through a first output stage connected to the first input stage; generating a second processing signal through a second output stage connected to the second input stage; and if the first signal and the second signal are the same, differentiating the first processing signal and the second processing signal.

[0009] The control unit of the memory disclosed in the present invention includes a first input stage, a second input stage, a first output stage and a second output stage. The first input stage and the second input stage are configured to receive a first signal and a second signal (i.e., from a memory controller). The first output stage and the second output stage are configured to generate a first processing signal and a second processing signal, which can be transmitted to an internal control circuit of the memory, or can be used as a clock signal of multiple data lines of the memory for synchronization. The state of the first input stage and the second input stage changes based on whether the first signal and the second signal are the same or different. If the first signal and the second signal are the same, the first input stage and the second input stage are open (or cut-off) to differentiate the first processing signal and the second processing signal. The first processing signal is separated from the first signal, and the second processing signal is separated from the second signal. If the first signal and the second signal are different, the first input stage and the second input stage conduct (or turn on) to associate the first processing signal and the second processing signal to the first signal and the second signal, respectively (i.e., the first processing signal and the second processing signal are the same as the first signal and the second signal, respectively). The adjustable state of the first input stage and the second input stage allows the control unit to accept the first signal and the second signal that violate the JEDEC standard (i.e., data selection signals with the same value). In the conducting state, the control unit is configured to let the first processing signal and the second processing signal follow the first signal and the second signal. In the open state, the control unit is configured to regenerate the first processing signal and the second processing signal separated from the first signal and the second signal. The memory can successfully operate with the first processing signal and the second processing signal.

[0010] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0012] Figure 1 is a block schematic diagram illustrating electronic components of some embodiments of the present disclosure.

[0013] Figure 2 is a circuit schematic diagram illustrating a control unit of a memory according to some implementations of the present disclosure.

[0014] Figure 3 is a block schematic diagram illustrating electronic components of some embodiments of the present disclosure.

[0015] Figure 4 is a circuit schematic diagram illustrating a control unit of a memory according to some implementations of the present disclosure.

[0016] Figure 5 is a timing diagram illustrating the operation of the memory according to some embodiments of the present disclosure.

[0017] Figure 6 is a timing diagram illustrating the operation of the memory according to some embodiments of the present disclosure.

[0018] Figure 7 is a timing diagram illustrating the operation of a memory modified by a control unit in some embodiments of the present disclosure.

[0019] Figure 8 is a circuit schematic diagram illustrating a control unit of a memory according to some implementations of the present disclosure.

[0020] Fig. 9 is a circuit schematic diagram illustrating a first portion of a control unit of a memory according to some implementations of the present disclosure.

[0021] Fig.10 is a circuit schematic diagram illustrating a second portion of a control unit of a memory according to some implementations of the present disclosure.

[0022] Fig.11is a flowchart diagram illustrating a memory control method according to some embodiments of the present disclosure.

[0023] Fig.12 is a flowchart diagram illustrating a memory control method according to some embodiments of the present disclosure.

[0024] Description of reference numerals:

[0025] 10: Controller

[0026] 100: Electronic components

[0027] 11: Memory

[0028] 111: Control unit

[0029] 12: Control unit

[0030] 121: p-type transistor

[0031] 122: n-type transistor

[0032] 123: p-type transistor

[0033] 124: n-type transistor

[0034] 12A: Part 1

[0035] 12B: Part 2

[0036] 12R1: Resistor

[0037] 12R2: Resistor

[0038] 12R3: Resistor

[0039] 12R4: Resistor

[0040] 200: Electronic components

[0041] 22: Control unit

[0042] 221: First input stage

[0043] 2211: First input terminal

[0044] 2212: Second input terminal

[0045] 2213: Terminal

[0046] 2214: Terminal

[0047] 222: First output stage

[0048] 222T: Transistor

[0049] 222R: Resistor

[0050] 223: Second input stage

[0051] 2231: First input terminal

[0052] 2232: Second input terminal

[0053] 2233: Terminal

[0054] 2234: Terminal

[0055] 224: Second output stage

[0056] 224R: Resistor

[0057] 224T: Transistor

[0058] 22A: Part I

[0059] 22B: Part 2

[0060] 32: Control unit

[0061] 321: First input stage

[0062] 323: Second input stage

[0063] 32A: Part I

[0064] 32B: Part 2

[0065] 32T1: First p-type transistor

[0066] 32T2: First n-type transistor

[0067] 32T3: Second p-type transistor

[0068] 32T4: Second n-type transistor

[0069] 32T5: The first p-type transistor

[0070] 32T6: The first n-type transistor

[0071] 32T7: Second p-type transistor

[0072] 32T8: Second n-type transistor

[0073] 400: Control Methods

[0074] 500: Control Methods

[0075] CS1: command control signal

[0076] D11: Drain

[0077] D22: Drain

[0078] DQ0, DQ1, ..., DQ15: data lines

[0079] DQS1: First signal

[0080] DQS1': The third signal

[0081] DQS2': The fourth signal

[0082] DQS2: Second signal

[0083] G11: Gate

[0084] G22: Gate

[0085] GND: Ground

[0086] PDQS1: First processed signal

[0087] PDQS2: Second processed signal

[0088] R21~R24: resistance value

[0089] R41~R44: resistance value

[0090] R31: resistance value

[0091] R50: resistance value

[0092] R51: resistance value

[0093] S11: Source

[0094] S22: Source

[0095] S401: Steps

[0096] S403: Steps

[0097] S405: Steps

[0098] S407: Steps

[0099] S409: Steps

[0100] S411: Steps

[0101] S509: Steps

[0102] S511: Steps

[0103] S513: Steps

[0104] S515: Steps

[0105] T0~T5:cycle period

[0106] T-1~T-4: Cycle

[0107] V1~V4: voltage value

[0108] VDD: power supply voltage DETAILED DESCRIPTION

[0109] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0110] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0111] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0112] Figure 1 1 is a block diagram illustrating an electronic component 100 of some embodiments of the present disclosure. The electronic component 100 includes a controller 10 and a memory 11, and the memory 11 is connected to the controller 10 via a line, a system bus or a wireless method. The controller 10 may include a CPU. The memory 11 may include a double data rate synchronous dynamic random access memory (DDR SDRAM) or the like.

[0113] The controller 10 is configured to access the memory 11. The memory 11 is configured to store data. The controller 10 is configured to generate a command control signal CS1 and transmit it to the memory 11 via, for example, a command line. The controller 10 and the memory 11 are communicatively connected to each other via data lines DQ0, DQ1, ..., DQ15. The data lines DQ0, DQ1, ..., DQ15 are configured to transmit data to and from the memory 11 or the controller 10. The controller 10 and the memory 11 are communicatively connected to each other via a bidirectional line that transmits a first signal (or an input signal) DQS1 and a second signal (or an input signal) DQS2 to or from the memory or the controller 10. The first signal DQS1 and the second signal DQS2 may be data strobe signals (i.e., write data strobe signals). The first signal DQS1 may be a positive data strobe signal, and the second signal DQS2 may be a negative data strobe signal. The memory 11 may be configured to transmit two data words per clock cycle using the positive and negative edges of the clock. For each data word, the first signal DQS1 and the second signal DQS2 are transmitted for synchronization.

[0114] The memory 11 includes a control unit 111 and a control unit 12, and the control unit 12 is in communication with the control unit 111. In some embodiments, the control unit 111 and the control unit 12 are integrated together.

[0115] The control unit 111 may include a command decoder, a one-bit multiplexer, a data input / output (I / O) circuit, and a clock generator. The command decoder is configured to interpret the command control signal CS1. The address multiplexer selects an appropriate memory bank and row / column address according to the command control signal CS1 and multiple address signals. The data input / output circuit is configured to process the input and output of data from or to the memory bank / array. The clock generator is configured to generate multiple clock signals for the memory 11.

[0116] The control unit 12 is configured to receive the first signal DQS1 and the second signal DQS2 and generate a third signal DQS1' and a fourth signal DQS2'. The control unit 12 may include a differential amplifier that amplifies the difference between the first signal DQS1 and the second signal DQS2 while suppressing any common mode signals. The enhanced third signal DQS1' and the fourth signal DQS2' are transmitted to the control unit 111 via, for example, a plurality of lines or a bus. The enhanced third signal DQS1' and the fourth signal DQS2' may be referred to as data strobe signals and are used as timing signals to align data with a clock signal during data transmission.

[0117] Figure 2 is a circuit schematic diagram illustrating a control unit (ie, control unit 12) of a memory (ie, memory 11) of some implementations of the present disclosure.

[0118] The control unit 12 may include a first portion 12A and a second portion 12B. The first portion 12A includes a p-type transistor 121, an n-type transistor 122, a resistor 12R1, and a resistor 12R2. The second portion 12B includes a p-type transistor 123, an n-type transistor 124, a resistor 12R3, and a resistor 12R4. The p-type transistor 121 and the p-type transistor 123 may include a p-type MOS field effect transistor (FET). The n-type transistor 122 and the n-type transistor 124 may include an n-type MOSFET.

[0119] The p-type transistor 121 has a source connected to a power supply voltage VDD, a gate configured to receive the second signal DQS2, and a drain connected to the resistor 12R1. The n-type transistor 122 has a drain connected to the drain of the p-type transistor 121, a gate connected to the resistor 12R1, and a source connected to the resistor 12R2 and configured to generate the third signal DQS1'. The resistor 12R1 is connected to the resistor 12R3. The resistor 12R2 is connected to the ground GND. The p-type transistor 123 has a source connected to the power supply voltage VDD, a gate configured to receive the first signal DQS1, and a drain connected to the resistor 12R3. The n-type transistor 124 has a drain connected to the drain of the p-type transistor 123, a gate connected to the resistor 12R3, and a source connected to the resistor 12R4 and configured to generate the fourth signal DQS2'. The resistor 12R4 is connected to the ground GND.

[0120] Table 1-1 describes logic values ​​of the first signal DQS1 , the second signal DQS2 , the third signal DQS1 ′, and the fourth signal DQS2 ′ according to the control unit 12 .

[0121] DQS1 DQS2 DQS1' DQS2' 0 0 1 1 0 1 0 1 1 0 1 0 1 1 0 0

[0122] Table 1-1

[0123] Assume that the first signal DQS1 and the second signal DQS2 are a differential pair, which means that the first signal DQS1 and the second signal DQS2 are complementary, for example, the first signal DQS1 has a high logic value "1", and the second signal DQS2 has a low logic value "0", and vice versa. In some cases, the first signal DQS1 and the second signal DQS2 may violate the JEDEC standard, such as accidentally being set to the same logic value, such as a logic high value "1" or a logic low value "0". The third signal DQS1' and the fourth signal DQS2' therefore have the same logic value. The non-complementary third signal DQS1' and the fourth signal DQS2' may cause the memory 11 to malfunction when transmitted to the control unit 111. In some embodiments, the non-complementary data select signals DQS1' and DQS2' may cause the data write operation of the memory 11 to fail.

[0124] Figure 3 is a block diagram illustrating an electronic component 200 of some embodiments of the present disclosure. Figure 3 The characteristics of components with the same component number in Figure 1 Related description. Figure 1 The control unit 12 of the electronic component 100 may be composed of Figure 3 In some embodiments, the control unit 12 may be retained in the memory 11, and the control unit 22 is a component in the memory 11 that first receives the first signal DQS1 and the second signal DQS2.

[0125] The control unit 22 is communicatively connected to the control unit 111 via a line and a system bus. The control unit 22 is configured to receive the first signal DQS1 and the second signal DQS2 and generate a first processing signal PDQS1 and a second processing signal PDQS2. Whether the first signal DQS1 and the second signal DQS2 are the same or different, the first processing signal PDQS1 and the second processing signal PDQS2 can be complementary. The memory can successfully operate with the complementary first processing signal PDQS1 and the second processing signal PDQS2. The complementary first processing signal PDQS1 and the second processing signal PDQS2 are called (write) data select signals and are used as timing signals to align data with the clock signal during data transmission. The memory 11 can be configured to transmit two data words per clock cycle using the positive and negative edges of the clock. For each data word, a differential pair of the first processing signal PDQS1 and the second processing signal PDQS2 is transmitted for synchronization.

[0126] Figure 4 is a circuit schematic diagram illustrating a control unit (ie, control unit 22) of a memory (ie, memory 11) of some implementations of the present disclosure.

[0127] The control unit 22 may include a first portion 22A and a second portion 22B. Figure 4 In the embodiment, for the purpose of explanation, the first portion 22A and the second portion 22B are separated. The first portion 22A and the second portion 22B may be physically connected or electrically connected.

[0128] The first part 22A of the control unit 22 includes a first input stage 221 and a first output stage 222, and the first output stage 222 is connected to the first input stage 221. The first input stage 221 is configured to receive a first signal DQS1 and a second signal DQS2. The first output stage 222 is configured to generate a first processed signal PDQS1. The first input stage 221 has a first input terminal 2211, a second input terminal 2212, a terminal 2213, and a terminal 2214. The first input terminal 2211 of the first input stage 221 is configured to receive the first signal DQS1. The second input terminal 2212 of the first input stage 221 is configured to receive the second signal DQS2. The terminal 2213 is connected to the first output stage 222. The terminal 2214 is connected to the power supply voltage VDD.

[0129] The first output stage 222 includes a transistor 222T and a resistor 222R. The transistor 222T may include an n-type MOSFET. The transistor 222T and the resistor 222R may be configured as a source follower. The transistor 222T has a drain D11 connected to the terminal 2213 of the first input stage 221, a gate G11 configured to receive the first signal DQS1, and a source S11 configured to output the first processing signal PDQS1. The source S11 of the transistor 222T is connected to the resistor 222R. The resistor 222R is connected to the ground GND. The first output stage 222 has an input terminal (i.e., gate G11) configured to receive the first signal DQS1 and an output terminal (i.e., source S11) configured to output the first processing signal PDQS1.

[0130] The second part 22B of the control unit 22 includes a second input stage 223 and a second output stage 224, and the second output stage 224 is connected to the second input stage 223. The second input stage 223 is configured to receive the first signal DQS1 and the second signal DQS2. The second output stage 224 is configured to generate the second processed signal PDQS2. The second input stage 223 has a first input terminal 2231, a second input terminal 2232, a terminal 2233 and a terminal 2234. The first input terminal 2231 of the second input stage 223 is configured to receive the second signal DQS2. The second input terminal 2232 of the second input stage 223 is configured to receive the first signal DQS1. The terminal 2233 is connected to the second output stage 224. The terminal 2234 is connected to the ground GND.

[0131] The second output stage 224 includes a transistor 224T and a resistor 224R. The transistor 224T may include a p-type MOSFET. The transistor 224T and the resistor 224R may be configured as a source follower. The transistor 224T has a drain D22 connected to the terminal 2233 of the second input stage 223, a gate G22 configured to receive the second signal DQS2, and a source S22 configured to output the second processing signal PDQS2. The source S22 of the transistor 224T is connected to the resistor 224R. The resistor 224R is connected to the power supply voltage VDD. The second output stage 224 has an input terminal (i.e., gate G22) configured to receive the second signal DQS2 and an output terminal (i.e., source S22) configured to output the second processing signal PDQS2.

[0132] Based on the first signal DQS1 and the second signal DQS2, the state of the first input stage 221 is adjustable. If the first signal DQS1 and the second signal DQS2 are the same, for example, have the same logic value, the first input stage 221 is open (or off). The open state of the first input stage 221 means that it is cut off. The equivalent resistance value of the first input stage 221 is significantly greater than the equivalent resistance value of the resistor 222R. If the first signal DQS1 and the second signal DQS2 are different, for example, have complementary logic values, the first input stage 221 is turned on (or turned on). The on state of the first input stage 221 means that it is turned on. The equivalent resistance value of the first input stage 221 is significantly less than the equivalent resistance value of the resistor 222R.

[0133] When the first input stage 221 is open, the output terminal S11 of the first output stage 222 is pulled down to ground regardless of the logic value of the first signal DQS1. The first processed signal PDQS1 may have a low logic value of "0". That is, the first input stage 221 is open to separate the first processed signal PDQS1 from the first signal DQS1.

[0134] Based on the first signal DQS1 and the second signal DQS2, the state of the second input stage 223 is adjustable. If the first signal DQS1 and the second signal DQS2 are the same, for example, have the same logic value, the second input stage 223 is open. The open state (or cut-off state) of the second input stage 223 means that it is cut off. The equivalent resistance value of the second input stage 223 is significantly greater than the equivalent resistance value of the resistor 224R. If the first signal DQS1 and the second signal DQS2 are different, for example, have complementary logic values, the second input stage 223 is turned on. The on state (or open state) of the second input stage 223 means that it is turned on. The equivalent resistance value of the second input stage 223 is significantly less than the equivalent resistance value of the resistor 224R.

[0135] When the second input stage 223 is open, the output terminal S22 of the second output stage 224 is pulled up to the power supply voltage VDD regardless of the logic value of the second signal DQS2. The second processed signal PDQS2 may have a high logic value "1". That is, the second input stage 223 is open to separate the second processed signal PDQS2 from the second signal DQS2.

[0136] If the first signal DQS1 and the second signal DQS2 are the same, the first processing signal PDQS1 and the second processing signal PDQS2 are different, for example, complementary. Table 1-2 describes the logic values ​​of the first signal DQS1, the second signal DQS2, the first processing signal PDQS1 and the second processing signal PDQS2 according to the control unit 22.

[0137] DQS1 DQS2 PDQS1 PDQS2 0 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1

[0138] Table 1-2

[0139] The adjustable states of the first input stage 221 and the second input stage 223 allow the control unit 22 to accept the first signal DQS1 and the second signal DQS2 (i.e., data strobe signals having the same logic value) that violate the JEDEC standard. In the open state, the control unit 22 is configured to regenerate the first processing signal PDQS1 and the second processing signal PDQS2 separated from the first signal DQS1 and the second signal DQS2. In the on state, the control unit 22 is configured to allow the first processing signal PDQS1 and the second processing signal PDQS2 to follow the first signal DQS1 and the second signal DQS2, respectively. The first processing signal PDQS1 and the second processing signal PDQS2 may be the same as the first signal DQS1 and the second signal DQS2, respectively. In the open state and the on state, the first processing signal PDQS1 and the second processing signal PDQS2 may be complementary. Through the control unit 22, the memory 11 may successfully operate using the first processing signal PDQS1 and the second processing signal PDQS2.

[0140] Figure 5 1 is a timing diagram illustrating the operation of the memory 11 in some embodiments of the present disclosure. Figure 5 As shown, the first signal DQS1 and the second signal DQS2 (i.e., write data strobe signal) have a low logic value "low" in the cycle periods T-4, T-3, T-2 and T-1. The data write operation of the memory 11 will fail because it violates the JEDEC standard. For example, the preamble in the cycle periods T0, T1, T2 and T3 before data transmission cannot be aligned with the first signal DQS1 and the second signal DQS2. Subsequently, the data signals in the cycle periods T4 and T5 will not be transmitted at the correct timing.

[0141] Figure 6 1 is a timing diagram illustrating the operation of the memory 11 in some embodiments of the present disclosure. Figure 6 As shown, the first signal DQS1 and the second signal DQS2 (i.e., the write data strobe signal) have a high logic value "high" in the cycle periods T-4, T-3, T-2 and T-1. The data write operation of the memory 11 will fail because it violates the JEDEC standard. For example, the preamble in the cycle periods T0, T1, T2 and T3 before data transmission cannot be aligned with the first signal DQS1 and the second signal DQS2. Subsequently, the data signals in the cycle periods T4 and T5 will not be transmitted at the correct timing.

[0142] Figure 7 1 is a timing diagram illustrating the operation of the memory 11 modified by the control unit 22 in some embodiments of the present disclosure. The control unit 22 is configured to regenerate a differential pair of data strobe signals, namely, the first processing signal PDQS1 and the second processing signal PDQS2. If the first signal DQS1 and the second signal DQS2 both have a first logic value, such as Figure 5 "Low" or Figure 6 In the cycle periods T-4, T-3, T-2 and T-1, the first processing signal PDQS1 and the second processing signal PDQS2 have a second logic value "low" or "high" different from the first logic value. The first processing signal PDQS1 and the second processing signal PDQS2 in the cycle periods T-4, T-3, T-2 and T-1 comply with the JEDEC standard. The preambles in the cycle periods T0, T1, T2 and T3 before data transmission can be aligned with the first processing signal PDQS1 and the second processing signal PDQS2. Subsequently, the data signals in the cycle periods T4 and T5 can be transmitted at the correct timing.

[0143] Figure 8 is a circuit diagram illustrating a control unit 32 of a memory (ie, memory 11) of some embodiments of the present disclosure. Figure 8The characteristics of components with the same component number can be referred to Figure 4 Related description.

[0144] The control unit 32 may include a first part 32A and a second part 32B. The first part 32A includes a first input stage 321, instead of Figure 4 The second part 32B includes a second input stage 323 instead of Figure 4 The second input stage 223.

[0145] The first input stage 321 includes a first p-type transistor 32T1, a first n-type transistor 32T2, a second p-type transistor 32T3 and a second n-type transistor 32T4. The first p-type transistor 32T1 and the second p-type transistor 32T3 may include a p-type MOSFET. The first n-type transistor 32T2 and the second n-type transistor 32T4 may include an n-type MOSFET. The first p-type transistor 32T1 and the first n-type transistor 32T2 are connected in series and are referred to as a first series circuit. The second p-type transistor 32T3 and the second n-type transistor 32T4 are connected in series and are referred to as a second series circuit. The first p-type transistor 32T1 and the second p-type transistor 32T3 are connected to the power supply voltage VDD. The first n-type transistor 32T2 and the second n-type transistor 32T4 are connected to the first output stage 222.

[0146] The first p-type transistor 32T1 and the second n-type transistor 32T4 are configured to receive the first signal DQS1. In some embodiments, each gate of the first p-type transistor 32T1 and the second n-type transistor 32T4 is configured to receive the first signal DQS1. The second p-type transistor 32T3 and the first n-type transistor 32T2 are configured to receive the second signal DQS2. In some embodiments, each gate of the second p-type transistor 32T3 and the first n-type transistor 32T2 is configured to receive the second signal DQS2.

[0147] If the first signal DQS1 and the second signal DQS2 are the same, for example, have a low logic value "0" or a high logic value "1", then both the first series circuit and the second series circuit are cut off. The first input stage 321 is open (or cut off). The equivalent resistance value of the first input stage 321 can be assumed to be infinite or significantly larger than the equivalent resistance value of the resistor 222R. In this way, the first output stage 222 pulls the first processing signal PDQS1 down to the ground GND. That is, the first input stage 321 is open to separate the first processing signal PDQS1 from the first signal DQS1. If the first signal DQS1 and the second signal DQS2 are different, for example, complementary, one has a low logic value "0" and the other has a high logic value "1", then at least one of the first series circuit and the second series circuit is turned on or turned on. The equivalent resistance value of the first input stage 321 is equal to the drain-source on-resistance value (R DS (on)) or an equivalent resistance value significantly smaller than the resistor 222R. The first output stage 222 is connected to the power supply voltage VDD via the turned-on first input stage 321. In this way, the first output stage 222 operates as a source follower to generate a first processed signal PDQS1 associated with the first signal DQS1. The first processed signal PDQS1 at the output terminal (i.e., source S11) can follow the first signal DQS1 at the input terminal (i.e., gate G11).

[0148] The second input stage 323 includes a first p-type transistor 32T5, a first n-type transistor 32T6, a second p-type transistor 32T7 and a second n-type transistor 32T8. The first p-type transistor 32T5 and the second p-type transistor 32T7 may include a p-type MOSFET. The first n-type transistor 32T6 and the second n-type transistor 32T8 may include an n-type MOSFET. The first p-type transistor 32T5 and the first n-type transistor 32T6 are connected in series and are referred to as a third series circuit. The second p-type transistor 32T7 and the second n-type transistor 32T8 are connected in series and are referred to as a fourth series circuit. The first p-type transistor 32T5 and the second p-type transistor 32T7 are connected to the second output stage 224. The first n-type transistor 32T6 and the second n-type transistor 32T8 are connected to the ground GND.

[0149] The first p-type transistor 32T5 and the second n-type transistor 32T8 are configured to receive the first signal DQS1. In some embodiments, each gate of the first p-type transistor 32T5 and the second n-type transistor 32T8 is configured to receive the first signal DQS1. The second p-type transistor 32T7 and the first n-type transistor 32T6 are configured to receive the second signal DQS2. In some embodiments, each gate of the second p-type transistor 32T7 and the first n-type transistor 32T6 is configured to receive the second signal DQS2.

[0150] If the first signal DQS1 and the second signal DQS2 are the same, for example, have a low logic value "0" or a high logic value "1", the third series circuit and the fourth series circuit are both turned off. The second input stage 323 is open (or cut off). The equivalent resistance value of the second input stage 323 can be assumed to be infinite or significantly larger than the equivalent resistance value of the resistor 224R. In this way, the second output stage 224 pulls up the second processing signal PDQS2 to the power supply voltage VDD. That is, the second input stage 323 is open to separate the second processing signal PDQS2 from the second signal DQS2. If the first signal DQS1 and the second signal DQS2 are different, for example, complementary, one has a low logic value "0" and the other has a high logic value "1", at least one of the third series circuit and the fourth series circuit is turned on. The equivalent resistance value of the second input stage 323 is equal to the drain-source on-resistance value (R DS (on)) or an equivalent resistance value significantly less than the resistor 224R. The second output stage 224 is connected to the ground GND via the conductive second input stage 323. In this way, the second output stage 224 operates as a source follower to generate a second processed signal PDQS2 associated with the second signal DQS2. The second processed signal PDQS2 at the output terminal (i.e., source S22) can follow the second signal DQS2 at the input terminal (i.e., gate G22).

[0151] The adjustable states of the first input stage 321 and the second input stage 323 allow the control unit 22 to accept the first signal DQS1 and the second signal DQS2 (i.e., data strobe signals having the same logic value) that violate the JEDEC standard. In the open state (or cut-off state), the control unit 22 is configured to regenerate the first processing signal PDQS1 and the second processing signal PDQS2 separated from the first signal DQS1 and the second signal DQS2. In the on state (or turn-on state), the control unit 22 is configured to let the first processing signal PDQS1 and the second processing signal PDQS2 follow the first signal DQS1 and the second signal DQS2, respectively. The first processing signal PDQS1 and the second processing signal PDQS2 may be the same as the first signal DQS1 and the second signal DQS2, respectively. In the open state and the on state, the first processing signal PDQS1 and the second processing signal PDQS2 may be complementary. The memory 11 may successfully operate using the first processing signal PDQS1 and the second processing signal PDQS2.

[0152] Fig. 9 is a circuit schematic diagram illustrating a first portion (ie, first portion 32A) of a control unit (ie, control unit 32) of a memory according to some implementations of the present disclosure. Fig. 9The operation of the first portion 32A in an analog signal is shown.

[0153] The first signal DQS1 has a voltage value V1. The second signal DQS2 has a voltage value V2. The first p-type transistor 32T1 has a resistance value R21. The first n-type transistor 32T2 has a resistance value R22. The second p-type transistor 32T3 has a resistance value R23. The second n-type transistor 32T4 has a resistance value R24. The equivalent resistance value of the first input stage 321 is (R21+R22) / / (R23+R24). The transistor 222T has a resistance value R11. The transistor 222R has a resistance value R50 which may be equal to 100K ohms.

[0154] A voltage value V3 of the first processed signal PDQS1 is obtained by the following equation:

[0155]

[0156] The ratio of the voltage value V3 of the first processing signal PDQS to the power supply voltage VDD is equal to the resistance value R50 divided by the sum of the resistance value R50, the resistance value R11, and the equivalent resistance value (R21+R22) / / (R23+R24).

[0157] In some embodiments, when the voltage value V1 of the first signal DQS1 is 0V and the voltage value V2 of the second signal DQS2 is 0V, the p-type transistors 32T1 and 32T3 are turned on, and the n-type transistors 32T2 and 32T4 and the transistor 222T are turned off. The resistance value R21 and the resistance value R23 are equal to about 0 ohms, the resistance value R22 and the resistance value R24 are equal to about 2M ohms, and the resistance value R11 is equal to about 2M ohms. The voltage value V3 of the first processing signal PDQS1 is equal to about 0.03V, which is close to 0V.

[0158] In some embodiments, when the voltage value V1 of the first signal DQS1 is 1V and the voltage value V2 of the second signal DQS2 is 1V, the p-type transistors 32T1 and 32T3 are turned off, and the n-type transistors 32T2 and 32T4 and the transistor 222T are turned on. The resistance value R21 and the resistance value R23 are equal to about 2M ohms, the resistance value R22 and the resistance value R24 are equal to about 0 ohms, and the resistance value R11 is equal to about 0 ohms. The voltage value V3 of the first processing signal PDQS1 is equal to about 0.09V, which is close to 0V.

[0159] In some embodiments, when the voltage value V1 of the first signal DQS1 is 1V and the voltage value V2 of the second signal DQS2 is 0V, the first p-type transistor 32T1 and the first n-type transistor 32T2 are turned off, and the second p-type transistor 32T3 and the second n-type transistor 32T4 and the transistor 222T are turned on. The resistance values ​​R21 and R22 are equal to about 2M ohms, the resistance values ​​R23 and R24 are equal to about 0 ohms, and the resistance value R11 is equal to about 0 ohms. The voltage value V3 of the first processing signal PDQS1 is equal to about 1V.

[0160] In some embodiments, when the voltage value V1 of the first signal DQS1 is 0.3V and the voltage value V2 of the second signal DQS2 is 0.7V, the resistance values ​​R21 and R22 are equal to about 30K ohms, the resistance values ​​R23 and R24 are equal to about 70K ohms, and the resistance value R11 is equal to about 70K ohms. The voltage value V3 of the first processing signal PDQS1 is equal to about 0.47V.

[0161] Fig.10 is a circuit diagram illustrating a second part (ie, second part 32B) of a control unit (ie, control unit 32) of a memory (ie, memory 11) according to some implementations of the present disclosure. Fig.10 The operation of the second portion 32B in an analog signal is shown.

[0162] The first signal DQS1 has a voltage value V1. The second signal DQS2 has a voltage value V2. The first p-type transistor 32T5 has a resistance value R41. The first n-type transistor 32T6 has a resistance value R42. The second p-type transistor 32T7 has a resistance value R43. The second n-type transistor 32T8 has a resistance value R44. The equivalent resistance value of the second input stage 323 is (R41+R42) / / (R43+R44). The transistor 224T has a resistance value R31. The transistor 224R has a resistance value R51 which can be equal to 100K ohms.

[0163] A voltage value V4 of the second processed signal PDQS2 is obtained by the following equation:

[0164]

[0165] The ratio of the voltage value V4 of the first processing signal PDQS1 to the power supply voltage VDD is equal to the sum of the resistor R31 and the equivalent resistor (R41+R42) / / (R43+R44) divided by the sum of the resistor R51, the resistor R31 and the equivalent resistor (R41+R42) / / (R43+R44).

[0166] In some embodiments, when the voltage value V1 of the first signal DQS1 is 0V and the voltage value V2 of the second signal DQS2 is 0V, the p-type transistors 32T5, 32T7 and the transistor 224T are turned on, and the n-type transistors 32T6, 32T8 are turned off. The resistance value R41 and the resistance value R43 are equal to about 0 ohm, the resistance value R42 and the resistance value R44 are equal to about 2M ohms, and the resistance value R31 is equal to about 0 ohm. The voltage value V4 of the second processing signal PDQS2 is equal to about 0.97V, which is close to 1V.

[0167] In some embodiments, when the voltage value V1 of the first signal DQS1 is 1V and the voltage value V2 of the second signal DQS2 is 0V, the first p-type transistor 32T5 and the first n-type transistor 32T6 are turned off, and the second p-type transistor 32T7 and the second n-type transistor 32T8 and the transistor 224T are turned on. The resistance values ​​R41 and R42 are equal to about 2M ohms, the resistance values ​​R43 and R44 are equal to about 0 ohms, and the resistance value R31 is equal to about 0 ohms. The voltage value V4 of the second processing signal PDQS2 is equal to about 0V.

[0168] Fig.11 4 is a flow chart illustrating a control method 400 of a memory (ie, the memory 11 ) according to some embodiments of the present disclosure.

[0169] The control method 400 starts at step S401, which includes receiving a first signal (i.e., first signal DQS1) and a second signal (i.e., second signal DQS2) through a first input stage (i.e., first input stage 221 or 321). The first signal and the second signal may be write data strobe signals from a controller (i.e., controller 10).

[0170] The control method 400 continues with step S403 , which includes receiving the first signal and the second signal through a second input stage (ie, the second input stage 223 or 323 ).

[0171] The control method 400 continues with step S405, including generating a first processed signal (i.e., first processed signal PDQS1) by a first output stage (i.e., first output stage 222) connected to the first input stage. The first output stage may have an input terminal configured to receive the first signal and an output terminal configured to output the first processed signal.

[0172] The control method 400 continues with step S407, including generating a second processed signal (i.e., second processed signal PDQS2) by a second output stage (i.e., second output stage 224) connected to the second input stage. The second output stage may have an input terminal configured to receive the second signal and an output terminal configured to output the second processed signal.

[0173] The control method 400 continues with step S409, including differentiating the first processed signal and the second processed signal if the first signal and the second signal are the same. The first processed signal and the second processed signal are complementary. Step S409 may include separating the first processed signal and the second processed signal from the first signal and the second signal, respectively.

[0174] The control method 400 continues with step S411, including associating the first processed signal and the second processed signal with the first signal and the second signal, respectively, if the first signal and the second signal are different. Step S411 may include letting the first processed signal and the second processed signal follow the first signal and the second signal.

[0175] Using the control method 400, the first processing signal and the second processing signal are complementary, regardless of whether the first signal and the second signal are the same or different. Even if the first signal and the second signal (i.e., the write data strobe signal from the controller) violate the JEDEC standard, the memory can successfully operate using the complementary first processing signal and the second processing signal.

[0176] The control method 400 is merely an example and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional steps may be provided before, during, or after each step of the control method 400, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, the control method 400 may include Fig.11 In some embodiments, the control method 400 may include: Fig.11 One or more steps shown.

[0177] Fig.12 is a flowchart illustrating a control method 500 of a memory (ie, memory 11) according to some embodiments of the present disclosure. Fig.12 The characteristics of components with the same component number can be referred to Fig.11 Related description.

[0178] The control method 500 includes steps S401 , S403 , S405 and S407 .

[0179] The control method 500 continues with step S509, including turning off the first input stage to separate the first signal from the first processed signal if the first signal and the second signal are the same. Step S509 may include pulling the first processed signal down to ground (ie, GND) by the first output stage.

[0180] The control method 500 continues with step S511, including turning off the second input stage to separate the second signal from the second processing signal if the first signal and the second signal are the same. Step S511 may include pulling the second processing signal up to the power supply voltage (ie, VDD) through the second output stage.

[0181] The control method 500 continues with step S513, including turning on the first input stage to associate the first signal with the first processed signal if the first signal and the second signal are different. Step S513 may include passing the first output stage to let the first processed signal follow the first signal.

[0182] The control method 500 continues with step S515, including turning on the second input stage to associate the second signal with the second processed signal if the first signal and the second signal are different. Step S515 may include passing the second output stage to make the second processed signal follow the second signal.

[0183] Using the control method 500, the regenerated first processing signal and the second processing signal are complementary, whether the first signal and the second signal are the same or different. Even if the first signal and the second signal (i.e., the write data strobe signal from a controller) violate the JEDEC standard, the memory can successfully operate using the first processing signal and the second processing signal PDQS2.

[0184] An embodiment of the present disclosure provides a control unit of a memory, comprising a first input stage, a second input stage, a first output stage and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processing signal. The second output stage is connected to the second input stage and configured to generate a second processing signal. If the first signal is the same as the second signal, the first processing signal is different from the second processing signal.

[0185] Another embodiment of the present disclosure provides a control unit of a memory, comprising a first input stage and a first output stage. The first input stage comprises a first input terminal configured to receive a first signal and a second input terminal configured to receive a second signal. The first output stage is connected to the first input stage and comprises an output terminal configured to generate a first processed signal. If the first signal and the second signal are the same, the first input stage is open circuited to separate the first processed signal from the first signal.

[0186] Another embodiment of the present disclosure provides a control method for a memory, comprising receiving a first signal and a second signal through a first input stage; receiving the first signal and the second signal through a second input stage; generating a first processing signal through a first output stage connected to the first input stage; generating a second processing signal through a second output stage connected to the second input stage; and if the first signal and the second signal are the same, differentiating the first processing signal and the second processing signal.

[0187] The control unit of the memory disclosed in the present invention includes a first input stage, a second input stage, a first output stage and a second output stage. The first input stage and the second input stage are configured to receive a first signal and a second signal (i.e., from a memory controller). The first output stage and the second output stage are configured to generate a first processing signal and a second processing signal, which can be transmitted to an internal control circuit of the memory, or can be used as a clock signal of multiple data lines of the memory for synchronization. The state of the first input stage and the second input stage changes based on whether the first signal and the second signal are the same or different. If the first signal and the second signal are the same, the first input stage and the second input stage are open (or cut-off) to differentiate the first processing signal and the second processing signal. The first processing signal is separated from the first signal, and the second processing signal is separated from the second signal. If the first signal and the second signal are different, the first input stage and the second input stage conduct (or turn on) to associate the first processing signal and the second processing signal to the first signal and the second signal, respectively (i.e., the first processing signal and the second processing signal are the same as the first signal and the second signal, respectively). The adjustable state of the first input stage and the second input stage allows the control unit to accept the first signal and the second signal that violate the JEDEC standard (i.e., data selection signals with the same value). In the conducting state, the control unit is configured to let the first processing signal and the second processing signal follow the first signal and the second signal. In the open state, the control unit is configured to regenerate the first processing signal and the second processing signal separated from the first signal and the second signal. The memory can successfully operate with the first processing signal and the second processing signal.

[0188] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0189] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A control unit of a memory, comprising: a first input stage configured to receive a first signal and a second signal; a second input stage configured to receive the first signal and the second signal; a first output stage connected to the first input stage and configured to generate a first processed signal; as well as a second output stage connected to the second input stage and configured to generate a second processed signal; If the first signal is the same as the second signal, then the first processed signal is different from the second processed signal. 2 . The memory control unit as claimed in claim 1 , wherein the first signal and the second signal are write data strobe signals. 3 . The memory control unit as claimed in claim 2 , wherein the first signal and the second signal are transmitted by a controller. 4 . The control unit of the memory as claimed in claim 1 , wherein if the first signal and the second signal are different, the first processed signal and the second processed signal are respectively the same as the first signal and the second signal. 5 . The memory control unit as claimed in claim 4 , wherein the first signal and the second signal are complementary. 6 . The memory control unit as claimed in claim 1 , wherein no matter the first signal and the second signal are the same or different, the first processing signal and the second processing signal are complementary.

7. The control unit of the memory as claimed in claim 1, wherein if both the first signal and the second signal have a first logic value, one of the first processing signal and the second processing signal has a second logic value different from the first logic value.

8. A control unit of a memory as described in claim 1, wherein the first output stage includes a first transistor and a first resistor, the first resistor is connected to the first transistor and ground, wherein the first transistor has a drain connected to the first input stage, a gate configured to receive the first signal, and a source configured to output the first processed signal.

9. The memory control unit of claim 1, wherein the first input stage comprises a first p-type transistor, a second p-type transistor, a first n-type transistor and a second n-type transistor, and wherein, The first p-type transistor is connected in series with the first n-type transistor, and the second p-type transistor is connected in series with the second n-type transistor. 10 . The memory control unit of claim 9 , wherein the first p-type transistor and the second n-type transistor are configured to receive the first signal, and the second p-type transistor and the first n-type transistor are configured to receive the second signal. 11 . The control unit of the memory as claimed in claim 10 , wherein the first p-type transistor and the second p-type transistor are connected to a power supply voltage, and the first n-type transistor and the second n-type transistor are connected to the first output stage.

12. A control unit of a memory as described in claim 1, wherein the second output stage includes a second transistor and a second resistor, the second resistor is connected to the second transistor and a power supply voltage, wherein the second transistor has a drain connected to the second input stage, a gate configured to receive the second signal, and a source configured to output the second processed signal.

13. A control unit of a memory as described in claim 1, wherein the second input stage includes a first p-type transistor, a second p-type transistor, a first n-type transistor and a second n-type transistor, and wherein the first p-type transistor and the first n-type transistor are connected in series, and the second p-type transistor and the second n-type transistor are connected in series. 14 . The memory control unit of claim 13 , wherein the first p-type transistor and the second n-type transistor are configured to receive the first signal, and the second p-type transistor and the first n-type transistor are configured to receive the second signal. 15 . The control unit of the memory as claimed in claim 14 , wherein the first p-type transistor and the second p-type transistor are connected to the second output stage, and the first n-type transistor and the second n-type transistor are connected to ground.

16. A control unit of a memory, comprising: a first input stage comprising a first input terminal configured to receive a first signal and a second input terminal configured to receive a second signal; as well as a first output stage connected to the first input stage and comprising an output terminal configured to generate a first processed signal; If the first signal and the second signal are the same, the first input stage is open circuited to separate the first processed signal from the first signal. 17 . The memory control unit as claimed in claim 16 , wherein the first output stage comprises a first resistor having a first resistance value, and the first input stage has a second resistance value greater than the first resistance value.

18. A control unit of a memory as described in claim 17, wherein the first output stage includes a first transistor connected to the first resistor and having a third resistance value, wherein a ratio of a value of the first processing signal to a power supply voltage is equal to the first resistance value divided by the sum of the first resistance value, the second resistance value and the third resistance value.

19. The control unit of the memory as claimed in claim 16, wherein if the first signal and the second signal are different, the first input stage is turned on to associate the first processing signal with the first signal. 20 . The memory control unit as claimed in claim 19 , wherein the first output stage comprises a first resistor having a first resistance value, and the first input stage has a second resistance value smaller than the first resistance value.

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