MOS device and forming method thereof
By forming a barrier layer on the polysilicon layer and etching to form a gate structure in the LELE etching process, the problem of head morphology damage in the gate structure caused by too thick hard mask layer is solved, and a shorter etching process time and lower damage risk is achieved.
Patent Information
- Application Number
- CN202411722460.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-04-15
AI Technical Summary
In the LELE etching process, the hard mask layer on the gate structure is too thick, and the head form of the gate structure is easily damaged when the hard mask layer is removed.
A barrier layer is formed on the polysilicon layer to protect the top surface of the polysilicon layer, and a portion of the barrier layer and the polysilicon layer are etched in the first etching process to form a gate structure. The second etching process of removing the barrier layer does not damage the gate structure.
By using a barrier layer to protect the gate structure, the etching process time and damage when removing the hard mask layer is reduced, and the problem of head morphology damage to the gate structure caused by too thick hard mask layer is solved.
Smart Images
Figure CN119833397A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a MOS device and a method for forming the same. Background Art
[0002] With the increasing demand for SRAM (Static Random-Access Memory) storage in DDIC (Display Driver IC) products, the 40nm node HV (High Voltage Device) platform uses a smaller SRAM design than the standard area, achieving a smaller area with the same performance. To achieve this goal, the formation of the gate structure (poly) requires a LELE (LITHO-ETCH-LITHO-ETCH) process, and a very thick hard mask (hardmask) is required on the gate structure head to meet the requirements of two etchings. In the 40nm node HV platform process, thicker silicon oxide (Oxide) is selected as a hard mask instead of silicon nitride (Nitride) hard mask, because a very thick silicon nitride hard mask is not only difficult to remove, but also damages the head morphology of the gate structure after removal. The thickness of the hard mask layer made of silicon oxide still needs to be at least 800 angstroms. When removing the hard mask layer, the etching process takes a long time and the etching process will damage the head morphology of the gate structure. Summary of the invention
[0003] The object of the present invention is to provide a MOS device and a method for forming the same, so as to solve the problem that the hard mask layer on the gate structure is too thick and the head shape of the gate structure is damaged when the hard mask layer is removed.
[0004] In order to solve the above technical problems, the present invention provides a method for forming a MOS device, comprising:
[0005] Providing a substrate, on which a polysilicon layer is formed;
[0006] forming a barrier layer, the barrier layer covering the polysilicon layer, the barrier layer being used to protect the top surface of the polysilicon layer in a subsequent etching process;
[0007] Performing a first etching process to sequentially etch a portion of the barrier layer and a portion of the polysilicon layer, and the remaining polysilicon layer constitutes a gate structure;
[0008] A second etching process is performed to remove the barrier layer on the gate structure.
[0009] Optionally, the barrier layer is made of titanium nitride.
[0010] Optionally, the barrier layer has a thickness of 80 angstroms to 200 angstroms.
[0011] Optionally, the second etching process includes an SC1 process and an SC2 process.
[0012] Optionally, after forming the barrier layer, the method further comprises:
[0013] forming a hard mask layer, wherein the hard mask layer covers the barrier layer;
[0014] A bottom anti-reflective coating and a patterned photoresist layer are sequentially formed, wherein the bottom anti-reflective coating covers the hard mask layer, and the patterned photoresist layer covers the bottom anti-reflective coating, wherein in the first etching process, the patterned photoresist layer is used as a mask to sequentially etch the bottom anti-reflective coating, the hard mask layer, the barrier layer and the polysilicon layer to form the gate structure.
[0015] Optionally, after performing the first etching process and before performing the second etching process, the method further includes:
[0016] The hard mask layer is etched and the etching stops on the barrier layer.
[0017] Optionally, the material of the hard mask layer is silicon oxide, and the thickness of the hard mask layer is 150 angstroms to 250 angstroms.
[0018] Optionally, the first etching process is a LELE process.
[0019] Optionally, the substrate includes a low-voltage device area, a medium-voltage device area and a high-voltage device area arranged in sequence, a gate oxide layer is formed between the polysilicon layer and the substrate, and the gate oxide layer of the low-voltage device area, the gate oxide layer of the medium-voltage device area and the gate oxide layer of the high-voltage device area have different thicknesses.
[0020] Based on the same inventive concept, the present invention further provides a MOS device, which is manufactured using any of the above-mentioned methods for forming a MOS device.
[0021] In the method for forming a MOS device provided by the present invention, a barrier layer is formed on the polysilicon layer, the barrier layer covers the polysilicon layer, and the barrier layer is used to protect the top surface of the polysilicon layer in the subsequent etching process. Then, a first etching process is performed to sequentially etch part of the barrier layer and part of the polysilicon layer, and the remaining polysilicon layer constitutes a gate structure. The second etching process for removing the barrier layer does not damage the gate structure and the substrate surface, and does not change the head morphology of the gate structure. The present invention can avoid the need to form a hard mask layer, or only form a very thin hard mask layer. When removing the hard mask layer, the etching process time is short, and the barrier layer protects the surface of the gate structure from being etched. The present invention solves the problem that the hard mask layer on the gate structure in the LELE etching process is too thick, and the head morphology of the gate structure is damaged when the hard mask layer is removed. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0023] Figure 1 It is a flow chart of a method for forming a MOS device according to an embodiment of the present invention.
[0024] Figures 2 to 9 It is a schematic structural diagram corresponding to the steps of a method for forming a MOS device according to an embodiment of the present invention.
[0025] In the attached figure:
[0026] 10-substrate; 10a-low voltage device area; 10b-medium voltage device area; 10c-high voltage device area; 11-shallow trench isolation structure; 12a-first gate oxide layer; 12b-second gate oxide layer; 12c-third gate oxide layer; 13-polysilicon layer; 13a-gate structure; 14-blocking layer; 15-hard mask layer; 16-bottom anti-reflective coating; 17-patterned photoresist layer. DETAILED DESCRIPTION
[0027] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0028] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0029] Figure 1 FIG. 1 is a flow chart of a method for forming a MOS device according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a MOS device, including:
[0030] Step S10, providing a substrate, on which a polysilicon layer is formed;
[0031] Step S20, forming a barrier layer, wherein the barrier layer covers the polysilicon layer, and the barrier layer is used to protect the top surface of the polysilicon layer in a subsequent etching process;
[0032] Step S30, performing a first etching process to sequentially etch a portion of the barrier layer and a portion of the polysilicon layer, and the remaining polysilicon layer constitutes a gate structure;
[0033] Step S40: performing a second etching process to remove the barrier layer on the gate structure.
[0034] Figures 2 to 9 1 is a schematic diagram of the structure corresponding to the steps of the method for forming a MOS device according to an embodiment of the present invention. Figures 2 to 9 The specific embodiments of the present invention are described in detail.
[0035] like Figure 2As shown, a substrate 10 is provided. The substrate 10 can provide an operating platform for subsequent processes. It can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 is a silicon substrate. The substrate 10 includes a low-voltage device area 10a, a medium-voltage device area 10b, and a high-voltage device area 10c arranged in sequence. A shallow trench isolation structure 11 is formed on the substrate 10, and the shallow trench isolation structure is used to isolate the low-voltage device area 10a, the medium-voltage device area 10b, and the high-voltage device area 10c. A gate oxide layer is also formed on the substrate 10. Specifically, a first gate oxide layer 12a is formed on the substrate of the low-voltage device area 10a, a second gate oxide layer 12b is formed on the substrate of the medium-voltage device area 10b, and a third gate oxide layer 12c is formed on the substrate of the high-voltage device area 10c. Due to the different withstand voltages of low-voltage devices, medium-voltage devices, and high-voltage devices, the thicknesses of the first gate oxide layer 12a on the low-voltage device area 10a, the second gate oxide layer 12b on the medium-voltage device area 10b, and the third gate oxide layer 12c on the high-voltage device area 10c are different. A polysilicon layer 13 is formed on the substrate 10, and the polysilicon layer 13 covers the first gate oxide layer 12a, the second gate oxide layer 12b, the third gate oxide layer 12c, and the shallow trench isolation structure 11. The thickness of the first gate oxide layer 12 a is, for example, 20 angstroms to 50 angstroms, the thickness of the second gate oxide layer 12 b is, for example, 180 angstroms to 250 angstroms, and the thickness of the third gate oxide layer 12 c is, for example, greater than 1000 angstroms.
[0036] like Figure 3 As shown, a barrier layer 14 is formed, and the barrier layer 14 is located on the polysilicon layer 13 and covers the polysilicon layer 13. The barrier layer 14 is used to protect the top surface of the polysilicon layer 13 from being etched in the subsequent etching process, that is, to protect the top surface of the polysilicon layer 13 from being damaged. The material of the barrier layer 14 is, for example, titanium nitride, and can be formed by a physical vapor deposition process. The thickness of the barrier layer 14 is, for example, 80 angstroms to 200 angstroms. In this embodiment, only the barrier layer 14 can be formed without forming a hard mask layer. The barrier layer 14 can also act as a hard mask layer, and does not need to be too thick, and the etching solution for removing the barrier layer 14 does not damage the polysilicon layer and the substrate surface.
[0037] like Figure 4As shown, in some embodiments, after forming the barrier layer 14, a hard mask layer 15 is formed, and the hard mask layer 15 is located on the barrier layer 14 and covers the barrier layer 14. The material of the hard mask layer 15 is, for example, silicon oxide, and is formed by a chemical vapor deposition process. The thickness of the hard mask layer 15 is, for example, 150 angstroms to 250 angstroms, and preferably, the thickness of the hard mask layer 15 is 200 angstroms. The thickness of the hard mask layer 15 in this embodiment is much smaller than the thickness of the hard mask layer in the LELE process in the prior art. The thickness of the hard mask layer 15 in this embodiment is reduced, and in the subsequent etching process for removing the hard mask layer, the required etching process time is shortened, and the barrier layer protects the top surface of the polysilicon layer, reducing the damage to the polysilicon layer and the substrate caused by the etching process for removing the hard mask layer.
[0038] like Figure 5 As shown, a bottom anti-reflective coating 16 and a patterned photoresist layer 17 are formed in sequence, wherein the bottom anti-reflective coating 16 is located on the hard mask layer 15 , and the patterned photoresist layer 17 is located on the bottom anti-reflective coating 16 in the gate structure definition area and covers the bottom anti-reflective coating 16 .
[0039] like Figure 6 As shown, a first etching process is performed, using the patterned photoresist layer 17 as a mask, and etching a portion of the hard mask layer 15, a portion of the barrier layer 14 and a portion of the polysilicon layer 13 in sequence, and the remaining polysilicon layer 13 constitutes a gate structure 13a. The first etching process is, for example, a LELE process. LELE (photolithography-etching-photolithography-etching) transfers a dense line-space pattern to the polysilicon layer 13 to form a gate structure 13a through two independent photolithography and etching steps. The first photolithography and etching includes forming a semi-dense pattern on the photoresist layer, and transferring the semi-dense pattern to the hard mask layer 15 by etching. Then, the photoresist layer after the first photolithography is removed. The second photolithography and etching includes performing photolithography again on the hard mask layer 15, using a position-shifted mask pattern to form a semi-dense pattern that is staggered from the first semi-dense pattern. Then, the pattern on the hard mask layer 15 is transferred to the barrier layer 14 and the polysilicon layer 13.
[0040] like Figure 7 As shown, after the step of forming the gate structure 13a, if the patterned photoresist layer 17 has not been completely consumed, a photoresist removal process is required, and an ashing process or a stripping method is usually used to remove the remaining patterned photoresist layer 17.
[0041] like Figure 8As shown, the hard mask layer 15 is etched and the etching stops on the barrier layer 14. The hard mask layer 15 is removed by dry etching. In the prior art, the formation of the gate structure requires an LELE process, and a very thick hard mask layer is required on the gate structure head to meet the etching requirements of the two etching processes. The thickness of the hard mask layer is at least 800 angstroms, and the thickness of the hard mask layer is usually 1500 angstroms. Such a thick hard mask layer will cause damage to the top of the gate structure and the surface of the substrate regardless of the wet etching process or the dry etching process. In this embodiment, a barrier layer 14 is formed between the hard mask layer 15 and the gate structure 13a. When etching the hard mask layer 15, the barrier layer 14 can protect the top of the gate structure 13a from being etched, that is, the top morphology of the gate structure 13a is not affected. In addition, in this embodiment, since a barrier layer 14 is formed on the gate structure 13a, the thickness of the hard mask layer 15 can be reduced. The thickness of the hard mask layer 15 in this embodiment is, for example, 200 angstroms. In some embodiments, the hard mask layer 15 may not be formed. As the thickness of the hard mask layer 15 is reduced, the etching process time for removing the hard mask layer 15 is shortened, and the damage to the surface of the substrate 10 by the etching process is reduced. If the hard mask layer 15 is not formed on the barrier layer 14, the hard mask layer 15 does not need to be removed, and the surface of the substrate 10 will not be damaged.
[0042] like Fig. 9 As shown, a second etching process is performed to remove the barrier layer 14 on the gate structure 13a. The second etching process includes an SC1 process and an SC2 process. The solution of the SC1 process is an APM solution (ammonia-hydroxide-hydrogen peroxide-water mixture) in the RCA cleaning process, which can remove organic matter and particles. This treatment forms a thin layer of silicon dioxide on the surface of the substrate 10, some of which will be removed in subsequent steps. The solution of the SC2 process is usually composed of 6 parts of deionized water, 1 part of hydrochloric acid and 1 part of hydrogen peroxide or HPM (hydrochloric acid and peroxide mixture). The SC2 process step effectively removes the remaining trace metal (ion) contaminants, some of which are introduced in the SC1 cleaning step. The material of the barrier layer 14 in this embodiment is titanium nitride, which is a metal nitride. The SC2 process removes titanium nitride well without damaging the morphology of the surface of the gate structure 13a and the surface of the substrate 10. In addition, the SC2 process leaves a thin passivation layer on the surface of the substrate 10 to protect the substrate 10 from contamination by subsequent processes.
[0043] like Fig. 9As shown, this embodiment also provides a MOS device, which is made by using any of the above-mentioned methods for forming a MOS device, and includes a substrate 10 and a shallow trench isolation structure 11 located in the substrate 10. The substrate 10 includes a low-voltage device area 10a, a medium-voltage device area 10b and a high-voltage device area 10c. The shallow trench isolation structure 11 is used to isolate the low-voltage device area 10a, the medium-voltage device area 10b and the high-voltage device area 10c. A gate oxide layer is also formed on the substrate 10. Specifically, a first gate oxide layer 12a is formed on the substrate of the low-voltage device area 10a, a second gate oxide layer 12b is formed on the substrate of the medium-voltage device area 10b, and a third gate oxide layer 12c is formed on the substrate of the high-voltage device area 10c. Due to the different withstand voltages of the low-voltage device, the medium-voltage device and the high-voltage device, the thicknesses of the first gate oxide layer 12a on the low-voltage device area 10a, the second gate oxide layer 12b on the medium-voltage device area 10b and the third gate oxide layer 12c on the high-voltage device area 10c are different. The thickness of the first gate oxide layer 12a is, for example, 20 angstroms to 50 angstroms, the thickness of the second gate oxide layer 12b is, for example, 180 angstroms to 250 angstroms, and the thickness of the third gate oxide layer 12c is, for example, greater than 1000 angstroms. A gate structure 13a is also formed on the substrate 10, and the gate structure 13a is respectively located on the first gate oxide layer 12a, the second gate oxide layer 12b, and the third gate oxide layer 12c.
[0044] From the above, it can be seen that in the method for forming a MOS device provided in an embodiment of the present invention, a barrier layer is formed on the polysilicon layer, the barrier layer covers the polysilicon layer, and the barrier layer is used to protect the top surface of the polysilicon layer in the subsequent etching process. Then, the first etching process is performed to sequentially etch part of the barrier layer and part of the polysilicon layer, and the remaining polysilicon layer constitutes a gate structure. The second etching process for removing the barrier layer does not damage the gate structure and the substrate surface, and does not change the head morphology of the gate structure. The present invention can avoid the need to form a hard mask layer, or form a very thin hard mask layer. When removing the hard mask layer, the etching process time is short, and the barrier layer protects the surface of the gate structure from being etched. The present invention solves the problem that the hard mask layer on the gate structure in the LELE etching process is too thick, and the head morphology of the gate structure is damaged when the hard mask layer is removed.
[0045] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.
[0046] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a MOS device, characterized in that: include: Providing a substrate, on which a polysilicon layer is formed; forming a barrier layer, the barrier layer covering the polysilicon layer, the barrier layer being used to protect the top surface of the polysilicon layer in a subsequent etching process; Performing a first etching process to sequentially etch a portion of the barrier layer and a portion of the polysilicon layer, with the remaining polysilicon layer constituting a gate structure; A second etching process is performed to remove the barrier layer on the gate structure.
2. The method for forming a MOS device according to claim 1, wherein: The material of the barrier layer is titanium nitride.
3. The method for forming a MOS device according to claim 1, wherein: The barrier layer has a thickness of 80 angstroms to 200 angstroms.
4. The method for forming a MOS device according to claim 1, wherein: The second etching process includes an SC1 process and an SC2 process.
5. The method for forming a MOS device according to claim 1, wherein: After forming the barrier layer, the method further comprises: forming a hard mask layer, wherein the hard mask layer covers the barrier layer; A bottom anti-reflective coating and a patterned photoresist layer are sequentially formed, wherein the bottom anti-reflective coating covers the hard mask layer, and the patterned photoresist layer covers the bottom anti-reflective coating, wherein in the first etching process, the patterned photoresist layer is used as a mask to sequentially etch the bottom anti-reflective coating, the hard mask layer, the barrier layer and the polysilicon layer to form the gate structure.
6. The method for forming a MOS device according to claim 5, characterized in that: After performing the first etching process and before performing the second etching process, the method further includes: The hard mask layer is etched and the etching stops on the barrier layer.
7. The method for forming a MOS device according to claim 5, characterized in that: The material of the hard mask layer is silicon oxide, and the thickness of the hard mask layer is 150 angstroms to 250 angstroms.
8. The method for forming a MOS device according to claim 1, wherein: The first etching process is a LELE process.
9. The method for forming a MOS device according to claim 1, wherein: The substrate includes a low-voltage device area, a medium-voltage device area and a high-voltage device area arranged in sequence, a gate oxide layer is formed between the polysilicon layer and the substrate, and the gate oxide layer of the low-voltage device area, the gate oxide layer of the medium-voltage device area and the gate oxide layer of the high-voltage device area have different thicknesses.
10. A MOS device, characterized in that: The MOS device is manufactured by the method for forming the MOS device according to any one of claims 1 to 9.