Method and monitoring area for monitoring gate oxide thickness

Abstract

The present invention provides a method and monitoring area for monitoring gate oxide thickness, wherein a plurality of monitoring areas are grouped and subjected to a well ion implantation process of PMOS and / or a well ion implantation process of NMOS; a gate oxide layer is grown on the monitoring area; a first measurement of the gate oxide layer of the monitoring area is performed; a polysilicon gate is formed on the monitoring area; a pre-doping implantation process is performed on a portion of the monitoring area subjected to the well ion implantation process of NMOS and a portion of the monitoring area not subjected to the well ion implantation process; a second measurement of the gate oxide layer of the monitoring area is performed; a lightly doped drain and source-drain doping implantation process of NMOS and / or PMOS is performed on a portion of the monitoring area subjected to the pre-doping implantation process and a portion of the monitoring area not subjected to the pre-doping implantation process; and a third measurement of the gate oxide layer of the monitoring area is performed. By performing different implantation processes on the monitoring area, the thickness of the gate oxide layer is monitored, and the influence of different implantation processes on the thickness of the gate oxide layer is determined.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for monitoring the thickness of a gate oxide layer and a monitoring area. Background Art

[0002] With the development of CMOS process technology, in order to improve carrier mobility and saturation current (Idsat), reducing the thickness of the gate oxide (GOX) and improving the gate oxide integrity (GOI) are the current research focuses.

[0003] At advanced process nodes, when the gate oxide thickness decreases by 0.1 nanometers, electron mobility decreases by 15%. In addition to the impact on electron mobility, the thickness of the gate oxide layer also has a significant impact on reliability. When the gate oxide thickness decreases by 0.1 nanometers, the bias temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) of the CMOS product are reduced by 1-2 orders of magnitude. Therefore, how to accurately monitor the gate oxide thickness is very critical.

[0004] In actual processes, ion implantation affects the thickness of the gate oxide layer, and also affects the electrical thickness and uniformity.

[0005] Therefore, how to accurately monitor the effect of ion implantation on the thickness of the gate oxide layer is critical. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method and a monitoring area for monitoring the thickness of a gate oxide layer, which can accurately monitor the influence of ion implantation on the thickness of the gate oxide layer.

[0007] In order to solve the above-mentioned problem, the present invention provides a method for monitoring the thickness of a gate oxide layer, comprising: providing a plurality of monitoring areas; performing a well ion implantation process on the plurality of monitoring areas in groups, wherein the well ion implantation process includes a well ion implantation process for PMOS and / or a well ion implantation process for NMOS; growing a gate oxide layer on the monitoring areas; performing a first measurement on the gate oxide layer in the monitoring areas, and determining the effect of the well ion implantation process on the thickness of the gate oxide layer based on the result of the first measurement; forming a polysilicon gate on the monitoring areas; and performing a pre-doping implantation process on a portion of the monitoring areas that has undergone the well ion implantation process for NMOS and a portion of the monitoring areas that has not undergone the well ion implantation process. Perform a second measurement on the gate oxide layer of the monitoring area, and judge the influence of the pre-doping injection process on the thickness of the gate oxide layer according to the result of the second measurement; perform a further injection process on the monitoring area that has partially implemented the pre-doping injection process and partially not implemented the pre-doping injection process, and the further injection process includes at least one of a lightly doped drain injection process of NMOS, a source-drain doping injection process of NMOS, a lightly doped drain injection process of PMOS, and a source-drain doping injection process of PMOS; perform a third measurement on the gate oxide layer of the monitoring area, and judge the influence of the further injection process on the thickness of the gate oxide layer according to the result of the third measurement.

[0008] In some embodiments, a plurality of monitoring areas are provided, the plurality of monitoring areas including a first monitoring area, a second monitoring area, a third monitoring area, a fourth monitoring area, and a fifth monitoring area; the step of performing a well ion implantation process on the plurality of monitoring areas in groups includes: performing a well ion implantation process on the PMOS in the second monitoring area; performing a well ion implantation process on the NMOS in the third monitoring area and the fifth monitoring area; the step of performing a pre-doping implantation process on a portion of the monitoring areas where the well ion implantation process on the NMOS and a portion of the monitoring areas where the well ion implantation process on the NMOS is not performed includes: performing the pre-doping implantation process on the polysilicon gates in the third monitoring area and the fourth monitoring area; the step of performing a further implantation process on a portion of the monitoring areas where the pre-doping implantation process on the NMOS and a portion of the monitoring areas where the pre-doping implantation process on the NMOS is not performed includes: performing a lightly doped drain implantation process on the NMOS and a source-drain doping implantation process on the NMOS in the third monitoring area and the fifth monitoring area;

[0009] A lightly doped drain implantation process of the PMOS and a source-drain doping implantation process of the PMOS are performed in the second monitoring region.

[0010] In some embodiments, the step of judging the influence of the well ion implantation process on the thickness of the gate oxide layer through the result of the first measurement further includes: comparing the thickness difference between the gate oxide layer in the first monitoring area and the gate oxide layer in the second monitoring area to judge the influence of the well ion implantation process of the PMOS on the thickness of the gate oxide layer; comparing the thickness difference between the gate oxide layer in the first monitoring area and the gate oxide layer in the third monitoring area to judge the influence of the well ion implantation process of the NMOS on the thickness of the gate oxide layer.

[0011] In some embodiments, the step of judging the influence of the pre-doping injection process on the thickness of the gate oxide layer through the second measurement result further includes: comparing the thickness difference between the gate oxide layer in the first monitoring area and the gate oxide layer in the fourth monitoring area, and judging the influence of the pre-doping injection process on the thickness of the gate oxide layer; comparing the thickness difference between the gate oxide layer in the third monitoring area and the gate oxide layer in the fifth monitoring area, and judging the influence of the pre-doping injection process on the thickness of the gate oxide layer based on the execution of the well ion implantation process.

[0012] In some embodiments, the step of judging the influence of the further injection process on the thickness of the gate oxide layer through the result of the third measurement further includes: comparing the thickness difference of the gate oxide layer in the third monitoring area between the result of the third measurement and the result of the second measurement, judging the influence of the lightly doped drain injection process of the NMOS superimposed on the source-drain doping injection process of the NMOS on the thickness of the gate oxide layer on the basis of performing the pre-doping injection process; comparing the thickness difference of the gate oxide layer in the fifth monitoring area between the result of the third measurement and the result of the second measurement, judging the influence of the lightly doped drain injection process of the NMOS superimposed on the source-drain doping injection process of the NMOS on the thickness of the gate oxide layer without performing the pre-doping injection process; comparing the thickness difference of the gate oxide layer in the second monitoring area between the result of the third measurement and the result of the second measurement, judging the influence of the lightly doped drain injection process of the PMOS superimposed on the source-drain doping injection process of the PMOS on the thickness of the gate oxide layer.

[0013] In some embodiments, the multiple monitoring areas also include a sixth monitoring area; the step of performing the well ion implantation process on the multiple monitoring areas in groups also includes: performing the well ion implantation process of the PMOS and the well ion implantation process of the NMOS in the sixth monitoring area; the step of performing the pre-doping implantation process on the monitoring areas that have partially implemented the well ion implantation process of the NMOS and partially not implemented the well ion implantation process also includes: performing the pre-doping implantation process on the polysilicon gate of the sixth monitoring area; the step of performing a further implantation process on the monitoring areas that have partially implemented the pre-doping implantation process and partially not implemented the pre-doping implantation process includes: performing the lightly doped drain process of the NMOS, the lightly doped drain process of the PMOS, the source-drain doping implantation process of the NMOS, and the source-drain doping implantation process of the PMOS in the sixth monitoring area.

[0014] In some embodiments, the sixth monitoring area is used to provide results of a deterioration experiment.

[0015] In some embodiments, in the step of providing a plurality of monitoring regions, shallow trench isolation processes are performed on the monitoring regions to form active regions.

[0016] In some embodiments, the monitoring area is placed on a scribe line of a wafer.

[0017] In some embodiments, the wafer and the monitoring area are implanted simultaneously.

[0018] In order to solve the above problems, the present invention also provides a monitoring area, including: a first monitoring area, the first monitoring area includes a first gate oxide layer and a first polysilicon layer; a second monitoring area, the second monitoring area includes a PMOS well, a second gate oxide layer and a second polysilicon layer, the second polysilicon layer includes a PMOS source / drain area formed by a PMOS lightly doped drain injection process and a PMOS source / drain doping injection process; a third monitoring area, the third monitoring area includes an NMOS well, a third gate oxide layer and a third polysilicon layer, the third polysilicon layer includes an NMOS source / drain area formed by a pre-doping injection process, an NMOS lightly doped drain injection process and an NMOS source / drain doping injection process; a fourth monitoring area, the fourth monitoring area includes a fourth gate oxide layer and a fourth polysilicon layer, the fourth polysilicon layer includes a pre-doped area formed by the pre-doping injection process; a fifth monitoring area, the fifth monitoring area includes an NMOS well, a fifth gate oxide layer and a fifth polysilicon layer, the fifth polysilicon layer includes an NMOS doped area formed by the NMOS lightly doped drain injection process and the NMOS source / drain doping injection.

[0019] In some embodiments, the monitoring area also includes a sixth monitoring area, the sixth monitoring area includes a composite well area formed by the superposition of the PMOS well and the NMOS well, a sixth gate oxide layer and a sixth polysilicon layer, the sixth polysilicon layer includes a composite doping area formed by the pre-doping injection process, the PMOS lightly doped drain injection process, the NMOS lightly doped drain injection process, the PMOS source and drain doping injection process and the NMOS source and drain doping injection process.

[0020] In some embodiments, the thickness differences of the second gate oxide layer, the third gate oxide layer, the fourth gate oxide layer, the fifth gate oxide layer, and the sixth gate oxide layer are compared with the first gate oxide layer to determine the impact of the implantation process on the thickness of the gate oxide layer.

[0021] The above technical solution performs a well ion implantation process of PMOS and / or a well ion implantation process of NMOS on a plurality of monitoring areas in a group; grows a gate oxide layer on the monitoring area; performs a first measurement on the gate oxide layer of the monitoring area; forms a polysilicon gate on the monitoring area; performs a pre-doping implantation process on a portion of the monitoring area that has performed the well ion implantation process of NMOS and a portion that has not performed the well ion implantation process; performs a second measurement on the gate oxide layer of the monitoring area; performs a lightly doped drain and source-drain doping implantation process of NMOS and / or PMOS on a portion of the monitoring area that has performed the pre-doping implantation process and a portion that has not performed the pre-doping implantation process; and performs a third measurement on the gate oxide layer of the monitoring area. By performing different implantation processes on the monitoring area, monitoring the thickness change of the gate oxide layer under different implantation processes, and judging the influence of different implantation processes on the thickness of the gate oxide layer, the thickness of the gate oxide layer can be more accurately controlled.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. Technologies, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 is a flow chart of a method for monitoring gate oxide thickness provided by one embodiment of the present invention;

[0025] Figure 2 This is a flow chart of specific steps of a method for monitoring gate oxide thickness provided by one embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a device structure formed by the steps of a PMOS well ion implantation process provided by one embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a device structure formed by the steps of an NMOS well ion implantation process provided by one embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of a device structure formed by the steps of growing a gate oxide layer according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of a device structure formed by the steps of forming a polysilicon gate provided in one embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of a device structure formed by the steps of a pre-doping implantation process provided in one embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram of a device structure formed by the steps of an NMOS lightly doped drain implantation process provided by an embodiment of the present invention;

[0032] Figure 9 This is a schematic diagram of a device structure formed by the steps of a PMOS lightly doped drain implantation process provided by one embodiment of the present invention;

[0033] Figure 10 This is a schematic diagram of a device structure formed by the steps of an NMOS source-drain doping implantation process provided by one embodiment of the present invention;

[0034] Figure 11 It is a schematic diagram of a device structure formed by the steps of a PMOS source-drain doping implantation process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] Please refer to Figures 1 to 11 ,in, Figure 1 is a flow chart of a method for monitoring gate oxide thickness provided by one embodiment of the present invention; Figure 2This is a flow chart of specific steps of a method for monitoring gate oxide thickness provided by one embodiment of the present invention; Figure 3 This is a schematic diagram of a device structure formed by the steps of a PMOS well ion implantation process provided by one embodiment of the present invention; Figure 4 This is a schematic diagram of a device structure formed by the steps of an NMOS well ion implantation process provided by one embodiment of the present invention; Figure 5 This is a schematic diagram of a device structure formed by the steps of growing a gate oxide layer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a device structure formed by the steps of forming a polysilicon gate provided in one embodiment of the present invention; Figure 7 This is a schematic diagram of a device structure formed by the steps of a pre-doping implantation process provided in one embodiment of the present invention; Figure 8 This is a schematic diagram of a device structure formed by the steps of an NMOS lightly doped drain implantation process provided by an embodiment of the present invention; Figure 9 This is a schematic diagram of a device structure formed by the steps of a PMOS lightly doped drain implantation process provided by one embodiment of the present invention; Figure 10 This is a schematic diagram of a device structure formed by the steps of an NMOS source-drain doping implantation process provided by one embodiment of the present invention;

[0037] Figure 11 It is a schematic diagram of a device structure formed by the steps of a PMOS source-drain doping implantation process provided by an embodiment of the present invention.

[0038] like Figure 1As shown, the method for monitoring the thickness of the gate oxide layer includes: step S1, providing a plurality of monitoring areas; step S2, performing a well ion implantation process on the plurality of monitoring areas in groups, wherein the well ion implantation process includes a well ion implantation process for PMOS and / or a well ion implantation process for NMOS; step S3, growing a gate oxide layer on the monitoring area; step S4, performing a first measurement on the gate oxide layer in the monitoring area, and judging the effect of the well ion implantation process on the thickness of the gate oxide layer according to the result of the first measurement; step S5, forming a polysilicon gate on the monitoring area; step S6, performing a pre-doping implantation process on a portion of the monitoring area that has undergone the well ion implantation process for NMOS and a portion of the monitoring area that has not undergone the well ion implantation process; Step S7, performing a second measurement on the gate oxide layer of the monitoring area, and judging the influence of the pre-doping injection process on the thickness of the gate oxide layer through the result of the second measurement; Step S8, performing a further injection process on the monitoring area where the pre-doping injection process is partially implemented and the pre-doping injection process is not implemented, and the further injection process includes at least one of the lightly doped drain injection process of NMOS, the source-drain doping injection process of NMOS, the lightly doped drain injection process of PMOS and the source-drain doping injection process of PMOS; Step S9, performing a third measurement on the gate oxide layer of the monitoring area, and judging the influence of the further injection process on the thickness of the gate oxide layer through the result of the third measurement.

[0039] The first embodiment of the present invention provides a specific implementation of the method for monitoring the thickness of the gate oxide layer.

[0040] like Figure 2As shown, in this embodiment, the method for monitoring the thickness of the gate oxide layer specifically includes: step S11, providing a plurality of monitoring areas, the plurality of monitoring areas including a first monitoring area, a second monitoring area, a third monitoring area, a fourth monitoring area, a fifth monitoring area and a sixth monitoring area; step S121, performing a well ion implantation process of PMOS in the second monitoring area and the sixth monitoring area; step S122, performing a well ion implantation process of NMOS in the third monitoring area, the fifth monitoring area and the sixth monitoring area; step S13, growing a gate oxide layer on the monitoring area; step S14, performing a first measurement on the gate oxide layer in the monitoring area, and judging the influence of the well ion implantation process on the thickness of the gate oxide layer according to the result of the first measurement; step S15, forming a polysilicon gate on the monitoring area; step S16, forming a polysilicon gate on the polysilicon gate in the third monitoring area, the fourth monitoring area and the sixth monitoring area Perform a pre-doping injection process; step S17, perform a second measurement on the gate oxide layer in the monitoring area, and judge the influence of the pre-doping injection process on the thickness of the gate oxide layer through the result of the second measurement; step S181, perform the lightly doped drain injection process of the NMOS in the third monitoring area, the fifth monitoring area and the sixth monitoring area; step S182, perform the lightly doped drain injection process of the PMOS in the second monitoring area and the sixth monitoring area; step S183, perform the source-drain doping injection process of the NMOS in the third monitoring area, the fifth monitoring area and the sixth monitoring area; step S184, perform the source-drain doping injection process of the PMOS in the second monitoring area and the sixth monitoring area; step S19, perform a third measurement on the gate oxide layer in the monitoring area, and judge the influence of the further injection process on the thickness of the gate oxide layer through the result of the third measurement.

[0041] The steps in this embodiment are described in detail below.

[0042] In this embodiment, the monitoring area is placed on a scribe line of a wafer. When an implantation process is performed on the wafer, the implantation process is also performed on the monitoring area.

[0043] Referring to step S11, a plurality of monitoring areas are provided, including a first monitoring area, a second monitoring area, a third monitoring area, a fourth monitoring area, a fifth monitoring area, and a sixth monitoring area. The monitoring areas are rectangular areas. For example, in this embodiment, the first monitoring area, the second monitoring area, the third monitoring area, the fourth monitoring area, the fifth monitoring area, and the sixth monitoring area are all 70 μm × 120 μm in size.

[0044] In this step, shallow trench isolation processes are performed on the six monitoring areas to form active areas. Furthermore, the formation of active areas in the monitoring areas is performed simultaneously with the formation of active areas on the wafer. Figure 3 The active areas on the first monitoring area TB1, the second monitoring area TB2, the third monitoring area TB3, the fourth monitoring area TB4, the fifth monitoring area TB5 and the sixth monitoring area TB6 are respectively the first active area 10, the second active area 20, the third active area 30, the fourth active area 40, the fifth active area 50 and the sixth active area 60.

[0045] This embodiment uses a mask to control whether different monitoring areas undergo the implantation process. When the mask used in the implantation process is exposed in a specific monitoring area, the implantation process is performed in that specific monitoring area. When the mask used in the implantation process is blocked in a specific monitoring area, the implantation process is not performed in that specific monitoring area.

[0046] Refer to step S121, Figure 3 , perform a PMOS well ion implantation process in the second monitoring area TB2 and the sixth monitoring area TB6. Figure 3 As shown, in the PMOS well ion implantation process, arrows indicate the direction of ion implantation, and a first reticle 1 is used. The first reticle 1 is exposed in the second monitoring area TB2 and the sixth monitoring area TB6; the first monitoring area TB1, the third monitoring area TB3, the fourth monitoring area TB4, and the fifth monitoring area TB5 are shielded. Accordingly, a second PMOS well 21 is formed in the second active area 20 of the second monitoring area TB2, and a sixth PMOS well 61 is formed in the sixth monitoring area TB6.

[0047] Refer to step S122, Figure 4 , perform the NMOS well ion implantation process in the third monitoring area TB3, the fifth monitoring area TB5 and the sixth monitoring area TB6. Figure 4 As shown, in the NMOS well ion implantation process, arrows indicate the direction of ion implantation, and the second mask 2 is used. The second mask 2 exposes the third monitoring area TB3, the fifth monitoring area TB5, and the sixth monitoring area TB6; it is blocked in the first monitoring area TB1, the second monitoring area TB2, and the fourth monitoring area TB4. Accordingly, a third NMOS well 32 is formed in the third active area 30 of the third monitoring area TB3, a fifth NMOS well 52 is formed in the fifth active area 50 of the fifth monitoring area TB5, and a composite well region 62, a superimposed PMOS well and NMOS well, is formed in the sixth monitoring area TB6.

[0048] Refer to step S13, Figure 5 , a gate oxide layer is grown on the monitoring area. Figure 5 As shown, the gate oxide layers formed on the first monitoring area TB1, the second monitoring area TB2, the third monitoring area TB3, the fourth monitoring area TB4, the fifth monitoring area TB5 and the sixth monitoring area TB6 are respectively the first gate oxide layer 13, the second gate oxide layer 23, the third gate oxide layer 33, the fourth gate oxide layer 43, the fifth gate oxide layer 53 and the sixth gate oxide layer 63.

[0049] Referring to step S14, a first measurement is performed on the gate oxide layer of the monitoring area, and the effect of the well ion implantation process on the thickness of the gate oxide layer is determined based on the result of the first measurement. This step further includes: comparing the thickness difference between the gate oxide layer of the first monitoring area and the gate oxide layer of the second monitoring area to determine the effect of the well ion implantation process of the PMOS on the thickness of the gate oxide layer; and comparing the thickness difference between the gate oxide layer of the first monitoring area and the gate oxide layer of the third monitoring area to determine the effect of the well ion implantation process of the NMOS on the thickness of the gate oxide layer.

[0050] refer to Figure 5 This step specifically includes: comparing the thickness difference between the first gate oxide layer 13 and the second gate oxide layer 23 to determine the influence of the well ion implantation process of the PMOS on the thickness of the gate oxide layer; comparing the thickness difference between the first gate oxide layer 13 and the third gate oxide layer 33 to determine the influence of the well ion implantation process of the NMOS on the thickness of the gate oxide layer.

[0051] Refer to step S15, Figure 6 , forming a polysilicon gate on the monitoring area. Figure 6 As shown, the polysilicon gates formed on the first monitoring area TB1, the second monitoring area TB2, the third monitoring area TB3, the fourth monitoring area TB4, the fifth monitoring area TB5 and the sixth monitoring area TB6 are respectively the first polysilicon gate 14, the second polysilicon gate 24, the third polysilicon gate 34, the fourth polysilicon gate 44, the fifth polysilicon gate 54 and the sixth polysilicon gate 64.

[0052] Refer to step S16, Figure 7 , a pre-doping implantation process is performed on the polysilicon gates of the third monitoring area TB3, the fourth monitoring area TB4, and the sixth monitoring area TB6. Figure 7As shown, in the pre-doping implantation process, arrows indicate the direction of ion implantation, and the third mask 3 is used. The third mask 3 exposes the third monitoring area TB3, the fourth monitoring area TB4, and the sixth monitoring area TB6; it is blocked in the first monitoring area TB1, the second monitoring area TB2, and the fifth monitoring area TB5. Accordingly, a third pre-doped region 35 is formed on the third polysilicon gate 34, a fourth pre-doped region 45 is formed on the fourth monitoring area TB4, and a sixth pre-doped region 65 is formed on the sixth monitoring area TB6.

[0053] Referring to step S17, a second measurement is performed on the gate oxide layer in the monitoring area, and the effect of the pre-doping injection process on the thickness of the gate oxide layer is determined based on the result of the second measurement. This step further includes: comparing the difference in thickness between the gate oxide layer in the first monitoring area and the gate oxide layer in the fourth monitoring area to determine the effect of the pre-doping injection process on the thickness of the gate oxide layer; and comparing the difference in thickness between the gate oxide layer in the third monitoring area and the gate oxide layer in the fifth monitoring area to determine the effect of the pre-doping injection process on the thickness of the gate oxide layer based on the execution of the well ion implantation process.

[0054] refer to Figure 7 This step specifically includes: comparing the thickness difference between the first gate oxide layer 13 and the fourth gate oxide layer 43 to determine the influence of the pre-doping injection process on the thickness of the gate oxide layer; comparing the thickness difference between the third gate oxide layer 33 and the fifth gate oxide layer 53 to determine the influence of the pre-doping injection process on the thickness of the gate oxide layer based on the execution of the well ion injection process.

[0055] Refer to step S181, Figure 8 , the NMOS lightly doped drain implantation process is performed in the third monitoring area TB3, the fifth monitoring area TB5 and the sixth monitoring area TB6. Figure 8 As shown, in the NMOS lightly doped drain implantation process, arrows indicate the direction of ion implantation, and the fourth mask 4 is used. The fourth mask 4 exposes the third monitoring area TB3, the fifth monitoring area TB5, and the sixth monitoring area TB6; it is blocked in the first monitoring area TB1, the second monitoring area TB2, and the fourth monitoring area TB4. Accordingly, the third pre-doped region 35 of the third monitoring area TB3 forms a third NMOS lightly doped drain region 36, the fifth NMOS lightly doped drain region 56 is formed on the fifth polysilicon gate 54 of the fifth monitoring area TB5, and the sixth NMOS lightly doped drain region 66 is formed in the pre-doped region 65 of the sixth monitoring area TB6.

[0056] Refer to step S182, Figure 9 , a lightly doped drain implantation process of PMOS is performed in the second monitoring area TB2 and the sixth monitoring area TB6. Figure 9 As shown, in the PMOS lightly doped drain implantation process, arrows indicate the direction of ion implantation, and the fifth mask 5 is used. The fifth mask 5 exposes the second monitoring area TB2 and the sixth monitoring area TB6; it is blocked in the first monitoring area TB1, the third monitoring area TB3, the fourth monitoring area TB4, and the fifth monitoring area TB5. Accordingly, a second PMOS lightly doped drain region 27 is formed on the second polysilicon gate 24 of the second monitoring area TB2, and the NMOS lightly doped drain region 66 of the sixth monitoring area TB6 is formed into a composite lightly doped drain region 67.

[0057] Refer to step S183, Figure 10 , perform NMOS source-drain doping implantation process in the third monitoring area TB3, the fifth monitoring area TB5 and the sixth monitoring area TB6. Figure 10 As shown, in the NMOS source / drain doping implantation process, arrows indicate the direction of ion implantation, and the sixth mask 6 is used. The sixth mask 6 is exposed in the third monitoring area TB3, the fifth monitoring area TB5, and the sixth monitoring area TB6; it is blocked in the first monitoring area TB1, the second monitoring area TB2, and the fourth monitoring area TB4. Accordingly, the third NMOS lightly doped drain region 36 in the third monitoring area TB3 is formed into an NMOS source / drain region 38, the fifth NMOS lightly doped drain region 56 in the fifth monitoring area TB5 is formed into an NMOS doped region 58, and the composite lightly doped drain region 67 in the sixth monitoring area TB6 is formed into a dual-type doped region 68.

[0058] Refer to step S184, Figure 11 , perform the source-drain doping implantation process of PMOS in the second monitoring area TB2 and the sixth monitoring area TB6. Figure 11 As shown, in the PMOS source / drain doping implantation process, arrows indicate the direction of ion implantation, and the seventh mask 7 is used. The seventh mask 7 is exposed in the second monitoring area TB2 and the sixth monitoring area TB6; it is blocked in the first monitoring area TB1, the third monitoring area TB3, the fourth monitoring area TB4, and the fifth monitoring area TB5. Accordingly, the second PMOS lightly doped drain region 27 in the second monitoring area TB2 forms a PMOS source / drain region 29, and the dual-type doped region 68 in the sixth monitoring area TB6 forms a composite doped region 69.

[0059] Referring to step S19, the gate oxide layer of the monitoring area is measured for the third time, and the effect of the further injection process on the thickness of the gate oxide layer is determined based on the result of the third measurement. This step further includes: comparing the thickness difference between the gate oxide layer 33 of the third monitoring area TB3 and the second measurement result, and determining the effect of the NMOS lightly doped drain injection process superimposed on the NMOS source-drain doping injection process on the thickness of the gate oxide layer on the basis of performing the pre-doping injection process; comparing the thickness difference between the gate oxide layer 53 of the fifth monitoring area TB5 and the second measurement result, and determining the effect of the NMOS lightly doped drain injection process superimposed on the NMOS source-drain doping injection process on the thickness of the gate oxide layer on the basis of not performing the pre-doping injection process; and comparing the thickness difference between the gate oxide layer 23 of the second monitoring area TB2 and the third measurement result, and determining the effect of the PMOS lightly doped drain injection process superimposed on the PMOS source-drain doping injection process on the thickness of the gate oxide layer.

[0060] Among them, no injection process is performed on the first monitoring area TB1 and can be used as a control group; the second monitoring area TB2 performs all injection processes related to PMOS manufacturing (PMOS manufacturing usually does not involve the pre-doping injection process); the third monitoring area TB3 performs all injection processes related to NMOS manufacturing; the fourth monitoring area TB4 only performs the pre-doping injection process; the fifth monitoring area TB5 performs other injection processes related to NMOS manufacturing except the pre-doping injection process; the sixth monitoring area TB6 performs all injection processes related to PMOS manufacturing and NMOS manufacturing.

[0061] The three measurement results are all based on the first monitoring area TB1 , the second monitoring area TB2 , the third monitoring area TB3 , the fourth monitoring area TB4 , and the fifth monitoring area TB5 .

[0062] Furthermore, the sixth monitoring zone TB6 may be used to provide the results of a deterioration experiment.

[0063] In some embodiments, the plurality of monitoring zones include only the first monitoring zone TB1, the second monitoring zone TB2, the third monitoring zone TB3, the fourth monitoring zone TB4, and the fifth monitoring zone TB5. During the process flow, when executing steps S11 to S19, the process operations for the sixth monitoring zone TB6 are removed, and the remaining steps remain unchanged.

[0064] The present invention focuses on the effect of the implantation process on the gate oxide thickness during the production process. Non-implantation processes can be performed between adjacent steps S11 to S19. For example, after step S16, this embodiment also performs an etching process for the polysilicon gate.

[0065] Based on the same inventive concept, an embodiment of the present application further provides a monitoring area.

[0066] refer to Figure 11 The monitoring area includes a first monitoring area TB1, a second monitoring area TB2, a third monitoring area TB3, a fourth monitoring area TB4, a fifth monitoring area TB5, and a sixth monitoring area TB6. Furthermore, active areas are formed in each of the monitoring areas. The active areas in the first monitoring area TB1, the second monitoring area TB2, the third monitoring area TB3, the fourth monitoring area TB4, the fifth monitoring area TB5, and the sixth monitoring area TB6 are a first active area 10, a second active area 20, a third active area 30, a fourth active area 40, a fifth active area 50, and a sixth active area 60, respectively.

[0067] The first monitoring region TB1 includes a first gate oxide layer and a first polysilicon layer. Specifically, the first monitoring region TB1 includes the first gate oxide layer 13 and the first polysilicon gate 14 .

[0068] The second monitoring region TB2 includes a PMOS well, a second gate oxide layer, and a second polysilicon layer. The second polysilicon layer includes a PMOS source / drain region formed by a PMOS lightly doped drain implantation process and a PMOS source / drain doping implantation process. Specifically, the second monitoring region TB2 includes a second PMOS well 21, a second gate oxide layer 23, a second polysilicon gate 24, and a PMOS source / drain region 29 formed by performing a PMOS lightly doped drain implantation process and a PMOS source / drain doping implantation process on the second polysilicon gate 24.

[0069] The third monitoring region TB3 includes an NMOS well, a third gate oxide layer, and a third polysilicon layer. The third polysilicon layer includes an NMOS source / drain region formed by a pre-doping implantation process, an NMOS lightly doped drain implantation process, and an NMOS source / drain doping implantation process. Specifically, the third monitoring region TB3 includes a third NMOS well 32, a third gate oxide layer 33, a third polysilicon gate 34, and an NMOS source / drain region 38 formed by performing the pre-doping implantation process, the NMOS lightly doped drain implantation process, and the NMOS source / drain doping implantation process on the third polysilicon gate 34.

[0070] The fourth monitoring region TB4 includes a fourth gate oxide layer and a fourth polysilicon layer, wherein the fourth polysilicon layer includes a pre-doped region formed by the pre-doping implantation process. Specifically, the fourth monitoring region TB4 includes a fourth gate oxide layer 43, a fourth polysilicon gate 44, and a pre-doped region 45 formed by performing the pre-doping implantation process on the fourth polysilicon gate 44.

[0071] The fifth monitoring region TB5 includes an NMOS well, a fifth gate oxide layer, and a fifth polysilicon layer. The fifth polysilicon layer includes an NMOS doped region formed by the NMOS lightly doped drain implantation and the NMOS source-drain doping implantation. Specifically, the fifth monitoring region TB5 includes a fifth NMOS well 52, a fifth gate oxide layer 53, a fifth polysilicon gate 54, and an NMOS doped region 58 formed by performing the NMOS lightly doped drain implantation process and the NMOS source-drain doping implantation on the fifth polysilicon gate 54.

[0072] The sixth monitoring area TB6 includes a composite well area formed by the superposition of the PMOS well and the NMOS well, a sixth gate oxide layer and a sixth polysilicon layer, and the sixth polysilicon layer includes a composite doping area formed by the pre-doping injection process, the PMOS lightly doped drain injection process, the NMOS lightly doped drain injection process, the PMOS source-drain doping injection process, and the NMOS source-drain doping injection process. Specifically, the sixth monitoring area TB6 includes a composite well area 62 formed by the superposition of the PMOS well and the NMOS well, a sixth gate oxide layer 63, a sixth polysilicon gate 64, and a composite doping area 69 formed by performing the pre-doping injection process, the PMOS lightly doped drain injection process, the NMOS lightly doped drain injection process, the PMOS source-drain doping injection process, and the NMOS source-drain doping injection process on the sixth polysilicon gate 64.

[0073] The thicknesses of the second gate oxide layer 23 , the third gate oxide layer 33 , the fourth gate oxide layer 43 , the fifth gate oxide layer 53 and the sixth gate oxide layer 63 are compared with the first gate oxide layer 13 to determine the effect of the implantation process on the thickness of the gate oxide layer.

[0074] Comparing the thickness difference between the sixth gate oxide layer 63 and the first gate oxide layer 13 can provide the result of the degradation experiment.

[0075] In some embodiments, the monitoring area only includes the first monitoring area TB1 , the second monitoring area TB2 , the third monitoring area TB3 , the fourth monitoring area TB4 , and the fifth monitoring area TB5 .

[0076] The above technical solution performs a well ion implantation process of PMOS and / or a well ion implantation process of NMOS on a plurality of monitoring areas in a group; grows a gate oxide layer on the monitoring area; performs a first measurement on the gate oxide layer of the monitoring area; forms a polysilicon gate on the monitoring area; performs a pre-doping implantation process on a portion of the monitoring area that has performed the well ion implantation process of NMOS and a portion that has not performed the well ion implantation process; performs a second measurement on the gate oxide layer of the monitoring area; performs a lightly doped drain and source-drain doping implantation process of NMOS and / or PMOS on a portion of the monitoring area that has performed the pre-doping implantation process and a portion that has not performed the pre-doping implantation process; and performs a third measurement on the gate oxide layer of the monitoring area. By performing different implantation processes on the monitoring area, monitoring the thickness change of the gate oxide layer under different implantation processes, and judging the influence of different implantation processes on the thickness of the gate oxide layer, the thickness of the gate oxide layer can be more accurately controlled.

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprise," or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for monitoring gate oxide thickness, characterized in that: include: Provide multiple monitoring areas; performing a well ion implantation process on a plurality of monitoring areas in groups, wherein the well ion implantation process includes a well ion implantation process for PMOS and / or a well ion implantation process for NMOS; growing a gate oxide layer on the monitoring area; performing a first measurement on the gate oxide layer in the monitoring area, and determining the effect of the well ion implantation process on the thickness of the gate oxide layer based on the result of the first measurement; and forming a polysilicon gate on the monitoring area; performing a pre-doping implantation process on a portion of the monitoring area that has undergone the NMOS well ion implantation process and a portion of the monitoring area that has not undergone the well ion implantation process; performing a second measurement on the gate oxide layer of the monitoring area, and determining the effect of the pre-doping implantation process on the thickness of the gate oxide layer based on the result of the second measurement; A further injection process is performed on a portion of the monitoring area where the pre-doping injection process has been implemented and a portion where the pre-doping injection process has not been implemented, wherein the further injection process includes at least one of a lightly doped drain injection process for NMOS, a source-drain doping injection process for NMOS, a lightly doped drain injection process for PMOS, and a source-drain doping injection process for PMOS; the gate oxide layer in the monitoring area is measured for a third time, and the influence of the further injection process on the thickness of the gate oxide layer is judged by the result of the third measurement.

2. The method according to claim 1, characterized in that The plurality of monitoring areas include a first monitoring area, a second monitoring area, a third monitoring area, a fourth monitoring area, and a fifth monitoring area; And / or the step of performing the well ion implantation process on the monitoring areas in groups includes: performing the well ion implantation process of the PMOS in the second monitoring area; performing the well ion implantation process of the NMOS in the third monitoring area and the fifth monitoring area; and / or the step of performing the pre-doping implantation process on the monitoring areas where the well ion implantation process of the NMOS is partially implemented and the well ion implantation process is not implemented includes: performing the pre-doping implantation process on the polysilicon gate of the third monitoring area and the polysilicon gate of the fourth monitoring area; and / or the step of performing the further implantation process on the monitoring areas where the pre-doping implantation process is partially implemented and the pre-doping implantation process is not implemented includes: performing the lightly doped drain implantation process of the NMOS and the source-drain doping implantation process of the NMOS in the third monitoring area and the fifth monitoring area; performing the lightly doped drain implantation process of the PMOS and the source-drain doping implantation process of the PMOS in the second monitoring area.

3. The method according to claim 2, characterized in that The step of judging the influence of the well ion implantation process on the thickness of the gate oxide layer through the result of the first measurement further includes: comparing the thickness difference of the gate oxide layer in the first monitoring area with that of the gate oxide layer in the second monitoring area, and judging the influence of the well ion implantation process of the PMOS on the thickness of the gate oxide layer; comparing the thickness difference of the gate oxide layer in the first monitoring area with that of the gate oxide layer in the third monitoring area, and judging the influence of the well ion implantation process of the NMOS on the thickness of the gate oxide layer.

4. The method according to claim 2, characterized in that The step of judging the influence of the pre-doping injection process on the thickness of the gate oxide layer through the result of the second measurement further includes: comparing the thickness difference between the gate oxide layer in the first monitoring area and the gate oxide layer in the fourth monitoring area, and judging the influence of the pre-doping injection process on the thickness of the gate oxide layer; comparing the thickness difference between the gate oxide layer in the third monitoring area and the gate oxide layer in the fifth monitoring area, and judging the influence of the pre-doping injection process on the thickness of the gate oxide layer based on the execution of the well ion implantation process.

5. The method according to claim 2, characterized in that The step of judging the influence of the further injection process on the thickness of the gate oxide layer through the result of the third measurement further includes: comparing the thickness difference of the gate oxide layer in the third monitoring area between the result of the third measurement and the result of the second measurement, judging the influence of the lightly doped drain injection process of the NMOS superimposed on the source-drain doping injection process of the NMOS on the thickness of the gate oxide layer on the basis of performing the pre-doping injection process; comparing the thickness difference of the gate oxide layer in the fifth monitoring area between the result of the third measurement and the result of the second measurement, judging the influence of the lightly doped drain injection process of the NMOS superimposed on the source-drain doping injection process of the NMOS on the thickness of the gate oxide layer without performing the pre-doping injection process; comparing the thickness difference of the gate oxide layer in the second monitoring area between the result of the third measurement and the result of the second measurement, judging the influence of the lightly doped drain injection process of the PMOS superimposed on the source-drain doping injection process of the PMOS on the thickness of the gate oxide layer.

6. The method according to claim 2, characterized in that The multiple monitoring areas also include a sixth monitoring area; and / or the step of performing the well ion implantation process on the multiple monitoring areas in groups also includes: performing the well ion implantation process of the PMOS and the well ion implantation process of the NMOS in the sixth monitoring area; and / or the step of performing the pre-doping implantation process on the monitoring areas where the well ion implantation process of the NMOS is partially implemented and the well ion implantation process is not implemented also includes: performing the pre-doping implantation process on the polysilicon gate of the sixth monitoring area; and / or the step of performing a further implantation process on the monitoring areas where the pre-doping implantation process is partially implemented and the pre-doping implantation process is not implemented includes: performing the lightly doped drain process of the NMOS, the lightly doped drain process of the PMOS, the source-drain doping implantation process of the NMOS and the source-drain doping implantation process of the PMOS on the sixth monitoring area.

7. The method according to claim 6, characterized in that The sixth monitoring area is used to provide the result of the deterioration experiment.

8. The method according to claim 1, characterized in that In the step of providing a plurality of monitoring areas, shallow trench isolation processes are performed on the monitoring areas to form active areas.

9. The method according to claim 1, characterized in that The monitoring area is placed on the scribe line of the wafer.

10. The method according to claim 9, characterized in that The wafer and the monitoring area are subjected to implantation processes simultaneously.

11. A monitoring area, characterized in that: include: a first monitoring region, the first monitoring region comprising a first gate oxide layer and a first polysilicon layer; a second monitoring area, wherein the second monitoring area includes a PMOS well, a second gate oxide layer, and a second polysilicon layer, and the second polysilicon layer includes a PMOS source / drain region formed by a PMOS lightly doped drain injection process and a PMOS source / drain doping injection process; a third monitoring area, wherein the third monitoring area includes an NMOS well, a third gate oxide layer, and a third polysilicon layer, and the third polysilicon layer includes an NMOS source / drain region formed by a pre-doping injection process, an NMOS lightly doped drain injection process, and an NMOS source / drain doping injection process; and a fourth monitoring area, wherein the fourth monitoring area includes a fourth gate oxide layer and a fourth polysilicon layer, and the fourth polysilicon layer includes a pre-doped region formed by the pre-doping injection process; The fifth monitoring area includes an NMOS well, a fifth gate oxide layer and a fifth polysilicon layer. The fifth polysilicon layer includes an NMOS doped area formed by the NMOS lightly doped drain implantation process and the NMOS source-drain doping implantation process.

12. The monitoring area according to claim 11, characterized in that The monitoring area also includes a sixth monitoring area, which includes a composite well area formed by the superposition of the PMOS well and the NMOS well, a sixth gate oxide layer and a sixth polysilicon layer. The sixth polysilicon layer includes a composite doping area formed by the pre-doping injection process, the PMOS lightly doped drain injection process, the NMOS lightly doped drain injection process, the PMOS source-drain doping injection process and the NMOS source-drain doping injection process.

13. The monitoring area according to claim 12, characterized in that The thickness differences of the second gate oxide layer, the third gate oxide layer, the fourth gate oxide layer, the fifth gate oxide layer and the sixth gate oxide layer with those of the first gate oxide layer are compared to determine the influence of the implantation process on the thickness of the gate oxide layer.

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