Synchronous etching method for through hole rich in trap layer and contact through hole

Abstract

The invention provides a trap-rich layer through hole and contact through hole synchronous etching method which comprises the following steps: providing a substrate which comprises a trap-rich layer, a first to-be-etched layer and a device layer which are stacked from bottom to top and is provided with an etching stop layer, a second to-be-etched layer and a mask layer which are stacked, a trap-rich layer through hole opening and a contact through hole opening are formed in the mask layer; performing high-load etching by adopting first etching gas, so that the trap-rich layer through hole penetrates through the second to-be-etched layer and the etching stop layer, and the contact through hole extends into the second to-be-etched layer; second etching gas is adopted to perform high-selection-ratio etching, so that the trap-rich layer through hole penetrates through the insulating layer and the first to-be-etched layer, and the contact through hole penetrates through the second to-be-etched layer to expose the etching stop layer; and etching the etch stop layer by using a third etching gas, so that the contact through hole penetrates through the etch stop layer. Through load effect etching and high selection ratio etching, the trap-rich layer through hole and the contact through hole are synchronously etched, the technological process is simplified, and the cost is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for synchronously etching a trap-rich layer through hole and a contact through hole. Background Art

[0002] In RF integrated circuit applications, the performance of RF switching devices or power amplifier devices will be affected by "parasitic surface charge", which will then produce harmonic effects. A rich trap layer is usually set in the device to introduce the "parasitic surface charge" into the rich trap layer through the through hole of the rich trap layer and "release" it. In the prior art, when making a through hole structure, due to the large difference in etching depth between the through hole of the rich trap layer and the contact through hole led by the electrode, and the different stop layers of the two during the etching process, step-by-step etching is usually adopted, and it is necessary to form the through hole of the rich trap layer first, and then form the contact through hole. The step-by-step etching of the through hole of the rich trap layer and the contact through hole makes the process complicated and the manufacturing cost high.

[0003] Therefore, how to provide a method for simultaneously etching trap-rich layer through holes and contact through holes to simplify the process flow and reduce costs has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for synchronously etching trap-rich layer vias and contact vias, so as to solve the problems of complex step-by-step etching process and high manufacturing cost of trap-rich layer vias and contact vias in the prior art.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for synchronously etching a trap-rich layer through hole and a contact through hole, comprising the following steps:

[0006] A substrate is provided, the substrate comprising a trap-rich layer, a first layer to be etched and a device layer stacked from bottom to top, the device layer comprising a semiconductor layer and an insulating layer located at the periphery of the semiconductor layer, wherein an etching stop layer, a second layer to be etched and a mask layer stacked from bottom to top are arranged on the substrate, and a trap-rich layer through-hole opening and a contact through-hole opening are arranged at a preset position of the mask layer to define the positions of the trap-rich layer through-hole and the contact through-hole;

[0007] Using the mask layer as a mask, high-load etching is performed using a first etching gas, so that the through hole of the trap-rich layer penetrates the second layer to be etched and the etching stop layer, and the contact through hole extends into the second layer to be etched but does not penetrate the second layer to be etched;

[0008] Using the mask layer as a mask, a second etching gas is used to perform high selectivity etching, so that the trap-rich layer through hole penetrates the insulating layer and the first layer to be etched to expose the trap-rich layer, and the contact through hole penetrates the second layer to be etched to expose the etch stop layer;

[0009] The etch stop layer is etched using a third etching gas so that the contact through hole penetrates the etch stop layer.

[0010] Optionally, a ratio between an opening width of the trap-rich layer through hole opening and an opening width of the contact through hole opening is not less than 3:1.

[0011] Optionally, the opening width of the trap-rich layer through hole opening is 300-800 nm, and the opening width of the contact through hole opening is 100-200 nm.

[0012] Optionally, the first etching gas includes CF 4 and C x H y F z (x>0,y>0,z>0), where CF 4 and C x H y F z The gas ratio range is 1:1 to 5:1.

[0013] Optionally, the second etching gas includes C x F y (x>0, y>0) and O 2 , where C x F y and O 2 The gas ratio range is 1:1 to 4:1.

[0014] Optionally, during etching using the second etching gas, a ratio between an etching rate of the second layer to be etched and an etching rate of the etching stop layer is not less than 6:1.

[0015] Optionally, the third etching gas includes C x H y F z (x>0,y>0,z>0),O 2 and Ar.

[0016] Optionally, a gate is formed on the semiconductor layer, and there are a plurality of contact holes, a portion of the contact holes penetrate the etch stop layer to expose the semiconductor layer, and a portion of the contact holes penetrate the etch stop layer to expose the gate.

[0017] Optionally, the step of providing the trap-rich layer through hole opening and the contact through hole opening at a preset position of the mask layer includes:

[0018] forming a photoresist layer on the mask layer, and patterning the photoresist layer to define positions of the trap-rich layer through-hole opening and the contact through-hole opening;

[0019] The mask layer is etched based on the patterned photoresist layer to form the trap-rich layer via opening and the contact via opening.

[0020] Optionally, the gas for etching the mask layer includes C x H y F z (x>0, y>0, z>0), O 2 and CO 2 .

[0021] As described above, in the method for simultaneously etching the trap-rich layer through holes and the contact through holes of the present invention, the trap-rich layer through holes and the contact through holes are simultaneously etched by load effect etching and high selectivity etching. Compared with the prior art of etching the trap-rich layer through holes and the contact through holes in steps, the four main processes of photolithography, plasma etching, photoresist ashing and polymer removal of the trap-rich layer through holes can be reduced, thereby greatly simplifying the process flow and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Process flow diagram showing the step-by-step etching of trap-rich layer vias and contact vias.

[0023] Figure 2 It shows a process flow chart of the simultaneous etching method of the trap-rich layer through hole and the contact through hole of the present invention.

[0024] Figure 3 It is a schematic diagram showing the formation and patterning of a photoresist layer on a mask layer in the method for simultaneously etching a trap-rich layer through hole and a contact through hole of the present invention.

[0025] Figure 4 It is a schematic diagram showing the formation of a trap-rich layer via opening and a contact via opening in a hard mask layer in the method for simultaneously etching the trap-rich layer via and the contact via of the present invention.

[0026] Figure 5 It is a schematic diagram showing the loading effect etching in the method for simultaneously etching the trap-rich layer through hole and the contact through hole of the present invention.

[0027] Figure 6 It is a schematic diagram showing high selectivity etching in the method for simultaneously etching the trap-rich layer through hole and the contact through hole of the present invention.

[0028] Figure 7The electron microscope picture of the trap-rich layer through hole after the mask layer is removed in the method for simultaneously etching the trap-rich layer through hole and the contact through hole of the present invention is shown.

[0029] Figure 8 The electron microscope picture of the contact through hole located above the semiconductor layer after the mask layer is removed in the method for simultaneously etching the trap-rich layer through hole and the contact through hole of the present invention is shown.

[0030] Fig. 9 Shown is an electron microscope picture of the contact through hole located above the gate after the mask layer is removed in the method for simultaneously etching the trap-rich layer through hole and the contact through hole of the present invention.

[0031] Fig.10 It is a schematic diagram showing etching of an etch stop layer in the method for simultaneously etching a trap-rich layer through hole and a contact through hole of the present invention.

[0032] Component number description

[0033] 1 Trap-rich layer

[0034] 2 The first layer to be etched

[0035] 3 Device Layer

[0036] 300 Semiconductor layer

[0037] 301 Insulation layer

[0038] 4 Etch stop layer

[0039] 5. Second layer to be etched

[0040] 6 Mask layer

[0041] 7 Trap-rich layer through-hole opening

[0042] 8 Contact via opening

[0043] 9 Grid

[0044] 10 Photoresist layer

[0045] 11 Trap-rich layer through hole

[0046] 12 Contact vias

[0047] Steps S1 to S4 DETAILED DESCRIPTION

[0048] like Figure 1As shown, it is a process flow chart for step-by-step etching of the trap-rich layer through hole and the contact through hole, and the steps are: 1) using a photolithography process to define the position of the trap-rich layer through hole; 2) using plasma etching to form the trap-rich layer through hole; 3) using an ashing process to remove the residual photoresist layer; 4) removing the polymer generated by etching the trap-rich layer through hole; 5) using a photolithography process to define the position of the contact through hole; 6) using plasma etching to form the contact through hole; 7) removing the polymer generated by etching the contact through hole. Step-by-step etching of the trap-rich layer through hole and the contact through hole requires two photomasks for the photolithography process, and its process flow is complicated and the manufacturing cost is high. Therefore, the present application provides a method for synchronously etching the trap-rich layer through hole and the contact through hole to optimize the process flow.

[0049] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] See also Figures 2 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0051] This embodiment provides a method for simultaneously etching a trap-rich layer through hole and a contact through hole. Figure 2 , which is a process flow chart of the etching method, includes the following steps:

[0052] S1: providing a substrate, the substrate comprising a trap-rich layer, a first layer to be etched and a device layer stacked from bottom to top, the device layer comprising a semiconductor layer and an insulating layer located at the periphery of the semiconductor layer, wherein an etching stop layer, a second layer to be etched and a mask layer stacked from bottom to top are arranged on the substrate, and a trap-rich layer through-hole opening and a contact through-hole opening are arranged at a preset position of the mask layer to define the positions of the trap-rich layer through-hole and the contact through-hole;

[0053] S2: using the mask layer as a mask and using a first etching gas to perform high-load etching, so that the through hole of the trap-rich layer penetrates the second layer to be etched and the etching stop layer, and the contact through hole extends into the second layer to be etched but does not penetrate the second layer to be etched;

[0054] S3: using the mask layer as a mask, and performing high selectivity etching with a second etching gas, so that the trap-rich layer through hole penetrates the insulating layer and the first layer to be etched to expose the trap-rich layer, and the contact through hole penetrates the second layer to be etched to expose the etching stop layer;

[0055] S4: etching the etch stop layer using a third etching gas, so that the contact through hole penetrates the etch stop layer.

[0056] First, see Figure 4 , perform step S1: provide a substrate, the substrate includes a trap-rich layer 1, a first layer to be etched 2 and a device layer 3 stacked from bottom to top, the device layer 3 includes a semiconductor layer 300 and an insulating layer 301 located at the periphery of the semiconductor layer 300, wherein an etch stop layer 4, a second layer to be etched 5 and a mask layer 6 stacked from bottom to top are arranged on the substrate, and a trap-rich layer through hole opening 7 and a contact through hole opening 8 are arranged at a preset position of the mask layer 6 to define the positions of the trap-rich layer through hole and the contact through hole.

[0057] As an example, a polysilicon gate 9 is disposed above the semiconductor layer 300 , wherein a source and a drain are formed in the semiconductor layer 300 by processes such as ion implantation.

[0058] As an example, the first layer to be etched 2 includes a buried oxide layer, and the first layer to be etched 2 and the semiconductor layer 300 constitute a silicon-on-insulator substrate. Generally, multiple devices are formed on a wafer, that is, the top silicon layer is divided into multiple semiconductor layer 300 regions, and adjacent semiconductor layers 300 are isolated by the insulating layer 301 composed of a silicon oxide layer.

[0059] As an example, the etching stop layer 4 comprises a silicon nitride layer having a thickness of The second to-be-etched layer 5 comprises a silicon oxide layer, and its thickness is The mask layer 6 and the second layer to be etched 5 have greatly different properties, which is conducive to the subsequent removal of the mask layer 6 from the second layer to be etched 5. For example, in this embodiment, the mask layer 6 is an amorphous carbon layer.

[0060] As an example, in the vertical direction, the trap-rich layer via opening 7 is located directly above the insulating layer 301 , and the contact via opening 8 is located directly above the semiconductor layer 300 .

[0061] As an example, the step of providing the trap-rich layer via opening 7 and the contact via opening 8 at a preset position of the mask layer 6 includes:

[0062] (1) Figure 3As shown, a photoresist layer 10 is formed on the mask layer 6, and the photoresist layer 10 is patterned to define the positions of the trap-rich layer through-hole opening 7 and the contact through-hole opening 8;

[0063] (2) Based on the patterned photoresist layer 10, C x H y F z (x>0, y>0, z>0), O 2 and CO 2 The mask layer 6 is etched to form the trap-rich layer via opening 7 and the contact via opening 8 .

[0064] Preferably, a stacked low-temperature silicon oxide layer and a bottom anti-reflection layer are arranged between the mask layer 6 and the photoresist layer 10. The bottom anti-reflection layer can prevent the photoresist layer 10 from generating a standing wave effect and multiple exposures during the exposure process, thereby improving the photolithography accuracy; the low-temperature silicon oxide layer is conducive to better transferring the pattern of the photoresist layer 10 to the mask layer 6 during the etching process.

[0065] As an example, take C x H y F z (x>0, y>0, z>0), O 2 and CO 2 When etching the mask layer 6 , over-etching is performed to ensure that the trap-rich layer through-hole opening 7 and the contact through-hole opening 8 completely penetrate the mask layer 6 .

[0066] As an example, the ratio between the opening width of the trap-rich layer through hole opening 7 and the opening width of the contact through hole opening 8 is not less than 3:1, wherein the opening width of the trap-rich layer through hole opening 7 is 300-800nm, and the opening width of the contact through hole opening 8 is 100-200nm.

[0067] Next, see Figure 5 , execute step S2: use the mask layer 6 as a mask and use the first etching gas to perform high-load etching, so that the trap-rich layer through hole 11 penetrates the second layer to be etched 5 and the etching stop layer 4, and the contact through hole 12 extends into the second layer to be etched 5 and does not penetrate the second layer to be etched 5.

[0068] As an example, the first etching gas includes CF 4 and C x H y F z (x>0,y>0,z>0), where CF 4 and C x H y F zThe gas ratio range is 1:1 to 5:1. When the first etching gas is used for etching, the etching pressure is 80-180mT, the high-frequency etching power is 200-800W, the low-frequency etching power is 100-900W, and the voltage is 200-600V. By adjusting CF 4 and C x H y F z The ratio of the two gases, etching pressure, etching power, etc. are used to achieve high-load etching. Specifically, in this embodiment, the first etching gas is CF 4 and CHF 3 , where CF 4 The gas flow rate is 120sccm, CHF 3 The gas flow rate is 80sccm and the etching pressure is 180mT.

[0069] As an example, typically within a short etch depth The volatile components generated by etching are easily removed from the holes or grooves, and the effective reaction components on the etching surface are easily updated, so it is not easy to produce a large load effect. The load etching depth difference can be greater than The high-load etching depth of the present invention is shown in Table 1 below, which realizes a large load effect within a short etching depth for two graphic widths with low aspect ratios (<4); specifically, in this embodiment, the opening width of the trap-rich layer through hole opening 7 is 630nm, and the opening width of the contact through hole opening 8 is 130nm. After high-load effect etching, the depth H1 of the trap-rich layer through hole 11 is 544nm, the depth H2 of the contact through hole 12 is 337nm, and the load etching depth difference ΔH is 207nm, that is, when the first etching gas is etching, a sufficient load etching depth difference is generated due to the load effect, so that the trap-rich layer through hole 11 is sufficient to etch through the etching stop layer 4 and extend into the insulating layer 301.

[0070] Table 1:

[0071]

[0072] Next, see Figure 6 , execute step S3: use the mask layer 6 as a mask and use a second etching gas to perform high selectivity etching, so that the trap-rich layer through hole 11 penetrates the insulating layer 301 and the first layer to be etched 2 to expose the trap-rich layer 1, and the contact through hole 12 penetrates the second layer to be etched 5 to expose the etching stop layer 4.

[0073] As an example, the second etching gas includes C x Fy (x>0, y>0) and O 2 , where C x F y and O 2 The gas ratio range is 1:1 to 4:1. When the second etching gas is used for etching, the pressure of the etching chamber is 30-120mT and the temperature is 20-60°C. By increasing C x F y and O 2 The ratio of the two gases, increasing the etching chamber pressure and adjusting the temperature can achieve high selective etching of silicon oxide and silicon nitride; specifically, in this embodiment, C x F y The flow rate is 45sccm, O 2 The flow rate is 20sccm, the etching chamber pressure is 30mT, and the temperature is 20℃.

[0074] As an example, during etching using the second etching gas, the ratio between the etching rate of the second layer 5 to be etched and the etching rate of the etch stop layer 4 is not less than 6:1 to ensure that the contact hole 12 stops at the etch stop layer 4.

[0075] As an example, appropriate over-etching is performed when the second etching gas is used for etching to ensure that the trap-rich layer through holes 11 completely open the first to-be-etched layer 2 .

[0076] As an example, after etching with the second etching gas, O 2 The remaining mask layer 6 is removed. Since the contact through hole 12 does not open the etching stop layer 4, 2 The semiconductor layer 300 will not be oxidized.

[0077] As an example, see Figures 7 to 9 , which is an electron microscope picture after removing the mask layer 6, wherein: Figure 7 The electron microscope image of the through hole 11 in the trap-rich layer is shown. Figure 8 The electron microscope image of the contact hole 12 located above the semiconductor layer 300 is shown. Fig. 9 It is shown as a contact through hole 12 located above the gate 9 , that is, after etching with the second etching gas, the trap-rich layer through hole 11 completely opens the insulating layer 301 and the first layer to be etched 2 to expose the trap-rich layer 1 , and the contact through hole 12 stops at the etching stop layer 4 .

[0078] Next, see Fig.10 , executing step S4: etching the etch stop layer 4 using a third etching gas, so that the contact through hole 12 passes through the etch stop layer 4.

[0079] As an example, the third etching gas includes C x H y F z (x>0,y>0,z>0),O 2 Specifically, in this embodiment, the third etching gas is CH 2 F 2 , O 2 After the etching stop layer 4 is etched with the third etching gas, N 2 and H 2 etc. to remove the polymers produced by the above etching process.

[0080] As an example, the trap-rich layer through hole 11 is used to introduce "parasitic surface charge" into the trap-rich layer for "releasing" it, and the contact through hole 12 is used as an extraction channel for the source, drain and gate of the device.

[0081] In summary, in the method for synchronously etching the trap-rich layer through-hole and the contact through-hole of the present invention, the trap-rich layer through-hole and the contact through-hole are synchronously etched by load effect etching and high selectivity etching. Compared with the prior art of etching the trap-rich layer through-hole and the contact through-hole in steps, the four main processes of photolithography, plasma etching, photoresist ashing and polymer removal of the trap-rich layer through-hole can be reduced, the process flow is greatly simplified, and the cost is reduced. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for simultaneously etching a trap-rich layer through hole and a contact through hole, characterized in that: The following steps are involved: A substrate is provided, the substrate comprising a trap-rich layer, a first layer to be etched and a device layer stacked from bottom to top, the device layer comprising a semiconductor layer and an insulating layer located at the periphery of the semiconductor layer, wherein an etching stop layer, a second layer to be etched and a mask layer stacked from bottom to top are arranged on the substrate, and a trap-rich layer through-hole opening and a contact through-hole opening are arranged at a preset position of the mask layer to define the positions of the trap-rich layer through-hole and the contact through-hole; Using the mask layer as a mask, high-load etching is performed using a first etching gas, so that the through hole of the trap-rich layer penetrates the second layer to be etched and the etching stop layer, and the contact through hole extends into the second layer to be etched but does not penetrate the second layer to be etched; Using the mask layer as a mask, a second etching gas is used to perform high selectivity etching, so that the trap-rich layer through hole penetrates the insulating layer and the first layer to be etched to expose the trap-rich layer, and the contact through hole penetrates the second layer to be etched to expose the etch stop layer; The etch stop layer is etched using a third etching gas so that the contact through hole penetrates the etch stop layer.

2. The method for simultaneously etching a trap-rich layer through hole and a contact through hole according to claim 1, characterized in that: The ratio between the opening width of the trap-rich layer through hole opening and the opening width of the contact through hole opening is not less than 3:

1.

3. The method for simultaneously etching the trap-rich layer through hole and the contact through hole according to claim 2, characterized in that: The opening width of the trap-rich layer through hole opening is 300-800 nm, and the opening width of the contact through hole opening is 100-200 nm.

4. The method for synchronously etching trap-rich layer through holes and contact through holes according to claim 1, characterized in that: The first etching gas includes CF4 and C x H y F z (x>0,y>0,z>0), where CF4 and C x H y F z The gas ratio range is 1:1 to 5:

1.

5. The method for synchronously etching a trap-rich layer through hole and a contact through hole according to claim 1, characterized in that: The second etching gas includes C x F y (x>0, y>0) and O2, where C x F y The gas ratio of oxygen to oxygen ranges from 1:1 to 4:

1.

6. The method for synchronously etching trap-rich layer through holes and contact through holes according to claim 5, characterized in that: During etching using the second etching gas, a ratio between an etching rate of the second layer to be etched and an etching rate of the etching stop layer is not less than 6:

1.

7. The method for synchronously etching a trap-rich layer through hole and a contact through hole according to claim 1, characterized in that: The third etching gas includes C x H y F z (x>0, y>0, z>0), O2 and Ar.

8. The method for synchronously etching a trap-rich layer through hole and a contact through hole according to claim 1, characterized in that: A gate is formed on the semiconductor layer. There are a plurality of contact holes. A portion of the contact holes penetrates the etch stop layer to expose the semiconductor layer, and a portion of the contact holes penetrates the etch stop layer to expose the gate.

9. The method for simultaneously etching a trap-rich layer through hole and a contact through hole according to claim 1, characterized in that: The step of providing the trap-rich layer through-hole opening and the contact through-hole opening at a preset position of the mask layer comprises: forming a photoresist layer on the mask layer, and patterning the photoresist layer to define positions of the trap-rich layer through-hole opening and the contact through-hole opening; The mask layer is etched based on the patterned photoresist layer to form the trap-rich layer via opening and the contact via opening.

10. The method for simultaneously etching a trap-rich layer through hole and a contact through hole according to claim 9, characterized in that: The gas used to etch the mask layer includes C x H y F z (x>0, y>0, z>0), O2 and CO2.

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