Voltage conversion rate adjusting circuit suitable for intelligent high-side switch

Abstract

The invention discloses a voltage conversion rate adjusting circuit suitable for an intelligent high-side switch, and the circuit is characterized in that when an IN enable signal is at a high level, an INV inversion signal is at a low level, a pull-up branch is switched on, a pull-down branch is switched off, the size of a pull-up current is adjusted according to the copy proportion of a current mirror in the pull-up branch and a feedback signal, and the voltage conversion rate is adjusted. The switching-on conversion rate of the intelligent high-side switch is changed; when the IN enable signal is at a low level, the INV inversion signal is at a high level, the pull-up branch is switched off, the pull-down branch is switched on, the size of the pull-down current is adjusted according to the copy proportion of the current mirror in the pull-down branch and the feedback signal, and the switching-off conversion rate of the intelligent high-side switch is changed. The conversion rate of the intelligent high-side switch can be regulated and controlled, the operation speed is high, and the power consumption and the area are superior to those of a traditional conversion rate adjusting circuit structure.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage conversion rate regulating circuits, and in particular to a voltage conversion rate regulating circuit suitable for an intelligent high-side switch. Background Art

[0002] High-side switches are known for their integrated multiple protection functions, including overload, overtemperature and short-circuit protection. These functions can quickly cut off the power supply when the high-side switch encounters abnormal conditions, effectively ensuring the safety of the high-side switch itself and the connected load. In many fields at the forefront of science and technology, such as automotive electronics, industrial automation, and motor drive technology, high-side switches are widely used due to their excellent performance. In particular, the voltage slew rate (SR) of high-side switches has become an important indicator for measuring their performance and stability. In application scenarios such as automotive electronic systems that pursue fast response or industrial automation control that requires instant adjustment of circuit status, faster voltage slew rates can significantly shorten system response time and thus improve overall work efficiency. At the same time, by carefully adjusting the voltage slew rate to an appropriate level, not only can the high performance of the circuit be maintained, but unnecessary electromagnetic radiation can also be effectively suppressed, reducing electromagnetic interference to the surrounding environment. In addition, precise control of the voltage slew rate of the high-side switch ensures that the load equipment always operates within a safe range when experiencing voltage changes, preventing equipment damage or failure caused by voltage fluctuations. Furthermore, by continuously optimizing the design structure and control logic of the high-side switch, it can be ensured that the stability of the voltage conversion rate can be maintained under various working conditions, which not only enhances the reliability of the high-side switch, but also extends the overall service life of the switch.

[0003] In the traditional high-side switch voltage conversion rate control circuit, it is realized through a resistor network. If the high-side switch needs to output a signal with a faster voltage conversion rate, the input signal is output after passing through a resistor with a smaller resistance value; if a signal with a slower voltage conversion rate needs to be output, the input signal is output after passing through a resistor with a larger resistance value. In order to overcome the problems of large resistance value differences and slow conversion speed in the resistor network, more complex circuit designs need to be adopted, such as inverted T-shaped resistor networks, which increases the complexity and difficulty of the design. The use of more complex circuit designs and higher performance components will undoubtedly increase the cost of the circuit.

[0004] In addition, CN106664083A describes a high-side driver circuit for controlling a high-side field effect transistor, which uses an operational amplifier to connect the output to the gate of the transistor to form a closed-loop voltage follower. In the circuit, a capacitor and a current source are connected in parallel between the non-inverting input of the amplifier and the ground to stabilize the input voltage, but this scheme can only control the conversion rate by the voltage ramp up and ramp down at the input end of the closed-loop voltage follower, and the start time needs to be optimized. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a voltage conversion rate regulation circuit suitable for an intelligent high-side switch, which can regulate the conversion rate of the intelligent high-side switch and has a fast operating speed, making the power consumption and area better than the traditional conversion rate adjustment circuit structure.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solutions: a voltage conversion rate regulating circuit suitable for an intelligent high-side switch, comprising: an enable control circuit, an N-type power tube, a pull-up branch, a pull-down branch and a voltage comparison circuit OUT_State, wherein the IN enable signal of the enable control circuit is used to control the on or off of the pull-up branch, and the INV inverted signal of the enable control circuit is used to control the on or off of the pull-down branch; the output end of the pull-up branch and the output end of the pull-down branch are both connected to the gate of the N-type power tube, and the voltage comparison circuit OUT_State compares the source voltage VOUT of the N-type power tube with the expected set voltage value to generate a feedback signal V1;

[0007] When the IN enable signal is at a high level, the INV inverted signal is at a low level, at which time the pull-up branch is turned on and the pull-down branch is turned off. The pull-up current I2 is adjusted according to the copy ratio of the current mirror in the pull-up branch and the feedback signal V1 to change the turn-on conversion rate of the intelligent high-side switch.

[0008] When the IN enable signal is at a low level, the INV inverted signal is at a high level. At this time, the pull-up branch is turned off and the pull-down branch is turned on. The size of the pull-down current I1 is adjusted according to the replication ratio of the current mirror in the pull-down branch and the feedback signal V1 to change the turn-off conversion rate of the intelligent high-side switch.

[0009] Furthermore, the drain of the N-type power tube is connected to the power supply voltage VBB; the enable control circuit is provided with an inverter, the input end of the inverter is the IN enable signal, and the output end of the inverter is the INV inverted signal.

[0010] Furthermore, the voltage comparison circuit OUT_State includes: a hysteresis voltage divider module, a current bias module, a secondary operational amplifier and a voltage stabilizing module, wherein the hysteresis voltage divider module is used to divide the power supply voltage VBB through a resistor network to obtain an expected set voltage value; the current bias module is used to provide a bias for the secondary operational amplifier; the secondary operational amplifier is used to compare the source voltage VOUT of the N-type power tube with the expected set voltage value to generate a feedback signal V1; the voltage stabilizing module is used to stabilize the feedback signal V1 to prevent voltage jitter.

[0011] Furthermore, the hysteresis voltage divider module includes: a third PMOS tube PM2, a third resistor R2, a fourth resistor R3 and a fifth resistor R4, the source of the third PMOS tube PM2 and one end of the third resistor R2 are both connected to the power supply voltage VBB, the gate of the third PMOS tube PM2 and the output end of the voltage stabilizing module are both used as the output end of the voltage comparison circuit, the drain of the third PMOS tube PM2 is respectively connected to the other end of the third resistor R2 and one end of the fourth resistor R3, the other end of the fourth resistor R3 and one end of the fifth resistor R4 are both connected to the input end of the secondary operational amplifier, and the other end of the fifth resistor R4 is grounded.

[0012] Further, the current bias module includes: a third current source Id3, an eleventh NMOS tube NM10, a twelfth NMOS tube NM11, and a fourth PMOS tube PM3, the input end of the third current source Id3 is connected to the power supply voltage VBB, the output end of the third current source Id3 is respectively connected to the gate of the eleventh NMOS tube NM10, the drain of the eleventh NMOS tube NM10, and the gate of the twelfth NMOS tube NM11, the drain of the twelfth NMOS tube NM11, the drain of the fourth PMOS tube PM3, and the gate of the fourth PMOS tube PM3 serve as the output end of the current bias module; the source of the fourth PMOS tube PM3 is connected to the power supply voltage VBB, and the source of the eleventh NMOS tube NM10 and the source of the twelfth NMOS tube NM11 are both grounded.

[0013] Further, the secondary operational amplifier includes: a fifth PMOS tube PM4, a sixth PMOS tube PM5, a seventh PMOS tube PM6, an eighth PMOS tube PM7, a thirteenth NMOS tube NM12, a fourteenth NMOS tube NM13, a fifteenth NMOS tube NM14 and a sixth resistor R5, one end of the sixth resistor R5 is connected to the source of the N-type power tube, the other end of the sixth resistor R5 is connected to the gate of the eighth PMOS tube PM7, the source of the eighth PMOS tube PM7 is respectively connected to the drain of the fifth PMOS tube PM4 and the source of the seventh PMOS tube PM6, the gate of the fifth PMOS tube PM4 and the gate of the sixth PMOS tube PM5 are both connected to the output end of the current bias module, the source of the fifth PMOS tube PM4 and the source of the sixth PMOS tube PM5 are connected to the output end of the current bias module, and the source of the fifth PMOS tube PM4 and the source of the sixth PMOS tube PM5 are connected to the output end of the current bias module. The gates of the seventh PMOS tube PM6 are connected to the power supply voltage VBB, the gate of the seventh PMOS tube PM6 is connected to one end connected to the fourth resistor R3 and the fifth resistor R4, the drain of the seventh PMOS tube PM6 is respectively connected to the drain of the thirteenth NMOS tube NM12, the gate of the thirteenth NMOS tube NM12, and the gate of the fourteenth NMOS tube NM13; the drain of the eighth PMOS tube PM7 is respectively connected to the drain of the fourteenth NMOS tube NM13 and the gate of the fifteenth NMOS tube NM14, the drain of the fifteenth NMOS tube NM14 and the drain of the sixth PMOS tube PM5 are both connected to the input end of the voltage stabilizing module as the output end of the secondary operational amplifier, and the source of the thirteenth NMOS tube NM12, the source of the fourteenth NMOS tube NM13, and the source of the fifteenth NMOS tube NM14 are all grounded.

[0014] Furthermore, the voltage stabilizing module is a Schmitt trigger, the input end of the Schmitt trigger is connected to the output end of the secondary operational amplifier, and the output end of the Schmitt trigger is connected to the gate of the third PMOS tube PM2, the input end of the pull-up branch, and the input end of the pull-down branch as the output end of the voltage comparison circuit.

[0015] Further, the pull-down branch includes: a first current source Id1, a second current source Id2, a first NMOS tube NM0, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM4 and a ninth NMOS tube NM8, the input end of the first current source Id1 and the input end of the second current source Id2 are both connected to the power supply voltage VBB, the output end of the first current source Id1 is respectively connected to the drain of the first NMOS tube NM0, the gate of the first NMOS tube NM0 and the gate of the second NMOS tube NM1, the drain of the second NMOS tube NM1 is connected to the source of the third NMOS tube NM2, the gate of the third NMOS tube NM2 is connected to the voltage comparison circuit O The output end of the pull-down branch is connected to the output end of UT_State, the drain of the third NMOS tube NM2 is respectively connected to the output end of the second current source Id2 and the drain of the ninth NMOS tube NM8, the gate of the ninth NMOS tube NM8 is connected to the INV inversion signal, the source of the ninth NMOS tube NM8 is respectively connected to the drain of the fourth NMOS tube NM3, the gate of the fourth NMOS tube NM3, and the gate of the fifth NMOS tube NM4, the drain of the fifth NMOS tube NM4 is connected to the gate of the N-type power tube as the output end of the pull-down branch, the source of the first NMOS tube NM0, the source of the second NMOS tube NM1, the source of the fourth NMOS tube NM3, and the source of the fifth NMOS tube NM4 are all connected to the relative ground signal LVSS.

[0016] Further, the pull-up branch includes: a sixth NMOS tube NM5, a seventh NMOS tube NM6, an eighth NMOS tube NM7, a tenth NMOS tube NM9, a first PMOS tube PM0 and a second PMOS tube PM1, the gate of the seventh NMOS tube NM6 is connected to the output end of the voltage comparison circuit OUT_State, the source of the seventh NMOS tube NM6 is connected to the drain of the sixth NMOS tube NM5, the source of the sixth NMOS tube NM5 is connected to the source of the eighth NMOS tube NM7, the gate of the sixth NMOS tube NM5 and the gate of the eighth NMOS tube NM7 are both connected to the drain of the first NMOS tube NM0, the first NMOS tube NM1 and the drain of the eighth NMOS tube NM2. The gate of the seventh NMOS tube NM6 and the drain of the eighth NMOS tube NM7 are both connected to the source of the tenth NMOS tube NM9, the gate of the tenth NMOS tube NM9 is connected to the IN enable signal, the drain of the tenth NMOS tube NM9 is respectively connected to the drain of the first PMOS tube PM0, the gate of the first PMOS tube PM0, and the gate of the second PMOS tube PM1, the source of the first PMOS tube PM0 and the source of the second PMOS tube PM1 are both connected to the charge pump voltage VCP, and the drain of the second PMOS tube PM1 is connected to the gate of the N-type power tube as the output end of the pull-up branch.

[0017] Furthermore, it also includes a first resistor R0 and a second resistor R1, one end of the first resistor R0 and one end of the second resistor R1 are both connected to the source of the N-type power tube, the other end of the first resistor R0 is grounded, and the other end of the second resistor R1 is respectively connected to the drain of the fifth NMOS tube NM4 and the drain of the second PMOS tube PM1.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] (1) The present invention is applicable to the enabling control circuit of the voltage conversion rate regulating circuit of the intelligent high-side switch, which adopts a simplified control logic and simplifies the control logic of the pull-up branch and the pull-down branch, thereby realizing rapid control of the pull-up branch and the pull-down branch, and realizing efficient switching of the conversion rate of the intelligent high-side switch;

[0020] (2) The voltage comparison circuit OUT_State of the voltage conversion rate adjustment circuit of the intelligent high-side switch of the present invention compares the source voltage VOUT of the N-type power tube with the expected set voltage value, which can more flexibly control the switching moment of the conversion rate of the intelligent high-side switch during the opening or closing process, and has more flexible regulation;

[0021] (3) The voltage conversion rate regulation circuit of the intelligent high-side switch of the present invention can realize conversion rate regulation, and the power consumption and area are better than the traditional conversion rate adjustment circuit structure, and the application scenario is less limited and is no longer overly affected by the parasitic capacitance of the power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The circuit diagram of the voltage conversion rate regulating circuit applicable to the intelligent high-side switch of the present invention;

[0023] Figure 2 It is a schematic diagram of a voltage comparison circuit in the present invention;

[0024] Figure 3 The present invention is a schematic diagram of the output voltage of a voltage conversion rate regulating circuit suitable for an intelligent high-side switch. DETAILED DESCRIPTION

[0025] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0026] like Figure 1The invention is a circuit diagram of a voltage conversion rate regulating circuit suitable for an intelligent high-side switch, wherein the voltage conversion rate regulating circuit comprises: an enable control circuit, an N-type power tube, a pull-up branch, a pull-down branch and a voltage comparison circuit OUT_State, wherein the enable control circuit is provided with an inverter, wherein the input end of the inverter is an IN enable signal, and the output end of the inverter is an INV inverted signal, wherein the IN enable signal of the enable control circuit is used to control the on or off of the pull-up branch, and the INV inverted signal of the enable control circuit is used to control the on or off of the pull-down branch; the output end of the pull-up branch and the output end of the pull-down branch are both connected to the gate of the N-type power tube, the drain of the N-type power tube is connected to the power supply voltage VBB, and the voltage The comparison circuit OUT_State compares the source voltage VOUT of the N-type power tube with the expected set voltage value to generate a feedback signal V1; when the IN enable signal is at a high level, the INV inverted signal is at a low level, at which time the pull-up branch is turned on and the pull-down branch is turned off, and the size of the pull-up current I2 is adjusted according to the copy ratio of the current mirror in the pull-up branch and the feedback signal V1, so as to change the turn-on conversion rate of the intelligent high-side switch; when the IN enable signal is at a low level, the INV inverted signal is at a high level, at which time the pull-up branch is turned off and the pull-down branch is turned on, and the size of the pull-down current I1 is adjusted according to the copy ratio of the current mirror in the pull-down branch and the feedback signal V1, so as to change the turn-off conversion rate of the intelligent high-side switch. When the pull-up branch and the pull-down branch of the intelligent high-side switch of the present invention are switched, the pull-up current I2 or the pull-down current I1 is adjusted to adjust the pull-up or pull-down capability of the pull-up branch or the pull-down branch accordingly, so as to achieve real-time adjustment of the voltage conversion rate.

[0027] like Figure 2 In the present invention, the voltage comparison circuit OUT_State includes: a hysteresis voltage divider module, a current bias module, a secondary operational amplifier and a voltage stabilizing module. The hysteresis voltage divider module is used to divide the power supply voltage VBB through a resistor network to obtain an expected set voltage value; the current bias module is used to provide a bias for the secondary operational amplifier; the secondary operational amplifier is used to compare the source voltage VOUT of the N-type power tube with the expected set voltage value to generate a feedback signal V1; the voltage stabilizing module is used to stabilize the feedback signal V1 to prevent voltage jitter.

[0028] The hysteresis voltage divider module includes: a third PMOS tube PM2, a third resistor R2, a fourth resistor R3 and a fifth resistor R4, the source of the third PMOS tube PM2 and one end of the third resistor R2 are both connected to the power supply voltage VBB, the gate of the third PMOS tube PM2 and the output end of the voltage stabilizing module are both used as the output end of the voltage comparison circuit, the drain of the third PMOS tube PM2 is respectively connected to the other end of the third resistor R2 and one end of the fourth resistor R3, the other end of the fourth resistor R3 and one end of the fifth resistor R4 are both connected to the input end of the secondary operational amplifier, and the other end of the fifth resistor R4 is grounded. The third PMOS tube PM2 plays a role in voltage hysteresis control, preventing the voltage jitter from affecting the input end voltage of the secondary operational amplifier, thereby affecting the feedback signal V1. When the feedback signal V1 is at a high level and the third PMOS tube PM2 is not turned on, the gate voltage of the seventh PMOS tube PM6 input to the secondary operational amplifier is obtained by dividing the voltage between VBB and GND through the resistors among the third resistor R2, the fourth resistor R3 and the fifth resistor R4; when the third PMOS tube PM2 is turned on, the third resistor R2 is short-circuited, and the gate voltage of the seventh PMOS tube PM6 input to the secondary operational amplifier is obtained by dividing the voltage between VBB and GND through the resistors among the fourth resistor R3 and the fifth resistor R4.

[0029] The current bias module includes: a third current source Id3, an eleventh NMOS tube NM10, a twelfth NMOS tube NM11, and a fourth PMOS tube PM3. The input end of the third current source Id3 is connected to the power supply voltage VBB, and the output end of the third current source Id3 is respectively connected to the gate of the eleventh NMOS tube NM10, the drain of the eleventh NMOS tube NM10, and the gate of the twelfth NMOS tube NM11. The drain of the twelfth NMOS tube NM11, the drain of the fourth PMOS tube PM3, and the gate of the fourth PMOS tube PM3 serve as the output end of the current bias module; the source of the fourth PMOS tube PM3 is connected to the power supply voltage VBB, and the source of the eleventh NMOS tube NM10 and the source of the twelfth NMOS tube NM11 are both grounded. The third current source Id3 of the internal reference current of the intelligent high-side switch provides current bias for the secondary operational amplifier through a current mirror structure composed of the eleventh NMOS tube NM10 and the twelfth NMOS tube NM11 and a current mirror structure composed of the fourth PMOS tube PM3 and the fifth PMOS tube PM4 in the secondary operational amplifier, thereby ensuring the normal operation of the secondary operational amplifier.

[0030] The secondary operational amplifier includes: a fourth PMOS tube PM3, a fifth PMOS tube PM4, a sixth PMOS tube PM5, a seventh PMOS tube PM6, an eighth PMOS tube PM7, a thirteenth NMOS tube NM12, a fourteenth NMOS tube NM13, a fifteenth NMOS tube NM14 and a sixth resistor R5, one end of the sixth resistor R5 is connected to the source of the N-type power tube, the other end of the sixth resistor R5 is connected to the gate of the eighth PMOS tube PM7, the source of the eighth PMOS tube PM7 is respectively connected to the drain of the fifth PMOS tube PM4 and the source of the seventh PMOS tube PM6, the gate of the fifth PMOS tube PM4 and the gate of the sixth PMOS tube PM5 are both connected to the output end of the current bias module, the source of the fifth PMOS tube PM4 and the source of the sixth PMOS tube PM5 are connected to the output end of the current bias module, and the source of the fifth PMOS tube PM4 and the source of the sixth PMOS tube PM5 are connected to the output end of the current bias module. The sources of the seventh PMOS tube PM6 are connected to the power supply voltage VBB, the gate of the seventh PMOS tube PM6 is connected to one end connected to the fourth resistor R3 and the fifth resistor R4, the drain of the seventh PMOS tube PM6 is respectively connected to the drain of the thirteenth NMOS tube NM12, the gate of the thirteenth NMOS tube NM12, and the gate of the thirteenth NMOS tube NM13; the drain of the eighth PMOS tube PM7 is respectively connected to the drain of the thirteenth NMOS tube NM13 and the gate of the thirteenth NMOS tube NM14, the drain of the fifteenth NMOS tube NM14 and the drain of the sixth PMOS tube PM5 are both connected to the input end of the voltage stabilizing module as the output end of the secondary operational amplifier, and the source of the thirteenth NMOS tube NM12, the source of the fourteenth NMOS tube NM13, and the source of the fifteenth NMOS tube NM14 are all grounded. The input stage amplification circuit of the secondary operational amplifier is composed of the fifth PMOS tube PM4, the seventh PMOS tube PM6, the eighth PMOS tube PM7, the thirteenth NMOS tube NM12 and the fourteenth NMOS tube NM13, wherein the seventh PMOS tube PM6 and the eighth PMOS tube PM7 form a PMOS differential input pair, and the differential input can effectively suppress the common mode signal interference compared with the single-ended input, and the thirteenth NMOS tube NM12 and the fourteenth NMOS tube NM13 form a current mirror as an active load; the output stage amplification circuit is composed of the sixth PMOS tube PM5 and the fifteenth NMOS tube NM14, wherein the fifteenth NMOS tube NM14 is a common source amplifier, and the sixth PMOS tube PM5 provides a constant bias current for it and serves as a second-stage output load. The seventh PMOS tube PM6 and the eighth PMOS tube PM7 are the first-stage differential input transconductance stage, which converts the differential mode input voltage into a differential mode current. The thirteenth NMOS tube NM12 and the fourteenth NMOS tube NM13 are the first-stage loads, which restore the differential mode current to a differential mode voltage. The fifteenth NMOS tube NM14 is the second transconductance stage, converting the differential mode voltage signal into current, and the sixth PMOS tube PM5 converts the current signal into a voltage output, thereby completing the comparison of the source voltage VOUT of the N-type power tube with the expected set voltage value to generate a stable feedback signal V1.

[0031] The voltage stabilizing module is a Schmitt trigger. The input of the Schmitt trigger is connected to the output of the secondary operational amplifier. The output of the Schmitt trigger is connected to the gate of the third PMOS tube PM2, the input of the pull-up branch, and the input of the pull-down branch as the output of the voltage comparison circuit. The Schmitt trigger has two threshold voltages, which are called the positive threshold voltage and the negative threshold voltage. The voltage difference between the positive threshold voltage and the negative threshold voltage is called the hysteresis voltage: when the input voltage rises from a low level to the positive threshold voltage or drops from a high level to the negative threshold voltage, the output of the Schmitt trigger changes. Due to the existence of the hysteresis voltage, the Schmitt trigger can prevent the input voltage from causing the output voltage of the Schmitt trigger to change due to a slight voltage jitter, thereby achieving a voltage stabilization effect.

[0032] The pull-down branch in the present invention includes: a first current source Id1, a second current source Id2, a first NMOS tube NM0, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM4 and a ninth NMOS tube NM8, the input end of the first current source Id1 and the input end of the second current source Id2 are both connected to the power supply voltage VBB, the output end of the first current source Id1 is respectively connected to the drain of the first NMOS tube NM0, the gate of the first NMOS tube NM0, and the gate of the second NMOS tube NM1, the drain of the second NMOS tube NM1 is connected to the source of the third NMOS tube NM2, and the gate of the third NMOS tube NM2 is connected to the output end of the voltage comparison circuit OUT_State , the drain of the third NMOS tube NM2 is respectively connected to the output end of the second current source Id2 and the drain of the ninth NMOS tube NM8, the drain of the fifth NMOS tube NM4 is connected to the gate of the N-type power tube, the gate of the ninth NMOS tube NM8 is connected to the INV inverted signal, the source of the ninth NMOS tube NM8 is respectively connected to the drain of the fourth NMOS tube NM3, the gate of the fourth NMOS tube NM3, and the gate of the fifth NMOS tube NM4, the drain of the fifth NMOS tube NM4 is connected to the gate of the N-type power tube as the output end of the pull-down branch, the source of the first NMOS tube NM0, the source of the second NMOS tube NM1, the source of the fourth NMOS tube NM3, and the source of the fifth NMOS tube NM4 are all connected to the relative ground signal LVSS. When the IN enable signal is low, the default intelligent high-side switch begins to enter the off state, the INV inverted signal is high, the ninth NMOS tube NM8 is turned on, and the pull-down branch begins to work. In the initial stage of the intelligent high-side switch being turned off, the voltage comparison circuit OUT_State does not work, the gate control signal V1 of the third NMOS tube NM2 is at a low level, and the third NMOS tube NM2 is turned off. At this time, the output current of the second current source Id2 all flows into the current mirror structure composed of the fourth NMOS tube NM3 and the fifth MOS tube NM4. At this moment, since the pull-down current I1 in the pull-down branch reaches the maximum value, the turn-off rate of the intelligent high-side switch reaches the designed maximum value; when the voltage comparison circuit OUT_State takes effect, the gate control signal V1 of the third NMOS tube NM2 is at a high level, and the third NMOS tube NM2 is turned on. At this time, the magnitude of the pull-down current I1 is the difference between the current drawn by the current mirror structure composed of the second current source Id2 and the first NMOS tube NM0 and the second NMOS tube NM1. The ratio of the current mirror structure composed of the first NMOS tube NM0 and the second NMOS tube NM1 can be used to adjust the ratio of the drawn current, and then adjust the magnitude of the pull-down current I1, so as to achieve the purpose of changing the voltage conversion rate regulation during the pull-down process.

[0033] The pull-up branch in the present invention includes: a sixth NMOS tube NM5, a seventh NMOS tube NM6, an eighth NMOS tube NM7, a tenth NMOS tube NM9, a first PMOS tube PM0 and a second PMOS tube PM1, the gate of the seventh NMOS tube NM6 is connected to the output end of the voltage comparison circuit OUT_State, the source of the seventh NMOS tube NM6 is connected to the drain of the sixth NMOS tube NM5, the source of the sixth NMOS tube NM5 is connected to the source of the eighth NMOS tube NM7, the gate of the sixth NMOS tube NM5 and the gate of the eighth NMOS tube NM7 are both connected to the drain of the first NMOS tube NM0 and the first NMOS tube NM1. The gate of the seventh NMOS tube NM6 and the drain of the eighth NMOS tube NM7 are connected to the source of the tenth NMOS tube NM9, the gate of the tenth NMOS tube NM9 is connected to the IN enable signal, the drain of the tenth NMOS tube NM9 is respectively connected to the drain of the first PMOS tube PM0, the gate of the first PMOS tube PM0, and the gate of the second PMOS tube PM1, the source of the first PMOS tube PM0 and the source of the second PMOS tube PM1 are connected to the charge pump voltage VCP, and the drain of the second PMOS tube PM1 is connected to the gate of the N-type power tube as the output end of the pull-up branch. When the IN enable signal is high, the default intelligent high-side switch starts to enter the open state, the INV inverted signal is low, the tenth NMOS tube NM9 is turned on, and the pull-up branch starts to work. In the initial stage of the intelligent high-side switch being turned on, the voltage comparison circuit OUT_State does not work, the gate control signal V1 of the seventh NMOS tube NM6 is at a low level, the seventh NMOS tube NM6 is turned off, and the output current of the first current source Id1 all flows into the current mirror structure composed of the first NMOS tube NM0 and the eighth NMOS tube NM7. The size of the pull-up current I2 can be adjusted by adjusting the ratio of the above-mentioned current mirror structure to achieve the purpose of changing the voltage conversion rate regulation in the pull-up process; when the voltage comparison circuit OUT_State takes effect, the gate control signal V1 of the seventh NMOS tube NM6 is at a high level, and the seventh NMOS tube NM6 is turned on. At this time, the size of the pull-up current I2 is the sum of the current generated by the current mirror structure composed of the first NMOS tube NM0 and the sixth NMOS tube NM5 and the current generated by the current mirror structure composed of the first NMOS tube NM0 and the eighth NMOS tube NM7. At this moment, since the pull-up current I2 in the pull-up branch reaches the maximum value, the turn-on rate of the intelligent high-side switch reaches the designed maximum value.

[0034] In the present invention, the gate of the third NMOS tube NM2 in the pull-down branch and the gate of the sixth NMOS tube NM5 in the pull-up branch are both provided by the feedback signal V1 of the voltage comparison circuit OUT_State. By controlling the opening or closing of the third NMOS tube NM2 and the sixth NMOS tube NM5, the pull-up dynamic current I2 and the pull-down dynamic current I1 can be dynamically adjusted, thereby adjusting the charging or discharging current of the Miller parasitic capacitor during the opening or closing process of the N-type power tube, and realizing precise control of the high-side switch conversion rate.

[0035] The voltage conversion rate regulating circuit in the present invention further includes: a first resistor R0 and a second resistor R1, one end of the first resistor R0 and one end of the second resistor R1 are both connected to the source of the N-type power tube, the other end of the first resistor R0 is grounded, and the other end of the second resistor R1 is respectively connected to the drain of the fifth NMOS tube NM4 and the drain of the second PMOS tube PM1. The first resistor R0 is the load impedance of the high-side switch output terminal VOUT, which can be used to adjust the output voltage VOUT state; the second resistor R1 is the gate-source terminal resistance of the N-type power tube, which can play a certain auxiliary role in the charging or discharging current size of the Miller parasitic capacitor in the process of dynamically adjusting the opening or closing of the N-type power tube, and is used to stabilize the opening or closing rate of the N-type power tube.

[0036] The present invention is applicable to the voltage comparison circuit OUT_State of the voltage conversion rate regulating circuit of the intelligent high-side switch. The current mirror structure composed of the eleventh NMOS tube NM10 and the twelfth NMOS tube NM11 is biased for the voltage comparison circuit OUT_State through the third current source Id3. According to the requirements of the designer, the third resistor R2, the fourth resistor R3, and the fifth resistor R4 are set to divide the resistor voltage and combined with the feedback signal V1 generated by the voltage comparison circuit OUT_State and the third PMOS tube PM2 to obtain the required hysteresis space. The conversion rate of the high-side switch mainly depends on the speed of charging and discharging the parasitic capacitance of the N-type power tube during the process of turning on or off the N-type power tube. In the process of turning on the N-type power tube, the larger the charging current of the parasitic Miller capacitance of the N-type power tube, the faster the switch is turned on; in the process of turning off the power tube, the smaller the discharge current of the parasitic Miller capacitance of the N-type power tube, the slower the switch is turned off. The feedback signal V1 generated by the voltage comparison circuit OUT_State is used to adjust the charging or discharging current of the Miller parasitic capacitor during the opening or closing of the N-type power tube, thereby controlling and adjusting the intelligent high-side switch conversion rate SR under different usage environments, thereby achieving precise control of the high-side switch conversion rate.

[0037] like Figure 3As shown, when the IN enable signal of the intelligent high-side switch is switched from a low level to a high level, due to the existence of the voltage conversion rate adjustment circuit inside the intelligent high-side switch, the pull-up voltage conversion rate of the intelligent high-side switch works according to the adjustment method in the pull-up process; similarly, when the IN enable signal is switched from a high level to a low level, the pull-down voltage conversion rate works according to the adjustment method in the pull-down process.

[0038] In one technical solution of the present invention, if only the components in the pull-up branch or the pull-down branch are simply adjusted to achieve the purpose of adjusting the voltage conversion rate; or the pull-up branch is used as the pull-down branch, and the pull-down branch is used as the pull-up branch to achieve the purpose of adjusting the voltage conversion rate, it should be deemed to fall within the protection scope of the present invention.

[0039] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A voltage conversion rate regulating circuit suitable for an intelligent high-side switch, characterized in that: include: An enable control circuit, an N-type power tube, a pull-up branch, a pull-down branch and a voltage comparison circuit OUT_State, wherein the IN enable signal of the enable control circuit is used to control the on or off of the pull-up branch, and the INV inverted signal of the enable control circuit is used to control the on or off of the pull-down branch; the output end of the pull-up branch and the output end of the pull-down branch are both connected to the gate of the N-type power tube, and the voltage comparison circuit OUT_State compares the source voltage VOUT of the N-type power tube with the expected set voltage value to generate a feedback signal V1; When the IN enable signal is at a high level, the INV inverted signal is at a low level, at which time the pull-up branch is turned on and the pull-down branch is turned off. The pull-up current I2 is adjusted according to the copy ratio of the current mirror in the pull-up branch and the feedback signal V1 to change the turn-on conversion rate of the intelligent high-side switch. When the IN enable signal is at a low level, the INV inverted signal is at a high level. At this time, the pull-up branch is turned off and the pull-down branch is turned on. The size of the pull-down current I1 is adjusted according to the replication ratio of the current mirror in the pull-down branch and the feedback signal V1 to change the turn-off conversion rate of the intelligent high-side switch.

2. A voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 1, characterized in that: The drain of the N-type power tube is connected to the power supply voltage VBB; the enable control circuit is provided with an inverter, the input end of the inverter is the IN enable signal, and the output end of the inverter is the INV inverted signal.

3. A voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 2, characterized in that: The voltage comparison circuit OUT_State includes: a hysteresis voltage divider module, a current bias module, a secondary operational amplifier and a voltage stabilizing module. The hysteresis voltage divider module is used to divide the power supply voltage VBB through a resistor network to obtain an expected set voltage value; the current bias module is used to provide a bias for the secondary operational amplifier; the secondary operational amplifier is used to compare the source voltage VOUT of the N-type power tube with the expected set voltage value to generate a feedback signal V1; the voltage stabilizing module is used to stabilize the feedback signal V1 to prevent voltage jitter.

4. The voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 3, characterized in that: The hysteresis voltage divider module includes: a third PMOS tube PM2, a third resistor R2, a fourth resistor R3 and a fifth resistor R4, the source of the third PMOS tube PM2 and one end of the third resistor R2 are both connected to the power supply voltage VBB, the gate of the third PMOS tube PM2 and the output end of the voltage stabilizing module are both used as the output end of the voltage comparison circuit, the drain of the third PMOS tube PM2 is respectively connected to the other end of the third resistor R2 and one end of the fourth resistor R3, the other end of the fourth resistor R3 and one end of the fifth resistor R4 are both connected to the input end of the secondary operational amplifier, and the other end of the fifth resistor R4 is grounded.

5. The voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 4, characterized in that: The current bias module includes: a third current source Id3, an eleventh NMOS tube NM10, a twelfth NMOS tube NM11, and a fourth PMOS tube PM3. The input end of the third current source Id3 is connected to the power supply voltage VBB, and the output end of the third current source Id3 is respectively connected to the gate of the eleventh NMOS tube NM10, the drain of the eleventh NMOS tube NM10, and the gate of the twelfth NMOS tube NM11. The drain of the twelfth NMOS tube NM11, the drain of the fourth PMOS tube PM3, and the gate of the fourth PMOS tube PM3 serve as the output end of the current bias module; the source of the fourth PMOS tube PM3 is connected to the power supply voltage VBB, and the source of the eleventh NMOS tube NM10 and the source of the twelfth NMOS tube NM11 are both grounded.

6. The voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 5, characterized in that: The secondary operational amplifier includes: a fifth PMOS tube PM4, a sixth PMOS tube PM5, a seventh PMOS tube PM6, an eighth PMOS tube PM7, a thirteenth NMOS tube NM12, a fourteenth NMOS tube NM13, a fifteenth NMOS tube NM14 and a sixth resistor R5, one end of the sixth resistor R5 is connected to the source of the N-type power tube, the other end of the sixth resistor R5 is connected to the gate of the eighth PMOS tube PM7, the source of the eighth PMOS tube PM7 is respectively connected to the drain of the fifth PMOS tube PM4 and the source of the seventh PMOS tube PM6, the gate of the fifth PMOS tube PM4 and the gate of the sixth PMOS tube PM5 are both connected to the output end of the current bias module, the source of the fifth PMOS tube PM4 and the source of the sixth PMOS tube PM5 are both connected to the drain of the fifth PMOS tube PM4 and the drain of the seventh PMOS tube PM6. The power supply voltage VBB is connected, the gate of the seventh PMOS tube PM6 is connected to one end connected with the fourth resistor R3 and the fifth resistor R4, the drain of the seventh PMOS tube PM6 is respectively connected to the drain of the thirteenth NMOS tube NM12, the gate of the thirteenth NMOS tube NM12, and the gate of the fourteenth NMOS tube NM13; the drain of the eighth PMOS tube PM7 is respectively connected to the drain of the fourteenth NMOS tube NM13 and the gate of the fifteenth NMOS tube NM14, the drain of the fifteenth NMOS tube NM14 and the drain of the sixth PMOS tube PM5 are both connected to the input end of the voltage stabilizing module as the output end of the secondary operational amplifier, and the source of the thirteenth NMOS tube NM12, the source of the fourteenth NMOS tube NM13, and the source of the fifteenth NMOS tube NM14 are all grounded.

7. The voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 6, characterized in that: The voltage stabilizing module is a Schmitt trigger, the input end of the Schmitt trigger is connected to the output end of the secondary operational amplifier, and the output end of the Schmitt trigger is connected to the gate of the third PMOS tube PM2, the input end of the pull-up branch, and the input end of the pull-down branch as the output end of the voltage comparison circuit.

8. The voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 7, characterized in that: The pull-down branch includes: a first current source Id1, a second current source Id2, a first NMOS tube NM0, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM4 and a ninth NMOS tube NM8. The input end of the first current source Id1 and the input end of the second current source Id2 are both connected to the power supply voltage VBB. The output end of the first current source Id1 is respectively connected to the drain of the first NMOS tube NM0, the gate of the first NMOS tube NM0 and the gate of the second NMOS tube NM1. The drain of the second NMOS tube NM1 is connected to the source of the third NMOS tube NM2. The gate of the third NMOS tube NM2 is connected to the voltage comparison circuit OUT. The output end of the pull-down branch is connected to the output end of the N-type power tube, the drain of the third NMOS tube NM2 is respectively connected to the output end of the second current source Id2 and the drain of the ninth NMOS tube NM8, the gate of the ninth NMOS tube NM8 is connected to the INV inversion signal, the source of the ninth NMOS tube NM8 is respectively connected to the drain of the fourth NMOS tube NM3, the gate of the fourth NMOS tube NM3 and the gate of the fifth NMOS tube NM4, the drain of the fifth NMOS tube NM4 is connected to the gate of the N-type power tube as the output end of the pull-down branch, the source of the first NMOS tube NM0, the source of the second NMOS tube NM1, the source of the fourth NMOS tube NM3 and the source of the fifth NMOS tube NM4 are all connected to the relative ground signal LVSS.

9. The voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 8, characterized in that: The pull-up branch includes: a sixth NMOS tube NM5, a seventh NMOS tube NM6, an eighth NMOS tube NM7, a tenth NMOS tube NM9, a first PMOS tube PM0 and a second PMOS tube PM1, the gate of the seventh NMOS tube NM6 is connected to the output end of the voltage comparison circuit OUT_State, the source of the seventh NMOS tube NM6 is connected to the drain of the sixth NMOS tube NM5, the source of the sixth NMOS tube NM5 is connected to the source of the eighth NMOS tube NM7, the gate of the sixth NMOS tube NM5 and the gate of the eighth NMOS tube NM7 are both connected to the drain of the first NMOS tube NM0 and the first NMOS tube NM1. The gate of the seventh NMOS tube NM6 and the gate of the eighth NMOS tube NM7 are connected to the source of the tenth NMOS tube NM9, the gate of the tenth NMOS tube NM9 is connected to the IN enable signal, the drain of the tenth NMOS tube NM9 is respectively connected to the drain of the first PMOS tube PM0, the gate of the first PMOS tube PM0, and the gate of the second PMOS tube PM1, the source of the first PMOS tube PM0 and the source of the second PMOS tube PM1 are both connected to the charge pump voltage VCP, and the drain of the second PMOS tube PM1 is connected to the gate of the N-type power tube as the output end of the pull-up branch.

10. The voltage conversion rate regulating circuit suitable for an intelligent high-side switch according to claim 9, characterized in that: It also includes a first resistor R0 and a second resistor R1, one end of the first resistor R0 and one end of the second resistor R1 are both connected to the source of the N-type power tube, the other end of the first resistor R0 is grounded, and the other end of the second resistor R1 is respectively connected to the drain of the fifth NMOS tube NM4 and the drain of the second PMOS tube PM1.

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