Pulse generator and method for generating pulse

Abstract

The invention discloses a pulse generator and a method for generating pulses, and relates to the technical field of pulses, the pulse generator comprises a parameter configuration module, a phase accumulator, a pulse generation module and a digital-to-analog converter; the parameter configuration module is used for acquiring pulse parameters when in a pulse output mode, calculating a frequency tuning word FTW value of each pulse according to the pulse parameters, and writing the pulse parameters and the FTW values into a memory; the phase accumulator is used for executing accumulation operation according to the FTW value to obtain a phase value, and when the phase value reaches the maximum capacity, generating a trigger instruction and sending the trigger instruction to the pulse generation module; the pulse generation module is used for generating a digital signal according to the pulse parameter and the FTW value and sending the digital signal to the digital-to-analog converter; the digital-to-analog converter is configured to receive a digital signal and convert it to an analog signal. The pulse generator in the application can output a parameter-controllable pulse sequence and generate pulse signals with different characteristics, so that the flexibility and operability of the test are improved.

Description

Technical Field

[0001] The present application relates to the field of pulse technology, and in particular to a pulse generator and a method for generating pulses. Background Art

[0002] With the continuous development of electronic technology, pulse signal generators, as an electronic device used to generate pulse signals with specific waveforms, frequencies and amplitudes, have been increasingly used in different systems, such as communication systems, radar systems, digital circuit test systems, etc. Among them, when testing power devices, it is necessary to input pulse signals with different parameters to the gate of the power device to be tested to test the switching properties of the device, and during the test process, it is necessary to fine-tune the pulse signal according to the measured data, so as to achieve flexible testing of the power device.

[0003] At present, the parameters of each pulse in the pulse sequence output by the pulse generator in the related technology are the same. When using arbitrary waves to output the pulse sequence, the number of pulses with different parameters in the pulse sequence is limited, and the pulse parameters cannot be adjusted in real time, resulting in poor test flexibility and operability. Summary of the invention

[0004] The purpose of the present application is to provide a pulse generator and a method for generating a pulse signal, which can output a pulse sequence with controllable parameters and generate pulse signals with different characteristics, thereby improving the flexibility and operability of the test.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] In a first aspect, the present application provides a pulse generator, comprising:

[0007] A parameter configuration module, a phase accumulator, a pulse generation module, and a digital-to-analog converter; the parameter configuration module is respectively connected to the phase accumulator and the pulse generation module, and the pulse generation module is respectively connected to the phase accumulator and the digital-to-analog converter;

[0008] The parameter configuration module is used to: when in pulse output mode, obtain pulse parameters, calculate the frequency tuning word FTW value of each pulse according to the pulse parameters, and write the pulse parameters and the FTW value into the memory;

[0009] The phase accumulator is used to: perform an accumulation operation according to the FTW value to obtain a phase value, and when the phase value reaches a maximum capacity, generate a trigger instruction and send it to the pulse generation module;

[0010] The pulse generating module is used to: generate a digital signal according to the pulse parameter and the FTW value and send the digital signal to the digital-to-analog converter;

[0011] The digital-to-analog converter is used to receive the digital signal and convert it into an analog signal.

[0012] Optionally, the parameter configuration module includes: an acquisition unit, a calculation unit and a storage unit, and the calculation unit is connected to the acquisition unit and the storage unit respectively;

[0013] The acquisition unit is used to: when in pulse output mode, acquire the pulse parameters of each pulse in the entire pulse sequence; the pulse parameters include: rising edge time, falling edge time, positive pulse width, negative pulse width, and the number of pulses in the entire pulse sequence; the positive pulse width is used to characterize the time corresponding to the positive pulse, and the negative pulse width is used to characterize the time corresponding to the negative pulse;

[0014] The calculation unit is used to: calculate the FTW value of each pulse according to the positive pulse width and the negative pulse width;

[0015] The storage unit is used to write the pulse parameters and the corresponding FTW values ​​of each pulse in the pulse sequence into the memory in sequence according to a first-to-last order and a preset format.

[0016] Optionally, the phase accumulator comprises: a latch unit and an accumulating unit, wherein the latch unit is connected to the accumulating unit;

[0017] The latch unit is used to: when a pulse cycle ends, perform a reset operation, read the i-th group of pulse parameters and FTW values ​​from the memory and latch the i-th group of pulse parameters and FTW values ​​into a local register, 0<i≤n, n is the number of pulses in the entire pulse sequence;

[0018] The accumulation unit is used to perform an accumulation operation according to the latched i-th group of pulse parameters and FTW value to obtain a current phase value, and if the current phase value reaches the maximum capacity, generate a trigger instruction and send it to the pulse generation module.

[0019] Optionally, the accumulating unit is further used for:

[0020] After performing an accumulation operation according to the latched i-th group of pulse parameters, detecting whether there is a rising edge of a high position;

[0021] When a rising edge of the high bit is detected, a next set of pulse parameters of the i-th set of pulse parameters is read from the memory and the next set of pulse parameters is latched into a local register;

[0022] When the current phase value reaches the maximum capacity and the trigger instruction is sent to the pulse generation module, an accumulation operation is performed according to the latched next set of pulse parameters to obtain the next phase value.

[0023] Optionally, the pulse generator further comprises: a clock signal module, wherein the clock signal module is respectively connected to the phase accumulator and the digital-to-analog converter;

[0024] The clock signal module is used to provide a clock signal to the phase accumulator and the digital-to-analog converter, so that the phase accumulator performs an accumulation operation according to the clock signal and the FTW value, and the digital-to-analog converter converts the digital signal into an analog signal according to the clock signal.

[0025] Optionally, the pulse generator is further used for:

[0026] When the analog signal corresponding to each pulse in the entire pulse sequence is converted, the control exits the pulse output mode.

[0027] In a second aspect, an embodiment of the present application provides a method for generating a pulse signal, which is applied to a pulse generator. The method for generating a pulse signal includes:

[0028] When in pulse output mode, obtaining pulse parameters, calculating a frequency tuning word FTW value of each pulse according to the pulse parameters, and writing the pulse parameters and the FTW value into a memory;

[0029] Performing an accumulation operation according to the FTW value to obtain a phase value;

[0030] When the phase value reaches a maximum capacity, a digital signal is generated and converted into an analog signal according to the pulse parameter and the FTW value.

[0031] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0032] The present application provides a pulse generator and a method for generating pulses. The pulse generator includes: a parameter configuration module, a phase accumulator, a pulse generation module, and a digital-to-analog converter. The parameter configuration module is respectively connected to the phase accumulator and the pulse generation module, and the pulse generation module is respectively connected to the phase accumulator and the digital-to-analog converter. The parameter configuration module is used to: when in a pulse output mode, obtain pulse parameters, calculate the frequency tuning word FTW value of each pulse according to the pulse parameters, and write the pulse parameters and the FTW value into a memory; the phase accumulator is used to: perform an accumulation operation according to the FTW value to obtain a phase value, and when the phase value reaches a maximum capacity, generate a trigger instruction and send it to the pulse generation module; the pulse generation module is used to: generate a digital signal according to the pulse parameters and the FTW value and send it to the digital-to-analog converter; the digital-to-analog converter is used to: receive the digital signal and convert it into an analog signal. Compared with the prior art, the pulse generator of the present application is provided with a parameter configuration device, so that the user can freely configure the pulse parameters according to the needs, so that the generation of the pulse signal is more flexible, and a parameter-controllable pulse sequence can be output, and the parameter configuration module can update the parameters in the memory according to the needs, so as to realize the generation of pulse signals with different characteristics in a pulse sequence, that is, the parameters of each pulse in the pulse sequence can be different and the number of pulses can be arbitrary, and the accurate FTW value is calculated according to the pulse parameters, which can ensure that the frequency and width of each pulse can be accurately controlled; the phase value is obtained by accumulating the FTW value through the phase accumulator, which can accurately reflect the phase information of the output signal, so that when the phase value reaches the maximum capacity, that is, the accumulator overflows, the pulse parameters and the FTW value are comprehensively considered, and the analog signal is accurately output through the pulse generation module and the digital-to-analog conversion module, so that the real-time adjustable parameters and the output of arbitrary pulses are realized, which greatly improves the performance of the output pulse and enhances the flexibility and operability of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a pulse generator provided in one embodiment of the present application;

[0035] Figure 2 A schematic diagram of the structure of a direct digital frequency synthesizer provided in one embodiment of the present application;

[0036] Figure 3 A schematic diagram of a pulse sequence formed based on the DDS principle provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the structure of a pulse generator provided in another embodiment of the present application;

[0038] Figure 5 A timing diagram for writing FTW values ​​and pulse parameters into a memory provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a structure of a location where pulse parameters and FTW values ​​are written in a memory according to an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the change trend of the FTW value and the corresponding phase accumulator provided in an embodiment of the present application;

[0041] Figure 8 A flow chart of a method for generating a pulse signal provided in one embodiment of the present application;

[0042] Fig. 9 A flow chart of a parameter updating method provided in an embodiment of the present application;

[0043] Description of reference numerals:

[0044] Parameter configuration module-10, acquisition unit-11, calculation unit-12, storage unit-13, phase accumulator-20, latch unit-21, accumulation unit-22, pulse generation module-30, digital-to-analog converter-40, clock signal module-50. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0047] As mentioned in the background technology, the parameters of each pulse in the pulse sequence output by the pulse generator in the related technology are the same. When using arbitrary waves to output the pulse sequence, the number of pulses with different parameters in the pulse sequence is limited, and the pulse parameters cannot be adjusted in real time, resulting in poor test flexibility and operability.

[0048] Based on the above defects, an embodiment of the present application provides a pulse generator. Compared with the prior art, the pulse generator of the present application is provided with a parameter configuration device, so that the user can freely configure the pulse parameters according to the needs, so that the generation of the pulse signal is more flexible, and a parameter-controllable pulse sequence can be obtained. Moreover, the parameter configuration module can update the parameters in the memory according to the needs, so as to realize the generation of pulse signals with different characteristics in a pulse sequence, that is, the parameters of each pulse in the pulse sequence can be different and the number of pulses can be arbitrary, and the accurate FTW value is calculated according to the pulse parameters, so as to ensure that the frequency and width of each pulse can be accurately controlled; the phase value is obtained by accumulating the FTW value through the phase accumulator, which can accurately reflect the phase information of the output signal, so that when the phase value reaches the maximum capacity, that is, the accumulator overflows, the pulse parameters and the FTW value are comprehensively considered, and the analog signal is accurately output through the pulse generation module and the digital-to-analog conversion module, so that the real-time adjustment of the parameters and the output of any pulse are realized, which greatly improves the performance of the output pulse and enhances the flexibility and operability of the test.

[0049] See also Figure 1 As shown, Figure 1 This is a structural schematic diagram of a pulse generator provided in an embodiment of the present application, wherein the pulse generator comprises: a parameter configuration module 10, a phase accumulator 20, a pulse generation module 30, and a digital-to-analog converter 40; the parameter configuration module 10 is respectively connected to the phase accumulator 20 and the pulse generation module 30, and the pulse generation module 30 is respectively connected to the phase accumulator 20 and the digital-to-analog converter 40.

[0050] The parameter configuration module 10 is used to: when in the pulse output mode, obtain the pulse parameters, calculate the frequency tuning word FTW value of each pulse according to the pulse parameters, and write the pulse parameters and the FTW value into the memory; the phase accumulator 20 is used to: perform the accumulation operation according to the FTW value to obtain the phase value, and when the phase value reaches the maximum capacity, generate a trigger instruction and send it to the pulse generation module; the pulse generation module 30 is used to: generate a digital signal according to the pulse parameters and the FTW value and send it to the digital-to-analog converter; the digital-to-analog converter 40 is used to: receive the digital signal and convert it into an analog signal.

[0051] It should be noted that the above-mentioned pulse parameters refer to parameters used to generate pulse signals, and the pulse parameters may include: rising edge time (Tr), falling edge time (Tf), positive pulse width (Tp), negative pulse width (Tn), and the number of pulses in the entire pulse sequence; the positive pulse width is used to characterize the time corresponding to the positive pulse, and the negative pulse width is used to characterize the time corresponding to the negative pulse. The above-mentioned parameter configuration module 10 is used to receive the pulse parameters input by the user, calculate the corresponding FTW value, and write the FTW value and pulse parameters into the memory, which can be RAM or other storage units for storing data. The above-mentioned phase accumulator is a core component in the pulse signal generator based on the direct digital frequency synthesizer (Direct Digital Synthesizer, DDS) technology. Its main function is to generate a phase value that varies with time by continuously accumulating the frequency tuning word (FTW), and it may include an accumulation circuit inside. The above-mentioned pulse generation module is used to generate the required digital signal according to the phase information provided by the phase accumulator and the pulse parameters provided by the parameter configuration module. The above-mentioned digital-to-analog converter is used to convert the digital signal into an analog signal.

[0052] Understandably, see Figure 2 As shown, Figure 2 The schematic diagram of the structure of the pulse generator based on the direct digital frequency synthesizer provided in the embodiment of the present application, DDS is a digital synthesis technology that converts a series of digital signals into analog signals through a D / A converter, and its basic principle mainly consists of a standard reference frequency source, a phase accumulator, a lookup table and a digital-to-analog converter DAC. Under the control of the clock pulse, the frequency control word FTW obtains the corresponding phase value by the accumulator, and processes and outputs the corresponding digital signal according to the lookup table, smoothes the digital signal through a filter, and converts the processed signal into a corresponding step wave through a digital-to-analog converter, that is, a continuously changing output waveform determined by the frequency control word FTW is obtained.

[0053] Among them, the above-mentioned standard reference frequency source is used to generate a reference clock to provide a stable reference frequency; the phase accumulator is a digital counter that increases in a certain step size. The accumulated value represents the instantaneous phase of the output signal and is used to track the current phase of the output function; the digital-to-analog converter (DAC): is used to convert digital signals into analog signals, that is, to convert the discrete amplitude values ​​found into continuous analog signals; the filter is used to smooth the output signal, reduce the aliasing effect, and remove unnecessary high-frequency components. The above-mentioned phase accumulator has N bits, and a waveform of one cycle is stored in the lookup table. Each time the phase accumulator overflows, a complete waveform cycle is output. After being filtered by the filter, it is converted into an analog signal output by the digital-to-analog converter DAC.

[0054] See also Figure 3As shown, Figure 3 A schematic diagram of a pulse sequence formed based on the DDS principle provided in an embodiment of the present application. Tr represents the time of the rising edge of the pulse, Tf represents the time of the falling edge of the pulse, Tp represents the positive pulse width, and Tn represents the negative pulse width. Assuming that a sequence has n pulse signals with independent parameters, the subscripts 1 to n are used to define the parameters of each part according to the order of the pulse output time, where Tr1, Tp1, Tf1, and Tn1 respectively represent the time of the rising edge, positive pulse width, falling edge time, and negative pulse width corresponding to the first pulse; Tr2, Tp2, Tf2, and Tn2 respectively represent the time of the rising edge, positive pulse width, falling edge time, and negative pulse width corresponding to the second pulse. After obtaining the number of bits of the phase accumulator, the FTW value, and the reference clock signal, the output frequency of the DDS is calculated, which can be expressed by the following formula:

[0055] fout = fref * FTW / 2^N;

[0056] Among them, fout is the output frequency of the signal, fref is the reference clock signal, N is the number of bits of the phase accumulator, which determines the frequency resolution of the system, and FTW is the frequency control word.

[0057] After calculating the output frequency of DDS, the period of a single pulse is calculated according to the output frequency of DDS. The pulse period T1 of the first pulse can be expressed by the following formula:

[0058] T1=Tp1+Tn1=1 / (fref*FTW1 / 2^N);

[0059] Similar to T1 above, the pulse period T2 of the second pulse is obtained by the following formula:

[0060] T2=Tp2+Tn2=1 / (fref*FTW2 / 2^N);

[0061] Among them, in the above formula, fref is the reference clock signal, N is the number of bits of the phase accumulator, and the number of bits determines the frequency resolution of the system, FTW1 is the frequency control word of the first pulse, FTW2 is the frequency control word of the second pulse, Tp1 is the positive pulse width of the first pulse, Tp2 is the positive pulse width of the second pulse, Tn1 is the negative pulse width of the first pulse, and Tn2 is the negative pulse width of the second pulse.

[0062] The remaining Tn are similar to T1 and T2. Similarly, other pulse signals can also get the corresponding cycle time. After the user sets the relevant pulse parameters, each module in the channel is turned on, and each module is processed in turn, so as to output each pulse signal of the entire pulse sequence in turn. The output signal is Mbits.

[0063] In the embodiment of the present application, an improvement is made based on the above-mentioned DDS principle, a parameter configuration module 10 is set and pulse parameters are obtained through the parameter configuration module 10, and the FTW value is calculated according to the pulse parameters input by the user and written into the memory RAM, and the phase accumulator is used to determine whether there is an overflow according to the FTW value. When there is an overflow, a pulse signal is output, and a pulse signal is output each time there is an overflow. After a pulse signal is output, the next set of parameters is switched, so that the phase accumulator continues to perform the accumulation processing according to the next set of parameters, and the above operations are performed in a loop, so that the parameters are continuously updated. In the process of continuous parameter updating, the output pulse shape will also change continuously according to the parameters, thereby realizing the generation of pulse signals with different characteristics in a pulse sequence, that is, the parameters of each pulse in the pulse sequence can be different and the number of pulses can be arbitrary.

[0064] In one embodiment, see Figure 4 As shown, the parameter configuration module 10 includes: an acquisition unit 11, a calculation unit 12 and a storage unit 13, and the calculation unit 12 is connected to the acquisition unit 11 and the storage unit 13 respectively.

[0065] The acquisition unit 11 is used to: when in the pulse output mode, obtain the pulse parameters of each pulse in the entire pulse sequence; the calculation unit 12 is used to: calculate the FTW value of each pulse according to the positive pulse width and the negative pulse width; the storage unit 13 is used to: write the pulse parameters and the corresponding FTW value of each pulse in the pulse sequence into the memory in sequence according to the order from first to last and the preset format.

[0066] Specifically, the acquisition unit 11 may include an input interface and a display unit connected to the input interface, which is responsible for interaction with the user. The input interface is used to receive the pulse parameters input by the user, and the display unit is used to display the currently set parameters and other related information, which is convenient for the user to confirm and adjust. After the pulse parameters of each pulse input by the user are obtained through the input interface, the parameters input by the user can be parsed, and the validity and consistency of the parameters can be ensured, including parameter validity check and consistency check. In the process of parameter validity check, it can be checked whether the input parameters meet the expected range and format; in the process of consistency check, it can be ensured that there is no contradiction between all related parameters, for example, the sum of the positive pulse width and the negative pulse width should be equal to a complete cycle. When the acquired pulse parameters are passed through the parameter validity check and consistency check, the FTW value corresponding to each pulse is calculated by the calculation unit 12 according to the pulse parameters input by the user, specifically, the FTW value of each pulse is calculated according to the positive pulse width and negative pulse width of each pulse, and then the calculated FTW value and related pulse parameters are written into the internal RAM according to the predetermined format through the storage unit 13.

[0067] In the process of writing the FTW value and pulse parameters into RAM, they can be formatted first, and the calculated FTW value and pulse parameters can be formatted into the agreed format P. The conversion format can be: P(x) = {FTW, Tr, Tf, Tp, Tn}. Among them, x is the number of pulses in the entire pulse sequence, FTW, Tr is the time of the rising edge, Tf is the time of the falling edge, Tp is the positive pulse width, and Tn is the negative pulse width. Then the formatted parameters are written to the specified location in the internal RAM.

[0068] See also Figure 5 and Figure 6 As shown, Figure 5 A timing diagram for writing FTW values ​​and pulse parameters into memory provided in an embodiment of the present application, Figure 6 A schematic diagram of the location structure of parameter writing provided in an embodiment of the present application, wherein the parameters after conversion format are P(0)~P(n-1), P(0)~P(n-1) represent the parameters of each pulse in a pulse sequence, and the parameters P(0), P(1), P(2), ..., P(n-3), P(n-2), P(n-1) are written into the memory RAM in an ascending order starting from address i in the order of address i=i+1.

[0069] In this embodiment, the parameter configuration module sets up an acquisition unit, a calculation unit and a storage unit, and the units cooperate with each other to ensure that the parameters input by the user can be correctly parsed, calculated and stored, and finally used by the phase accumulator and the pulse generation module. The parameter configuration module can not only provide a user-friendly interactive interface, but also ensure the efficient operation and accurate output of the pulse signal generator.

[0070] The above-mentioned phase accumulator 20 may include an accumulator register and an accumulator circuit. The accumulator register may be understood as a register with high resolution for storing the current phase value. The number of bits of the phase accumulator determines the maximum phase value that it can represent, and also directly affects the frequency resolution of the output signal. In the process of continuous accumulation and summation, the phase accumulator 20 may read the FTW value from the internal RAM, and update the FTW value through the formula PHASE_ACC=PHASE_ACC+FTW, thereby continuously accumulating and summing through the accumulator circuit. When the phase accumulator overflows, a trigger instruction is generated and sent to the pulse generation module 30 to output the corresponding digital signal. Wherein, a pulse is output each time the phase accumulator overflows.

[0071] The pulse generating module 30 may include a pulse circuit therein, which is used to read the pulse parameters and FTW values ​​in the memory, and process the pulse parameters and FTW values ​​using the pulse circuit to generate a digital signal and send it to the digital-to-analog converter 40, so that the digital-to-analog converter 40 converts the digital signal into an analog signal.

[0072] The present application provides a pulse generator, which includes: a parameter configuration module, a phase accumulator, a pulse generation module, and a digital-to-analog converter. The parameter configuration module is respectively connected to the phase accumulator and the pulse generation module, and the pulse generation module is respectively connected to the phase accumulator and the digital-to-analog converter. The parameter configuration module is used to: when in a pulse output mode, obtain pulse parameters, calculate the frequency tuning word FTW value of each pulse according to the pulse parameters, and write the pulse parameters and the FTW value into a memory; the phase accumulator is used to: perform an accumulation operation according to the FTW value to obtain a phase value, and when the phase value reaches a maximum capacity, generate a trigger instruction and send it to the pulse generation module; the pulse generation module is used to: generate a digital signal according to the pulse parameters and the FTW value and send it to the digital-to-analog converter; the digital-to-analog converter is used to: receive the digital signal and convert it into an analog signal. Compared with the prior art, the pulse generator of the present application is provided with a parameter configuration device, so that the user can freely configure the pulse parameters according to the needs, so that the generation of the pulse signal is more flexible, and a parameter-controllable pulse sequence can be obtained. Moreover, the parameter configuration module can update the parameters in the memory according to the needs, so as to realize the generation of pulse signals with different characteristics in a pulse sequence, that is, the parameters of each pulse in the pulse sequence can be different and the number of pulses can be arbitrary, and the accurate FTW value is calculated according to the pulse parameters, which can ensure that the frequency and width of each pulse can be accurately controlled; the phase value is obtained by accumulating the FTW value through the phase accumulator, which can accurately reflect the phase information of the output signal, so that when the phase value reaches the maximum capacity, that is, the accumulator overflows, the pulse parameters and the FTW value are comprehensively considered, and the analog signal is accurately output through the pulse generation module and the digital-to-analog conversion module, so that the real-time adjustable parameters and the output of arbitrary pulses are realized, which greatly improves the performance of the output pulse and enhances the flexibility and operability of the test.

[0073] In one of the embodiments, in one of the embodiments, please continue to see Figure 4 As shown, the phase accumulator 20 comprises:

[0074] The latch unit 21 and the accumulation unit 22 are connected; the latch unit 21 is used to: when a pulse cycle ends, perform a reset operation, read the i-th group of pulse parameters and FTW values ​​from the memory and latch the i-th group of pulse parameters and FTW values ​​into a local register, 0<i≤n, n is the number of pulses in the entire pulse sequence; the accumulation unit 22 is used to: perform an accumulation operation according to the latched i-th group of pulse parameters and FTW values ​​to obtain a current phase value, and if the current phase value reaches the maximum capacity, generate a trigger instruction and send it to the pulse generation module.

[0075] It should be noted that the (frequency tuning word) FTW value read from the memory of the parameter configuration module 10 is the incremental value accumulated by the phase accumulator each time, which determines the frequency of the output signal. The larger the FTW value, the faster the accumulation rate of the phase accumulator, and the higher the frequency of the output signal.

[0076] Optional, please continue to see Figure 1 As shown, the above-mentioned pulse generator also includes: a clock signal module 50, which is connected to the phase accumulator 20 and the digital-to-analog converter 40 respectively; the clock signal module 50 is used to: provide a clock signal to the phase accumulator 20 and the digital-to-analog converter 40, so that the phase accumulator 20 performs an accumulation operation according to the clock signal and the FTW value, and the digital-to-analog converter 40 converts the digital signal into an analog signal according to the clock signal.

[0077] It should be noted that the clock signal module 50 is used to generate a clock signal, and the operation of the phase accumulator 20 is controlled by the clock signal. When each cycle of the clock signal arrives, the phase accumulator 20 adds the FTW value to the current phase value. When the phase value of the phase accumulator 20 reaches the maximum capacity, it indicates that the phase accumulator 20 overflows. At this time, the phase accumulator 20 performs a reset operation to the initial state, and an overflow event or trigger signal can be generated.

[0078] Specifically, before the phase accumulator 20 starts working, it will be initialized to zero or a preset initial phase value. Every time a cycle of the reference clock passes, the phase accumulator reads the i-th group of pulse parameters and FTW values ​​from the memory and latches the i-th group of pulse parameters and FTW values ​​into the local register. The accumulator performs a release operation, and then performs an accumulation operation based on the latched i-th group of pulse parameters and FTW values, that is, the currently stored phase value is added to the FTW value to obtain the current phase value. This operation can be expressed as: PHASE_ACC = PHASE_ACC + FTW. When the current phase value of the phase accumulator 20 reaches the maximum capacity, an overflow will occur. At this time, the value of the phase accumulator will be reset to zero and an overflow signal will be generated. This signal can be used to trigger the pulse generation module 30 to indicate that a new pulse should be output.

[0079] Optionally, the above-mentioned accumulation unit 22 is also used to: after performing the accumulation operation according to the latched i-th group of pulse parameters, detect whether there is a high-bit rising edge; when the high-bit rising edge is detected, read the next group of pulse parameters of the i-th group of pulse parameters from the memory and latch the next group of pulse parameters to the local register; if the current phase value reaches the maximum capacity and sends a trigger instruction to the pulse generation module 30, perform the accumulation operation according to the latched next group of pulse parameters to obtain the next phase value.

[0080] The phase accumulator 20 and the pulse generation module 30 are very sensitive to the update time of the parameters, especially the change of the FTW value, see Figure 7 As shown, Figure 7 A schematic diagram of the change trend of the FTW value and the corresponding phase accumulator provided in the embodiment of the present application, for example, FTW1=5, FTW2=6, and the change trend of the corresponding phase accumulator can be seen in the figure. Before the phase accumulator 20 overflows, the system needs to determine in advance whether it is about to overflow, and update the FTW value and other related parameters at an appropriate time. The overflowed part still belongs to the previous pulse. After the FTW value is switched, it starts to accumulate from 0 instead of accumulating from the overflow. The specific process is to detect whether there is a rising edge of the high position of the phase accumulator 20. When a rising edge is detected in the high position (most significant bit, MSB) of the phase accumulator, the next set of parameters is read from the memory and latched into the local register, waiting to be used at the next overflow, and the new parameters are updated at the moment of the phase accumulator 20 overflow, and so on, so as to achieve parameter update.

[0081] In this embodiment, by setting a latch unit and an accumulation unit, a very high frequency resolution and phase accuracy can be achieved according to the clock signal, and the frequency of the output signal can be quickly changed by simply changing the FTW value. It is suitable for application scenarios that require fast frequency hopping. At the same time, the operation of the phase accumulator depends on a stable clock signal, ensuring the stability and consistency of the output signal. The design of the phase accumulator can support a variety of different FTW values, so that the system can generate signals with different frequency and phase characteristics, increasing flexibility.

[0082] Optionally, the pulse generation module 30 may include a phase information reading unit, a parameter reading unit, a pulse logic control unit, and a pulse signal output unit. The phase information reading unit is used to read the current phase value from the phase accumulator. The phase value is used to determine the instantaneous state of the pulse signal, and the instantaneous state is used to characterize whether there is a pulse output at the current moment. The pulse parameters and FTW values ​​are read from the memory through the parameter reading unit. The pulse parameters include FTW value, rising edge time (Tr), falling edge time (Tf), positive pulse width (Tp) and negative pulse width (Tn), etc. Then, the pulse logic control unit controls the generation of the pulse signal according to the phase information and pulse parameters. The pulse logic control unit may include: a phase comparator, a pulse width controller, and an edge controller. The phase comparator is used to compare the current phase value with a preset threshold to determine whether it is in a high level or low level state of the pulse; the pulse width controller is used to control the duration of the pulse according to the positive pulse width (Tp) and the negative pulse width (Tn); the edge controller is used to control the edge slope of the pulse according to the rising edge time (Tr) and the falling edge time (Tf). The pulse signal output unit is used to generate a digital signal, which is a pulse signal, and output the pulse signal to a digital-to-analog converter (DAC), thereby outputting an analog signal.

[0083] In this embodiment, before the pulse generation module 30 starts working, it will read the parameters of the first pulse from the memory RAM, initialize the subunits such as the phase comparator, the pulse width controller and the edge controller, and then regularly read the current phase value from the phase accumulator. The phase value reflects the instantaneous phase information of the output signal, and the phase comparator determines whether a high level or a low level should be output at the current moment according to the phase value. When the phase value falls within the phase interval corresponding to the positive pulse width (Tp), a high level is output; when the phase value falls within the phase interval corresponding to the negative pulse width (Tn), a low level is output. The pulse width controller controls the duration of the pulse according to the positive pulse width (Tp) and the negative pulse width (Tn) to ensure that the width of each pulse meets the set value. The edge controller can control the rising and falling edges of the pulse according to the rising edge time (Tr) and the falling edge time (Tf) through a delay circuit or an edge adjustment algorithm. Once the high and low level states and duration of the pulse are determined, the pulse signal output unit will output the generated digital pulse signal to the digital-to-analog converter (DAC), and the DAC will convert the digital signal into an analog signal for output. When the phase accumulator sends an overflow signal, the pulse generation module reads the next set of pulse parameters from the memory and updates its internal state, thus ensuring that each pulse can be generated according to the new parameters.

[0084] The pulse generation module in this embodiment can generate highly accurate pulse signals by controlling the width and edge of the pulse, and can dynamically adjust the pulse parameters according to different application requirements, making the system highly flexible, ensuring the stable output of the pulse signal through the stable phase accumulator output and precise pulse control logic, and can respond to the output of the phase accumulator in real time to quickly generate pulse signals, thereby improving the signal generation efficiency.

[0085] Optionally, the pulse generator is also used to: control the exit from the pulse output mode after the conversion of the analog signal corresponding to each pulse in the entire pulse sequence is completed.

[0086] When the pulse generator is in the pulse output mode, the pulse parameters are obtained through the parameter configuration module 10, the frequency tuning word FTW value of each pulse is calculated according to the pulse parameters, and the pulse parameters and the FTW value are written into the memory, and then the phase accumulator 20 performs an accumulation operation according to the FTW value to obtain the phase value. When the phase value reaches the maximum capacity, a trigger instruction is generated and sent to the pulse generation module 30, so that the pulse generation module 30 generates a digital signal according to the pulse parameters and the FTW value and sends it to the digital-to-analog converter 40, and the digital signal is received by the digital-to-analog converter 40 and converted into an analog signal, thereby exiting the pulse output mode.

[0087] In this embodiment, the user can freely configure the pulse parameters according to the needs, so that the generation of the pulse signal is more flexible, and a pulse sequence with controllable parameters can be obtained. Moreover, the parameter configuration module can update the parameters in the memory according to the needs, and by dividing the pulse sequence into multiple independent pulses, the FTW value of each pulse is obtained according to the positive pulse width and the negative pulse width, so as to ensure that the frequency and width of each pulse can be accurately controlled. The phase value is obtained by accumulating the FTW value through the phase accumulator, which can accurately reflect the phase information of the output signal. Therefore, when the phase value reaches the maximum capacity, that is, the accumulator overflows, the pulse parameters and the FTW value are comprehensively considered, and the analog signal is accurately output through the pulse generation module and the digital-to-analog conversion module, so that the real-time adjustment of the parameters and the output of any pulse are realized, and the operability and convenience of the device test are enhanced.

[0088] On the other hand, an embodiment of the present application provides a method for generating a pulse, which is applied to the pulse generator provided in the above embodiment, see Figure 8 As shown, the method for generating pulses includes:

[0089] Step S101, when in pulse output mode, obtain pulse parameters, calculate the frequency tuning word FTW value of each pulse according to the pulse parameters, and write the pulse parameters and FTW value into the memory.

[0090] Step S102: Perform an accumulation operation according to the FTW value to obtain a phase value.

[0091] Step S103: When the phase value reaches the maximum capacity, a digital signal is generated according to the pulse parameter and the FTW value and the digital signal is converted into an analog signal.

[0092] Specifically, the pulse generator may include multiple modes, including a pulse output mode and a rest mode. The pulse output mode is used to be in a working state to output a pulse signal; the rest mode is used to be in a resting state and stop working. When a pulse signal needs to be output, the pulse generator can be controlled to be in a pulse output mode. When the pulse generator is set to the pulse output mode, it can receive and respond to the user's input operation instructions to obtain pulse parameters. The pulse parameters include: rising edge time Tr, falling edge time Tf, positive pulse width Tp, negative pulse width Tn, and the number of pulses in the entire pulse sequence; the positive pulse width is used to characterize the time corresponding to the positive pulse, and the negative pulse width is used to characterize the time corresponding to the negative pulse. The user's input operation instruction can be triggered by touching the display unit or by pressing a button on the display unit. This embodiment does not impose any limitation on the input operation instruction, and the input operation instruction may include the pulse parameters input by the user.

[0093] The pulse generator receives and responds to the input operation instruction, obtains the pulse parameters, calculates the FTW value of each pulse according to the pulse parameters, and then writes the calculated FTW value and the related pulse parameters into the internal RAM according to a predetermined format.

[0094] As an implementable method, in the process of obtaining pulse parameters, calculating the FTW value of each pulse according to the pulse parameters, and writing the pulse parameters and the FTW value into the memory, when in the pulse output mode, the pulse parameters of each pulse in the entire pulse sequence are obtained; the FTW value of each pulse is calculated according to the positive pulse width and the negative pulse width; and the pulse parameters and the corresponding FTW value of each pulse in the pulse sequence are written into the memory in sequence according to the order from first to last and the preset format.

[0095] Among them, the above preset format can be customized according to actual needs, for example, it can be P(x)={FTW, Tr, Tf, Tp, Tn}, and the order from first to last can be the arrangement order of each pulse in the entire pulse sequence.

[0096] After obtaining the pulse parameters and the corresponding FTW values, an accumulation operation can be performed according to the FTW values ​​to obtain a phase value, including: when a pulse cycle ends, a reset operation is performed, the i-th group of pulse parameters are read from the memory and the i-th group of pulse parameters are latched into a local register, 0<i≤n, n is the number of pulses in the entire pulse sequence; an accumulation operation is performed according to the latched i-th group of pulse parameters to obtain the current phase value.

[0097] It should be noted that in order to ensure the accuracy and stability of the DDS-based pulse generator when generating pulse signals, careful management and control are required during the operation of the phase accumulator to ensure that the parameters can be correctly predicted and switched before the phase accumulator overflows.

[0098] After performing the accumulation operation according to the latched i-th group of pulse parameters, the method also includes: detecting whether there is a high-bit rising edge; when the high-bit rising edge is detected, reading the next group of pulse parameters of the i-th group of pulse parameters from the memory and latching the next group of pulse parameters to the local register; when the current phase value reaches the maximum capacity and sends a trigger instruction to the pulse generation module, performing the accumulation operation according to the latched next group of pulse parameters to obtain the next phase value.

[0099] Specifically, see Fig. 9 As shown, when the user enters the pulse output mode, the pulse parameters are obtained, and the FTW value is calculated based on the positive pulse width and the negative pulse width, and the pulse parameters and the FTW value are written into the memory RAM, and then when a pulse cycle ends, the phase accumulator needs to be reset to start the accumulation of a new pulse cycle. The purpose of the reset is to return the accumulator to the initial state to ensure the accurate generation of the next pulse. After the phase accumulator is reset, the parameters of the first pulse need to be read from the internal RAM and latched into the local register, which can be read according to the RAM address i, and then the phase accumulator starts the accumulation operation, for example, working with the data of the RAM address i. At this point, the accumulator is no longer affected by the change of external parameters until the next pulse cycle begins. In order to avoid errors caused by accumulator overflow, it is necessary to predict when the phase accumulator is close to its maximum value. Predicting overflow can be achieved by monitoring the high state of the phase accumulator. When a rising edge appears in the high bit (most significant bit, MSB) of the accumulator, this indicates that the phase accumulator is about to overflow.

[0100] Detect whether the phase accumulator overflows, specifically, detect the rising edge of the high position of the phase accumulator. When the rising edge of the high position of the phase accumulator is not detected, it indicates that there is no overflow; when the rising edge of the high position of the accumulator is detected, it indicates that there is an overflow, and the next set of parameters is immediately read from the memory RAM according to the RAM address i=i+1, and latched into the local register. This ensures that when the accumulator overflows, the new parameters are ready and can be used immediately for the generation of the next pulse. When the phase accumulator actually overflows, the new parameters will be used for the next accumulation. At this time, the accumulator will start a new accumulation process from zero instead of continuing to accumulate from the overflow position, thereby outputting the pulse signal of the pulse sequence and converting it into a digital signal through the digital-to-analog converter. After outputting the digital signal of the entire pulse sequence, the user exits the pulse output mode.

[0101] In this embodiment, by reading the pulse parameters and FTW values ​​from the memory and latching them into the local register, it can be ensured that even if the parameters in the RAM change during the subsequent accumulation process, the accumulator can still operate according to the parameters initially read, and it can be ensured that the phase accumulator will not affect the pulse signal being generated when switching parameters, thereby ensuring the accuracy and stability of the output signal.

[0102] In summary, the method for generating pulses provided in the present application, when in pulse output mode, obtains pulse parameters, calculates the frequency tuning word FTW value of each pulse based on the pulse parameters, writes the pulse parameters and FTW value into the memory, and performs an accumulation operation based on the FTW value to obtain a phase value. When the phase value reaches the maximum capacity, a digital signal is generated based on the pulse parameters and the FTW value and the digital signal is converted into an analog signal. Compared with the prior art, in this solution, users can freely configure pulse parameters according to needs, so that the generation of pulse signals is more flexible, and a pulse sequence with controllable parameters can be obtained. Moreover, the parameter configuration module can update the parameters in the memory according to needs, so as to realize the generation of pulse signals with different characteristics in a pulse sequence, that is, the parameters of each pulse in the pulse sequence can be different and the number of pulses can be arbitrary, and the accurate FTW value is calculated according to the pulse parameters, which can ensure that the frequency and width of each pulse can be accurately controlled; the phase value is obtained by accumulating the FTW value through the phase accumulator, which can accurately reflect the phase information of the output signal, so that when the phase value reaches the maximum capacity, that is, the accumulator overflows, the pulse parameters and the FTW value are comprehensively considered, and the analog signal is accurately output through the pulse generation module and the digital-to-analog conversion module, realizing the real-time adjustable parameters and the output of arbitrary pulses, greatly improving the performance of the output pulse, and enhancing the flexibility and operability of the test.

[0103] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A pulse generator, characterized in that: The pulse generator comprises: A parameter configuration module, a phase accumulator, a pulse generation module, and a digital-to-analog converter; the parameter configuration module is respectively connected to the phase accumulator and the pulse generation module, and the pulse generation module is respectively connected to the phase accumulator and the digital-to-analog converter; The parameter configuration module is used to: when in pulse output mode, obtain pulse parameters, calculate the frequency tuning word FTW value of each pulse according to the pulse parameters, and write the pulse parameters and the FTW value into the memory; The phase accumulator is used to: perform an accumulation operation according to the FTW value to obtain a phase value, and when the phase value reaches a maximum capacity, generate a trigger instruction and send it to the pulse generation module; The pulse generating module is used to: generate a digital signal according to the pulse parameter and the FTW value and send the digital signal to the digital-to-analog converter; The digital-to-analog converter is used to receive the digital signal and convert it into an analog signal.

2. The pulse generator according to claim 1, characterized in that The parameter configuration module includes: an acquisition unit, a calculation unit and a storage unit, wherein the calculation unit is connected to the acquisition unit and the storage unit respectively; The acquisition unit is used to: when in pulse output mode, acquire the pulse parameters of each pulse in the entire pulse sequence; the pulse parameters include: rising edge time, falling edge time, positive pulse width, negative pulse width, and the number of pulses in the entire pulse sequence; the positive pulse width is used to characterize the time corresponding to the positive pulse, and the negative pulse width is used to characterize the time corresponding to the negative pulse; The calculation unit is used to: calculate the FTW value of each pulse according to the positive pulse width and the negative pulse width; The storage unit is used to write the pulse parameters and the corresponding FTW values ​​of each pulse in the pulse sequence into the memory in sequence according to a first-to-last order and a preset format.

3. The pulse generator according to claim 1, characterized in that The phase accumulator comprises: a latch unit and an accumulating unit, wherein the latch unit is connected to the accumulating unit; The latch unit is used to: when a pulse cycle ends, perform a reset operation, read the i-th group of pulse parameters and FTW values ​​from the memory and latch the i-th group of pulse parameters and FTW values ​​into a local register, 0<i≤n, n is the number of pulses in the entire pulse sequence; The accumulation unit is used to perform an accumulation operation according to the latched i-th group of pulse parameters and FTW value to obtain a current phase value, and if the current phase value reaches the maximum capacity, generate a trigger instruction and send it to the pulse generation module.

4. The pulse generator according to claim 3, characterized in that: The accumulating unit is also used for: After performing an accumulation operation according to the latched i-th group of pulse parameters, detecting whether there is a rising edge of a high position; When a rising edge of the high bit is detected, a next set of pulse parameters of the i-th set of pulse parameters is read from the memory and the next set of pulse parameters is latched into a local register; When the current phase value reaches the maximum capacity and the trigger instruction is sent to the pulse generation module, an accumulation operation is performed according to the latched next set of pulse parameters to obtain the next phase value.

5. The pulse generator according to claim 1, characterized in that: The pulse generator further comprises: a clock signal module, wherein the clock signal module is respectively connected to the phase accumulator and the digital-to-analog converter; The clock signal module is used to provide a clock signal to the phase accumulator and the digital-to-analog converter, so that the phase accumulator performs an accumulation operation according to the clock signal and the FTW value, and the digital-to-analog converter converts the digital signal into an analog signal according to the clock signal.

6. The pulse generator according to claim 2, characterized in that: The pulse generator is also used for: When the analog signal corresponding to each pulse in the entire pulse sequence is converted, the control exits the pulse output mode.

7. A method for generating a pulse, characterized in that Applied to the pulse generator according to any one of claims 1 to 6 above, the method comprises: When in pulse output mode, obtaining pulse parameters, calculating a frequency tuning word FTW value of each pulse according to the pulse parameters, and writing the pulse parameters and the FTW value into a memory; Performing an accumulation operation according to the FTW value to obtain a phase value; When the phase value reaches a maximum capacity, a digital signal is generated and converted into an analog signal according to the pulse parameter and the FTW value.

8. The method for generating pulses according to claim 7, characterized in that When in the pulse output mode, the pulse parameters are obtained, the frequency tuning word FTW value of each pulse is calculated according to the pulse parameters, and the pulse parameters and the FTW value are written into the memory, including: When in pulse output mode, the pulse parameters of each pulse in the entire pulse sequence are obtained; the pulse parameters include: rising edge time, falling edge time, positive pulse width, negative pulse width, and the number of pulses in the entire pulse sequence; the positive pulse width is used to characterize the time corresponding to the positive pulse, and the negative pulse width is used to characterize the time corresponding to the negative pulse; Calculating the FTW value of each pulse according to the positive pulse width and the negative pulse width; The pulse parameters and the corresponding FTW values ​​of the pulses in the pulse sequence are sequentially written into the memory in a first-to-last order and in a preset format.

9. The method for generating pulses according to claim 7, characterized in that Performing an accumulation operation according to the FTW value to obtain a phase value includes: When a pulse cycle ends, a reset operation is performed, the i-th group of pulse parameters is read from the memory and the i-th group of pulse parameters is latched into a local register, 0<i≤n, n is the number of pulses in the entire pulse sequence; An accumulation operation is performed according to the latched i-th group of pulse parameters to obtain a current phase value.

10. The method for generating pulses according to claim 9, characterized in that After performing the accumulation operation according to the latched i-th group of pulse parameters, the method further includes: Detect whether there is a rising edge of the high bit; When a rising edge of the high bit is detected, a next set of pulse parameters of the i-th set of pulse parameters is read from the memory and the next set of pulse parameters is latched into a local register; When the current phase value reaches the maximum capacity and the trigger instruction is sent to the pulse generation module, an accumulation operation is performed according to the latched next set of pulse parameters to obtain the next phase value.

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