Time-to-digital converter circuit based on standard delay unit in storage and calculation unit

Abstract

The invention belongs to the field of integrated circuit storage and calculation, and particularly relates to a time-to-digital converter circuit based on a standard delay unit in a storage and calculation unit. A rising and falling edge alternating quantization method is adopted, so that the charging and discharging times of a standard delay unit on a main link are reduced in the quantization process, and the power consumption is reduced; a carry-in-advance module which enables signal operation and a quantization process to be parallel is adopted, a transmission gate is used for controlling the quantization process through an operation result, and quantization errors are reduced in the high-speed quantization process. And the reusability and the expandability are ensured by the whole structure. The delay unit chain adopted in the invention is composed of the standard delay units in the storage and calculation unit, so that the number of the delay units in the operation can be directly associated with the time quantization result, and the method is particularly suitable for storage and calculation integration.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit storage and computing, and specifically relates to a time-to-digital converter circuit based on a standard delay unit in a storage and computing unit, and relates to a quantization method for in-memory computing in the time domain. Background Art

[0002] In existing storage and computing integration scenarios, time quantization technology has gradually become one of the core methods for achieving efficient computing. In such scenarios, the time length of the calculation result is often represented by a delay unit chain, that is, a specific calculation process is converted into a corresponding time value by accumulating delays. In this way, the total delay time of the delay unit chain can be regarded as the output of the calculation.

[0003] However, to accurately quantize the delay results into digital values ​​for further storage and analysis, a high-precision, low-error time-to-digital converter (TDC) is required. Many current TDCs are limited by the circuit structure and the structure of the delay unit, and it is often difficult to balance high resolution and power consumption, which can easily lead to insufficient quantization accuracy or high conversion power consumption, affecting the practicality of the delay unit chain in storage and computing integration. Summary of the invention

[0004] In view of the above-mentioned problems or shortcomings, and to solve the problem that the existing TDC is difficult to balance high resolution and power consumption limitation, the present invention provides a time-to-digital converter circuit based on a standard delay unit in a storage and calculation unit; a standard delay unit consistent with the calculation array is used for quantization in the fine counting module, and the rising edge and the falling edge are used to quantize the signal to reduce energy consumption; in addition, a carry-ahead mechanism is introduced to reduce errors that may occur in the quantization process.

[0005] A time-to-digital converter circuit based on a standard delay unit in a storage and calculation unit comprises a fine counting module, a coarse counting module, an advance carry unit, a positive and negative edge switching module and a decoder.

[0006] The fine counting module includes a main link, a feedback loop and a fine counting output module.

[0007] The main link consists of a two-to-one multiplexer and N standard delay units, where N ≥ 3.

[0008] The 0 input of the two-to-one multiplexer is grounded, the 1 input is connected to the output of the feedback loop, and the control end receives the quantized signal C; the output of the two-to-one multiplexer is the 0th bit signal r of the main link. <0> , and connected to the input of the first standard delay unit and a fine counting output unit.

[0009] N standard delay units are connected in series in sequence, and the output of each standard delay unit corresponds to the 1st to Nth bit signal r<1:N> of the main link; the 0th to Nth bit signal r<0:N> of the main link are connected to the input end of the transmission gate of N+1 fine counting output units in sequence; where r <n-1>The signal is also transmitted to the inverter in the feedback loop.

[0010] The feedback loop consists of an inverter, a standard delay unit and a transmission gate. <n-1>The signal is transmitted to the input of the standard delay unit of the feedback loop through the inverter, and the output of the standard delay unit is connected to the input of the transmission gate of the feedback loop; the control end of the transmission gate is connected to the CTR signal output by the carry-ahead unit, and the output end of the transmission gate is connected to the 1 input end of the two-to-one multiplexer.

[0011] The fine count output module includes N+1 fine count output units, each of which includes an output buffer and a transmission gate; the control end of each transmission gate is connected to the signal to be quantized C, the input end of the transmission gate is connected to the N+1-bit signal r<0:N> in the main link in a one-to-one correspondence, and the output end of the transmission gate is connected to the output buffer input end of the corresponding fine count output unit in a one-to-one correspondence; the output end of each output buffer is the low-weight codeword corresponding to each signal r<0:N>, which is recorded as signal LWB<0:N> and output to the decoder; LWB <n-1>The signal is also connected to the input terminal of the first-stage inverter of the positive and negative edge switching module.

[0012] The carry-ahead unit is composed of a two-input XOR gate, whose inputs are the highest bit LWB of the low-weight codeword <n>The second highest position LWB <n-1>The output is a CTR signal, which is connected to the control end of the transmission gate in the feedback loop and the control end of the transmission gate in the D flip-flop link of the coarse counting module.

[0013] The positive and negative edge switching module is composed of a first-stage inverter, a second-stage inverter and a two-to-one multiplexer; the positive and negative edge switching module converts the second highest signal LWB of the fine counting module into <n-1>Converted to a uniform rising edge signal. Signal LWB <n-1>After passing through the first stage inverter, it is connected to the 1 input of the two-to-one multiplexer and the input of the second stage inverter, and after passing through the first and second stages inverter, it is connected to the 0 input of the two-to-one multiplexer. The control end of the two-to-one multiplexer is connected to the MWB of the high-weight codeword. <0> Signal, the output of the two-to-one multiplexer is the positive and negative edge switching signal SEL.

[0014] The coarse counting module includes a D flip-flop chain and a reset unit for recording the signal LWB <n>The number of flips.

[0015] The D flip-flop chain includes an M-bit D flip-flop and a transmission gate, M≥2.

[0016] The D input of the first D flip-flop is connected to its own Q non-output terminal, its clock input is connected to the SEL signal output by the positive and negative edge switching module, and the Q output is connected to the input of the transmission gate; the control end of the transmission gate is connected to the CTR signal output by the advance carry unit, and the output is the lowest bit high-weight codeword MWB <0> .

[0017] For the M-1-bit D flip-flop in the next stage: signal MWB <0> Connected to the clock input of the second (next) D flip-flop, the D input of the second D flip-flop is connected to its own Q non-output terminal, and the Q output of the second D flip-flop is the corresponding second high-weight codeword MWB <1> ; The subsequent M-2-bit D flip-flops are connected in the same structural order as the 2nd-bit D flip-flop, that is, the Q non-output terminal of the i-th D flip-flop is connected to the D input terminal of the i-th D flip-flop, and the Q output terminal of the i-th D flip-flop outputs the i-1-th high-weight codeword MWB <i-1>The clock input of the i-th D flip-flop is connected to the i-2-th high-weight codeword MWB <i-2>, M≥i≥2; the output of the D flip-flop chain constitutes a high-weight codeword, MWB<0:M-1>.

[0018] The reset unit is composed of a standard delay unit and a two-to-one multiplexer; the input of the standard delay unit is the signal C to be quantized, and the output is connected to the control end of the two-to-one multiplexer; the 0 input end of the two-to-one multiplexer is connected to the power supply end of the circuit, the 1 input end is connected to the ground end of the circuit, and the output end of the two-to-one multiplexer is connected to the reset end of all D flip-flops; when the output of the two-to-one multiplexer is high, the outputs of all D flip-flops are reset; when the output of the two-to-one multiplexer is not high, the outputs of all D flip-flops remain unchanged.

[0019] The decoder inputs a low-weight codeword LWB<0:N> and a high-weight codeword MWB<0:M-1>, and outputs a quantization result A after decoding.

[0020] The above-mentioned time-to-digital converter circuit based on the standard delay unit in the storage and calculation unit has the following working process:

[0021] 1). When the signal to be quantized C is low: the 0 input of the two-to-one multiplexer in the main link of the fine counting module is selected and output, ensuring that the input and output of all standard delay units in the main link are low at this time; and in the feedback loop, due to the input r of the inverter <n-1>The signal is low, so the output of the inverter is high, and is connected to the 1 input of the two-to-one multiplexer through the standard delay unit and the transmission gate in the feedback loop; at this time, due to LWB <n-1>With LWB <n>The signals are at the same low level, the carry-ahead unit output is high, so the transmission gate on the feedback loop is in the on state, and at this time the control ends of all transmission gates of the fine counting unit output module are low signals, so the transmission gate of the fine counting module is in the off state.

[0022] 2). When the high level time T of the signal C to be quantified is less than the total delay of each standard delay unit in the main link, that is, T<N×Δt, Δt is the standard delay, the rising edge signal will propagate in the main link. In this case, the coarse counting module does not participate in the quantization process. The specific workflow is as follows:

[0023] When the signal to be quantized C is pulled high, the main link and the fine count output module of the fine count module are activated. At this time, the control end of the two-to-one multiplexer in the main link is also pulled high, and the 0 input end is switched to the 1 input end, and its output signal r <0> The signal changes from low to high. In the main link, each standard delay unit converts the signal level from low to high step by step, and the output of each delay unit is connected to the transmission gate input of the fine counting output module in turn.

[0024] When the signal to be quantized C is pulled low, the transmission gate in the fine counting unit output module is closed. However, the output of the transmission gate will record the level state of each delay unit on the main link and output the state to the buffer. The buffer will convert the possible intermediate level into a high-low signal, that is, the low-weight codeword LWB<0:N>. At this time, the output of the low-weight codeword is "11...10...00", j is the number of bits of the low-weight codeword with the last bit output as 1, N≥j≥0, then the low-weight quantization result n=j.

[0025] When T<N×Δt, for the coarse counting module, the D flip-flop chain is not flipped, and the high-weight codeword MWB is all 0 at this time, so the high-weight quantization result m=0; for the quantization result A, A=n+m×(N+1), because m is 0, the quantization result is A=n.

[0026] 3). When the time of the quantized signal is greater than the total delay of each standard delay unit in the main link, that is, T>N×Δt, the rising and falling edge signals are alternately propagated in the main link, and the coarse counting module works.

[0027] When the quantized signal C is pulled high and the quantization time is less than Δt, the working mechanism of the fine counting module is similar to the case where the duration of the quantized signal is less than the total delay of each standard delay unit of the main link, but the difference is that when the high level is successively propagated to LWB <n-1>and LWB <n>When , the advance carry unit and the coarse counting module will be triggered. The specific process is as follows:

[0028] When the output of the N-1th standard delay unit on the main link is pulled high, that is, LWB <n-1>is pulled high while LWB <n>When it is still low, two key actions will occur. First, the inverter on the feedback loop of the fine counting module will capture r <n-1>The rising edge of LWB is converted into a falling edge signal, and then the falling edge signal is transmitted to the input of the transmission gate on the feedback loop through a standard delay unit. <n-1>The signal will also be transmitted to the input of the first stage inverter of the positive and negative edge switching module. At this moment, due to LWB <n-1>and LWB <n>The signal state is different, the exclusive-OR logic output in the carry-ahead unit is 0, that is, CTR is 0. At this time, the CTR signal controls the states of two transmission gates: one is located in the feedback loop and connected to the control end of the transmission gate; the other is connected to the control end of the transmission gate of the coarse counting module. When CTR = 0, the transmission gate on the feedback loop is in a closed state, so the falling edge signal output by the inverter in the feedback loop cannot be transmitted to the two-to-one multiplexer, and naturally cannot enter the main link for further propagation. In addition, although the output Q of the first D flip-flop of the coarse counting module changes due to the flip of the SEL signal (the output changes from low level 0 to high level 1), since the signal CTR that controls the transmission gate of the coarse counting module is still 0, the high-weight codeword MWB in the D flip-flop link <0> The output remains at 0.

[0029] As the rising edge signal in the main link continues to propagate backward, when LWB <n-1>and LWB <n>When both are pulled high, the two inputs in the carry-ahead unit are high, causing the CTR signal to rise to a high level. At this time, the transmission gate on the feedback loop is turned on, and the low level is transmitted to the beginning of the main link, that is, the low level is propagated in the main link. At the same time, the transmission gate in the coarse counting module is also turned on, and the lowest bit MWB of the high-weight codeword <0> Is pulled high to 1. The high-level signal in the main link completes one propagation, that is, LWB <n>The coarse counting module will count once the signal is flipped; after quantization, the output MWB<0:M-1> of the coarse counting module records LWB <n>The number of signal flips represents the high-weight quantization result m.

[0030] It should be noted that when the propagation signal in the main link changes to a falling edge, that is, MWB <0> When it is pulled high to 1, the number of bits of the low-weight quantization result n changes, that is, from "11...10...00" to "00...01...11", and at this time the number of bits of the low-weight codeword with the last bit output as 0 is k (propagated with the rising edge), that is, MWB <0> When j is 0, N≥k≥0, and the low-weight quantization result is n=k.

[0031] The quantization result A is obtained by the formula A=n+m×(N+1).

[0032] The present invention has the following characteristics:

[0033] 1. In the quantization process of the fine counting module, the present invention adopts the rising and falling edge alternating quantization method, so that the power consumption on the main link is reduced; in the quantization process, the energy consumption caused by the charging and discharging of the standard delay unit occupies the main part of the entire quantization process. Compared with the traditional method of using the rising edge for quantization, it can reduce the energy consumption by up to half.

[0034] This is because the traditional rising edge quantization method (single edge method) needs to perform a reset operation after each charging of the standard delay unit to pull down the signal that has been pulled up. In this process, energy is wasted and the pulling down process may consume time. The rising and falling edge alternating quantization method (dual edge method) of the present invention utilizes the falling edge and combines the reset operation with the quantization process, thereby reducing power consumption.

[0035] Specifically: assuming that a single standard delay unit is charged once, that is, the output is charged from 0 to 1, the energy required is E, and the high level time of the signal C to be quantized is T=p×Δt, p>N. The traditional method requires the standard delay unit to be charged p times, and the energy consumed is p*E; while the rising and falling edge alternating quantization method of the present invention requires the standard delay unit to be charged p-×[p / 2], where [] represents rounding, and the energy consumed is E×(p-×[p / 2]). When p is an even number, the energy consumed is reduced by half compared with the traditional single edge method.

[0036] 2. The carry-ahead module adopted in the present invention can reduce the error generated during quantization in the process of high-speed quantization: because in the traditional quantization process, the time consumed by the necessary signal operation in the circuit will affect the accuracy of quantization; while the present invention runs the signal operation in parallel with the quantization process, and uses the discrimination module (transmission gate) to control the quantization process through the operation results, so that the main error time is accumulated in the time of the discrimination module, and thus the delay error is reduced.

[0037] 3. The main link and coarse counting module adopted in the present invention are very easy to expand the number of quantized bits, ensuring the reusability and scalability of the design.

[0038] In summary, the present invention provides a TDC based on a standard delay unit chain, which constructs a TDC that can accurately quantify the length of time through a series of preset standard delay units. Since the delay unit chain used in the present invention is composed of standard delay units in the storage and calculation unit, the TDC can directly associate the number of delay units in the calculation with the time quantization result, thereby quickly and accurately converting time information into a storable numerical result. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is an application scenario of TDC in the storage and computing module of the embodiment;

[0040] Figure 2 is a schematic block diagram of the structure of the TDC of the present invention;

[0041] Figure 3 It is a structural schematic diagram of a fine counting module, a positive and negative edge switching module and an advance carry unit in a TDC of the present invention;

[0042] Figure 4 It is a schematic diagram of the structure of the rough counting module in the TDC of the present invention;

[0043] Figure 5 is a timing diagram of a carry-ahead unit of the present invention;

[0044] Figure 6 is a waveform diagram of a low-weight codeword during a quantization process of an embodiment;

[0045] Figure 7 It is a step diagram of the quantitative results of the embodiment. DETAILED DESCRIPTION

[0046] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0047] This embodiment takes the application scenario of the TDC circuit in the storage and computing module as an example. Figure 1 is the corresponding block diagram; in the storage and calculation module, the standard delay unit is used to perform delay and logic operations to obtain the signal C to be quantized, and its high-level time T represents the total delay of the standard delay units turned on on the delay link. Therefore, from T=A×Δt, it can be seen that the number of standard delay units turned on on the delay link is A, and this result represents the calculation result of the storage and calculation array.

[0048] The time-to-digital converter circuit based on the standard delay unit in the storage and calculation unit provided by the present invention is as follows: Figure 2 As shown, it includes a fine counting module, a coarse counting module, an advance carry unit, a positive and negative edge switching unit and a decoder. Figure 3 It is a structural diagram of a fine counting module, a positive and negative edge switching module and an advance carry unit; Figure 4 It is a structural diagram of the rough counting module.

[0049] Specifically, it is divided into: a main link 1, a fine counting module consisting of a fine counting output module 2 and a feedback loop 3; a carry-ahead unit 4 consisting of a two-input XNOR gate; a positive and negative edge switching module 5 consisting of a first-stage inverter, a second-stage inverter and a two-to-one multiplexer; a reset unit 6 consisting of a standard delay unit and a two-to-one multiplexer; and a D flip-flop link 7 consisting of an M-bit D flip-flop and a transmission gate.

[0050] The decoder input is a low-weight codeword LWB<0:N> and a high-weight codeword MWB<0:M-1>, and outputs a quantized result A after decoding, which is also the calculation result of the storage and calculation array, that is, the calculation result of the storage and calculation array is quantized and output through the present invention.

[0051] This embodiment is based on a time-to-digital converter circuit of a standard delay unit in a storage unit, and its specific working process is described as follows:

[0052] 1. When the signal to be quantized C is low: the 0 input of the two-to-one multiplexer in the main link 1 of the fine counting module is selected and output, ensuring that the input and output of all standard delay units in the main link 1 are low at this time; and in the feedback loop 3, due to the input r of the inverter <n-1>The signal is low, so the output of the inverter is high, and is connected to the 1 input of the two-to-one multiplexer through the standard delay unit and the transmission gate on the feedback loop 3; at this time, due to LWB <n-1>With LWB <n>The signals are at the same low level, the carry-ahead unit output is high, so the transmission gate on the feedback loop 3 is in the on state, and at this time the control ends of all transmission gates of the fine counting unit output module 2 are low signals, so the transmission gate of the fine counting module 2 is in the off state.

[0053] 2. When the high level time T of the signal to be quantized C is less than the total delay of each standard delay unit in the main link 1, that is, T<N×Δt, the rising edge signal is propagated in the main link 1. In this case, the coarse counting module does not participate in the quantization process. The details are as follows:

[0054] When the signal to be quantized C is pulled high, the main link 1 of the fine counting module and the fine counting output module 2 are activated. At this time, the control end of the two-to-one multiplexer in the main link 1 is also pulled high, and the 0 input end is switched to the 1 input end, and its output is connected to the input signal r of the first standard delay unit of the main link 1. <0> The signal changes from low to high. In the main link 1, each standard delay unit converts the signal level from low to high step by step, and the output of each delay unit is connected to the transmission gate input of the fine count output module 2 in turn.

[0055] When the signal to be quantized C is pulled low, the transmission gate in the fine count output module 2 is closed. However, the output of the transmission gate will record the level state of each delay unit on the main link and output the state to the buffer. The buffer will convert the possible intermediate level into a high-low signal, that is, the low-weight codeword LWB<0:N>. At this time, the output of the low-weight codeword is "11...10...00", and the number of bits of the low-weight codeword with the last bit output as 1 is j, N≥j≥0, then the low-weight quantization result n=j.

[0056] When T<N×Δt, for the coarse counting module, the D flip-flop link 7 is not flipped, and the high-weight codeword MWB is all 0 at this time, so the high-weight quantization result m=0; for the quantization result A, A=n+m×(N+1), because m is 0, the quantization result is A=n.

[0057] 3. When the time of the quantized signal is greater than the total delay of each standard delay unit in the main link 1, that is, T>N×Δt, the rising and falling edge signals are alternately propagated in the main link 1, and the coarse counting module works.

[0058] When the quantized signal C is pulled high and the quantization time is less than Δt, the working mechanism of the fine counting module is similar to the case where the duration of the quantized signal is less than the total delay of each standard delay unit of the main link, but the difference is that when the high level is successively propagated to LWB <n-1>and LWB <n>When , the advance carry unit 4 and the rough counting module will be triggered to work. The details are as follows:

[0059] When the output of the N-1th standard delay unit on the main link 1 is pulled high, that is, LWB <n-1>is pulled high while LWB <n>When it is still low, two key operations will occur. First, the inverter on the fine counting module feedback loop 3 will capture r <n-1>The rising edge of LWB is converted into a falling edge signal, and then the falling edge signal is transmitted to the transmission gate input terminal on the feedback loop 3 through a standard delay unit. <n-1>The signal will also be transmitted to the input of the first stage inverter of the positive and negative edge switching module. At this moment, due to LWB <n-1>and LWB <n>The signal state is different, the exclusive-OR logic output in the carry-ahead unit 4 is 0, that is, CTR=0. At this time, the CTR signal controls the states of two transmission gates: one is located on the feedback loop 3 and connected to the control end of the transmission gate; the other is connected to the control end of the transmission gate in the D flip-flop link 7. When CTR=0, the transmission gate on the feedback loop 3 is in a closed state, so the falling edge signal output by the inverter in the feedback loop 3 cannot be transmitted to the two-to-one multiplexer, and naturally cannot enter the main link 1 for propagation. In addition, although the output Q of the first D flip-flop of the coarse counting module changes due to the flipping of the SEL signal (the output changes from low level 0 to high level 1), since the signal CTR that controls the transmission gate of the coarse counting module is still 0, the high-weight codeword MWB <0> The output remains at 0.

[0060] As the rising edge signal in the main link 1 continues to propagate backward, when LWB <n-1>and LWB <n>When both are pulled high, the two inputs in the carry-ahead unit 5 are high, causing the CTR signal to rise to a high level. At this time, the transmission gate on the feedback loop 3 is turned on, and the low level is transmitted to the beginning of the main link, that is, the low level is propagated in the main link 1. At the same time, the transmission gate in the coarse counting module is also turned on, and the lowest bit MWB of the high-weight codeword <0> Is pulled high to 1. The high-level signal in the main link completes one propagation, that is, LWB <n>The coarse counting module will count once the signal is flipped; after quantization, the output MWB<0:M-1> of the coarse counting module records LWB <n>The number of signal flips represents the high-weight quantization result m.

[0061] It should be noted that when the propagation signal in the main link changes to a falling edge, that is, MWB <0> When it is pulled high to 1, the number of bits of the low-weight quantization result n changes, that is, from "11...10...00" to "00...01...11", and the number of bits of the low-weight codeword with the last bit output as 0 is k; it is propagated along the rising edge, that is, MWB <0> When j is 0, N≥k≥0, and the low-weight quantization result is n=k.

[0062] The quantization result A is obtained by the formula A=n+m×(N+1).

[0063] In the present invention, the design purpose of the carry-ahead unit is to ensure that when the rising or falling edge signal transmitted in the main link is switched, that is, LWB <n>Signal and LWB <0> The delay between signals is still the standard delay Δt. <n-1>When the flip is performed, the falling edge signal is obtained through the inverter and standard delay unit of the feedback loop and stored at the input end of the transmission gate. However, because the control end of the transmission gate is still not turned on, the output end signal does not change; after the transmission of the last level of the standard delay unit of the main link is completed, that is, LWB <n>After the signal is pulled high, the advance carry signal CTR is pulled high, the transmission gate opens, and the falling edge signal is quickly transmitted back to the starting point of the main link, thus reducing the delay caused by the inverter and the standard delay unit in the feedback loop; at the same time, in the feedback loop, the existence of the standard delay unit ensures that when the signal in the feedback loop drives the first standard delay unit on the main link, it is the same as the driving situation of other standard delay units on the main link, rather than directly driving the first standard delay unit on the main link by the inverter on the feedback loop, thereby ensuring the accuracy of the first standard delay.

[0064] In the coarse counting module, the carry-ahead method reduces the delay caused by the flip of the first D flip-flop, avoiding the delay affecting the accuracy of the subsequent decoder. That is, by activating the D flip-flop of the coarse counting module in advance to flip it, and only when the carry-ahead signal is valid, the output of the D flip-flop is passed to the high-weight codeword, thereby effectively reducing the error caused by the flip of the D flip-flop.

[0065] The positive and negative edge switching module plays a key role in the operation of the coarse counting module. Usually, the D flip-flop of the coarse counting module is triggered by the rising edge jump of the clock input. However, due to the alternating rising and falling edges in the main link, LWB <n>The change is that the rising and falling edges appear alternately, and the clock input of the D flip-flop in the coarse counting module cannot count correctly with the jump of the falling edge. Therefore, the positive and negative switching modules are used to capture LWB at the same time. <n>The specific working conditions are as follows: First, the LWB of the main link <n-1>The rising and falling edges of the signal will be transmitted to the first-stage inverter of the positive and negative edge switching module; secondly, the control end of the two-to-one multiplexer of the positive and negative edge switching module will be connected according to the MWB <0> The high or low level of the signal switches the 0 or 1 input terminal, and these two input terminals are connected to the first-stage inverter and the second-stage inverter respectively. The output of these two inverters always has a rising edge signal, and the rising edge signal will change with the MWB <0> The signal changes and appears at the 0 or 1 input. <0> To control the output of the rising edge signal.

[0066] Figure 5 It is a timing diagram of the carry-ahead unit of the present invention; it explains the role of the carry-ahead unit in reducing quantization errors. In the traditional quantization process, the time consumed by the necessary signal operations in the circuit will affect the accuracy of quantization; while the present invention runs the signal operation in parallel with the quantization process, and uses a discrimination module (transmission gate) to control the quantization process through the operation results, so that the main error time is accumulated in the time of the discrimination module, and thus the delay error is reduced.

[0067] Figure 6 1 is a waveform diagram of a low-weight codeword in the quantization process of the embodiment; 2 is a simulation waveform diagram of a low-weight codeword when N=6, that is, there are 6 standard delay units in the main link of the fine counting module, and T>6×Δt.

[0068] Figure 7 3 is a step diagram of the quantization result of the embodiment, which is a step diagram of the quantization result and the quantization time obtained by simulation when N=6, M=2 and Δt=52ps.

[0069] It can be seen from the above embodiments that the present invention adopts the rising and falling edge alternating quantization method in the quantization process of the fine counting module, so that the power consumption on the main link is reduced; in the quantization process, the energy consumption caused by the charging and discharging of the standard delay unit occupies the main part of the entire quantization process. Compared with the traditional method of using the rising edge for quantization, it can reduce the energy consumption by up to half. A carry-ahead module that parallelizes the signal operation and the quantization process is adopted, and a transmission gate is used to control the quantization process through the operation result, so as to reduce the quantization error in the high-speed quantization process; and the overall structure ensures reusability and scalability. Since the delay unit chain used in the present invention is composed of the standard delay units in the storage and computing units, it is possible to directly associate the number of delay units in the operation with the time quantization result, which is particularly suitable for storage and computing integration. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A time-to-digital converter circuit based on a standard delay unit in a storage unit, characterized in that: It includes a fine counting module, a coarse counting module, a carry-ahead unit, a positive and negative edge switching module and a decoder; The fine counting module includes a main link, a feedback loop and a fine counting output module; The main link consists of a two-to-one multiplexer and N standard delay units, N ≥ 3; The 0 input of the two-to-one multiplexer is grounded, the 1 input is connected to the output of the feedback loop, and the control end receives the quantized signal C; the output of the two-to-one multiplexer is the 0th bit signal r of the main link. <0> , and connected to the input of the first standard delay unit and a fine counting output unit; N standard delay units are connected in series in sequence, and the output of each standard delay unit corresponds to the 1st to Nth bit signal r<1:N> of the main link; the 0th to Nth bit signal r<0:N> of the main link are connected to the input end of the transmission gate of N+1 fine counting output units in sequence; where r <n-1> The signal is also transmitted to the inverter in the feedback loop; The feedback loop consists of an inverter, a standard delay unit and a transmission gate; <n-1> The signal is transmitted to the input end of the standard delay unit of the feedback loop through the inverter, and the output of the standard delay unit is connected to the input end of the transmission gate of the feedback loop; the control end of the transmission gate is connected to the CTR signal output by the carry-ahead unit, and the output end of the transmission gate is connected to the 1 input end of the two-to-one multiplexer; The fine count output module includes N+1 fine count output units, each of which includes an output buffer and a transmission gate; the control end of each transmission gate is connected to the signal to be quantized C, the input end of the transmission gate is connected to the N+1-bit signal r<0:N> in the main link in a one-to-one correspondence, and the output end of the transmission gate is connected to the output buffer input end of the corresponding fine count output unit in a one-to-one correspondence; the output end of each output buffer is the low-weight codeword corresponding to each signal r<0:N>, which is recorded as signal LWB<0:N> and output to the decoder; LWB <n-1> The signal is also connected to the input terminal of the first stage inverter of the positive and negative edge switching module; The carry-ahead unit is composed of a two-input XOR gate; its inputs are the highest bit LWB of the low-weight codeword <n>The second highest position LWB <n-1> , the output is a CTR signal connected to the control end of the transmission gate in the feedback loop and the control end of the transmission gate in the D flip-flop chain of the coarse counting module; < / n> The positive and negative edge switching module is composed of a first-stage inverter, a second-stage inverter and a two-to-one multiplexer; the positive and negative edge switching module converts the second highest signal LWB of the fine counting module into <n-1>Converted to a unified rising edge signal; signal LWB <n-1> After passing through the first stage inverter, it is connected to the 1 input terminal of the two-to-one multiplexer and the input terminal of the second stage inverter, and after passing through the first and second stages inverter, it is connected to the 0 input terminal of the two-to-one multiplexer; the control terminal of the two-to-one multiplexer is connected to the MWB of the high-weight codeword <0> Signal, the output of the two-to-one multiplexer is the positive and negative edge switching signal SEL; The coarse counting module includes a D flip-flop chain and a reset unit for recording the signal LWB <n> The number of flips;< / n> The D flip-flop chain includes an M-bit D flip-flop and a transmission gate, M ≥ 2; The D input of the first D flip-flop is connected to its own Q non-output terminal, its clock input terminal is connected to the SEL signal, and the Q output terminal is connected to the input terminal of the transmission gate; the control terminal of the transmission gate is connected to the CTR signal, and the output is the lowest bit high-weight codeword MWB <0> ; For the M-1-bit D flip-flop in the next stage: signal MWB <0> Connected to the clock input of the second D flip-flop, the D input of the second D flip-flop is connected to its own Q non-output terminal, and the Q output of the second D flip-flop is the corresponding second high-weight codeword MWB <1> ; The subsequent M-2-bit D flip-flops are connected in the same structural order as the 2nd-bit D flip-flop, that is, the Q non-output terminal of the i-th D flip-flop is connected to the D input terminal of the i-th D flip-flop, and the Q output terminal of the i-th D flip-flop outputs the i-1-th high-weight codeword MWB <i-1>The clock input of the i-th D flip-flop is connected to the i-2-th high-weight codeword MWB <i-2> , M≥i≥2; the output of the D flip-flop chain constitutes a high-weight codeword, MWB<0:M-1>; The reset unit is composed of a standard delay unit and a two-to-one multiplexer; the input of the standard delay unit is the signal C to be quantized, and the output is connected to the control end of the two-to-one multiplexer; the 0 input end of the two-to-one multiplexer is connected to the power supply end of the circuit, the 1 input end is connected to the ground end of the circuit, and the output end of the two-to-one multiplexer is connected to the reset end of all D flip-flops; when the output of the two-to-one multiplexer is high, the outputs of all D flip-flops are reset; when the output of the two-to-one multiplexer is not high, the outputs of all D flip-flops remain unchanged; The decoder inputs a low-weight codeword LWB<0:N> and a high-weight codeword MWB<0:M-1>, and outputs a quantization result A after decoding.

2. The time-to-digital converter circuit based on the standard delay unit in the storage and calculation unit as claimed in claim 1, characterized in that: The specific workflow is as follows: 1). When the signal to be quantized C is low: the 0 input of the two-to-one multiplexer in the main link of the fine counting module is selected and output, ensuring that the input and output of all standard delay units in the main link are low at this time; and in the feedback loop, due to the input r of the inverter <n-1>The signal is low, so the output of the inverter is high, and is connected to the 1 input of the two-to-one multiplexer through the standard delay unit and the transmission gate in the feedback loop; at this time, due to LWB <n-1>With LWB <n> The signals are at the same low level, the carry-ahead unit output is high, so the transmission gate on the feedback loop is in the on state, and at this time the control ends of all transmission gates of the fine counting unit output module are low signals, so the transmission gate of the fine counting module is in the off state;< / n> 2). When the high level time T of the signal C to be quantized is less than the total delay of each standard delay unit in the main link, that is, T<N×Δt, Δt is the standard delay, the rising edge signal is propagated in the main link. In this case, the coarse counting module does not participate in the quantization process; 3) When the time of the quantized signal is greater than the total delay of each standard delay unit in the main link, that is, T>N×Δt, the rising and falling edge signals are alternately propagated in the main link, and the coarse counting module works; When the quantized signal C is pulled high and the quantization time is less than Δt, when the high level is successively propagated to LWB <n-1>and LWB <n> When , the advance carry unit and the coarse counting module are triggered.< / n> 3. The time-to-digital converter circuit based on the standard delay unit in the storage and calculation unit as claimed in claim 2, characterized in that: The coarse counting module does not participate in the quantization process specifically: When the signal to be quantized C is pulled high, the main link and the fine count output module of the fine count module are activated; at this time, the control end of the two-to-one multiplexer in the main link is also pulled high, and the 0 input end is switched to the 1 input end, and its output signal r <0> The signal changes from low to high; in the main link, each standard delay unit converts the signal level from low to high step by step, and the output of each delay unit is connected to the transmission gate input of the fine counting output module in turn; When the signal to be quantized C is pulled low, the transmission gate in the fine count output module is closed; however, the output end of the transmission gate will record the level state of each delay unit on the main link and output the state to the buffer. The buffer will convert the possible intermediate level into a high-low signal, that is, the low-weight codeword LWB<0:N>. At this time, the low-weight quantization result n=j, j is the number of bits of the low-weight codeword whose last bit is output as 1, N≥j≥0; When T<N×Δt, for the coarse counting module, the D flip-flop chain is not flipped, and the high-weight codeword MWB is all 0 at this time, so the high-weight quantization result m=0; For the quantization result A, A=n+m×(N+1). Since m is 0, the quantization result is A=n.

4. The time-to-digital converter circuit based on the standard delay unit in the storage and calculation unit as claimed in claim 2, characterized in that: The specific working process of the carry-ahead unit and the coarse counting unit is as follows: LWB <n-1>is pulled high while LWB <n> When it is still low:< / n> First, the inverter in the feedback loop of the fine counting module will capture r <n-1> The rising edge of the feedback loop is converted into a falling edge signal, and then the falling edge signal is transmitted to the input end of the transmission gate on the feedback loop through a standard delay unit; Second, LWB <n-1>The signal will also be transmitted to the input of the first stage inverter of the positive and negative edge switching module. At this moment, due to LWB <n-1>and LWB <n> The signal states are different. The exclusive-OR logic output in the carry-ahead unit is 0, that is, CTR = 0; CTR = 0, the transmission gate on the feedback loop is in the closed state, so the falling edge signal output by the inverter in the feedback loop cannot be transmitted to the two-to-one multiplexer and cannot enter the main link for further propagation; CTR = 0, the high-weight codeword MWB in the D flip-flop link <0> The output remains 0;< / n> As the rising edge signal in the main link continues to propagate backward, when LWB <n-1>and LWB <n>When both are pulled high, the two inputs in the carry-ahead unit are high, causing the CTR signal to rise to a high level. At this time, the transmission gate on the feedback loop is turned on, and the low level is transmitted to the beginning of the main link, that is, the low level is propagated in the main link; at the same time, the transmission gate in the coarse counting module is also turned on, and the lowest bit MWB of the high-weight codeword <0> Is pulled high to 1; the high-level signal in the main link completes one propagation, that is, LWB <n>The coarse counting module will count once the signal is flipped; after quantization, the output MWB<0:M-1> of the coarse counting module records LWB <n> The number of signal flips, which represents the high-weight quantization result m;< / n> < / n> < / n> When the propagation signal in the main link changes to a falling edge, that is, MWB <0> When it is pulled high to 1, the number of bits of the low-weight quantization result n changes, and at this time the number of bits of the low-weight codeword with the last bit output as 0 is k, that is, MWB <0> When j is 0, N≥k≥0, then the low-weight quantization result is n=k; The quantization result A is obtained by the formula A=n+m×(N+1).

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