Printed circuit board and manufacturing method thereof

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a first substrate including a first wiring layer; a second substrate disposed on the first substrate and including a second wiring layer; the metal layer is arranged between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate. Each of the first substrate and the second substrate includes an organic material, and the bonding layer includes an inorganic material.

Description

[0001] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0157812 filed on November 15, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0136403 filed on October 13, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board (eg, a package substrate) and a method for manufacturing the same. Background Art

[0003] Due to the improved performance of semiconductor chips, the demand for high-density packaging substrates has increased. Therefore, it may be necessary to develop packaging substrates that can reduce bump pitch, can be multi-layered and have a large area, and can improve signal and power characteristics. In particular, the implementation of fine circuits is important to respond to the increased number of input terminals / output terminals. In the case of developing fine circuits of substrates, single chip packages (SCPs) and single / multi-chip packages (MCPs) and 2.5D silicon interposers can be replaced. Summary of the invention

[0004] An aspect of the present disclosure is to provide a multilayer printed circuit board including a fine circuit.

[0005] An aspect of the present disclosure is to provide a printed circuit board that can reduce manufacturing costs through high yield and process efficiency.

[0006] An aspect of the present disclosure is to manufacture a multilayer printed circuit board by manufacturing a first substrate including a fine circuit and a second substrate, and combining the first substrate and the second substrate using hybrid metal bonding.

[0007] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a first wiring layer; a second substrate disposed on the first substrate and including a second wiring layer; a metal layer disposed between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate. Each of the first substrate and the second substrate includes an organic material, and the bonding layer includes an inorganic material.

[0008] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a first wiring layer; a second substrate disposed on the first substrate and including a second wiring layer; a metal layer disposed between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate. The line width of a wiring line having a minimum line width among the wiring lines of the second wiring layer is smaller than the line width of a wiring line having a minimum line width among the wiring lines of the first wiring layer.

[0009] For example, according to an example embodiment, a method for manufacturing a printed circuit board includes: preparing a first substrate including a plurality of first wiring layers and having a first metal layer formed on the outermost side; forming a first inorganic insulating film covering at least a portion of the first metal layer on the outermost side of the first substrate; preparing a second substrate including a plurality of second wiring layers and having a second metal layer formed on the outermost side; forming a second inorganic insulating film covering at least a portion of the second metal layer on the outermost side of the second substrate; and combining the first substrate and the second substrate with each other so that the first inorganic insulating film and the second inorganic insulating film are combined with each other, and so that the first metal layer and the second metal layer are combined with each other, wherein each of the first substrate and the second substrate includes an organic material.

[0010] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers; a second substrate disposed on the first substrate and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers; a metal layer disposed between the first substrate and the second substrate to connect the first via layer closest to the second substrate among the plurality of first via layers and the second via layer closest to the first substrate among the plurality of second via layers to each other; and an insulating bonding layer disposed between the first substrate and the second substrate to connect the first substrate and the second substrate to each other. The first via layer closest to the second substrate among the plurality of first via layers and the second via layer closest to the first substrate among the plurality of second via layers taper in opposite directions.

[0011] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a plurality of first insulating layers, a plurality of first wiring layers respectively arranged on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers; a second substrate disposed on the first substrate and including a plurality of second insulating layers, a plurality of second wiring layers respectively arranged on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers; a metal layer disposed between the first substrate and the second substrate to connect the first via layer closest to the second substrate among the plurality of first via layers and the second via layer closest to the first substrate among the plurality of second via layers to each other; and an insulating bonding layer disposed between the first substrate and the second substrate to connect the first substrate and the second substrate to each other. The outermost second via layer among the plurality of second via layers connected to the outermost second wiring layer among the plurality of second wiring layers has a tapered shape so that the width of the outermost second via layer increases in a direction toward the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram illustrating an example of an electronic device system; Figure 2 is a perspective view showing an example of an electronic device; Figure 3 is a cross-sectional view showing an example of a printed circuit board; Figure 4 It is shown Figure 3 A cross-sectional view of a modified example of a printed circuit board in FIG. FIG. 5A to FIG. 5D is shown with Figure 3 An enlarged cross-sectional view of various examples of mixed metal bonding corresponding to region A; Fig. 6A and Figure 6B are enlarged cross-sectional views showing various examples of interfaces in intermetallic bonding; Figure 7 is a diagram illustrating an example of a method of manufacturing a printed circuit board; FIG. 8A to FIG. 8C is a cross-sectional view showing a process of an example of a method of manufacturing a first substrate portion; 9A to 9C is a cross-sectional view showing a process of an example of a method of manufacturing the second substrate portion; Fig. 10A and Fig. 10Bis a cross-sectional view showing an example of combining a first substrate portion and a second substrate portion; Fig.11 is a cross-sectional view showing mixed metal bonding; Fig.12 is a graph illustrating temperature variation of mixed metal bonding according to example embodiments; Fig.13 is a cross-sectional view showing another example of mixed metal bonding; Fig.14 is a cross-sectional view showing another example of mixed metal bonding; Fig.15 is a cross-sectional view showing another example of a printed circuit board; Fig.16 It is shown Fig.15 A cross-sectional view of a modified example of a printed circuit board in FIG. Fig.17 is a cross-sectional view showing another example of a printed circuit board; Fig.18 It is shown Fig.17 A cross-sectional view of a modified example of a printed circuit board in FIG. Fig.19 is a cross-sectional view showing another example of a printed circuit board; and Fig. 20 It is shown Fig.19 sectional view of a modified example of the printed circuit board in FIG. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0014] Electronic Devices Figure 1 is a block diagram illustrating an example of an electronic device system.

[0015] Reference Figure 1 , the electronic device 1000 may contain a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to the mainboard 1010. These components may also be connected to other electronic components described below through various signal lines 1090.

[0016] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0017] The network-related components 1030 may include components that are compatible with or communicate using various protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G), Fourth Generation Mobile Communication Technology (4G) and Fifth Generation Mobile Communication Technology (5G) protocols, and any other wireless and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include various other wireless standards or protocols or other wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 together with each other.

[0018] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, the other electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. Depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0021] Figure 2 is a perspective view showing an example of an electronic device.

[0022] Reference Figure 2 , the electronic device may be a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the component 1120 may be a chip-related component, for example, a component package 1121, but example embodiments thereof are not limited thereto. The component package 1121 may have the form of a printed circuit board with electronic components (including active components and / or passive components) mounted on the surface. Alternatively, the component package 1121 may be constructed in the form of a printed circuit board with active components and / or passive components buried therein. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0023] Printed Circuit Board Figure 3 is a cross-sectional view showing an example of a printed circuit board.

[0024] Reference Figure 3According to the example, a printed circuit board 500A may include: a first substrate 100, including a plurality of first wiring layers 121, 122, 123, 124, 125 and 126, and including a first metal layer M1 disposed on an upper side thereof; a second substrate 200, disposed on the first substrate 100, and including a plurality of second wiring layers 221, 222, 223, 224, 225 and 226 and a second metal layer M2 disposed on a lower side thereof; and an insulating layer 300 (or referred to as a bonding layer 300), disposed between the first substrate 100 and the second substrate 200, and burying at least a portion of each of the first metal layer M1 and the second metal layer M2. If necessary, the printed circuit board 500A may further include a first anti-etching layer 150 and a second anti-etching layer 250, the first anti-etching layer 150 being disposed on the lower side of the first substrate 100 and having a plurality of first openings h1 exposing at least a portion of the 1-1 wiring layer 121, and the second anti-etching layer 250 being disposed on the second substrate 200 and having a plurality of second openings h2 exposing at least a portion of the 2-1 wiring layer 221. As described later, each of the first substrate 100 and the second substrate 200 may be configured as a multi-layer substrate. The second substrate 200 may be configured as a fine circuit substrate having a relatively fine pitch compared to the first substrate 100. For example, the second substrate 200 may be configured as a circuit substrate having a higher wiring density than that of the first substrate 100. The first metal layer M1 and the second metal layer M2 may be bonded to each other together with the insulating layer 300 using mixed metal bonding. For example, the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be bonded to each other. The first metal layer M1 and the second metal layer M2 may be bonded to each other and may be integrated into the metal layer M. The boundary between the first metal layer M1 and the second metal layer M2 may be distinct or may not be distinct. The bonding layer 300 may be disposed adjacent to the metal layer M. The first substrate 100 and the second substrate 200 may include an organic material, and the bonding layer 300 may include an inorganic material. In the present disclosure, the metal layer M may also be regarded as a part independent of the first substrate 100 and the second substrate 200.

[0025] In order to realize fine circuits, the substrate may use a semi-additive process (SAP) or an embedded trace substrate (ETS) method. For example, through the ETS method, when etching the seed layer of chemical copper plating, a structure in which the pattern can be buried in the insulating material can occur, and undercutting does not occur, so that the adhesion between the pattern and the insulating material can be excellent. However, regardless of the excellence of the SAP or ETS method, the low yield of the layer in which the fine circuit can be realized may affect the overall yield.

[0026] A printed circuit board 500A according to an example may have a structure in which a first substrate 100 having a relatively large wiring density and a second substrate 200 having a relatively small wiring density can be manufactured separately and can be combined using mixed metal bonding. In this case, even when a low-density substrate is manufactured at a high yield and a high-density substrate is manufactured at a lower yield, only high-quality substrates can be combined with each other, thereby reducing the reduction in the final cumulative yield. In addition, by using an optimized process based on the density of wiring, the line width of the wiring line, the distance between the wiring lines, and the spacing of the wiring pads, the process efficiency can be improved, and the efficiency in terms of cost can be obtained. In addition, since the first substrate 100 and the second substrate 200 can be combined with each other by the insulating layer 300 and the first metal layer M1 and the second metal layer M2 through mixed metal bonding, the total thickness of the substrate can be reduced, the bonding reliability can be improved, and since it may be necessary to form a bonding pad, the degree of freedom in design can be increased.

[0027] In the following description, components of a printed circuit board 500A according to an example may be described in more detail with reference to the accompanying drawings.

[0028] The first substrate 100 may be configured as a multilayer printed circuit board. For example, the first substrate 100 may include: a plurality of first insulating layers 111, 112, 113, 114, and 115; a plurality of first wiring layers 121, 122, 123, 124, 125, and 126, respectively disposed on or in the plurality of first insulating layers 111, 112, 113, 114, and 115; and a plurality of first via layers 131, 132, 133, 134, and 135, respectively penetrating the plurality of first insulating layers 111, 112, 113, 114, and 115. Among the plurality of first wiring layers 121, 122, 123, 124, 125, and 126, the 1-6 wiring layers 126 disposed on the uppermost side may include the first metal layer M1. The first substrate 100 may be configured as a coreless multilayer printed circuit board that does not include a core layer. At least one of the plurality of first insulating layers 111 , 112 , 113 , 114 , and 115 may include an organic material.

[0029] The plurality of first insulating layers 111, 112, 113, 114, and 115 may be configured as organic insulating layers. For example, the plurality of first insulating layers 111, 112, 113, 114, and 115 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or a material containing an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material, such as a copper clad laminate (CCL), an Ajinomoto build-up film (ABF), or a prepreg (PPG), but the exemplary embodiments thereof are not limited thereto, and other polymer materials may be used. If desired, at least one of the plurality of first insulating layers 111, 112, 113, 114, and 115 may include other types of insulating materials other than organic insulating materials, such as glass and ceramics. However, even in this case, the other layers may include an organic insulating material.

[0030] Each of the plurality of first wiring layers 121, 122, 123, 124, 125, and 126 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments thereof are not limited thereto. Each of the plurality of first wiring layers 121, 122, 123, 124, 125, and 126 may perform various functions according to design. For example, a signal pattern, a power pattern, and a ground pattern may be included. The pattern may have various forms, such as a line form, a plane form, and a pad form. Each of the plurality of first wiring layers 121, 122, 123, 124, 125, and 126 may include a seed layer and a plating layer formed on the seed layer. The seed layer may be an electroless plating layer (e.g., chemical copper plating) and / or a sputtering layer, and the plating layer may be an electrolytic plating layer (e.g., electrolytic copper plating), but embodiments thereof are not limited thereto. The 1-1 wiring layer 121 may be buried in the lower side of the 1-1 insulating layer 111 so that the lower surface may be exposed from the lower surface of the 1-1 insulating layer 111. The 1-2 wiring layer 122 may be disposed on the upper surface of the 1-1 insulating layer 111 and may be buried in the 1-2 insulating layer 112. The 1-3 wiring layer 123 may be disposed on the upper surface of the 1-2 insulating layer 112 and may be buried in the 1-3 insulating layer 113. The 1-4 wiring layer 124 may be disposed on the upper surface of the 1-3 insulating layer 113 and may be buried in the 1-4 insulating layer 114. The 1-5 wiring layer 125 may be disposed on the upper surface of the 1-4 insulating layer 114 and may be buried in the 1-5 insulating layer 115. The 1-6 wiring layer 126 may be disposed on an upper surface of the 1-5 insulating layer 115. However, embodiments thereof are not limited thereto.

[0031] The first metal layer M1 may include various types of conductor patterns. The first metal layer M1 may be disposed at a position substantially corresponding to the second metal layer M2, and the conductor pattern of the first metal layer M1 may have a shape substantially corresponding to the conductor pattern of the second metal layer M2. The 1-6 wiring layer 126 including the first metal layer M1 may be planarized as in a process described later, and may have a thickness smaller than that of the other 1-1 wiring layer 121, 1-2 wiring layer 122, 1-3 wiring layer 123, 1-4 wiring layer 124, and 1-5 wiring layer 125.

[0032] Each of the plurality of first via layers 131, 132, 133, 134, and 135 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but the embodiment thereof is not limited thereto. Each of the plurality of first via layers 131, 132, 133, 134, and 135 may include a filled via that fills the via hole, or may also include a conformal via formed along the wall of the via hole. The plurality of first via layers 131, 132, 133, 134, and 135 may perform various functions according to the design. For example, a ground via, a power via, and a signal via may be included. Each of the plurality of first via layers 131, 132, 133, 134, and 135 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of an electroless plating layer (e.g., chemical copper plating), and if necessary, a sputtering layer and an electroless plating layer may be included. Each via in the 1-1 via layer 131, the 1-2 via layer 132, the 1-3 via layer 133, the 1-4 via layer 134, and the 1-5 via layer 135 may have a shape tapered in the same direction in a cross section. For example, in each cross section, the upper end may be larger than the lower end.

[0033] The second substrate 200 may be configured as a multilayer printed circuit board. For example, the second substrate 200 may include: a plurality of second insulating layers 211, 212, 213, 214, and 215; a plurality of second wiring layers 221, 222, 223, 224, 225, and 226, respectively disposed on or in the plurality of second insulating layers 211, 212, 213, 214, and 215; and a plurality of second via layers 231, 232, 233, 234, and 235, respectively penetrating the plurality of second insulating layers 211, 212, 213, 214, and 215. Among the plurality of second wiring layers 221, 222, 223, 224, 225, and 226, the 2-6 wiring layers 226 disposed on the lowermost side may include the second metal layer M2. The second substrate 200 may be configured as a coreless multilayer printed circuit board that does not include a core layer. At least one of the plurality of second insulating layers 211 , 212 , 213 , 214 , and 215 may include an organic material.

[0034] The plurality of second insulating layers 211, 212, 213, 214, and 215 may be organic insulating layers. For example, the plurality of second insulating layers 211, 212, 213, 214, and 215 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material containing an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto deposited film (ABF), or a prepreg (PPG), but example embodiments thereof are not limited thereto, and other polymer materials may be used. If desired, the plurality of second insulating layers 211, 212, 213, 214, and 215 may each include a photosensitive insulating material such as a photosensitive dielectric (PID). If necessary, at least one of the plurality of second insulating layers 211, 212, 213, 214, and 215 may include other types of insulating materials other than organic insulating materials, such as glass and ceramics. However, even in this case, the other layers may include organic insulating materials.

[0035] The plurality of second insulating layers 211, 212, 213, 214, and 215 may have the same number of layers as the plurality of first insulating layers 111, 112, 113, 114, and 115, and may have a total thickness substantially the same as the total thickness of the plurality of first insulating layers 111, 112, 113, 114, and 115. In addition, the plurality of second wiring layers 221, 222, 223, 224, 225, and 226 may have the same number of layers as the plurality of first wiring layers 121, 122, 123, 124, 125, and 126. In addition, the plurality of second insulating layers 211, 212, 213, 214, and 215 may include an insulating material substantially the same as that of the plurality of first insulating layers 111, 112, 113, 114, and 115. For example, the first substrate 100 and the second substrate 200 may have a substantially symmetrical structure. However, embodiments thereof are not limited thereto, and the plurality of second insulating layers 211, 212, 213, 214, and 215 may include an insulating material different from that of the plurality of first insulating layers 111, 112, 113, 114, and 115. For example, the plurality of first insulating layers 111, 112, 113, 114, and 115 may include a non-photosensitive insulating material such as Ajinomoto built-up film (ABF) and prepreg (PPG), and the plurality of second insulating layers 211, 212, 213, 214, and 215 may include a photosensitive insulating material such as photosensitive dielectric (PID). In this case, the 2-1 insulation layer 211, the 2-2 insulation layer 212, the 2-3 insulation layer 213, the 2-4 insulation layer 214, and the 2-5 insulation layer 215 may have the same thickness as the 1-1 insulation layer 111, the 1-2 insulation layer 112, the 1-3 insulation layer 113, the 1-4 insulation layer 114, and the 1-5 insulation layer 115, respectively, but the embodiment is not limited thereto. In addition, in this case, the 2-1 wiring layer 221, the 2-2 wiring layer 222, the 2-3 wiring layer 223, the 2-4 wiring layer 224, the 2-5 wiring layer 225, and the 2-6 wiring layer 226 may have the same thickness as the 1-1 wiring layer 121, the 1-2 wiring layer 122, the 1-3 wiring layer 123, the 1-4 wiring layer 124, the 1-5 wiring layer 125, and the 1-6 wiring layer 126, respectively, but the embodiment is not limited thereto.

[0036] The plurality of second wiring layers 221, 222, 223, 224, 225 and 226 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. Preferably, copper (Cu) may be included, but the embodiment is not limited thereto. Each of the plurality of second wiring layers 221, 222, 223, 224, 225 and 226 may perform various functions according to the design. For example, a signal pattern, a power pattern and a ground pattern may be included. Each of the patterns may have various forms, such as a line form, a plane form and a pad form. Each of the plurality of second wiring layers 221, 222, 223, 224, 225 and 226 may include a seed layer and a plating layer formed on the seed layer. The seed layer may be an electroless plating layer (e.g., chemical copper plating) and / or a sputtering layer, and the plating layer may be an electrolytic plating layer (e.g., electrolytic copper plating), but embodiments thereof are not limited thereto. The 2-1 wiring layer 221 may be buried in the upper side of the 2-1 insulating layer 211 so that the upper surface may be exposed from the upper surface of the 2-1 insulating layer 211. The 2-2 wiring layer 222 may be disposed on the lower surface of the 2-1 insulating layer 211 and may be buried in the 2-2 insulating layer 212. The 2-3 wiring layer 223 may be disposed on the lower surface of the 2-2 insulating layer 212 and may be buried in the 2-3 insulating layer 213. The 2-4 wiring layer 224 may be disposed on the lower surface of the 2-3 insulating layer 213 and may be buried in the 2-4 insulating layer 214. The 2-5 wiring layer 225 may be disposed on the lower surface of the 2-4 insulating layer 214 and may be buried in the 2-5 insulating layer 215. The 2-6 wiring layer 226 may be disposed on a lower surface of the 2-5 insulating layer 215. However, embodiments thereof are not limited thereto.

[0037] At least one of the plurality of second wiring layers 221 , 222 , 223 , 224 , 225 , and 226 (eg, 2-1 wiring layer 221 , 2-2 wiring layer 222 , and 2-3 wiring layer 223 ) may include a fine circuit pattern P. The fine circuit pattern P may have a line width / space (L / S) of 10µm / 10µm or less (eg, 2µm / 2µm or less). For example, the minimum line width of the wiring lines, the minimum distance between the wiring lines, and the minimum spacing between the wiring pads of the 2-1 wiring layer 221, the 2-2 wiring layer 222, and the 2-3 wiring layer 223 may be respectively smaller than the minimum line width of the wiring lines, the minimum distance between the wiring lines, and the minimum spacing between the wiring pads of at least one of the multiple first wiring layers 121, 122, 123, 124, 125, and 126 (preferably, the multiple first wiring layers 121, 122, 123, 124, 125, and 126), and the wiring density of the 2-1 wiring layer 221, the 2-2 wiring layer 222, and the 2-3 wiring layer 223 may be higher than the wiring density of at least one of the multiple first wiring layers 121, 122, 123, 124, 125, and 126. For example, the line width / spacing (L / S) of the line patterns for signal connection of the 2-1 wiring layer 221, the 2-2 wiring layer 222 and the 2-3 wiring layer 223 are respectively smaller than the line width / spacing (L / S) of the line patterns for signal connection of at least one of the multiple first wiring layers 121, 122, 123, 124, 125 and 126 (preferably, the multiple first wiring layers 121, 122, 123, 124, 125 and 126).

[0038] The second metal layer M2 may include various types of conductor patterns. The second metal layer M2 may be disposed at a position substantially corresponding to the first metal layer M1, and the conductor pattern of the second metal layer M2 may have a shape substantially corresponding to the conductor pattern of the first metal layer M1. The 2-6 wiring layer 226 including the second metal layer M2 may be planarized as in the process described later, and thus may be thinner than the other 2-1 wiring layer 221, 2-2 wiring layer 222, 2-3 wiring layer 223, 2-4 wiring layer 224, and 2-5 wiring layer 225, respectively.

[0039] Each of the plurality of second via layers 231, 232, 233, 234, and 235 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but the embodiment thereof is not limited thereto. Each of the plurality of second via layers 231, 232, 233, 234, and 235 may include a filled via that fills the via hole, or may also include a conformal via formed along the wall surface of the via hole. The plurality of second via layers 231, 232, 233, 234, and 235 may perform various functions according to the design. For example, a ground via, a power via, and a signal via may be included. Each of the plurality of second via layers 231, 232, 233, 234, and 235 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of an electroless plating layer (e.g., a chemical copper plating layer), and if necessary, a sputtering layer and an electroless plating layer may be included. Each via in the 2-1 via layer 231, the 2-2 via layer 232, the 2-3 via layer 233, the 2-4 via layer 234, and the 2-5 via layer 235 may have a shape that tapers in the same direction in the cross section. For example, in each cross section, the lower end may be larger than the upper end. For example, the vias in the 1-1 via layer 131, the 1-2 via layer 132, the 1-3 via layer 133, the 1-4 via layer 134, and the 1-5 via layer 135 and the vias in the 2-1 via layer 231, the 2-2 via layer 232, the 2-3 via layer 233, the 2-4 via layer 234, and the 2-5 via layer 235 may taper in opposite directions in the cross section, respectively.

[0040] Among the plurality of first via layers 131, 132, 133, 134, and 135, the 1-5 via layer 135 disposed on the uppermost side may include a first connection via connected to the first metal layer M1, and among the plurality of second via layers 231, 232, 233, 234, and 235, the 2-5 via layer 235 disposed on the lowermost side may include a second connection via connected to the second metal layer M2, wherein the first connection via and the second connection via may taper in opposite directions. For example, in a cross section, the width of the upper end of the first connection via may be greater than the width of the lower end. In a cross section, the width of the lower end of the second connection via may be greater than the width of the upper end.

[0041] The insulating layer 300 may include an insulating material that can be used for mixed metal bonding. For example, the insulating layer 300 may include an inorganic insulating material. The inorganic insulating material may include, for example, at least one of SiO2, SiN, and SiCN, but its embodiment is not limited thereto. The insulating layer 300 may embed at least a portion of each of the first metal layer M1 and the second metal layer M2. For example, the insulating layer 300 may cover at least a portion of the side surface of each of the first metal layer M1 and the second metal layer M2. However, the insulating layer 300 may be spaced apart from the lower surface of the first metal layer M1 and the upper surface of the second metal layer M2. The thickness of the bonding layer 300 may be substantially the same as the thickness of the metal layer M.

[0042] The first resist layer 150 and the second resist layer 250 may include a liquid solder resist or a film type solder resist, but the embodiment thereof is not limited thereto, and may include other organic insulating materials such as ABF. The first resist layer 150 and the second resist layer 250 may have a first opening h1 and a second opening h2, respectively. A plurality of first openings h1 and a plurality of second openings h2 may be provided. The first opening h1 and the second opening h2 may be formed as solder mask defined (SMD) and / or non-solder mask defined (NSMD). The first opening h1 and the second opening h2 may expose at least a portion of the 1-1 wiring layer 121 and at least a portion of the 2-1 wiring layer 221, respectively, and a surface treatment layer may be provided on the exposed surface of the pattern. The surface treatment layer may be formed by electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) process, electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, direct immersion gold (DIG) plating, and hot air solder leveling (HASL), but the embodiment thereof is not limited thereto.

[0043] Figure 4 It is shown Figure 3 sectional view of a modified example of a printed circuit board.

[0044] Reference Figure 4, unlike the printed circuit board 500A, the printed circuit board 600A according to the modified example may further include: a plurality of first connection metal members 410, respectively disposed in a plurality of first openings h1 of the first anti-etching layer 150, and respectively connected to at least a portion of the 1-1 wiring layer 121; a plurality of second connection metal members 420, respectively disposed in at least a portion of the second openings h2 of the second anti-etching layer 250, and respectively connected to at least a portion of the 2-1 wiring layer 221; and a semiconductor chip 450, surface-mounted on the second anti-etching layer 250 through the plurality of second connection metal members 420. For example, the printed circuit board 500A according to one example may have a packaged substrate structure, and the printed circuit board 600A according to the modified example may have a semiconductor package structure including the packaged substrate structure. The printed circuit board 600A according to the modified example may be connected to and / or mounted on another substrate 900 (such as a main board) through the plurality of first connection metal members 410.

[0045] Each of the first connection metal member 410 and the second connection metal member 420 may be formed using a low melting point metal (e.g., a solder such as tin (Sn)-aluminum (Al)-copper (Cu)), but example embodiments thereof are not limited thereto. The first connection metal member 410 and the second connection metal member 420 may be a ball, a pin, or the like. The first connection metal member 410 and the second connection metal member 420 may be formed as a multilayer or a single layer. When formed as a multilayer, a copper column and a solder may be included, and when formed as a single layer, a tin-silver solder may be included, but example embodiments thereof are not limited thereto. A plurality of first connection metal members 410 and a plurality of second connection metal members 420 may be provided, and the number of the first connection metal member 410 and the second connection metal member 420 is not limited to any particular example.

[0046] The semiconductor chip 450 may include an integrated circuit (IC) die in which hundreds to millions of elements are integrated into the chip. In this case, the integrated circuit may be configured as, for example, a controller chip, such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (AP), an analog-to-digital converter, or an application-specific IC (ASIC), but its example embodiments are not limited thereto, and the integrated circuit may be configured as a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM or flash memory), a high bandwidth memory (HBM), or configured as other types of chips, such as a power management IC (PMIC). The semiconductor chip 450 may be formed based on an active wafer, in which case silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material of each body. Various circuits may be formed in the body. A connection pad may be formed on the body, and the connection pad may include a conductive material such as aluminum (Al) and / or copper (Cu). The semiconductor chip 450 may be configured as a bare die, in which case metal bumps may be provided on the connection pads. The semiconductor chip 450 may be configured as a packaged die, in which case an additional redistribution layer may be formed on the connection pads, and the metal bumps may be provided on the redistribution layer. A plurality of semiconductor chips 450 may be provided, in which case the semiconductor chips 450 may be of the same type or of different types.

[0047] If necessary, an electronic component (not shown) may be surface mounted on the second anti-etching layer 250 through a plurality of second connection metal parts 420. The electronic component (not shown) may be a chip component, such as a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-fired ceramic (LTCC) component, an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), etc., but the embodiment is not limited thereto. A plurality of electronic components (not shown) may be provided, in which case the electronic components (not shown) may be of the same type or of different types.

[0048] The other descriptions may be substantially the same as those in the printed circuit board 500A according to the aforementioned example. Therefore, a repeated description will not be provided.

[0049] FIG. 5A to FIG. 5D is shown with Figure 3 Region A corresponds to an enlarged cross-sectional view of various examples of mixed metal bonding.

[0050] Reference Figure 5A, the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be directly bonded to each other. The first metal layer M1 and the second metal layer M2 may be directly bonded to each other and may form a metal layer M. The boundary between the first metal layer M1 and the second metal layer M2 may be obvious. The first metal layer M1 may include a 1-1 metal layer m1-1 as a seed layer and a 1-2 metal layer m1-2 as a plating layer. The second metal layer M2 may include a 2-1 metal layer m2-1 as a seed layer and a 2-2 metal layer m2-2 as a plating layer. Each of the first metal layer M1 and the second metal layer M2 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, preferably copper (Cu), but embodiments thereof are not limited thereto. The insulating layer 300 may include a first insulating film 310 and a second insulating film 320. Each of the first insulating film 310 and the second insulating film 320 may include an inorganic insulating film. Each of the first insulating film 310 and the second insulating film 320 may include an inorganic insulating material, preferably SiO2, but the embodiment thereof is not limited thereto. The first insulating film 310 may be disposed on the upper side of the first substrate 100 and may cover at least a portion of the side surface of the first metal layer M1. The second insulating film 320 may be disposed on the lower side of the second substrate 200 and may cover at least a portion of the side surface of the second metal layer M2. The boundary between the first insulating film 310 and the second insulating film 320 may be inconspicuous, for example, the first insulating film 310 and the second insulating film 320 may be integrated with each other. The first metal layer M1 and the second metal layer M2 and the first insulating film 310 and the second insulating film 320 may be bonded to each other by mixed metal bonding. The upper surface of the first metal layer M1 and the upper surface of the first insulating film 310 may be substantially coplanar with each other, and the lower surface of the second metal layer M2 and the lower surface of the second insulating film 320 may be substantially coplanar with each other, but the embodiment thereof is not limited thereto. This bonding structure can be applied to the printed circuit board 500A according to the above example and the printed circuit board 600A according to the modified example. In addition, this bonding structure can also be applied to printed circuit boards 500B, 500C and 500D according to other examples described later and printed circuit boards 600B, 600C and 600D according to the modified examples.

[0051] Reference Figure 5B, the first metal layer M1 and the second metal layer M2 may be combined so that the side surface of the first metal layer M1 and the side surface of the second metal layer M2 may be set to be offset from each other. For example, at least a portion of the side surface of the metal layer M may have a step difference. Here, the step difference may include a step difference between vertical side surfaces and a step difference between curved side surfaces including a shape that bends outward or inward. For example, even when the side surface of the metal layer M is substantially S-shaped, a step difference may be formed when the upper and lower portions of the metal layer M are sufficiently offset from each other. For example, the step difference may refer to a step difference caused by misalignment between the first metal layer M1 and the second metal layer M2 during bonding, and may be distinguished from a simple unevenness (such as surface roughness) formed on the side surface. In this case, the insulating layer 300 may cover at least a portion of each of the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2. Therefore, improved adhesion may be obtained. In addition, reliability may also be improved. Other descriptions may be referred to with reference to Figure 5A The description of the bonding structure described is the same. The bonding structure can also be applied to the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example. In addition, the bonding structure can also be applied to the printed circuit boards 500B, 500C and 500D according to other examples described later and the printed circuit boards 600B, 600C and 600D according to the modified examples.

[0052] Reference Figure 5C , the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be bonded to each other through a third metal layer M3 including a metal different from the first metal layer M1 and the second metal layer M2. For example, a heterogeneous third metal layer M3 may be provided in the metal layer M. For example, the first metal layer M1 and the second metal layer M2 may include copper (Cu), and the third metal layer M3 may include silver (Ag) and / or gold (Au), but embodiments thereof are not limited thereto. When the third metal layer M3 is used, the adhesion between the first metal layer M1 and the second metal layer M2 may be improved. Other descriptions may be referred to with reference to Figure 5A The description of the bonding structure described is the same. The bonding structure can also be applied to the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example. In addition, the bonding structure can also be applied to the printed circuit boards 500B, 500C and 500D according to other examples described later and the printed circuit boards 600B, 600C and 600D according to the modified examples.

[0053] Reference Figure 5D, the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be bonded to each other through a third metal layer M3 including a metal different from the metals of the first metal layer M1 and the second metal layer M2. For example, a heterogeneous third metal layer M3 may be provided in the metal layer M. For example, the first metal layer M1 and the second metal layer M2 may include copper (Cu), and the third metal layer M3 may include silver (Ag) and / or gold (Au). In this case, the adhesion between the first metal layer M1 and the second metal layer M2 may be improved. In addition, the first metal layer M1 and the second metal layer M2 may be bonded to each other so that the side surface of the first metal layer M1 and the side surface of the second metal layer M2 may be offset from each other. For example, at least a portion of the side surface of the metal layer M may have a step difference. Here, the step difference may include a step difference between vertical side surfaces and a step difference between curved side surfaces including a shape that is bent outward or inward. For example, even when the side surface of the metal layer M is substantially S-shaped, the step difference may be obtained when the upper and lower portions of the metal layer M are sufficiently offset from each other. For example, the step difference may refer to a step difference formed by misalignment between the first metal layer M1 and the second metal layer M2 during bonding, and can be distinguished from a simple unevenness (such as surface roughness) formed on the side surface. In this case, the insulating layer 300 may cover at least a portion of each of the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2, and thus may have improved adhesion and reliability. In addition, at least a portion of the third metal layer M3 may be set to deviate from at least one of the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2. For example, a portion of the third metal layer M3 may be set to extend beyond the upper surface of the first metal layer M1, in which case a portion of the lower surface of the third metal layer M3 may contact the insulating layer 300. Therefore, adhesion can be improved. Alternatively, for example, a portion of the third metal layer M3 may be set to extend beyond the lower surface of the second metal layer M2, in which case a portion of the upper surface of the third metal layer M3 may contact the insulating layer 300, so that adhesion can be improved. Other descriptions may be related to Figure 5A The description of the bonding structure in is the same. The bonding structure can also be applied to the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example. In addition, the bonding structure can also be applied to the printed circuit boards 500B, 500C and 500D according to other examples described later and the printed circuit boards 600B, 600C and 600D according to the modified examples.

[0054] Fig. 6A and Figure 6B are enlarged cross-sectional views showing various examples of interfaces in intermetallic bonding.

[0055] Reference Fig. 6A, in the case where the first metal layer M1 and the second metal layer M2 are directly bonded to each other by mixed metal bonding, the first metal layer M1 and the second metal layer M2 may have a plurality of first grains g1 and a plurality of second grains g2, respectively. In this case, in the metal bonding interface between the first metal layer M1 and the second metal layer M2, the plurality of first grains g1 and the plurality of second grains g2 may include, for example, a plurality of triple junctions of approximately 90 degrees. The bonding structure may be applied to the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example. In addition, the bonding structure may also be applied to the printed circuit boards 500B, 500C, and 500D according to other examples described later and the printed circuit boards 600B, 600C, and 600D according to the modified example.

[0056] Reference Figure 6B , since the surface energy of the grain boundary is reduced, the interface of the metal bonding may have a diffusion wedge. For example, the interface between the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may have at least one protrusion v protruding toward the inside of the first metal layer M1 and / or the second metal layer M2, and the protrusion v may include a diffusion wedge caused by the diffusion of metal particles. For example, in the metal bonding interface between the first metal layer M1 and the second metal layer M2, the plurality of first crystal grains g1 and the plurality of second crystal grains g2 may include, for example, a plurality of triple junctions of about 120 degrees. The bonding structure may also be applied to the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example. In addition, the bonding structure may also be applied to the printed circuit boards 500B, 500C and 500D according to other examples described later and the printed circuit boards 600B, 600C and 600D according to the modified example.

[0057] Figure 7 is a diagram illustrating an example of a method of manufacturing a printed circuit board.

[0058] Reference Figure 7 , a method for manufacturing a printed circuit board according to an example may include: forming a first substrate portion (S1); forming a second substrate portion (S2); and combining the first substrate portion and the second substrate portion with each other (S3). Forming the first substrate portion (S1) may include: preparing a first substrate including a first metal layer and a plurality of first wiring layers (S1-1); forming a first insulating film covering the first metal layer on the first substrate (S1-2); and exposing the first metal layer (S1-3). Forming the second substrate portion (S2) may include: preparing a second substrate including a second metal layer and a plurality of second wiring layers (S2-1); forming a second insulating film covering the second metal layer on the second substrate (S2-2); and exposing the second metal layer (S2-3).

[0059] In the following description, a method of manufacturing a printed circuit board according to examples may be described in more detail with reference to the accompanying drawings.

[0060] FIG. 8A to FIG. 8C 2 are cross-sectional views showing the process of an example of a method of manufacturing the first substrate portion.

[0061] Reference Fig. 8A , a first substrate 100 including a plurality of first wiring layers 121, 122, 123, 124, 125 and 126 and having a first metal layer M1 formed on one side may be prepared. The first substrate 100 may be a multilayer substrate as described above. The first substrate 100 may be formed on the carrier 800 by a substrate process (e.g., an ETS process and a deposition process). Thereafter, a first insulating film 310 covering at least a portion of the first metal layer M1 may be formed on one side of the first substrate 100. As described above, the first insulating film 310 may be an inorganic insulating film. The first insulating film 310 may be formed by a coating process (such as deposition). The first insulating film 310 may conformally cover the first substrate 100.

[0062] Reference Figure 8B , the first metal layer M1 and the first insulating film 310 may be planarized, and the surface of the first metal layer M1 may be exposed. Grinding may be used as a planarization process. Through the planarization process, the thickness of the first metal layer M1 and the thickness of the first insulating film 310 may become substantially the same. In addition, the thickness of the first metal layer M1 may be less than the thickness of each of the other 1-1 wiring layer 121, 1-2 wiring layer 122, 1-3 wiring layer 123, 1-4 wiring layer 124, and 1-5 wiring layer 125.

[0063] Reference Figure 8C , the carrier 800 may be separated. The carrier 800 may be physically separated, but the embodiment is not limited thereto. After removing the carrier 800, an etching process for removing a residual metal film from the carrier 800 may be performed, in which a concave step difference may be formed in the 1-1 wiring layer 121, but the embodiment is not limited thereto, and if necessary, the formation of the concave step difference may be prevented.

[0064] Through a series of processes, the first substrate portion 100 - 1 may be prepared. Other descriptions may be substantially the same as those of the printed circuit board 500A according to the aforementioned example, and a repeated description will not be provided.

[0065] 9A to 9C 2 are cross-sectional views showing the process of an example of a method of manufacturing the second substrate unit.

[0066] Reference Fig. 9A, a second substrate 200 including a plurality of second wiring layers 221, 222, 223, 224, 225, and 226 and having a second metal layer M2 formed on one side may be prepared. As described above, the second substrate 200 may be configured as a multilayer substrate including a fine circuit pattern P, and the line width of the wiring line of the fine circuit pattern P and the distance between the wiring lines are respectively smaller than the line width of the wiring line of each of the plurality of first wiring layers 121, 122, 123, 124, 125, and 126 of the first substrate 100 and the distance between the wiring lines. The second substrate 200 may be formed on the carrier 800 by a substrate process such as an ETS process and a deposition process. Thereafter, a second insulating film 320 covering at least a portion of the second metal layer M2 may be formed on one side of the second substrate 200. As described above, the second insulating film 320 may be an inorganic insulating film. The second insulating film 320 may be formed by a coating process such as deposition. The second insulating film 320 may conformally cover the second substrate 200.

[0067] Reference Fig. 9B , the second metal layer M2 and the second insulating film 320 may be planarized, and the surface of the second metal layer M2 may be exposed. Grinding may be used as a planarization process. Through the planarization process, the thickness of the second metal layer M2 and the thickness of the second insulating film 320 may become substantially the same. In addition, the thickness of the second metal layer M2 may be less than the thickness of each of the other 2-1 wiring layer 221, 2-2 wiring layer 222, 2-3 wiring layer 223, 2-4 wiring layer 224, and 2-5 wiring layer 225.

[0068] Reference Fig. 9C , the carrier 800 may be separated. The carrier 800 may be physically separated, but the embodiment is not limited thereto. After removing the carrier 800, an etching process for removing another residual metal film from the carrier 800 may be performed, in which a concave step difference may be formed in the 2-1 wiring layer 221, but the embodiment is not limited thereto, and if necessary, the formation of the concave step difference may be prevented.

[0069] Through a series of processes, the second substrate portion 200 - 1 may be prepared. Other descriptions may be substantially the same as those of the printed circuit board 500A according to the aforementioned example, and a repeated description will not be provided.

[0070] Fig. 10A and Fig. 10B is a cross-sectional view showing an example of combining the first substrate portion and the second substrate portion.

[0071] Reference Fig. 10A, the first substrate portion 100-1 and the second substrate portion 200-1 may be bonded to each other by bonding the first insulating film 310 and the second insulating film 320 to each other, and bonding the first metal layer M1 and the second metal layer M2 to each other. In order to bond the first insulating film 310 and the second insulating film 320 to each other and bond the first metal layer M1 and the second metal layer M2 to each other, a hybrid metal bonding described later may be used.

[0072] Reference Fig. 10B , a first resist layer 150 and a second resist layer 250 may be formed on both sides of the combined first and second substrate parts 100-1 and 200-1. In addition, a plurality of first openings h1 and a plurality of second openings h2 may be formed on the first and second resist layers 150 and 250, respectively.

[0073] Through a series of processes, the printed circuit board 500A according to the aforementioned example may be manufactured. Other descriptions may be substantially the same as those of the printed circuit board 500A according to the aforementioned example, and a repeated description will not be provided.

[0074] Fig.11 is a cross-sectional view showing mixed metal bonding.

[0075] Fig.12 is a graph illustrating temperature variation of mixed metal bonding according to example embodiments.

[0076] Reference Fig.11 and Fig.12 , the first insulating film 310 and the second insulating film 320 may be brought into contact with each other, and the first metal layer M1 and the second metal layer M2 may also be brought into contact with each other. Before the contact, the surfaces of the first insulating film 310 and the second insulating film 320 and the first metal layer M1 and the second metal layer M2 may be processed by wet cleaning or plasma activation. In this case, an inwardly curved concave portion may be formed on the surface of each of the first metal layer M1 and the second metal layer M2. The first insulating film 310 and the second insulating film 320 may be brought into contact with each other and the first metal layer M1 and the second metal layer M2 may be brought into contact with each other at room temperature (RT). Thereafter, the first insulating film 310 and the second insulating film 320 may be bonded to each other at a first temperature. For example, at a first temperature T1, the first insulating film 310 and the second insulating film 320 may be directly bonded to each other and may be integrated into the insulating layer 300. The first temperature T1 may be lower than the second temperature T2. Thereafter, the first metal layer M1 and the second metal layer M2 may be bonded to each other at the second temperature T2. For example, at the second temperature T2, the first metal layer M1 and the second metal layer M2 may be directly bonded to each other and may form the metal layer M. For example, during the annealing process at the second temperature T2, each metal may be directly bonded to each other by increasing the grain size. The second temperature T2 may be a temperature higher than the first temperature T1.

[0077] Through a series of processes, the aforementioned first substrate part 100-1 and the second substrate part 200-1 may be combined with each other. Other descriptions may be substantially the same as the description of the printed circuit board 500A according to the aforementioned example, and a repeated description will not be provided.

[0078] Fig.13 is a cross-sectional view showing another example of mixed metal bonding.

[0079] Reference Fig.13 , combining the aforementioned first substrate portion 100-1 and the second substrate portion 200-1 with each other may also include: applying a metal paste M3' including a metal different from the metal of the first metal layer M1 and the second metal layer M2 between the first metal layer M1 and the second metal layer M2. For example, before allowing the first insulating film 310 and the second insulating film 320 and the first metal layer M1 and the second metal layer M2 to contact each other, the metal paste M3' may be applied on the upper surface of the first metal layer M1 and / or the lower surface of the second metal layer M2. Thereafter, through the aforementioned hot pressing process, the first insulating film 310 and the second insulating film 320 may be directly combined with each other, and the first metal layer M1 and the second metal layer M2 may be combined with each other through the third metal layer M3. Therefore, the insulating layer 300 and the metal layer M may be formed.

[0080] Through a series of processes, the aforementioned first substrate part 100-1 and the second substrate part 200-1 may be combined with each other. Other descriptions may be substantially the same as the description of the printed circuit board 500A according to the aforementioned example, and a repeated description will not be provided.

[0081] Fig.14 is a cross-sectional view showing another example of mixed metal bonding.

[0082] Reference Fig.14 , the first metal layer M1 and the second metal layer M2 may be formed using nano twinned copper instead of ordinary copper, and the insulating layer 300 may be formed using a non-conductive paste. For example, the non-conductive paste 300' may be applied to the first metal layer M1 formed using a nano twinned copper film, the second metal layer M2 formed using a nano twinned copper film may be pressed thereon, and the first metal layer M1 and the second metal layer M2 may be directly bonded to each other at a high temperature. Alternatively, the non-conductive paste 300' may be applied to the second metal layer M2 formed using a nano twinned copper film, the first metal layer M1 formed using a nano twinned copper film may be pressed thereon, and the first metal layer M1 and the second metal layer M2 may be directly bonded to each other at a high temperature. Therefore, a metal layer M and an insulating layer 300 that buries the metal layer M may be formed. If necessary, the above-mentioned first insulating film 310 and / or the second insulating film 320 may be formed using the non-conductive paste 300', in which case the insulating layer 300 may include the first insulating film 310 and / or the second insulating film 320.

[0083] Through a series of processes, the aforementioned first substrate part 100-1 and the second substrate part 200-1 may be combined with each other. Other descriptions may be substantially the same as the description of the printed circuit board 500A according to the aforementioned example, and a repeated description will not be provided.

[0084] Fig.15 is a cross-sectional view showing another example of a printed circuit board.

[0085] Fig.16 It is shown Fig.15 sectional view of a modified example of the printed circuit board in FIG.

[0086] Reference Fig.15 and Fig.16, unlike the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example, in the printed circuit board 500B according to another example and the printed circuit board 600B according to the modified example, the first substrate 100 and the second substrate 200 may have an asymmetric structure. For example, the thickness of the second substrate 200 may be smaller than the thickness of the first substrate 100. For example, the number of the plurality of second insulating layers 211, 212, and 215 may be smaller than the number of the plurality of first insulating layers 111, 112, 113, 114, and 115, and the total thickness of the plurality of second insulating layers 211, 212, and 215 may also be smaller than the total thickness of the plurality of first insulating layers 111, 112, 113, 114, and 115. In addition, the number of the plurality of second wiring layers 221, 222, 225, and 226 may be smaller than the number of the plurality of first wiring layers 121, 122, 123, 124, 125, and 126. In addition, the number of the plurality of second via layers 231, 232, and 235 may be smaller than the number of the plurality of first via layers 131, 132, 133, 134, and 135. The thickness of the 2-1 insulation layer 211, the 2-2 insulation layer 212, and the 2-5 insulation layer 215 may be smaller than the thickness of the 1-1 insulation layer 111, the 1-2 insulation layer 112, the 1-3 insulation layer 113, the 1-4 insulation layer 114, and the 1-5 insulation layer 115. In addition, the thickness of the 2-1 wiring layer 221, the 2-2 wiring layer 222, the 2-5 wiring layer 225, and the 2-6 wiring layer 226 may be smaller than the thickness of the 1-1 wiring layer 121, the 1-2 wiring layer 122, the 1-3 wiring layer 123, the 1-4 wiring layer 124, the 1-5 wiring layer 125, and the 1-6 wiring layer 126. In addition, the width of the upper end and the width of the lower end of the vias in the 2-1 via layer 231, the 2-2 via layer 232, and the 2-5 via layer 235 may be respectively smaller than the width of the lower end and the width of the upper end of the vias in the 1-1 via layer 131, the 1-2 via layer 132, the 1-3 via layer 133, the 1-4 via layer 134, and the 1-5 via layer 135. The wirings of the 2-1 wiring layer 221, the 2-2 wiring layer 222, the 2-5 wiring layer 225, and the 2-6 wiring layer 226 may have a finer pitch than the pitch of the wirings of the 1-1 wiring layer 121, the 1-2 wiring layer 122, the 1-3 wiring layer 123, the 1-4 wiring layer 124, the 1-5 wiring layer 125, and the 1-6 wiring layer 126. In addition, the pitch of the vias of each of the 2-1 via layer 231, the 2-2 via layer 232, and the 2-5 via layer 235 may be finer than the pitch of the vias of each of the 1-1 via layer 131, the 1-2 via layer 132, the 1-3 via layer 133, the 1-4 via layer 134, and the 1-5 via layer 135. For example, the first substrate 100 and the second substrate 200 may have an asymmetric structure having different numbers of layers.

[0087] The other descriptions may be substantially the same as those of the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example. Therefore, a repeated description will not be provided.

[0088] Fig.17 is a cross-sectional view showing another example of a printed circuit board.

[0089] Fig.18 It is shown Fig.17 sectional view of a modified example of the printed circuit board in FIG.

[0090] Reference Fig.17 and Fig.18, unlike the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example, in the printed circuit board 500C according to another example and the printed circuit board 600C according to the modified example, the first substrate 100 may be a core type multilayer printed circuit board rather than a coreless type multilayer printed circuit board. For example, the first substrate 100 may include: a 1-1 insulating layer 111; a 1-1 wiring layer 121 and a 1-2 wiring layer 122, which are respectively arranged on the lower surface and the upper surface of the 1-1 insulating layer 111; a 1-1 via layer 131, which penetrates the 1-1 insulating layer 111 and connects the 1-1 wiring layer 121 and the 1-2 wiring layer 122 to each other; a 1-2 insulating layer 112, which is arranged on the lower surface of the 1-1 insulating layer 111 and covers the 1-1 wiring layer 121; a 1-3 wiring layer 123, which is arranged on the lower surface of the 1-2 insulating layer 112; a 1-2 via layer 132, which penetrates the 1-2 insulating layer 112 and connects the 1-1 wiring layer 121 and the 1-3 wiring layer 123 to each other; a 1-3 insulating layer 113, which is arranged on the upper surface of the 1-1 insulating layer 111 and covers the 1-2 wiring layer 122; a 1-4 wiring layer 124, which is arranged on the 1-3 insulating layer 1-3 via layer 133, penetrating the 1-3 insulating layer 133 and connecting the 1-2 wiring layer 122 and the 1-4 wiring layer 124 to each other; the 1-4 insulating layer 114, arranged on the lower surface of the 1-2 insulating layer 112 and covering the 1-3 wiring layer 123; the 1-5 wiring layer 125, arranged on the lower surface of the 1-4 insulating layer 114; the 1-4 via layer 134, penetrating the 1-4 insulating layer 114, and connecting the 1-3 wiring layer 123 and the 1-5 wiring layer 125 to each other; the 1-5 insulating layer 115, arranged on the upper surface of the 1-3 insulating layer 113 and covering the 1-4 wiring layer 124; the 1-6 wiring layer 126, arranged on the upper surface of the 1-5 insulating layer 115; and the 1-5 via layer 135, penetrating the 1-5 insulating layer 115, and connecting the 1-4 wiring layer 124 and the 1-6 wiring layer 126 to each other. The first insulating film 310 may be disposed on the upper surface of the 1-5 insulating layer 115 and may cover at least a portion of the first metal layer M1. The first anti-etching layer 150 may be disposed on the lower surface of the 1-4 insulating layer 114 and may cover at least a portion of the 1-5 wiring layer 125. The plurality of first openings h1 may expose at least a portion of the 1-5 wiring layer 125. As described above, the first substrate 100 (a low-density substrate having a relatively small wiring density) may be manufactured as a core-type multilayer printed circuit board, and the second substrate 200 (a high-density substrate having a relatively high wiring density) may be manufactured as a coreless multilayer printed circuit board. The 1-1 insulating layer 111 may be a core layer, and the 1-2 insulating layer 112, the 1-3 insulating layer 113, the 1-4 insulating layer 114, and the 1-5 insulating layer 115 may be buildup layers.The thickness of the 1-1 insulating layer 111 may be greater than the thickness of the 1-2 insulating layer 112, the thickness of the 1-3 insulating layer 113, the thickness of the 1-4 insulating layer 114, and the thickness of the 1-5 insulating layer 115. The 1-1 insulating layer 111 may include a copper clad laminate (CCL), and each of the 1-2 insulating layer 112, the 1-3 insulating layer 113, the 1-4 insulating layer 114, and the 1-5 insulating layer 115 may include an Ajinomoto built-up film (ABF) or a prepreg (PPG), but the embodiment is not limited thereto. The 1-1 insulating layer 111 may include an insulating material of a type other than an organic insulating material, such as glass and ceramic. If necessary, the component may further include a metal covered with an insulating film. The cross-section of the 1-1 via layer 131 may have an hourglass shape or a column shape. In addition, the vias in the 1-2 via layer 132 and the 1-4 via layer 134 may have a tapered shape in which the width of the lower end in the cross-section may be greater than the width of the upper end. Furthermore, the vias in the 1-3 via layer 133 and the 1-5 via layer 135 may have a tapered shape in which the width of the lower end may be smaller than the width of the upper end in the cross section. However, embodiments thereof are not limited thereto, and various forms of via structures may be applied.

[0091] The other descriptions may be substantially the same as those of the printed circuit board 500A according to the aforementioned example and the printed circuit board 600A according to the modified example. Therefore, a repeated description will not be provided.

[0092] Fig.19 is a cross-sectional view showing another example of a printed circuit board.

[0093] Fig. 20 It is shown Fig.19 sectional view of a modified example of the printed circuit board in FIG.

[0094] Reference Fig.19 and Fig. 20, unlike the printed circuit board 500C according to the above-mentioned other example and the printed circuit board 600C according to the modified example, in the printed circuit board 500D according to the other example and the printed circuit board 600D according to the modified example, the first substrate 100 and the second substrate 200 may have various forms of asymmetric structures. For example, the first substrate 100 may be a core-type multilayer printed circuit board, the second substrate 200 may be a coreless multilayer printed circuit board, the number of the plurality of second insulating layers 211, 212, and 215 may be less than the number of the plurality of first insulating layers 111, 112, 113, 114, and 115, and the total thickness of the plurality of second insulating layers 211, 212, and 215 may also be less than the total thickness of the plurality of first insulating layers 111, 112, 113, 114, and 115. In addition, the number of the plurality of second wiring layers 221, 222, 225, and 226 may be less than the number of the plurality of first wiring layers 121, 122, 123, 124, 125, and 126. In addition, the number of the plurality of second via layers 231, 232, and 235 may be smaller than the number of the plurality of first via layers 131, 132, 133, 134, and 135. In addition, the thickness of the second substrate 200 may be smaller than the thickness of the first substrate 100. The thickness of the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-5 insulating layer 215 may be smaller than the thickness of the 1-1 insulating layer 111, the 1-2 insulating layer 112, the 1-3 insulating layer 113, the 1-4 insulating layer 114, and the 1-5 insulating layer 115. In addition, the thickness of the 2-1 wiring layer 221, the 2-2 wiring layer 222, the 2-5 wiring layer 225, and the 2-6 wiring layer 226 may be smaller than the thickness of the 1-1 wiring layer 121, the 1-2 wiring layer 122, the 1-3 wiring layer 123, the 1-4 wiring layer 124, the 1-5 wiring layer 125, and the 1-6 wiring layer 126. Furthermore, the width of the upper end and the width of the lower end of the vias in the 2-1 via layer 231, the 2-2 via layer 232, and the 2-5 via layer 235 may be respectively smaller than the width of the upper end and the width of the lower end of the vias in the 1-2 via layer 132 and the 1-4 via layer 134, and the width of the lower end and the width of the upper end of the vias in the 1-3 via layer and the 1-5 via layer 135. The wirings of the 2-1 wiring layer 221, the 2-2 wiring layer 222, the 2-5 wiring layer 225, and the 2-6 wiring layer 226 may have a finer pitch than the pitch of the wirings of the 1-1 wiring layer 121, the 1-2 wiring layer 122, the 1-3 wiring layer 123, the 1-4 wiring layer 124, the 1-5 wiring layer 125, and the 1-6 wiring layer 126. Furthermore, the pitch of the vias of the 2-1 via layer 231, the 2-2 via layer 232, and the 2-5 via layer 235 may be finer than the pitch of the vias of the 1-1 via layer 131, the 1-2 via layer 132, the 1-3 via layer 133, the 1-4 via layer 134, and the 1-5 via layer 135. For example, the first substrate 100 and the second substrate 200 may have an asymmetric structure having different numbers of layers.

[0095] The other descriptions may be substantially the same as the descriptions of the printed circuit board 500A according to the aforementioned example, the printed circuit board 600A according to the modified example, the printed circuit board 500C according to the aforementioned another example, and the printed circuit board 600C according to the modified example. Therefore, a repeated description will not be provided.

[0096] According to the aforementioned example embodiments, a multilayer printed circuit board including fine circuits may be provided.

[0097] Furthermore, a printed circuit board can be provided that can reduce manufacturing costs through high yield and process efficiency.

[0098] In the present disclosure, the term "covering" may include a configuration in which a component is completely covered and a configuration in which at least a portion of a component is covered, and may also include a configuration in which a component is directly covered or indirectly covered. In addition, the term "filling" may include a configuration in which a component is completely filled and a configuration in which at least a portion of a component is filled, and may also include a configuration in which a component is roughly filled. For example, there may be a gap. In addition, the term "surrounding" may include a configuration in which a component is completely surrounded and a configuration in which a component is roughly surrounded. In addition, the term "exposing" may include a configuration in which a component is completely exposed or a portion of a component is exposed, and "exposing" may refer to exposing from a component for embedding. For example, a configuration in which an opening may expose a pad may refer to exposing a pad from an anti-etching layer, and a surface treatment layer may be further provided on the exposed pad.

[0099] In example embodiments, the configuration in which the component is disposed in the through-portion or through-hole may include a configuration in which the component is completely disposed in the through-portion or through-hole and a configuration in which the component partially protrudes to the upper side or the lower side in a cross section. For example, in the case in which the component is disposed in the through-portion or through-hole on a plane, the configuration may be understood in a broader sense.

[0100] In the present disclosure, the term "cross section" or "cross-sectional view" indicates a diagram showing a cross-sectional shape when an object is cut vertically or a diagram showing a shape when an object is viewed from the side. In addition, the configuration of a component on a plane may indicate a cross-sectional shape when an object is cut horizontally or a plane shape when the object is viewed from above or below.

[0101] In the present disclosure, the terms "lower side", "lower part" and "lower surface" may be used to indicate a downward direction based on a cross section of the drawings, and "upper side", "upper part" and "upper surface" may be used to indicate the opposite direction. However, this direction is defined for convenience of description, and the scope of the patent claims is not particularly limited by the description of this direction, and the terms "upper side" and "lower side" may be relative terms.

[0102] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" through an adhesive layer or the like. Furthermore, the term "electrical connection" may include a case where an element is "physically connected" and a case where an element is "not physically connected." Furthermore, the terms "first," "second," and the like may be used to distinguish one element from another, and may not limit the order and / or importance associated with the elements, etc. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of example embodiments.

[0103] Thickness, width, length, depth, line width, distance, spacing, etc. can be measured using a scanning microscope or an optical microscope based on a cross section of a printed circuit board obtained by polishing or cutting. The cross section can be a vertical cross section or a horizontal cross section, and each value can be measured based on the desired cross section. For example, the width of the upper and / or lower ends of the via can be measured on a cross section cut along the central axis of the via. In this case, when the value is non-constant, the value can be determined as the average of the values ​​measured at 5 random points. The minimum value can be determined as the minimum value measured on the corresponding layer or area.

[0104] In the example embodiments, the term "example embodiment" or "example" may not refer to the same example embodiment or example, but may be provided to describe and emphasize the unique features of each example embodiment. The example embodiments set forth above may be implemented without excluding the possibility of combining features with other example embodiments. For example, unless otherwise specified, even if a feature described in an example embodiment is not described in another example embodiment, the feature may be understood to be related to another example embodiment.

[0105] Unless it has a clearly different meaning in the context, an expression used in the singular includes the expression in the plural.

[0106] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A first substrate including a first wiring layer; A second substrate, disposed on the first substrate and comprising a second wiring layer; A metal layer, disposed between the first substrate and the second substrate; as well as a bonding layer disposed between the first substrate and the second substrate, wherein each of the first substrate and the second substrate comprises an organic material, and Wherein, the bonding layer comprises an inorganic material.

2. The printed circuit board according to claim 1, in, The metal layer includes a first metal layer disposed on an uppermost side of the first substrate and a second metal layer disposed on a lowermost side of the second substrate.

3. The printed circuit board according to claim 2, in, The first metal layer and the second metal layer are bonded to each other such that a side surface of the first metal layer and a side surface of the second metal layer are disposed to be offset from each other.

4. The printed circuit board according to claim 2, wherein: An upper surface of the first metal layer and a lower surface of the second metal layer are directly bonded to each other.

5. The printed circuit board according to claim 4, wherein: An interface between the upper surface of the first metal layer and the lower surface of the second metal layer has at least one protrusion protruding toward the inside of the first metal layer and / or the second metal layer.

6. The printed circuit board according to claim 5, wherein: The protrusions include diffuse wedges of metal particles.

7. The printed circuit board according to claim 2, wherein: The metal layer further includes a third metal layer disposed between the first metal layer and the second metal layer and including a metal different from metals of the first metal layer and the second metal layer.

8. The printed circuit board according to claim 7, wherein: At least a portion of the third metal layer is disposed beyond at least one of an upper surface of the first metal layer and a lower surface of the second metal layer.

9. The printed circuit board according to claim 7, in, Each of the first metal layer and the second metal layer includes Cu, and Wherein, the third metal layer includes Ag and / or Au.

10. The printed circuit board according to claim 1, wherein The bonding layer includes an inorganic insulating film.

11. The printed circuit board according to claim 10, wherein: The inorganic insulating film includes at least one of SiO 2 , SiN and SiCN.

12. The printed circuit board according to claim 1, in, The first substrate includes a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers, and The second substrate includes a plurality of second insulating layers, a plurality of second wiring layers respectively arranged on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers. wherein at least one of the plurality of first insulating layers comprises an organic material, and Wherein, at least one second insulating layer among the plurality of second insulating layers comprises an organic material.

13. The printed circuit board according to claim 12, wherein: A density of at least one of the plurality of second wiring layers is greater than a density of at least one of the plurality of first wiring layers.

14. The printed circuit board according to claim 12, wherein: At least one of the plurality of second wiring layers includes a fine circuit pattern having a line / space of 2 μm / 2 μm or less.

15. The printed circuit board according to claim 12, wherein: The thickness of the second substrate is smaller than the thickness of the first substrate.

16. The printed circuit board according to claim 12, wherein: An organic insulating material included in the at least one second insulating layer among the plurality of second insulating layers is different from an organic insulating material included in the at least one first insulating layer among the plurality of first insulating layers.

17. The printed circuit board according to claim 12, in, Among the plurality of first via layers, a first via layer disposed on an uppermost side includes a first connection via connected to the metal layer, wherein, among the plurality of second via layers, the second via layer disposed on the lowermost side includes a second connection via connected to the metal layer, and Wherein, the first connecting via and the second connecting via taper in opposite directions.

18. The printed circuit board according to claim 17, in, In the cross-sectional view, the width of the upper end of the first connection via is greater than the width of the lower end of the first connection via, and Wherein, in the cross-sectional view, the width of the lower end of the second connecting via is greater than the width of the upper end of the second connecting via.

19. The printed circuit board according to claim 12, in, The first substrate comprises a core-type multilayer printed circuit board, and Wherein, the second substrate comprises a coreless multilayer printed circuit board.

20. The printed circuit board according to claim 12, further comprising: a first anti-etching layer disposed on the lower side of the first substrate; as well as a second anti-etching layer disposed on the upper side of the second substrate, wherein the first anti-etching layer has a plurality of first openings, each of the plurality of first openings exposing at least a portion of the first wiring layer disposed on the lowermost side of the plurality of first wiring layers, and The second etching resist layer has a plurality of second openings, each of the plurality of second openings exposing at least a portion of the second wiring layer disposed on the uppermost side of the plurality of second wiring layers.

21. The printed circuit board according to claim 20, further comprising: a plurality of first connection metal members, respectively disposed in the plurality of first openings and each connected to at least a portion of the first wiring layer disposed on the lowermost side; a plurality of second connection metal members, respectively disposed in at least a portion of the plurality of second openings, and each connected to at least a portion of the second wiring layer disposed on the uppermost side; as well as A semiconductor chip is provided on the second resist layer and is connected to the second wiring layer provided on the uppermost side through the plurality of second connection metal members.

22. A printed circuit board, comprising: A first substrate including a first wiring layer; A second substrate, disposed on the first substrate and comprising a second wiring layer; A metal layer, disposed between the first substrate and the second substrate; as well as a bonding layer, disposed between the first substrate and the second substrate, The line width of the wiring line with the smallest line width among the wiring lines of the second wiring layer is smaller than the line width of the wiring line with the smallest line width among the wiring lines of the first wiring layer.

23. The printed circuit board according to claim 22, wherein: A minimum distance among distances between wiring lines of the second wiring layer is smaller than a minimum distance among distances between wiring lines of the first wiring layer.

24. The printed circuit board according to claim 22, wherein: A minimum pitch among pitches of wiring pads of the second wiring layer is smaller than a minimum pitch among pitches of wiring pads of the first wiring layer.

25. The printed circuit board according to claim 22, further comprising: a heterogeneous metal layer disposed in the metal layer, The heterogeneous metal layer includes a metal different from that of the metal layer.

26. The printed circuit board according to claim 22, in, The bonding layer is disposed adjacent to the metal layer, and Wherein, the thickness of the bonding layer is the same as the thickness of the metal layer.

27. The printed circuit board according to claim 22, in, Each of the first substrate and the second substrate includes an organic material, and Wherein, the bonding layer comprises an inorganic material.

28. The printed circuit board according to claim 22, wherein: The metal layer includes nano-twinned copper.

29. A method for manufacturing a printed circuit board, the method comprising: preparing a first substrate including a plurality of first wiring layers and having a first metal layer formed on the outermost side; forming a first inorganic insulating film covering at least a portion of the first metal layer on the outermost side of the first substrate; preparing a second substrate including a plurality of second wiring layers and having a second metal layer formed on the outermost side; forming a second inorganic insulating film covering at least a portion of the second metal layer on the outermost side of the second substrate; as well as bonding the first substrate and the second substrate to each other, bonding the first inorganic insulating film and the second inorganic insulating film to each other, and bonding the first metal layer and the second metal layer to each other, Wherein, each of the first substrate and the second substrate includes an organic material.

30. The method of claim 29, wherein: When preparing the second substrate, a wiring density of at least one of the plurality of second wiring layers is greater than a wiring density of at least one of the plurality of first wiring layers.

31. The method of claim 29, wherein: In preparing the second substrate, at least one of the plurality of second wiring layers is formed to include a fine circuit pattern having a line / space of 2 μm / 2 μm or less.

32. The method of claim 29, further comprising: After forming the first inorganic insulating film, exposing a surface of the first metal layer by planarizing the first metal layer and the first inorganic insulating film; as well as After forming the second inorganic insulating film, a surface of the second metal layer is exposed by planarizing the second metal layer and the second inorganic insulating film.

33. The method of claim 32, wherein: The step of bonding the first substrate and the second substrate to each other includes: bringing the first inorganic insulating film and the second inorganic insulating film into contact with each other, and bringing the first metal layer and the second metal layer into contact with each other; bonding the first inorganic insulating film and the second inorganic insulating film to each other at a first temperature; and bonding the first metal layer and the second metal layer to each other at a second temperature, Wherein, the second temperature is higher than the first temperature.

34. The method of claim 32, wherein: The step of bonding the first substrate and the second substrate to each other includes: Applying a metal paste between the first metal layer and the second metal layer, the metal paste comprising a metal different from the first metal layer and the second metal layer; bringing the first inorganic insulating film and the second inorganic insulating film into contact with each other, and bringing the first metal layer and the second metal layer into contact with the metal paste; bonding the first inorganic insulating film and the second inorganic insulating film to each other at a first temperature; and bonding the first metal layer and the second metal layer to each other through the metal paste at a second temperature, Wherein, the second temperature is higher than the first temperature.

35. The method according to claim 29, in, The first substrate includes a plurality of first insulating layers, a plurality of first wiring layers respectively arranged on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers, and the second substrate includes a plurality of second insulating layers, a plurality of second wiring layers respectively arranged on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers, wherein at least one of the plurality of first insulating layers comprises an organic material, wherein at least one of the plurality of second insulating layers comprises an organic material, wherein, among the plurality of first wiring layers, the first wiring layer disposed on the uppermost side includes the first metal layer, and Among the plurality of second wiring layers, the second wiring layer disposed on the lowermost side includes the second metal layer.

36. A printed circuit board comprising: A first substrate includes a plurality of first insulating layers, a plurality of first wiring layers respectively arranged on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers; A second substrate, disposed on the first substrate, and comprising a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers; a metal layer disposed between the first substrate and the second substrate to connect a first via layer among the plurality of first via layers that is closest to the second substrate and a second via layer among the plurality of second via layers that is closest to the first substrate; as well as an insulating bonding layer disposed between the first substrate and the second substrate to connect the first substrate and the second substrate to each other, The first via layer closest to the second substrate among the plurality of first via layers and the second via layer closest to the first substrate among the plurality of second via layers taper in opposite directions.

37. The printed circuit board according to claim 36, wherein The metal layer includes a first metal layer disposed on an uppermost side of the first substrate and a second metal layer disposed on a lowermost side of the second substrate.

38. The printed circuit board according to claim 37, wherein: The first metal layer and the second metal layer are bonded to each other such that a side surface of the first metal layer and a side surface of the second metal layer are disposed to be offset from each other.

39. The printed circuit board according to claim 37, wherein: The first metal layer and the second metal layer are directly bonded to each other.

40. The printed circuit board according to claim 37, wherein: The metal layer further includes a third metal layer disposed between the first metal layer and the second metal layer and including a metal different from metals of the first metal layer and the second metal layer.

41. The printed circuit board according to claim 37, in, The thickness of the first metal layer is smaller than the thickness of each of the plurality of first wiring layers, and The thickness of the second metal layer is smaller than the thickness of each of the plurality of second wiring layers.

42. The printed circuit board of claim 36, wherein: The insulating bonding layer includes a material different from that of the plurality of first insulating layers and the plurality of second insulating layers.

43. The printed circuit board according to claim 36, wherein: A density of at least one of the plurality of second wiring layers is greater than a density of at least one of the plurality of first wiring layers.

44. A printed circuit board comprising: A first substrate includes a plurality of first insulating layers, a plurality of first wiring layers respectively arranged on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers; A second substrate, disposed on the first substrate, and comprising a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers; a metal layer disposed between the first substrate and the second substrate to connect a first via layer among the plurality of first via layers that is closest to the second substrate and a second via layer among the plurality of second via layers that is closest to the first substrate; as well as an insulating bonding layer disposed between the first substrate and the second substrate to connect the first substrate and the second substrate to each other, The outermost second via layer among the plurality of second via layers connected to the outermost second wiring layer among the plurality of second wiring layers has a tapered shape such that a width of the outermost second via layer increases in a direction toward the metal layer.

45. The printed circuit board according to claim 44, wherein The metal layer includes a first metal layer disposed on an uppermost side of the first substrate and a second metal layer disposed on a lowermost side of the second substrate.

46. ​​The printed circuit board according to claim 45, wherein The first metal layer and the second metal layer are directly bonded to each other.

47. The printed circuit board according to claim 45, wherein The metal layer further includes a third metal layer disposed between the first metal layer and the second metal layer and including a metal different from metals of the first metal layer and the second metal layer.

48. The printed circuit board of claim 44, wherein: The density of at least one wiring in the plurality of second wiring layers is greater than the density of at least one wiring in the plurality of first wiring layers.

49. The printed circuit board of claim 44, wherein: An outermost first via layer among the plurality of first via layers connected to an outermost first wiring layer among the plurality of first wiring layers has a tapered shape such that a width of the outermost first via layer increases in a direction toward the metal layer.

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