Printed circuit board and manufacturing method thereof

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a first substrate including a first antenna pattern; a second substrate disposed on the first substrate and including a second antenna pattern; the metal layer is arranged between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate. At least one of the first substrate and the second substrate has a cavity, at least a portion of the cavity is disposed between the first antenna pattern and the second antenna pattern, each of the first substrate and the second substrate includes an organic material, and the bonding layer includes an inorganic material.

Description

[0001] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0157808 filed on November 15, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0136405 filed on October 13, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board (eg, an antenna substrate) and a method of manufacturing the same. Background Art

[0003] With the commercialization of the fifth generation mobile communication technology (5G) and the rapid increase in data usage, the performance of antennas used for wireless communication has become increasingly important. In particular, phased array antennas have been widely used in various wireless communication environments (such as battlefields and base stations based on mobile devices (including smart phones)). In the case of phased array antennas, small-sized antennas can be designed in the form of patches, which can be arranged in parallel or in series, and can have the advantages of being able to transmit and receive data faster in the desired direction, and can also be miniaturized if necessary, so that with the introduction of 5G, phased array antennas have been adopted in mobile devices. Since the performance of patch antennas can be determined by the shape, structure and material properties of the antenna, they have been actively studied in relevant academic circles and companies. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board including an antenna pattern and having an air gap structure.

[0005] An aspect of the present disclosure is to provide a printed circuit board that can improve antenna performance.

[0006] An aspect of the present disclosure is to separately form a first substrate including a first antenna pattern and a second substrate including a second antenna pattern, form a cavity in at least one of the first substrate and the second substrate, and then combine the first substrate and the second substrate using hybrid metal bonding.

[0007] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a first antenna pattern; a second substrate disposed on the first substrate and including a second antenna pattern; a metal layer disposed between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate. At least one of the first substrate and the second substrate has a cavity having at least a portion disposed between the first antenna pattern and the second antenna pattern, each of the first substrate and the second substrate includes an organic material, and the bonding layer includes an inorganic material.

[0008] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a first antenna pattern; a second substrate disposed on the first substrate and including a second antenna pattern; a metal layer disposed between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate. At least one of the first substrate and the second substrate has a cavity, the cavity has at least a portion disposed between the first antenna pattern and the second antenna pattern, and at least a portion of a side surface of the metal layer has a step difference.

[0009] For example, according to an example embodiment, a method of manufacturing a printed circuit board includes: preparing a first substrate including a first antenna pattern and having a first metal layer formed on an outermost side of the first substrate; forming a first inorganic insulating film covering at least a portion of the first metal layer on the outermost side of the first substrate; preparing a second substrate including a second antenna pattern and having a second metal layer formed on an outermost side of the second substrate; forming a second inorganic insulating film covering at least a portion of the second metal layer on the outermost side of the second substrate; forming a cavity in at least one of the first substrate and the second substrate; and bonding the first substrate and the second substrate to each other so that the first inorganic insulating film and the second inorganic insulating film are bonded to each other and the first metal layer and the second metal layer are bonded to each other. Each of the first substrate and the second substrate includes an organic material.

[0010] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a first antenna pattern; a second substrate disposed on the first substrate and including a second antenna pattern; a metal layer disposed between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate and covering a side surface of the metal layer. At least one of the first substrate and the second substrate has a cavity having at least a portion disposed between the first antenna pattern and the second antenna pattern. The thickness of a portion of the bonding layer located between the first substrate and the cavity is less than the thickness of a portion of the bonding layer located between the first substrate and the second substrate.

[0011] For example, according to an example embodiment, a printed circuit board includes: a first substrate including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers, one of the plurality of first wiring layers including a first antenna pattern; a second substrate disposed on the first substrate and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers, one of the plurality of second wiring layers including a second antenna pattern; a metal layer disposed between the first substrate and the second substrate; and a bonding layer disposed between the first substrate and the second substrate and covering a side surface of the metal layer. At least one of the first substrate and the second substrate has a cavity having at least a portion disposed between the first antenna pattern and the second antenna pattern. A first via layer connected to the metal layer among the plurality of first via layers and a second via layer connected to the metal layer among the plurality of second via layers taper in opposite directions. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram illustrating an example of an electronic device system; Figure 2 is a plan view showing an example of an electronic device; Figure 3 is a cross-sectional view showing an example of a printed circuit board; Figure 4 is a cross-sectional view showing another example of a printed circuit board; FIG. 5A to FIG. 5D is shown with Figure 3 An enlarged cross-sectional view of various examples of mixed metal bonding corresponding to region A; Fig. 6A and Figure 6B are enlarged cross-sectional views showing various examples of interfaces in intermetallic bonding; 7A to 7E are plan views showing various examples of cavities; Figure 8 is a diagram illustrating an example of a method of manufacturing a printed circuit board; 9A to 9C is a cross-sectional view showing an example of a process of manufacturing a first substrate portion; FIG. 10A to FIG. 10E is a cross-sectional view showing an example of a process of manufacturing the second substrate portion; Fig.11is a cross-sectional view showing an example of bonding of a first substrate portion and a second substrate portion; Fig.12 is a cross-sectional view illustrating a process of mixed metal bonding according to example embodiments; Fig.13 is a graph illustrating temperature change of mixed metal bonding according to example embodiments; Fig.14 is a cross-sectional view illustrating another example of mixed metal bonding according to example embodiments; and Fig.15 is a cross-sectional view illustrating another example of mixed metal bonding according to example embodiments. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0014] Electronic Devices Figure 1 is a block diagram illustrating an example of an electronic device system.

[0015] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to the mainboard 1010. These components may be connected to other electronic components to be described below via various signal lines 1090.

[0016] The chip-related components 1020 may include memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0017] The network-related components 1030 may include components that are compatible with or communicate using protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G), Fourth Generation Mobile Communication Technology (4G) and Fifth Generation Mobile Communication Technology (5G) protocols, and any other wireless and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or communicating with various other wireless standards or protocols or other wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0018] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, the other electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. Depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0021] Figure 2 is a plan view showing an example of an electronic device.

[0022] Reference Figure 2 , the electronic device may be a smart phone 1100. A modem 1101, a rigid printed circuit board, a flexible printed circuit board, and / or various types of antenna substrates or modules 1102, 1103, 1104, 1105, and 1106 connected to the modem 1101 through a rigid-flexible printed circuit board may be provided in the smart phone 1100. If necessary, a WiFi substrate or module 1107 may also be provided. The antenna substrates or modules 1102, 1103, 1104, 1105, and 1106 may include antenna substrates or modules for various frequency bands for 5G mobile communication, for example, an antenna substrate or module 1102 for a 3.5 GHz band frequency, an antenna substrate or module 1103 for a 5 GHz band frequency, an antenna substrate or module 1104 for a 28 GHz band frequency, and an antenna substrate or module 1105 for a 39 GHz band frequency, and may further include another 4G antenna substrate or module 1106, but example embodiments thereof are not limited thereto. The electronic device may not necessarily be limited to the smart phone 1100 , and may be implemented as other electronic devices as described above.

[0023] Printed Circuit Board Figure 3 is a cross-sectional view showing an example of a printed circuit board.

[0024] Reference Figure 3, a printed circuit board 500 according to an example may include: a first substrate 100 including a first antenna pattern P1 and a first metal layer M1 disposed on an upper side thereof; a second substrate 200 disposed on the first substrate 100, including a second antenna pattern P2, and including a second metal layer M2 disposed on a lower side thereof; and a bonding layer 300 disposed between the first substrate 100 and the second substrate 200, and burying at least a portion of each of the first metal layer M1 and the second metal layer M2. Each of the first substrate 100 and the second substrate 200 may include an organic material. The bonding layer 300 may include an inorganic material. At least one of the first substrate 100 and the second substrate 200 may have a cavity C. For example, the second substrate 200 may have a cavity C having at least a portion disposed between the first antenna pattern P1 and the second antenna pattern P2. The first metal layer M1 and the second metal layer M2 may be bonded to each other using mixed metal bonding. For example, the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be bonded to each other. The first metal layer M1 and the second metal layer M2 may be combined with each other and may be integrated into the metal layer M. The boundary between the first metal layer M1 and the second metal layer M2 may be obvious or may be indistinct. The bonding layer 300 may be disposed adjacent to the metal layer M. In the present disclosure, the metal layer M may also be regarded as a portion independent of the first substrate 100 and the second substrate 200.

[0025] In a general patch antenna substrate or module structure, the size and performance of the antenna may be closely related to the dielectric constant of the material forming the antenna. In this case, since the antenna substrate or module can generally be manufactured by the process of manufacturing a printed circuit board, the dielectric constant of the material may ultimately be limited to the dielectric constant of the material of the printed circuit board. Generally, when the dielectric constant of the material forming the antenna is low, the antenna performance can be improved, so that materials with low dielectric constants may generally be preferred, but there may be a problem of increased antenna size, so it is not necessary to use low-κ materials. However, because the size of the antenna can be reduced according to the design and structural characteristics of the patch, it may be desirable to use low-κ materials to improve the performance of the antenna. Therefore, it may be necessary to improve the performance of the antenna by providing a low dielectric constant while using the same general material for the printed circuit board.

[0026] Furthermore, in a patch antenna structure, generally, when the dielectric constant of the substrate material is relatively high, the size of the antenna can be reduced, in which case the bandwidth of the antenna can also be reduced. When the dielectric constant of the substrate material is low, the size of the antenna can be increased and the bandwidth of the antenna can be increased. Therefore, in the case of a patch antenna, it may be necessary to find an optimal point that can increase the bandwidth while reducing the size. For example, a low-κ material for the substrate can be used to reduce the size by modifying the patch design in various ways.

[0027] The dielectric constant of the low-κ material of the substrate may be higher than the dielectric constant of air. For example, the dielectric constant of a material may be expressed as a number proportional to 1 (the dielectric constant in a vacuum state), and therefore, the dielectric constant of a material may be close to 1 but not 1, and air may be a substance having a dielectric constant closest to 1. Therefore, when manufacturing an antenna substrate or module, when manufacturing an air gap structure having an area corresponding to a patch antenna, the dielectric constant may be reduced to close to 1 in a portion where the air gap is formed, regardless of the insulating material of the substrate, and therefore, the highest bandwidth may be achieved.

[0028] From this point of view, in the printed circuit board 500 according to the example, the first antenna pattern P1 and the second antenna pattern P2 may include a coupling pattern and a patch pattern, respectively, and the cavity C formed on the second substrate 200 may be arranged between the patch pattern and the coupling pattern, and at least a portion of the cavity C may be filled with air. Therefore, when the first substrate 100 and the second substrate 200 are bonded to each other by hybrid metal bonding, an antenna substrate or a module structure having an air gap structure may be provided, and thus, excellent antenna characteristics may be achieved. Specifically, by freely forming the cavity C based on the shape or size of the first antenna pattern P1 and the second antenna pattern P2, the degree of freedom in designing the air gap may be increased and the antenna performance may be improved. In addition, since the first substrate 100 and the second substrate 200 are bonded to each other by hybrid metal bonding using the bonding layer 300 and the metal layer M, the total thickness of the substrate may be reduced, the bonding reliability may be improved, and since another bonding pad may not need to be formed, the degree of freedom in design may be increased.

[0029] Hereinafter, components of a printed circuit board 500 according to an example will be described in more detail with reference to the accompanying drawings.

[0030] The first substrate 100 may be configured as a multilayer printed circuit board. For example, the first substrate 100 may include a plurality of first insulating layers 111, 112, and 113, a plurality of first wiring layers 121, 122, 123, and 124 respectively disposed on or in the plurality of first insulating layers 111, 112, and 113, and a plurality of first via layers 131, 132, and 133 respectively penetrating the plurality of first insulating layers 111, 112, and 113. At least one of the plurality of first insulating layers 111, 112, and 113 may include an organic material. At least one of the plurality of first wiring layers 121, 122, 123, and 124 may include a first antenna pattern P1. Each of the plurality of first wiring layers 121, 122, 123, and 124 may include a feeding pattern. Each of the plurality of first via layers 131, 132, and 133 may include a feeding via. Among the plurality of first wiring layers 121, 122, 123, and 124, the 1-3 wiring layer 123 disposed on the uppermost side may include the first metal layer M1. The first substrate 100 may be configured as a core type multilayer substrate including the 1-1 insulating layer 111 as a core layer, or may also be configured as a coreless type multilayer substrate not including a core layer.

[0031] Each of the plurality of first insulating layers 111, 112, and 113 may be configured as an organic insulating layer. For example, the plurality of first insulating layers 111, 112, and 113 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material containing a thermosetting resin or a thermoplastic resin and an inorganic filler, an organic filler, and / or glass fiber (such as glass fabric (e.g., glass cloth)). For example, the organic insulating material may be a non-photosensitive insulating material (such as a copper clad laminate (CCL), an Ajinomoto build-up film (ABF), or a prepreg (PPG)), but example embodiments thereof are not limited thereto, and other polymer materials may be used. For example, thermoplastic resins such as polyimide (PI), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyphenylene sulfide (PPS), polyphenylene ether (PPE), and modified polyester, or thermosetting resins such as modified polyimide and modified epoxy resin may be used. If desired, at least one of the plurality of first insulating layers 111, 112, and 113 (e.g., 1-1 insulating layer 111) may include other types of insulating materials other than organic insulating materials, such as glass and ceramics. Even in this case, the other 1-2 insulating layers 112 and 1-3 insulating layers 113 may include organic insulating materials. The 1-1 insulating layer 111 may be configured as a core layer, and each of the 1-2 insulating layer 112 and the 1-3 insulating layer 113 may be a buildup layer. The thickness of the 1-1 insulating layer 111 may be greater than the thickness of the 1-2 insulating layer 112 and the thickness of the 1-3 insulating layer 113, respectively.

[0032] Each of the plurality of first wiring layers 121, 122, 123, and 124 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but exemplary embodiments thereof are not limited thereto. Each of the plurality of first wiring layers 121, 122, 123, and 124 may perform various functions according to design. For example, a signal pattern, a power pattern, and a ground pattern may be included. Each of the patterns may have various forms, such as a line form, a plane form, and a pad form. The plurality of first wiring layers 121, 122, 123, and 124 may include a seed layer and a plating layer formed on the seed layer, respectively. The seed layer may be an electroless plating layer (e.g., a chemical copper plating layer) and / or a sputtering layer, and the plating layer may be an electroplating layer (e.g., an electroplated copper layer), but exemplary embodiments thereof are not limited thereto. The 1-1 wiring layer 121 and the 1-2 wiring layer 122 may be respectively disposed on the upper and lower surfaces of the 1-1 insulating layer 111, and the 1-3 wiring layer 123 and the 1-4 wiring layer 124 may be respectively disposed on the upper and lower surfaces of the 1-2 insulating layer 112 and 1-3 insulating layer 113, but example embodiments thereof are not limited thereto.

[0033] The first antenna pattern P1 may include a coupling pattern. The coupling pattern may be disposed on the lower side of the air gap and the patch pattern. For example, the coupling pattern may overlap at least a portion of the air gap and at least a portion of the patch pattern on a plane. Through electromagnetic coupling between the coupling pattern and the patch pattern, an additional resonant frequency close to the natural resonant frequency may be obtained, and thus a wider bandwidth may be obtained.

[0034] The first metal layer M1 may include various types of conductor patterns. For example, the first metal layer M1 may include conductor patterns such as lines, pads, and planes. The first metal layer M1 may be disposed at a position substantially corresponding to the second metal layer M2, and the conductor pattern of the first metal layer M1 may have a shape substantially corresponding to the conductor pattern of the second metal layer M2. The 1-3 wiring layer 123 including the first metal layer M1 may be planarized as in a process described later, and thus may have a thickness smaller than the thickness of the other 1-1 wiring layer 121, the thickness of the 1-2 wiring layer 122, and the thickness of the 1-4 wiring layer 124. For example, the thickness of the first metal layer M1 may be smaller than the thickness of the first antenna pattern P1.

[0035] Each of the plurality of first via layers 131, 132, and 133 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but the exemplary embodiment thereof is not limited thereto. Each of the plurality of first via layers 131, 132, and 133 may include a filled via that fills the via hole, or may also include a conformal via formed along the wall surface of the via hole. The plurality of first via layers 131, 132, and 133 may perform various functions according to the design. For example, a ground via, a power via, and a signal via may be included. The plurality of first via layers 131, 132, and 133 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplating copper layer), respectively. A sputtering layer may be included instead of the electroless plating layer (e.g., the chemical copper plating layer), or if necessary, a sputtering layer and an electroless plating layer may be included. The 1-1 via layer 131 may have an hourglass shape or a pillar shape in cross section. The 1-2 via layer 132 and the 1-3 via layer 133 may have shapes tapered in opposite directions in cross section.

[0036] The second substrate 200 may be configured as a multilayer printed circuit board. For example, the second substrate 200 may have a plurality of second insulating layers 211, 212, and 213, a plurality of second wiring layers 221, 222, 223, and 224 respectively disposed on or in the plurality of second insulating layers 211, 212, and 213, and a plurality of second via layers 231, 232, and 233 respectively penetrating the plurality of second insulating layers 211, 212, and 213. At least one of the plurality of second insulating layers 211, 212, and 213 may include an organic material. At least one of the plurality of second wiring layers 221, 222, 223, and 224 may include a second antenna pattern P2. Each of the plurality of second wiring layers 221, 222, 223, and 224 may include a feeding pattern. Each of the plurality of second via layers 231, 232, and 233 may include a feeding via. Among the plurality of second wiring layers 221, 222, 223, and 224, the 2-3 wiring layer 223 disposed on the lowermost side may include the second metal layer M2. The second substrate 200 may be configured as a core-type multilayer substrate including the 2-1 insulating layer 211 as a core layer, or may also be configured as a coreless multilayer substrate not including a core layer.

[0037] Each of the plurality of second insulating layers 211, 212, and 213 may be an organic insulating layer. For example, the plurality of second insulating layers 211, 212, and 213 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material containing a thermosetting resin or a thermoplastic resin and an inorganic filler, an organic filler, and / or glass fiber (such as glass fabric (e.g., glass cloth)). For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto deposited film (ABF), or a prepreg (PPG), but the exemplary embodiments thereof are not limited thereto, and other polymer materials may be used. For example, thermoplastic resins such as polyimide (PI), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyphenylene sulfide (PPS), polyphenylene ether (PPE), and modified polyester, or thermosetting resins such as modified polyimide and modified epoxy resin may be used. If desired, at least one of the plurality of second insulating layers 211, 212, and 213 (e.g., the 2-1 insulating layer 211) may include other types of insulating materials other than organic insulating materials, such as glass and ceramics. However, even in this case, the other 2-2 insulating layers 212 and 2-3 insulating layers 213 may include organic insulating materials. The 2-1 insulating layer 211 may be a core layer, and each of the 2-2 insulating layer 212 and the 2-3 insulating layer 213 may be a buildup layer. The thickness of the 2-1 insulating layer 211 may be greater than the thickness of each of the 2-2 insulating layer 212 and the 2-3 insulating layer 213.

[0038] Each of the plurality of second wiring layers 221, 222, 223, and 224 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but exemplary embodiments thereof are not limited thereto. Each of the plurality of second wiring layers 221, 222, 223, and 224 may perform various functions according to design. For example, a signal pattern, a power pattern, and a ground pattern may be included. Each of the patterns may have various forms, such as a line form, a plane form, and a pad form. The plurality of second wiring layers 221, 222, 223, and 224 may include a seed layer and a plating layer formed on the seed layer, respectively. The seed layer may be an electroless plating layer (e.g., a chemical copper plating layer) and / or a sputtering layer, and the plating layer may be an electroplating layer (e.g., an electroplated copper layer), but exemplary embodiments thereof are not limited thereto. The 2-1 wiring layer 221 and the 2-2 wiring layer 222 may be respectively disposed on the lower surface and the upper surface of the 2-1 insulating layer 211, and the 2-3 wiring layer 223 and the 2-4 wiring layer 224 may be respectively disposed on the lower surface of the 2-2 insulating layer 212 and the upper surface of the 2-3 insulating layer 213, but example embodiments thereof are not limited thereto.

[0039] The second antenna pattern P2 may include a patch pattern. The patch pattern may receive an RF signal through a feeding pattern and a feeding via in the first substrate 100 and the second substrate 200, and may transmit a signal in the thickness direction. The RF signal received in the thickness direction may be transmitted to an electronic component (such as a radio frequency integrated circuit (RFIC)) mounted on the substrate through the feeding pattern and the feeding via in the first substrate 100 and the second substrate 200. The patch pattern may have an inherent resonant frequency (e.g., 28 GHz, 39 GHz, etc.) depending on inherent factors (such as the shape of the pattern, the size of the pattern, the dielectric constant of the insulating layer, and the dielectric constant of the air gap). For example, the patch pattern may be electrically connected to a radio frequency integrated circuit (RFIC), and may transmit and receive, for example, a horizontal pole (H pole) RF signal and a vertical pole (V pole) RF signal polarized to each other.

[0040] The second metal layer M2 may include various types of conductor patterns. For example, the second metal layer M2 may include conductor patterns such as lines, pads, and planes. The second metal layer M2 may be disposed at a position substantially corresponding to the first metal layer M1, and the conductor pattern of the second metal layer M2 may have a shape substantially corresponding to the conductor pattern of the first metal layer M1. The 2-3 wiring layer 223 including the second metal layer M2 may be planarized as in a process described later, and thus may have a thickness smaller than the thickness of each of the other 2-1 wiring layers 221, 2-2 wiring layers 222, and 2-4 wiring layers 224. For example, the thickness of the second metal layer M2 may be smaller than the thickness of the second antenna pattern P2.

[0041] Each of the plurality of second via layers 231, 232, and 233 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but the exemplary embodiment thereof is not limited thereto. Each of the plurality of second via layers 231, 232, and 233 may include a filled via that fills the via hole, but may also include a conformal via formed along the wall surface of the via hole. The plurality of second via layers 231, 232, and 233 may perform various functions according to the design. For example, a ground via, a power via, and a signal via may be included. The plurality of second via layers 231, 232, and 233 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplating copper layer), respectively. A sputtering layer may be included instead of the electroless plating layer (e.g., a chemical copper plating layer), or if necessary, a sputtering layer and an electroless plating layer may be included. The 2-1 via layer 231 may have an hourglass shape or a pillar shape in cross section. The 2-2 via layer 232 and the 2-3 via layer 233 may have shapes tapered in opposite directions in cross section.

[0042] Among the plurality of first via layers 131, 132, and 133, the 1-2 via layer 132 disposed on the uppermost side may include a first connection via connected to the first metal layer M1, and among the plurality of second via layers 231, 232, and 233, the 2-2 via layer 232 disposed on the lowermost side may include a second connection via connected to the second metal layer M2. The first connection via and the second connection via may taper in opposite directions. For example, in a cross section, the width of the upper end of the first connection via may be wider than the width of the lower end. In a cross section, the width of the lower end of the second connection via may be wider than the width of the upper end.

[0043] The bonding layer 300 may include an insulating material for mixed metal bonding. For example, the bonding layer 300 may include an inorganic insulating material. The inorganic insulating material may include, for example, an inorganic oxide film or an inorganic nitride film, and more specifically, the material may include at least one of SiO2, SiN, and SiCN, but its example embodiments are not limited thereto. The bonding layer 300 may cover at least a portion of each of the first metal layer M1 and the second metal layer M2. For example, the bonding layer 300 may cover at least a portion of the side surface of each of the first metal layer M1 and the second metal layer M2. However, the bonding layer 300 may be spaced apart from the lower surface of the first metal layer M1 and the upper surface of the second metal layer M2. In an area where the cavity C is not formed (for example, in an area that does not overlap with the cavity C on a plane), the thickness of the bonding layer 300 may be substantially the same as the thickness of the metal layer M.

[0044] The cavity C may be disposed between the first antenna pattern P1 and the second antenna pattern P2, and an air gap structure may be provided. For example, at least a portion of the cavity C may be filled with air. The cavity C may penetrate a portion of the second substrate 200. For example, the cavity C may penetrate the 2-2 insulating layer 212. However, its exemplary embodiment is not limited thereto, and if necessary, the cavity C may further penetrate at least a portion of the 2-1 insulating layer 211 and / or at least a portion of the 2-3 insulating layer 213. For example, the depth of the air gap may be freely adjusted. In addition, the cavity C may penetrate a portion of the bonding layer 300. Therefore, the bottom surface of the cavity C may be formed by the bonding layer 300, and the wall surface of the cavity C may expose a portion of the side surface of the bonding layer 300, but its exemplary embodiment is not limited thereto. From this point of view, the thickness of the portion of the bonding layer 300 located between the first substrate 100 and the cavity C may be less than the thickness of the portion of the bonding layer 300 located between the first substrate 100 and the second substrate 200, but its exemplary embodiment is not limited thereto.

[0045] Figure 4 is a cross-sectional view showing another example of a printed circuit board.

[0046] Reference Figure 4, the printed circuit board 600 according to another example may further include a semiconductor chip 400 mounted on the lower side of the first substrate 100 in the printed circuit board 500 according to the above example. For example, the printed circuit board 500 according to the example may have an antenna substrate structure, and the printed circuit board 600 according to another example may have an antenna module structure including the antenna substrate structure. The semiconductor chip 400 may be connected to the 1-4 wiring layers 124 of the first substrate 100 through the connecting member 450.

[0047] There may be one or more semiconductor chips 400 , and the one or more semiconductor chips 400 may include a radio frequency integrated circuit (RFIC), a power management IC (PMIC), etc. If necessary, chip passive components (e.g., chip capacitors or chip inductors) may also be mounted on the lower side of the first substrate 100 together with the semiconductor chips 400 .

[0048] The connection member 450 may be formed using a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), but this is only an example, and the material is not limited thereto. The connection member 450 may be a ball, a pin, etc. The connection member 450 may include a plurality of layers or a single layer. When the connection member 450 includes a plurality of layers, a copper column and a solder may be included, and when the connection member 450 includes a single layer, a tin-silver solder may be included, but example embodiments thereof are not limited thereto. A plurality of connection members 450 may be included, and the number of the connection members 450 is not limited to any particular example.

[0049] The other description may be substantially the same as the description of the printed circuit board 500 according to the above-described example. Therefore, a repeated description may not be provided.

[0050] FIG. 5A to FIG. 5D is shown with Figure 3 Region A corresponds to an enlarged cross-sectional view of various examples of mixed metal bonding.

[0051] Reference Figure 5A, the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be directly bonded to each other. For example, the metal layer M may be formed by directly bonding the first metal layer M1 and the second metal layer M2 to each other. The boundary between the first metal layer M1 and the second metal layer M2 may be obvious. The first metal layer M1 may include a 1-1 metal layer m1-1 as a seed layer and a 1-2 metal layer m1-2 as a plating layer. The second metal layer M2 may include a 2-1 metal layer m2-1 as a seed layer and a 2-2 metal layer m2-2 as a plating layer. Each of these layers may include the above-mentioned metal, preferably copper (Cu), but the exemplary embodiment thereof is not limited thereto. The bonding layer 300 may include a first insulating film 310 and a second insulating film 320. The first insulating film 310 and the second insulating film 320 may be inorganic insulating films. These films may include the above-mentioned inorganic insulating material, preferably SiO2, but the exemplary embodiment thereof is not limited thereto. The first insulating film 310 may be disposed on the upper side of the first substrate 100 and may cover at least a portion of the side surface of the first metal layer M1. The second insulating film 320 may be disposed on the lower side of the second substrate 200 and may cover at least a portion of the side surface of the second metal layer M2. The boundary between the first insulating film 310 and the second insulating film 320 may be inconspicuous, for example, these films may be integrated with each other. The first metal layer M1 and the second metal layer M2 and the first insulating film 310 and the second insulating film 320 may be bonded to each other by mixed metal bonding. The upper surface of the first metal layer M1 and the upper surface of the first insulating film 310 may be coplanar with each other, and the lower surface of the second metal layer M2 and the lower surface of the second insulating film 320 may be coplanar with each other, but the example embodiment is not limited thereto. The bonding structure may be applied to the printed circuit board 500 according to the above example and the printed circuit board 600 according to another example.

[0052] Reference Figure 5B , the first metal layer M1 and the second metal layer M2 may be bonded to each other so that the side surface of the first metal layer M1 and the side surface of the second metal layer M2 may be offset from each other. For example, at least a portion of the side surface of the metal layer M may have a step difference. Here, the step difference may include a step difference between vertical side surfaces and a step difference between curved side surfaces having a shape that bends outward or inward. For example, even when the side surface of the metal layer M is S-shaped, a step difference can be obtained when the upper and lower ends of the metal layer M are sufficiently offset from each other. For example, the step difference may be a step difference caused by misalignment between the first metal layer M1 and the second metal layer M2 when bonding, and may be different from a simple unevenness (such as surface roughness) formed on the side surface. In this case, the bonding layer 300 may also cover at least a portion of each of the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2. Therefore, improved adhesion can be obtained. Therefore, reliability can also be improved. Other descriptions and Figure 5AThe bonding structure is the same as described in the bonding structure of FIG. The bonding structure can also be applied to the printed circuit board 500 according to the above example and the printed circuit board 600 according to another example.

[0053] Reference Figure 5C , the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be bonded to each other through a third metal layer M3 including a metal different from the first metal layer M1 and the second metal layer M2. For example, a heterogeneous third metal layer M3 may be provided in the metal layer M. For example, the first metal layer M1 and the second metal layer M2 may include copper (Cu), and the third metal layer M3 may include silver (Ag) and / or gold (Au), but example embodiments thereof are not limited thereto. When the third metal layer M3 is used, the adhesion between the first metal layer M1 and the second metal layer M2 may be improved. Other descriptions may be similar to Figure 5A The bonding structure is the same as described in the bonding structure of FIG. The bonding structure can also be applied to the printed circuit board 500 according to the above example and the printed circuit board 600 according to another example.

[0054] Reference Figure 5D, the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may be bonded to each other through a third metal layer M3 including a metal different from the first metal layer M1 and the second metal layer M2. For example, a heterogeneous third metal layer M3 may be provided in the metal layer M. For example, the first metal layer M1 and the second metal layer M2 may include copper (Cu), and the third metal layer M3 may include silver (Ag) and / or gold (Au). In this case, the adhesion between the first metal layer M1 and the second metal layer M2 may be improved. In addition, the first metal layer M1 and the second metal layer M2 may be bonded to each other so that the side surface of the first metal layer M1 and the side surface of the second metal layer M2 may be offset from each other. For example, at least a portion of the side surface of the metal layer M may have a step difference. Here, the step difference may include a step difference between vertical side surfaces and a step difference between curved side surfaces having a shape that is bent outward or inward. For example, even when the side surface of the metal layer M is S-shaped, the step difference may be obtained when the upper end and the lower end of the metal layer M are sufficiently offset from each other. For example, the step difference may refer to a step difference caused by misalignment between the first metal layer M1 and the second metal layer M2 during bonding, and the step difference may be distinguished from unevenness (such as surface roughness) formed on the side surface. In this case, the bonding layer 300 may also cover at least a portion of each of the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2, and thus, adhesion and reliability may be improved. In addition, at least a portion of the third metal layer M3 may be set to deviate from at least one of the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2. For example, a portion of the third metal layer M3 may be set to extend beyond the upper surface of the first metal layer M1, in which case a portion of the lower surface of the third metal layer M3 may contact the bonding layer 300, and adhesion may be improved. Alternatively, for example, a portion of the third metal layer M3 may be set to extend beyond the lower surface of the second metal layer M2, in which case a portion of the upper surface of the third metal layer M3 may contact the bonding layer 300, and adhesion may be improved. Other descriptions may be related to Figure 5A The bonding structure is the same as described in the bonding structure of FIG. The bonding structure can also be applied to the printed circuit board 500 according to the above example and the printed circuit board 600 according to another example.

[0055] Fig. 6A and Figure 6B are enlarged cross-sectional views showing various examples of interfaces in intermetallic bonding.

[0056] Reference Fig. 6AIn the case where the first metal layer M1 and the second metal layer M2 are directly bonded to each other through mixed metal bonding, the first metal layer M1 and the second metal layer M2 may include a plurality of first crystal grains g1 and a plurality of second crystal grains g2, respectively. In this case, in the metal-to-metal bonding interface between the first metal layer M1 and the second metal layer M2, the plurality of first crystal grains g1 and the plurality of second crystal grains g2 may include, for example, a plurality of triple junctions of approximately 90 degrees. The metal-to-metal bonding interface may be applied to the printed circuit board 500 according to the above example and the printed circuit board 600 according to another example.

[0057] Reference Figure 6B , due to the reduced surface energy of the grain boundaries, the interface of the metal-to-metal bonding may have a diffusion wedge. For example, the interface between the upper surface of the first metal layer M1 and the lower surface of the second metal layer M2 may have at least one protrusion v protruding toward the inside of at least one of the first metal layer M1 and the second metal layer M2, and the protrusion v may include a diffusion wedge caused by the diffusion of metal particles. For example, in the metal-to-metal bonding interface between the first metal layer M1 and the second metal layer M2, the plurality of first crystal grains g1 and the plurality of second crystal grains g2 may include a plurality of trifurcated crystal boundaries (e.g., approximately 120 degrees). The metal-to-metal bonding interface may also be applied to the printed circuit board 500 according to the above example and the printed circuit board 600 according to another example.

[0058] 7A to 7E are plan views showing various examples of cavities.

[0059] Reference 7A to 7E In the plane, the cavity C may have various shapes, such as a rectangular shape, a circular shape, a "shape," " shape, a shape in which an island o is provided in a rectangular or circular space. In this case, the island o may be formed by the 2-2 insulating layer 212 and may be spaced apart from the wall surface of the cavity C. Here, the wall surface may be a surface providing an edge of the cavity C on a plane. In addition, a plurality of cavities C may be formed. In this way, the cavity C serving as an air gap may be formed in various shapes without any particular limitation, and thus, the antenna performance may be improved. For ease of description, components other than the 2-2 insulating layer 212 and the cavity C may be omitted. The cavity C having the above shape may be applied to the printed circuit board 500 according to the above example and the printed circuit board 600 according to another example.

[0060] Figure 8 is a diagram illustrating an example of a method of manufacturing a printed circuit board.

[0061] Reference Figure 8, according to the example, the method of manufacturing a printed circuit board may include: forming a first substrate portion (S1); forming a second substrate portion (S2); and combining the first substrate portion and the second substrate portion (S3). Forming the first substrate portion (S1) may include: preparing a first substrate including a first antenna pattern and a first metal layer (S1-1); forming a first insulating film covering the first metal layer on the first substrate (S1-2); and exposing the first metal layer (S1-3). Forming the second substrate portion (S2) may include: preparing a second substrate including a second antenna pattern and a second metal layer (S2-1); forming a second insulating film covering the second metal layer on the second substrate (S2-2); forming a cavity in the second substrate (S2-3); and exposing the second metal layer (S2-4).

[0062] Hereinafter, a method of manufacturing a printed circuit board according to examples will be described in more detail with reference to the accompanying drawings.

[0063] 9A to 9C is a cross-sectional view showing an example of a process of manufacturing the first substrate section.

[0064] Reference Fig.9A , a first substrate 100 including a first antenna pattern P1 and having a first metal layer M1 formed on one side may be prepared. The first substrate 100 may be configured as a multi-layer organic substrate as described above. The first substrate 100 may be formed using a substrate process such as a double-sided build-up process or a coreless process.

[0065] Reference Fig. 9B , a first insulating film 310 covering at least a portion of the first metal layer M1 may be formed on one side of the first substrate 100. As described above, the first insulating film 310 may be an inorganic insulating film. The first insulating film 310 may be formed by a coating process such as deposition. The first insulating film 310 may conformally cover the first substrate 100, but example embodiments thereof are not limited thereto.

[0066] Reference Fig. 9C , the surface of the first metal layer M1 may be exposed by planarizing the first metal layer M1 and the first insulating film 310. A grinding process may be used as a planarization process. Through the planarization process, the thickness of the first metal layer M1 and the thickness of the first insulating film 310 may become substantially the same. In addition, the thickness of the first metal layer M1 may be smaller than the thickness of each of the other 1-1 wiring layer 121, 1-2 wiring layer 122, and 1-4 wiring layer 124.

[0067] Through a series of processes, the first substrate portion 100 - 1 may be prepared. Other descriptions may be substantially the same as those of the printed circuit board 500 according to the above-described example, and a repeated description will not be provided.

[0068] FIG. 10A to FIG. 10Eis a cross-sectional view showing an example of a process of manufacturing the second substrate section.

[0069] Reference Fig. 10A , a second substrate 200 including a second antenna pattern P2 and having a second metal layer M2 formed on one side thereof may be prepared. The second substrate 200 may be a multi-layer organic substrate as described above. The second substrate 200 may be formed using a substrate process such as a double-sided build-up process or a coreless process.

[0070] Reference Fig. 10B , a second insulating film 320 covering at least a portion of the second metal layer M2 may be formed on one side of the second substrate 200. As described above, the second insulating film 320 may be an inorganic insulating film. The second insulating film 320 may be formed by a coating process such as deposition. The second insulating film 320 may conformally cover the second substrate 200, but example embodiments thereof are not limited thereto.

[0071] Reference Fig. 10C , a cavity C' may be formed on the second substrate 200. For example, a cavity C' may be formed that penetrates the second insulating film 320 and also penetrates a portion of the second substrate 200. The cavity C' may be formed by various methods such as a sandblasting process or a laser process. If necessary, the cavity C' may be formed on the first substrate 100.

[0072] Reference Fig. 10D , the barrier layer S can be removed (such as FIG. 10A to FIG. 10C ). The barrier layer S may be removed by chemical etching. Alternatively, the barrier layer S may be removed by grinding. For example, the barrier layer S may be removed during a planarization process (such as a grinding process) to be described later. If necessary, the barrier layer S may not be provided, in which case the process of removing the barrier layer S may not be performed. When the barrier layer S is removed, a cavity C having a greater depth may be formed.

[0073] Reference Fig.10E By planarizing the second metal layer M2 and the second insulating film 320, the surface of the second metal layer M2 can be exposed. A grinding process can be used as a planarization process. Through the planarization process, the thickness of the second metal layer M2 and the thickness of the second insulating film 320 can become substantially the same. In addition, the thickness of the second metal layer M2 can be less than the thickness of each of the other 2-1 wiring layer 221, 2-2 wiring layer 222, and 2-4 wiring layer 224.

[0074] Through a series of processes, the second substrate portion 200 - 1 may be prepared. Other descriptions may be substantially the same as those of the printed circuit board 500 according to the above-described example, and a repeated description will not be provided.

[0075] Fig.11 is a cross-sectional view showing an example of bonding of the first substrate portion and the second substrate portion.

[0076] Reference Fig.11 , the first substrate portion 100-1 and the second substrate portion 200-1 may be bonded to each other by bonding the first insulating film 310 and the second insulating film 320 to each other, and bonding the first metal layer M1 and the second metal layer M2 to each other. In order to bond the first insulating film 310 and the second insulating film 320 to each other and bond the first metal layer M1 and the second metal layer M2 to each other, a hybrid metal bonding described later may be used.

[0077] Through a series of processes, the printed circuit board 500 according to the above-described example may be manufactured. Other descriptions may be substantially the same as those of the printed circuit board 500 according to the above-described example, and a repeated description will not be provided.

[0078] Fig.12 is a cross-sectional view illustrating a process of mixed metal bonding according to example embodiments.

[0079] Fig.13 is a graph indicating temperature variation of mixed metal bonding according to example embodiments.

[0080] Reference Fig.12 and Fig.13 , the first insulating film 310 and the second insulating film 320 may be brought into contact with each other, and the first metal layer M1 and the second metal layer M2 may also be brought into contact with each other. Before the contact, the surfaces of the first insulating film 310 and the second insulating film 320 and the first metal layer M1 and the second metal layer M2 may be processed by wet cleaning or plasma activation. In this case, a recess may be formed in the surface of each of the first metal layer M1 and the second metal layer M2. The first insulating film 310 and the second insulating film 320 may be brought into contact with each other and the first metal layer M1 and the second metal layer M2 may be brought into contact with each other at room temperature (RT). Thereafter, the first insulating film 310 and the second insulating film 320 may be bonded to each other at a first temperature T1. For example, at the first temperature T1, the first insulating film 310 and the second insulating film 320 may be directly bonded to each other and may be integrated into a bonding layer 300. The first temperature T1 may be lower than the second temperature T2. Thereafter, the first metal layer M1 and the second metal layer M2 may be bonded to each other at the second temperature T2. For example, at the second temperature T2, the first metal layer M1 and the second metal layer M2 may be directly bonded to each other, and the metal layer M may be formed. For example, during the annealing process at the second temperature T2, the first metal layer M1 and the second metal layer M2 may be bonded to each other by increasing the grain size of the metal. The second temperature T2 may be a temperature higher than the first temperature T1. When the first insulating film 310 and the second insulating film 320 are bonded to each other and the first metal layer M1 and the second metal layer M2 are bonded to each other, the bottom surface of the cavity C may be formed with the bonding layer 300 (e.g., the second insulating film 320).

[0081] Through a series of processes, the first substrate part 100-1 and the second substrate part 200-1 described above may be combined with each other. Other descriptions may be substantially the same as the description of the printed circuit board 500 according to the above example, and a repeated description will not be provided.

[0082] Fig.14 is a cross-sectional view illustrating another example of mixed metal bonding according to example embodiments.

[0083] Reference Fig.14 , combining the first substrate portion 100-1 and the second substrate portion 200-1 with each other may further include applying a metal paste M3' including a metal different from the first metal layer M1 and the second metal layer M2 between the first metal layer M1 and the second metal layer M2. For example, before allowing the first insulating film 310 and the second insulating film 320 to contact each other and the first metal layer M1 and the second metal layer M2 to contact each other, the metal paste M3' may be applied on the upper surface of the first metal layer M1 and / or the lower surface of the second metal layer M2. Thereafter, through the above-mentioned hot pressing process, the first insulating film 310 and the second insulating film 320 may be directly combined with each other, and the first metal layer M1 and the second metal layer M2 may be combined with each other through the third metal layer M3. Therefore, the bonding layer 300 and the metal layer M may be formed. When the first insulating film 310 and the second insulating film 320 are combined with each other and the first metal layer M1, the second metal layer M2 and the third metal layer M3 are combined with each other, the bottom surface of the cavity C may be formed with the bonding layer 300 (e.g., the second insulating film 320).

[0084] Through a series of processes, the first substrate part 100-1 and the second substrate part 200-1 described above may be combined with each other. Other descriptions may be substantially the same as the description of the printed circuit board 500 according to the above example, and a repeated description will not be provided.

[0085] Fig.15 is a cross-sectional view illustrating another example of mixed metal bonding according to example embodiments.

[0086] Reference Fig.15, the first metal layer M1 and the second metal layer M2 may be formed using nano twin copper instead of ordinary copper, and the bonding layer 300 may be formed using a non-conductive paste. For example, the non-conductive paste 300' may be applied to the first metal layer M1 formed as a nano twin copper film, the second metal layer M2 formed as a nano twin copper film may be pressed, and then the bonding may be performed at a high temperature, and the first metal layer M1 and the second metal layer M2 may be directly bonded to each other. Alternatively, the non-conductive paste 300' may be applied to the second metal layer M2 formed as a nano twin copper film, the first metal layer M1 formed as a nano twin copper film may be pressed, and then the bonding may be performed at a high temperature, and the first metal layer M1 and the second metal layer M2 may also be directly bonded to each other. Therefore, a bonding layer 300 of a metal layer M and a buried metal layer M may be formed. If necessary, the non-conductive paste 300' may be applied while forming the above-mentioned first insulating film 310 and / or the second insulating film 320, in which case the bonding layer 300 may include the first insulating film 310 and / or the second insulating film 320. When the cured product of the non-conductive paste 300' and the first and second metal layers M1 and M2 are bonded to each other, the bottom surface of the cavity C may be formed by the bonding layer 300, for example, by the cured product of the non-conductive paste 300'. If necessary, the cavity C may be blocked from the lower side in advance with an appropriate substance.

[0087] According to the aforementioned example embodiments, a printed circuit board including an antenna pattern and having an air gap structure may be provided.

[0088] Additionally, a printed circuit board may be provided that may improve antenna performance.

[0089] In the present disclosure, the term "covering" may include a configuration in which a component is completely covered and a configuration in which a portion of a component is covered, and may also include a configuration in which a component is directly covered or indirectly covered. In addition, the term "filling" may include a configuration in which a component is completely filled and a configuration in which at least a portion of a component is filled, and may also include a configuration in which a component is roughly filled. For example, there may be a gap. In addition, the term "surrounding" may include a configuration in which a component is completely surrounded and a configuration in which a component is roughly surrounded. In addition, the term "exposing" may include a configuration in which a component is completely exposed or a configuration in which a portion of a component is exposed, and "exposing" may refer to exposure from a component for burying. For example, a configuration in which an opening may expose a pad may refer to exposing a pad from an anti-etching layer, and a surface treatment layer may be further provided on the exposed pad.

[0090] In example embodiments, the configuration in which the component is disposed in the through-portion or through-hole may include a configuration in which the component is completely disposed in the through-portion or through-hole and a configuration in which the component partially protrudes to the upper side or the lower side in a cross section. For example, in the case in which the component is disposed in the through-portion or through-hole on a plane, the configuration may be understood in a broader sense.

[0091] In the present disclosure, "cross-sectional view or cross section" indicates a view showing the cross-sectional shape when an object is cut vertically or a view showing the shape when the object is observed from the side. In addition, "plan view or on a plane" may mean a view showing the cross-sectional shape when an object is cut horizontally or a view showing the plane shape when the object is observed from above or below.

[0092] In the present disclosure, the terms "lower side", "lower part" and "lower surface" may be used to indicate a downward direction based on a cross section of the drawings, and "upper side", "upper part" and "upper surface" may be used to indicate the opposite direction. However, this direction is defined for convenience of description, and the scope of the patent claims is not particularly limited by the description of this direction, and the terms "upper side" and "lower side" may be relative terms.

[0093] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" through an adhesive layer or the like. Furthermore, the term "electrical connection" may include a case where an element is "physically connected" and a case where an element is "not physically connected." Furthermore, the terms "first," "second," and the like may be used to distinguish one element from another, and may not limit the order and / or importance associated with the elements, etc. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of example embodiments.

[0094] Thickness, width, length, depth, line width, distance, spacing, etc. can be measured using a scanning microscope or an optical microscope based on a cross section of a printed circuit board obtained by polishing or cutting. The cross section can be a vertical cross section or a horizontal cross section, and each value can be measured based on the desired cross section. For example, the width of the upper end and / or lower end of the via can be measured on a cross section cut along the central axis of the via. In this case, when the value is not constant, the value can be determined as the average of the values ​​measured at 5 random points. The minimum value can be determined as the lowest value measured on the corresponding layer or area.

[0095] In the example embodiments, the term "example embodiment" or "example" may not refer to the same example embodiment or example, but may be provided to describe and emphasize the unique features of each example embodiment or example. The example embodiments set forth above may be implemented without excluding the possibility of combining features with other example embodiments. For example, unless otherwise specified, even if a feature described in an example embodiment is not described in another example embodiment, the feature may be understood to be related to another example embodiment.

[0096] Unless it has a clearly different meaning in the context, an expression used in the singular includes the expression in the plural.

[0097] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A first substrate including a first antenna pattern; a second substrate, disposed on the first substrate and comprising a second antenna pattern; A metal layer, disposed between the first substrate and the second substrate; as well as a bonding layer, disposed between the first substrate and the second substrate, wherein at least one of the first substrate and the second substrate has a cavity, the cavity having at least a portion disposed between the first antenna pattern and the second antenna pattern, wherein each of the first substrate and the second substrate comprises an organic material, and Wherein, the bonding layer comprises an inorganic material.

2. The printed circuit board according to claim 1, in, The metal layer includes a first metal layer disposed on an uppermost side of the first substrate and a second metal layer disposed on a lowermost side of the second substrate.

3. The printed circuit board according to claim 2, in, The first metal layer and the second metal layer are bonded to each other such that a side surface of the first metal layer and a side surface of the second metal layer are offset from each other.

4. The printed circuit board according to claim 2, wherein: An upper surface of the first metal layer and a lower surface of the second metal layer are directly bonded to each other.

5. The printed circuit board according to claim 4, wherein: An interface between the upper surface of the first metal layer and the lower surface of the second metal layer has at least one protrusion protruding toward an inner portion of at least one of the first metal layer and the second metal layer.

6. The printed circuit board according to claim 5, wherein: The protrusions include diffuse wedges of metal particles.

7. The printed circuit board according to claim 2, wherein: The metal layer further includes a third metal layer disposed between the first metal layer and the second metal layer and including a metal different from metals of the first metal layer and the second metal layer.

8. The printed circuit board according to claim 7, wherein: At least a portion of the third metal layer is disposed beyond at least one of an upper surface of the first metal layer and a lower surface of the second metal layer.

9. The printed circuit board according to claim 7, in, The first metal layer and the second metal layer include Cu, and Wherein, the third metal layer includes Ag and / or Au.

10. The printed circuit board according to claim 2, in, The thickness of the first metal layer is smaller than the thickness of the first antenna pattern, and Wherein, the thickness of the second metal layer is smaller than the thickness of the second antenna pattern.

11. The printed circuit board according to claim 1, wherein: The bonding layer includes an inorganic insulating film.

12. The printed circuit board according to claim 11, wherein The inorganic insulating film includes at least one of SiO 2 , SiN and SiCN.

13. The printed circuit board according to claim 1, in, The first antenna pattern includes a coupling pattern, and Wherein, the second antenna pattern includes a patch pattern.

14. The printed circuit board according to claim 1, wherein: At least a portion of the cavity is filled with air.

15. The printed circuit board according to claim 1, wherein The cavity penetrates a portion of the second substrate.

16. The printed circuit board according to claim 15, wherein The bottom surface of the cavity is formed by the bonding layer.

17. The printed circuit board according to claim 16, in, The cavity also extends through a portion of the bonding layer, and Wherein, a portion of the wall surface of the cavity is formed by the bonding layer.

18. The printed circuit board according to claim 16, wherein A thickness of a portion of the bonding layer located between the first substrate and the cavity is smaller than a thickness of a portion of the bonding layer located between the first substrate and the second substrate.

19. The printed circuit board according to claim 1, wherein: An island is provided in the cavity and is spaced apart from a wall surface of the cavity.

20. The printed circuit board according to claim 1, in, The first substrate includes a plurality of first insulating layers, a plurality of first wiring layers respectively arranged on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers. The second substrate includes a plurality of second insulating layers, a plurality of second wiring layers respectively arranged on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers. wherein at least one of the plurality of first insulating layers comprises an organic material, wherein at least one of the plurality of second insulating layers comprises an organic material, wherein at least one of the plurality of first wiring layers includes the first antenna pattern, and At least one of the plurality of second wiring layers includes the second antenna pattern.

21. The printed circuit board according to claim 20, in, Among the plurality of first via layers, a first via layer disposed on an uppermost side includes a first connection via connected to the metal layer, wherein, among the plurality of second via layers, the second via layer disposed on the lowermost side includes a second connection via connected to the metal layer, and Wherein, the first connecting via and the second connecting via taper in opposite directions.

22. The printed circuit board according to claim 21, in, In the cross-sectional view, the width of the upper end of the first connection via is greater than the width of the lower end of the first connection via, and Wherein, in the cross-sectional view, the width of the lower end of the second connecting via is greater than the width of the upper end of the second connecting via.

23. The printed circuit board according to claim 1, further comprising: a semiconductor chip mounted on the lower side of the first substrate, Wherein, the semiconductor chip includes a radio frequency integrated circuit.

24. A printed circuit board, comprising: A first substrate including a first antenna pattern; a second substrate, disposed on the first substrate and comprising a second antenna pattern; A metal layer, disposed between the first substrate and the second substrate; as well as a bonding layer, disposed between the first substrate and the second substrate, wherein at least one of the first substrate and the second substrate has a cavity, the cavity having at least a portion disposed between the first antenna pattern and the second antenna pattern, and Wherein, at least a portion of the side surface of the metal layer has a step difference.

25. The printed circuit board according to claim 24, further comprising: a heterogeneous metal layer disposed in the metal layer, The heterogeneous metal layer includes a metal different from the metal of the metal layer.

26. The printed circuit board according to claim 24, in, The bonding layer is disposed adjacent to the metal layer, and Wherein, in an area not overlapping with the cavity on a plane, the thickness of the bonding layer is the same as the thickness of the metal layer.

27. The printed circuit board according to claim 24, in, Each of the first substrate and the second substrate includes an organic material, and Wherein, the bonding layer comprises an inorganic material.

28. The printed circuit board according to claim 24, wherein The metal layer includes nano-twinned copper.

29. A method for manufacturing a printed circuit board, the method comprising: preparing a first substrate, the first substrate including a first antenna pattern and having a first metal layer formed on the outermost side of the first substrate; forming a first inorganic insulating film covering at least a portion of the first metal layer on the outermost side of the first substrate; preparing a second substrate, the second substrate including a second antenna pattern and having a second metal layer formed on an outermost side of the second substrate; forming a second inorganic insulating film covering at least a portion of the second metal layer on the outermost side of the second substrate; forming a cavity in at least one of the first substrate and the second substrate; as well as bonding the first substrate and the second substrate to each other, bonding the first inorganic insulating film and the second inorganic insulating film to each other, and bonding the first metal layer and the second metal layer to each other, Wherein, each of the first substrate and the second substrate includes an organic material.

30. The method of claim 29, wherein: In the step of forming the cavity, the cavity penetrates the second inorganic insulating film and also penetrates a portion of the second substrate.

31. The method of claim 29, further comprising: After forming the first inorganic insulating film, exposing a surface of the first metal layer by planarizing the first metal layer and the first inorganic insulating film; as well as After forming the second inorganic insulating film, a surface of the second metal layer is exposed by planarizing the second metal layer and the second inorganic insulating film.

32. The method according to claim 31, in, The step of bonding the first substrate and the second substrate to each other includes: bringing the first inorganic insulating film and the second inorganic insulating film into contact with each other, and bringing the first metal layer and the second metal layer into contact with each other; bonding the first inorganic insulating film and the second inorganic insulating film to each other at a first temperature; and bonding the first metal layer and the second metal layer to each other at a second temperature, Wherein, the second temperature is higher than the first temperature.

33. The method according to claim 31, wherein: The step of bonding the first substrate and the second substrate to each other includes: Applying a metal paste between the first metal layer and the second metal layer, the metal paste comprising a metal different from the first metal layer and the second metal layer; bringing the first inorganic insulating film and the second inorganic insulating film into contact with each other, and bringing the first metal layer and the second metal layer into contact with the metal paste; bonding the first inorganic insulating film and the second inorganic insulating film to each other at a first temperature; and bonding the first metal layer and the second metal layer to each other through the metal paste at a second temperature, Wherein, the second temperature is higher than the first temperature.

34. The method according to claim 29, in, The first substrate includes a plurality of first insulating layers, a plurality of first wiring layers respectively arranged on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers. The second substrate includes a plurality of second insulating layers, a plurality of second wiring layers respectively arranged on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers. At least one of the plurality of first insulating layers comprises an organic material, At least one of the plurality of second insulating layers comprises an organic material, At least one of the plurality of first wiring layers includes the first antenna pattern, At least one of the plurality of second wiring layers includes the second antenna pattern, Among the plurality of first wiring layers, a first wiring layer disposed on an uppermost side includes the first metal layer, and Among the plurality of second wiring layers, the second wiring layer disposed on the lowermost side includes the second metal layer.

35. A printed circuit board comprising: A first substrate including a first antenna pattern; a second substrate, disposed on the first substrate and comprising a second antenna pattern; A metal layer, disposed between the first substrate and the second substrate; as well as a bonding layer, disposed between the first substrate and the second substrate and covering a side surface of the metal layer, wherein at least one of the first substrate and the second substrate has a cavity, the cavity having at least a portion disposed between the first antenna pattern and the second antenna pattern, and The thickness of a portion of the bonding layer located between the first substrate and the cavity is smaller than the thickness of a portion of the bonding layer located between the first substrate and the second substrate.

36. The printed circuit board according to claim 35, wherein The metal layer includes a first metal layer disposed on an uppermost side of the first substrate and a second metal layer disposed on a lowermost side of the second substrate.

37. The printed circuit board according to claim 36, wherein An upper surface of the first metal layer and a lower surface of the second metal layer are directly bonded to each other.

38. The printed circuit board according to claim 36, wherein The metal layer further includes a third metal layer disposed between the first metal layer and the second metal layer and including a metal different from metals of the first metal layer and the second metal layer.

39. The printed circuit board according to claim 35, wherein: The bonding layer includes at least one of SiO2, SiN and SiCN.

40. The printed circuit board according to claim 35, wherein At least a portion of the cavity is filled with air.

41. A printed circuit board comprising: A first substrate includes a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers, wherein one of the plurality of first wiring layers includes a first antenna pattern; a second substrate, disposed on the first substrate, and comprising a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on or in the plurality of second insulating layers, and a plurality of second via layers respectively penetrating the plurality of second insulating layers, one of the plurality of second wiring layers comprising a second antenna pattern; A metal layer, disposed between the first substrate and the second substrate; as well as a bonding layer, disposed between the first substrate and the second substrate and covering a side surface of the metal layer, wherein at least one of the first substrate and the second substrate has a cavity, the cavity having at least a portion disposed between the first antenna pattern and the second antenna pattern, and The first via layers connected to the metal layer among the plurality of first via layers and the second via layers connected to the metal layer among the plurality of second via layers are tapered in opposite directions.

42. The printed circuit board according to claim 41, wherein The metal layer includes a first metal layer disposed on an uppermost side of the first substrate and a second metal layer disposed on a lowermost side of the second substrate.

43. The printed circuit board according to claim 42, wherein An upper surface of the first metal layer and a lower surface of the second metal layer are directly bonded to each other.

44. The printed circuit board according to claim 42, wherein The metal layer further includes a third metal layer disposed between the first metal layer and the second metal layer and including a metal different from metals of the first metal layer and the second metal layer.

45. The printed circuit board of claim 41, wherein: The bonding layer includes at least one of SiO2, SiN and SiCN.

46. ​​The printed circuit board of claim 41, wherein: At least a portion of the cavity is filled with air.

47. The printed circuit board of claim 41, wherein: The cavity is spaced apart from the plurality of first wiring layers and the plurality of second wiring layers.

Images