Printed circuit board and manufacturing method thereof

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. A printed circuit board according to an embodiment includes: a first insulating layer; a first wiring layer buried in the first insulating layer; a first via hole disposed in a first via hole in the first insulating layer; the second insulating layer is arranged below the first insulating layer; a second wiring layer buried in the second insulating layer; the first solder resist layer is arranged on the first insulating layer; and a cavity extending along a height direction of the printed circuit board by penetrating through the first solder resist layer and penetrating through a portion of the first insulating layer. The cavity includes a first portion, a second portion, and a third portion having different widths. Along the height direction, the first portion is disposed on the second portion, and the third portion is disposed on the first portion. The first via is exposed through the second portion of the cavity.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board and a method for manufacturing the same. Background Art

[0002] In a printed circuit board, a circuit pattern is formed at an insulating material using a conductive material such as copper. As electronic devices (including mobile phones) in the IT field become smaller, a method of forming a cavity in a printed circuit board and mounting electronic components such as active elements, passive elements, etc. in the cavity has been proposed.

[0003] The height of a portion of the electronic component mounted within the printed circuit board may vary according to the depth of a cavity of the printed circuit board in which the electronic component is mounted.

[0004] As the depth of the cavity of the printed circuit board increases, most of the electronic component can be mounted within the cavity, and the overall thickness of a product packaging the electronic component and the printed circuit board can be reduced.

[0005] However, when forming a cavity in a printed circuit board, it is difficult to adjust the depth of the cavity, and a peripheral circuit pattern may be damaged in order to increase the depth of the cavity.

[0006] Additionally, if the size of the mounting connection between the electronic component mounted within the cavity and the printed circuit board is small, it may be difficult to accurately mount the electronic component on and / or in the printed circuit board. Summary of the invention

[0007] An aspect of the present disclosure is to provide a printed circuit board and a method of manufacturing the same, which can form a cavity that may have a desired depth and can increase mounting accuracy without damaging a circuit pattern around the cavity.

[0008] However, the problems to be solved by the present disclosure are not limited to the above-mentioned problems, and various extensions can be made within the scope of the technical concept included in the present disclosure.

[0009] A printed circuit board according to an embodiment includes: a first insulating layer; a first wiring layer buried in the first insulating layer; a first via hole arranged in a first access hole in the first insulating layer; a second insulating layer arranged below the first insulating layer; a second wiring layer buried in the second insulating layer; a first solder resist layer arranged on the first insulating layer; and a cavity extending along the height direction of the printed circuit board by penetrating the first solder resist layer and penetrating a portion of the first insulating layer. The cavity includes a first portion, a second portion, and a third portion having different widths. Along the height direction, the first portion is arranged on the second portion, and the third portion is arranged on the first portion. The first via hole is exposed through the second portion of the cavity.

[0010] The second portion of the cavity may be plural in number, and the first insulating layer may have a plurality of protrusions protruding toward the first portion between the plurality of second portions of the cavity.

[0011] Each of the first via hole and the first via hole may be plural in number, and a plurality of the second portions may overlap the plurality of the first via holes in the height direction, respectively.

[0012] A first width of the first portion may be greater than a second width of the second portion, and may be less than a third width of the third portion.

[0013] The second width of the second portion may be smaller than each of the first width of the first portion and the third width of the third portion.

[0014] The printed circuit board may further include a first-first via hole, which is arranged in the second via hole of the first insulating layer and connected to the first wiring layer, and a first depth of the first portion may be substantially equal to a first thickness of the first wiring layer, and a second depth of the second portion may be less than a second thickness of the first-first via hole.

[0015] A third depth of the third portion may be substantially equal to a third thickness of the first solder resist layer.

[0016] The printed circuit board may further include: a second via hole disposed in the second via hole in the second insulating layer; a third insulating layer disposed below the second insulating layer; and a third via hole disposed in the third via hole in the third insulating layer.

[0017] The printed circuit board may further include: a first pad layer buried by the first solder resist layer; a first additional pad layer disposed in the opening of the first solder resist layer and in contact with the first pad layer; and a second additional pad layer disposed on the first additional pad layer.

[0018] The cavity may further include a fourth portion defined by a side surface of the second additional pad layer.

[0019] The width of the fourth portion may be different from the first width of the first portion, the second width of the second portion, and the third width of the third portion.

[0020] According to an embodiment, a method for manufacturing a printed circuit board includes: forming a first wiring layer and a first sacrificial layer; forming a plurality of dummy patterns on the first sacrificial layer; forming a first insulating layer burying the first wiring layer, the first sacrificial layer and the plurality of dummy patterns; forming a first via hole overlapping the first wiring layer and a plurality of second via holes overlapping the plurality of dummy patterns in the first insulating layer; forming a first via hole and a plurality of second via holes in the first via hole and the plurality of second via holes of the first insulating layer, respectively; forming a second sacrificial layer on the first sacrificial layer; forming a first portion of a cavity by etching the second sacrificial layer and the first sacrificial layer; and removing the plurality of dummy patterns to form a second portion of the cavity, thereby exposing the plurality of second via holes.

[0021] The first sacrificial layer may be disposed at a side surface of the first wiring layer and may be formed to have the same thickness as that of the first wiring layer, and the plurality of dummy patterns may be disposed at a side surface of the first via hole and may be formed to have a thickness less than that of the first via hole.

[0022] The manufacturing method may also include: forming a first pad layer on the first wiring layer, the first pad layer being the same layer as the second sacrificial layer; and forming a first solder resist layer, the first solder resist layer including a first opening exposing the second sacrificial layer and a second opening exposing a portion of the first pad layer, and forming a third portion of the cavity in the first solder resist layer.

[0023] The manufacturing method may further include forming a second insulating layer disposed below the first insulating layer, and forming a third via hole disposed in a third via hole formed in the second insulating layer.

[0024] The manufacturing method may further include: forming a first additional pad layer disposed within the second opening of the first solder resist layer and in contact with the first pad layer; and forming a second additional pad layer disposed on the first additional pad layer.

[0025] The cavity may be formed to further include a fourth portion defined by a side surface of the second additional pad layer.

[0026] A first width of the first portion, a second width of the second portion, and a third width of the third portion may be differently formed.

[0027] The second width of the second portion may be formed to be smaller than each of the first width of the first portion and the third width of the third portion.

[0028] The width of the fourth portion may be formed to be different from the first width of the first portion, the second width of the second portion, and the third width of the third portion.

[0029] According to the present disclosure, a printed circuit board and a method of manufacturing the same can be provided, which can form a cavity that can have a desired depth and can increase mounting accuracy without damaging a circuit pattern around the cavity.

[0030] It is apparent that the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a cross-sectional view of a printed circuit board according to an embodiment.

[0032] Figures 2 to 10 is a cross-sectional view illustrating a method of manufacturing a printed circuit board according to an embodiment.

[0033] Fig.11 is a cross-sectional view of a printed circuit board according to another embodiment.

[0034] Fig.12 is a cross-sectional view of a printed circuit board according to another embodiment. DETAILED DESCRIPTION

[0035] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0036] In order to clearly describe the present disclosure, parts or portions irrelevant to the description are omitted, and the same or similar constituent elements are denoted by the same reference numerals throughout the specification.

[0037] In addition, the accompanying drawings are provided only to make the embodiments disclosed in this specification easy to understand and will not be interpreted as limiting the spirit disclosed in this specification. It will be understood that the present disclosure includes all modifications, equivalents and replacements without departing from the scope and spirit of the present disclosure.

[0038] In addition, in the drawings, the size (e.g., thickness) of each element is arbitrarily shown for the convenience of description, and the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and regions are exaggerated for the convenience of description.

[0039] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "above" another element, the element may be directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "above..." mean being disposed on or below an object portion, and do not necessarily mean being disposed on the upper side of the object portion based on the direction of gravity.

[0040] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0041] Furthermore, throughout the specification, the phrase “in a plan view” or “on a plane” means observing an object portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the object portion from the side.

[0042] In addition, throughout the specification, "connection" means not only a case where two or more elements are directly connected, but also a case where two or more elements are indirectly connected through other elements and a case where two or more elements are physically connected or electrically connected. In addition, "connection" may also refer to a case where, although two or more elements are named differently according to position or function, they are actually integrated and linked to each other.

[0043] Hereinafter, various embodiments and modifications will be described in detail with reference to the accompanying drawings.

[0044] Reference Figure 1 , describing a printed circuit board according to an embodiment. Figure 1 is a cross-sectional view of a printed circuit board according to an embodiment.

[0045] Reference Figure 1 According to the present embodiment, the printed circuit board 100 may include a plurality of stacked insulating layers IL, a plurality of wiring layers ML buried in the plurality of insulating layers IL, a plurality of vias MV arranged in a plurality of via holes VA of the plurality of insulating layers IL, a plurality of pad layers MP, a solder resist layer PL, and a cavity CV formed in a portion of the plurality of insulating layers IL and the solder resist layer PL.

[0046] The plurality of insulating layers IL may include a first insulating layer IL1 and a second insulating layer IL2 disposed under the first insulating layer IL1 in the height direction DRH.

[0047] The plurality of wiring layers ML may include a first wiring layer ML1 buried by the first insulating layer IL1 , and second and third wiring layers ML2 and ML22 buried by the second insulating layer IL2 .

[0048] The plurality of via holes MV may include: a first via hole MV1 disposed in a first via hole VA1 formed in the first insulating layer IL1; a second via hole MV11 disposed in a second via hole VA11 formed in the first insulating layer IL1; a third via hole MV2 disposed in a third via hole VA2 formed in the second insulating layer IL2; and a fourth via hole MV22 disposed in a fourth via hole VA22 formed in the second insulating layer IL2. For example, the second via hole MV11 and the second via hole VA11 may be plural in number.

[0049] The plurality of pad layers MP may include a first pad layer MP1 disposed on the first insulating layer IL1 , and second and third pad layers MP2 and MP22 disposed under the second insulating layer IL2 .

[0050] A portion of the first wiring layer ML1 and a portion of the second wiring layer ML2 may be connected via the first via MV1, the second via MV11 may be connected to a portion of the third wiring layer ML22, a portion of the second wiring layer ML2 and the second pad layer MP2 may be connected via the third via MV2, the first pad layer MP1 may be connected to the first wiring layer ML1, and a portion of the third wiring layer ML22 and the third pad layer MP22 may be connected to each other via the fourth via MV22.

[0051] The solder resist layer PL may include: a first solder resist layer PL1, which is disposed on the first insulating layer IL1 and exposes a portion of the first pad layer MP1 through the second opening OP2; and a second solder resist layer PL2, which is disposed under the second insulating layer IL2 and exposes a portion of the second pad layer MP2 and a portion of the third pad layer MP22 through the third opening OP3A and the fourth opening OP3B.

[0052] The cavity CV may include first and second portions CV1 and CV2 formed in the first insulating layer IL1 and having different widths and different heights, and a third portion CV3 formed in the first solder resist layer PL1 .

[0053] A first portion CV1 of the cavity CV is disposed at a side surface of the first wiring layer ML1, a second portion CV2 of the cavity CV is disposed at a side surface of the first via MV1 and overlaps the second via MV11, and a third portion CV3 of the cavity CV is disposed at a side surface of the first solder resist layer PL1.

[0054] Along the height direction DRH, the first portion CV1 of the cavity CV may be disposed on the second portion CV2 of the cavity CV, and the third portion CV3 of the cavity CV may be disposed on the first portion CV1 of the cavity CV.

[0055] The second via hole MV11 may be exposed through the second portion CV2 of the cavity CV. Along the height direction DRH, a lower surface of the second portion CV2 of the cavity CV and an upper surface of the second via hole MV11 may be located on substantially the same plane.

[0056] Along a plane direction DRW perpendicular to the height direction DRH, a first portion CV1 of the cavity CV formed at the first insulating layer IL1 may have a first width W1, a second portion CV2 of the cavity CV formed at the first insulating layer IL1 may have a second width W2, and a third portion CV3 of the cavity CV formed at the first solder resist layer PL1 may have a third width W3.

[0057] Although in the printed circuit board 100 according to the present embodiment, the first width W1 of the first portion CV1 of the cavity CV is greater than the second width W2 of the second portion CV2 of the cavity CV and less than the third width W3 of the third portion CV3 of the cavity CV, this is only an example. That is, the first width W1 of the first portion CV1 of the cavity CV may be different from the second width W2 of the second portion CV2 of the cavity CV and the third width W3 of the third portion CV3 of the cavity CV.

[0058] The second portion CV2 of the cavity CV may be plural in number and may overlap with the plurality of second via holes MV11, respectively. For example, the second width W2 of each second portion CV2 of the cavity CV may be greater than the width of a portion of the corresponding second via hole MV11 exposed by the corresponding second portion CV2.

[0059] Along the height direction DRH, the second portion CV2 of the cavity CV may overlap the first portion CV1 of the cavity CV.

[0060] The third width W3 of the third portion CV3 of the cavity CV may be greater than the first width W1 of the first portion CV1 of the cavity CV.

[0061] The sidewalls of the cavity CV may not be arranged in a line in the height direction DRH, and a step may be formed between the sidewalls of the cavity CV.

[0062] Along the height direction DRH, a first depth H1 of the first portion CV1 of the cavity CV may be substantially equal to a first thickness D1 of the first wiring layer ML1 buried by the first insulating layer IL1, a second depth H2 of the second portion CV2 of the cavity CV may be less than a second thickness D2 of the first via hole MV1 disposed in the first via hole VA1 formed in the first insulating layer IL1, and a third depth H3 of the third portion CV3 of the cavity CV may be substantially the same as a third thickness D3 of the first solder resist layer PL1.

[0063] Reference is parallel to Figure 1In the first virtual line L1 shown in the direction of the plane direction DRW in FIG. 1 , portions of the first insulating layer IL1 between the plurality of second portions CV2 of the cavity CV may protrude upward to form a plurality of protrusions, and upper surfaces of the plurality of protrusions may be located on substantially the same plane as the lower surface of the first wiring layer ML1.

[0064] According to the printed circuit board of the present embodiment, the cavity CV may be formed in a portion of the first insulating layer IL1 and the first solder resist layer PL1, and the total depth HT of the cavity CV may be substantially equal to the sum of the first thickness D1 of the first wiring layer ML1 buried by the first insulating layer IL1, the thickness of a portion of the first via MV1 disposed in the first via hole VA1 formed in the first insulating layer IL1, and the thickness (i.e., the third thickness D3) of the first solder resist layer PL1. The portion of the first insulating layer IL1 between the second portions CV2 of the cavity CV protrudes, thereby protecting the plurality of wiring layers ML and the plurality of vias MV buried in the plurality of insulating layers IL. Therefore, the circuit pattern around the cavity CV may not be damaged.

[0065] In addition, a portion of the first insulating layer IL1 disposed between the second portions CV2 of the cavity CV may protrude from the lower surface of the second portions CV2, thereby forming a plurality of protrusions between the second portions CV2, and the plurality of protrusions serve as spacers. A plurality of protrusions may be included in the cavity CV, so that if an electronic component is installed in the cavity CV, a space is generated around the electronic component, and heat generated by the electronic component, etc., is diffused through the space.

[0066] In addition, the plurality of second portions CV2 of the cavity CV may overlap with the plurality of second vias MV11, and a connection portion for connection between the electronic component to be mounted in the cavity CV and the printed circuit board 100 may be provided in the plurality of second portions CV2. Therefore, even if the size of the connection portion is reduced, the connection portion may be provided in the plurality of second portions CV2, thereby stably maintaining the connection between the electronic component and the printed circuit board 100.

[0067] If an electronic component is mounted on the printed circuit board 100, the electronic component may be disposed within the cavity CV of the printed circuit board 100. Therefore, the overall thickness of the package of the electronic component may decrease as the depth of the cavity CV increases.

[0068] According to the printed circuit board of the present embodiment, the cavity CV having a desired depth can be formed without damaging the circuit pattern around the cavity CV, so that the overall thickness of the package of the electronic component can be reduced without causing defects.

[0069] Then, refer to Figures 2 to 10 Combined with Figure 1 , a method of manufacturing a printed circuit board according to an embodiment will be described. Figures 2 to 10is a cross-sectional view illustrating a method of manufacturing a printed circuit board according to an embodiment.

[0070] Reference Figure 2 , a first copper foil layer TC1 and a first wiring layer ML1 may be formed on a carrier substrate (or carrier board) CS including a core CL and thin film metal layers MS stacked at both sides of the core CL. At this time, a first sacrificial layer SF1 may be formed together, and the first sacrificial layer SF1 is disposed at a position where the cavity CV will be formed. Since the first sacrificial layer SF1 is formed together with the first wiring layer ML1, the first sacrificial layer SF1 may be made of the same material as that of the first wiring layer ML1 and may have the same thickness as the first thickness D1 of the first wiring layer ML1.

[0071] like Figure 3 As shown in FIG, a plurality of dummy patterns DP are formed on the first sacrificial layer SF1. The dummy pattern DP may include a layer made of a material different from that of the wiring layer ML and the via MV. For example, the dummy pattern DP may include nickel, but the embodiment is not limited thereto. For example, the thickness of each of the plurality of dummy patterns DP may be less than the thickness of the first via MV1.

[0072] like Figure 4 As shown in, a first insulating layer IL1 is formed on a first wiring layer ML1, a first sacrificial layer SF1 and a plurality of dummy patterns DP, a first via hole VA1 overlapping the first wiring layer ML1 and a second via hole VA11 overlapping the plurality of dummy patterns DP are formed in the first insulating layer IL1, a first via hole MV1 arranged in the first via hole VA1 and a second via hole MV11 arranged in the second via hole VA11 are formed, and a second wiring layer ML2 overlapping the first via hole MV1 and a third wiring layer ML22 overlapping the second via hole MV11 are formed.

[0073] Reference Figure 5 A second insulating layer IL2 and a second copper foil layer TC2 are formed on the second wiring layer ML2 and the third wiring layer ML22 so that the second wiring layer ML2 and the third wiring layer ML22 are buried by the second insulating layer IL2.

[0074] Next, if Figure 6 As shown in FIG. 8 , the substrate portion SUB is peeled off from both sides of the carrier substrate CS.

[0075] Hereinafter, one substrate portion SUB peeled from the carrier substrate CS will be described.

[0076] like Figure 7As shown in , the first copper foil layer TC1 is removed from the substrate portion SUB, the second sacrificial layer SF2 is formed on the first sacrificial layer SF1, and the first pad layer MP1 is formed on the first wiring layer ML1. In addition, the second copper foil layer TC2 is removed from the substrate portion SUB, and a third via hole VA2 overlapping the second wiring layer ML2 and a fourth via hole VA22 overlapping the third wiring layer ML22 are formed in the second insulating layer IL2, a third via hole MV2 is formed in the third via hole VA2 and a fourth via hole MV22 is formed in the fourth via hole VA22, and a second pad layer MP2 overlapping the third via hole MV2 and a third pad layer MP22 overlapping the fourth via hole MV22 are formed. Here, the second copper foil layer TC2 may also be removed together with the first copper foil layer TC1.

[0077] In the present embodiment, after the substrate portion SUB is peeled off from both sides of the carrier substrate CS, the third via hole VA2, the fourth via hole VA22, the third via hole MV2, the fourth via hole MV22, the second pad layer MP2, and the third pad layer MP22 are formed, but the embodiment is not limited thereto. According to another embodiment, the third via hole VA2, the fourth via hole VA22, the third via hole MV2, the fourth via hole MV22, the second pad layer MP2, and the third pad layer MP22 may also be formed before the substrate portion SUB is peeled off from both sides of the carrier substrate CS.

[0078] Reference Figure 8 , a first solder resist layer PL1 is formed on the first insulating layer IL1 , and a second solder resist layer PL2 is formed under the second insulating layer IL2 .

[0079] The first solder resist layer PL1 may include a first opening OP1 exposing the entirety of the second sacrificial layer SF2 and a second opening OP2 overlapping at least a portion of the first pad layer MP1, and the second solder resist layer PL2 may include a third opening OP3A overlapping the second pad layer MP2 and a fourth opening OP3B overlapping the third pad layer MP22.

[0080] like Fig. 9 As shown in FIG, a first mask layer MSK1 is disposed on the first solder resist layer PL1, the first mask layer MSK1 covers the second opening OP2 of the first solder resist layer PL1 and exposes the first opening OP1, and a second mask layer MSK2 is disposed under the second solder resist layer PL2 to cover the third opening OP3A and the fourth opening OP3B. Portions other than the region where the cavity CV is to be formed may be covered by the first mask layer MSK1 and the second mask layer MSK2.

[0081] The first and second sacrificial layers SF1 and SF2 disposed at a region where the cavity CV is to be formed are etched using the first and second mask layers MSK1 and MSK2 as etching masks.

[0082] Reference Fig.10 , the first mask layer MSK1 and the second mask layer MSK2 are removed, thereby forming a first portion CV1 of the cavity CV at a portion of the first insulating layer IL1 and forming a third portion CV3 of the cavity CV in the first solder resist layer PL1.

[0083] Thereafter, the plurality of dummy patterns DP buried in the first insulating layer IL1 are removed to form the second portion CV2 of the cavity CV, thereby forming Figure 1 A printed circuit board 100 is provided.

[0084] The plurality of dummy patterns DP buried in the first insulating layer IL1 may be removed so that the second via hole MV11 is exposed through the second portion CV2 of the cavity CV. Along the height direction DRH, a lower surface of the second portion CV2 of the cavity CV and an upper surface of the second via hole MV11 may be located on substantially the same plane.

[0085] In addition, although the manufacturing method of the printed circuit board according to the present embodiment is described above, it will be appreciated by those skilled in the art that some of the steps may be omitted. For example, a manufacturing method of the printed circuit board may include: forming a first wiring layer ML1 and a first sacrificial layer SF1; forming a plurality of dummy patterns DP on the first sacrificial layer SF1; forming a first insulating layer IL1 burying the first wiring layer ML1, the first sacrificial layer SF1 and the plurality of dummy patterns DF; forming a first via hole VA1 overlapping the first wiring layer ML1 and a plurality of second via holes VA11 overlapping the plurality of dummy patterns DP in the first insulating layer IL1; forming a first via hole MV1 and a plurality of second via holes MV11 in the first via hole VA1 and the plurality of second via holes VA11 of the first insulating layer IL1, respectively; forming a second sacrificial layer SF2 on the first sacrificial layer SF1; forming a first portion CV1 of a cavity CV by etching the second sacrificial layer SF2 and the first sacrificial layer SF1; and removing the plurality of dummy patterns DP to form a second portion CV2 of the cavity CV, thereby exposing the plurality of second via holes MV11. According to the method for manufacturing a printed circuit board of the present embodiment, a plurality of dummy patterns DP and a first sacrificial layer SF1 may be formed to be buried in the first insulating layer IL1, a second sacrificial layer SF2 may be formed using the same layer as the first pad layer MP1, and a cavity CV may be formed in the printed circuit board by etching the second sacrificial layer SF2, the first sacrificial layer SF1, and the plurality of dummy patterns DP using the first mask layer MSK1 and the second mask layer MSK2 as etching masks. Therefore, the cavity CV may be formed in a portion of the first insulating layer IL1 and the first solder resist layer PL1, and a depth HT of the cavity CV may be greater than a sum of a first thickness D1 of the first wiring layer ML1 buried by the first insulating layer IL1 and a third thickness D3 of the first solder resist layer PL1, and the difference between them is a second depth H2 of the second portion CV2 of the cavity CV.

[0086] When forming the third portion CV3 and the first portion CV1 of the cavity CV, the plurality of second via holes MV11 may be covered and protected by the plurality of dummy patterns DP. Therefore, the plurality of second via holes MV11 exposed by the cavity CV may be prevented from being damaged during the formation process of the cavity CV, thereby improving the mounting accuracy when mounting electronic components in the cavity CV.

[0087] By leaving a portion of the first insulating layer IL1 in the cavity CV, the plurality of wiring layers ML buried in the plurality of insulating layers IL can be protected by the portion of the first insulating layer IL1 so that the circuit pattern around the cavity CV is not damaged, and the thickness of the first wiring layer ML1 buried by the first insulating layer IL1 can be adjusted, thereby adjusting the total depth HT of the cavity CV. The portion of the first insulating layer IL1 disposed between the second portions CV2 of the cavity CV can protrude from the lower surface of the second portions CV2 to form a plurality of protrusions between the second portions CV2. The plurality of protrusions can serve as spacers so that if an electronic component is mounted in the cavity CV, a space is generated around the electronic component, and heat generated by the electronic component, etc., is diffused through the space.

[0088] In addition, the plurality of second portions CV2 of the cavity CV may overlap with the plurality of second vias MV11, and a connection portion for connection between the electronic component to be mounted in the cavity CV and the printed circuit board 100 may be provided in the plurality of second portions CV2. Therefore, even if the size of the connection portion is reduced, the connection portion may be provided in the plurality of second portions CV2, thereby stably maintaining the connection between the electronic component and the printed circuit board 100.

[0089] Then, refer to Fig.11 , describing a printed circuit board according to another embodiment. Fig.11 is a cross-sectional view of a printed circuit board according to another embodiment.

[0090] Reference Fig.11 The printed circuit board 101 according to this embodiment is similar to the printed circuit board 101 according to the reference Figure 1 The printed circuit board 100 of the embodiment is described. Detailed description of the same components is omitted.

[0091] Reference Fig.11 , and according to Figure 1Unlike the printed circuit board 100 of the embodiment shown in , the printed circuit board 101 according to the present embodiment may further include: a third insulating layer IL3 disposed under the second insulating layer IL2; a fourth wiring layer ML3 and a fifth wiring layer ML33 buried by the third insulating layer IL3; and a fifth via MV3 and a sixth via MV33 disposed in the fifth via hole VA3 and the sixth via hole VA33 of the third insulating layer IL3, respectively. The second pad layer MP2 may be connected to the fifth via hole MV3, and the third pad layer MP22 may be connected to the sixth via hole MV33.

[0092] Other contents and according to previous reference Figures 1 to 10 The contents of the printed circuit board 100 and the method for manufacturing the printed circuit board 100 of the described embodiments are substantially the same, and thus redundant descriptions thereof are omitted.

[0093] Reference Fig.12 , describing a printed circuit board according to another embodiment. Fig.12 is a cross-sectional view of a printed circuit board according to another embodiment.

[0094] Reference Fig.12 , the printed circuit board 102 according to the present embodiment is similar to the printed circuit boards 100 and 101 according to the above-described embodiments. Detailed descriptions of the same components are omitted.

[0095] Reference Fig.12 , and according to Figure 1 Unlike the printed circuit board 100 of the embodiment shown in , the printed circuit board 102 according to the present embodiment may further include: a third insulating layer IL3 disposed under the second insulating layer IL2; a fourth wiring layer ML3 and a fifth wiring layer ML33 buried by the third insulating layer IL3; and a fifth via MV3 and a sixth via MV33 disposed in the fifth via hole VA3 and the sixth via hole VA33 of the third insulating layer IL3, respectively. The second pad layer MP2 may be connected to the fifth via hole MV3, and the third pad layer MP22 may be connected to the sixth via hole MV33.

[0096] In addition, unlike the printed circuit boards 100 and 101 according to the above-mentioned embodiments, the printed circuit board 102 according to the present embodiment may further include: a first additional pad layer MP11, which is arranged in the second opening OP2 of the first solder resist layer PL1, overlaps with at least a portion of the first pad layer MP1, and contacts the first pad layer MP1; and a second additional pad layer MP12, which is arranged on the first solder resist layer PL1 and contacts the first additional pad layer MP11.

[0097] In addition, the cavity CV may further include a fourth portion CV4 defined by a side surface of the second additional pad layer MP12 .

[0098] The fourth width W4 of the fourth portion CV4 of the cavity CV may be different from the first width W1 of the first portion CV1 of the cavity CV formed at the first insulating layer IL1, the second width W2 of the second portion CV2 of the cavity CV formed at the first insulating layer IL1, and the third width W3 of the third portion CV3 of the cavity CV formed at the first solder resist layer PL1.

[0099] The total depth HT of the cavity CV may be substantially equal to the sum of the first thickness D1 of the first wiring layer ML1 buried by the first insulating layer IL1, the thickness of a portion of the first via hole MV1 disposed in the first via hole VA1 formed in the first insulating layer IL1, the third thickness D3 of the first solder resist layer PL1, and the thickness of the second additional pad layer MP12.

[0100] A first additional pad layer MP11 in contact with the first pad layer MP1 and a second additional pad layer MP12 in contact with the first additional pad layer MP11 may be further included, thereby adjusting the total depth HT of the cavity CV to be deeper.

[0101] Other contents and according to previous reference Figures 1 to 10 The contents of the printed circuit board 100 and the method for manufacturing the printed circuit board 100 of the described embodiments are substantially the same, and thus redundant descriptions thereof are omitted.

[0102] While the disclosure has been described in connection with what are presently considered to be practical embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; a first wiring layer buried in the first insulating layer; a first via hole disposed in a first passage hole in the first insulating layer; a second insulating layer, disposed below the first insulating layer; a second wiring layer buried in the second insulating layer; a first solder resist layer, disposed on the first insulating layer; as well as a cavity extending in a height direction of the printed circuit board by penetrating the first solder resist layer and penetrating a portion of the first insulating layer, wherein the cavity comprises a first portion, a second portion and a third portion having different widths, Along the height direction, the first portion is disposed on the second portion, and the third portion is disposed on the first portion, and The first via is exposed through the second portion of the cavity.

2. The printed circuit board according to claim 1, wherein: The second portion of the cavity is plural in number, and the first insulating layer has a plurality of protrusions protruding toward the first portion between the plurality of second portions of the cavity.

3. The printed circuit board according to claim 2, wherein: Each of the first via hole and the first via hole is plural in number, and the plurality of second portions overlap the plurality of first via holes in the height direction, respectively.

4. The printed circuit board according to claim 1, wherein: A first width of the first portion is greater than a second width of the second portion, and smaller than a third width of the third portion.

5. The printed circuit board according to claim 1, wherein The second width of the second portion is less than each of the first width of the first portion and the third width of the third portion.

6. The printed circuit board according to claim 1, wherein The printed circuit board further includes a first-first via hole, the first-first via hole being disposed in the second via hole of the first insulating layer and connected to the first wiring layer, and The first depth of the first portion is equal to the first thickness of the first wiring layer, and the second depth of the second portion is less than the second thickness of the first-first via hole.

7. The printed circuit board according to claim 6, wherein: A third depth of the third portion is equal to a third thickness of the first solder resist layer.

8. The printed circuit board according to claim 1, further comprising: a second via hole disposed in a second passage hole in the second insulating layer; a third insulating layer, disposed below the second insulating layer; as well as The third via hole is disposed in the third passage hole in the third insulating layer.

9. The printed circuit board according to claim 8, further comprising: a first pad layer, buried by the first solder resist layer; a first additional pad layer disposed within the opening of the first solder resist layer and in contact with the first pad layer; as well as The second additional pad layer is arranged on the first additional pad layer.

10. The printed circuit board according to claim 9, wherein: The cavity also includes a fourth portion defined by a side surface of the second additional pad layer.

11. The printed circuit board according to claim 10, wherein: The width of the fourth portion is different from the first width of the first portion, the second width of the second portion, and the third width of the third portion.

12. A method for manufacturing a printed circuit board, the method comprising: forming a first wiring layer and a first sacrificial layer; forming a plurality of dummy patterns on the first sacrificial layer; forming a first insulating layer burying the first wiring layer, the first sacrificial layer, and the plurality of dummy patterns; forming a first via hole overlapping the first wiring layer and a plurality of second via holes overlapping the plurality of dummy patterns in the first insulating layer; forming a first via hole and a plurality of second via holes in the first via hole and the plurality of second via holes of the first insulating layer, respectively; forming a second sacrificial layer on the first sacrificial layer; forming a first portion of a cavity by etching the second sacrificial layer and the first sacrificial layer; as well as The plurality of dummy patterns are removed to form a second portion of the cavity, thereby exposing the plurality of second via holes.

13. The manufacturing method according to claim 12, wherein: The first sacrificial layer includes a material that is the same as that of the first wiring layer and is formed to have the same thickness as that of the first wiring layer, and the plurality of dummy patterns include a material that is different from that of the first via, and a thickness of each of the plurality of dummy patterns is formed to be smaller than a thickness of the first via.

14. The manufacturing method according to claim 13, further comprising: forming a first pad layer on the first wiring layer, the first pad layer being the same layer as the second sacrificial layer; as well as A first solder resist layer is formed, the first solder resist layer including a first opening exposing the second sacrificial layer and a second opening exposing a portion of the first pad layer, and a third portion of the cavity is formed in the first solder resist layer.

15. The manufacturing method according to claim 14, further comprising: forming a second insulating layer under the first insulating layer, and forming a third insulating layer under the second insulating layer; as well as A third via hole is formed, the third via hole being disposed in a third passage hole formed in the third insulating layer.

16. The manufacturing method according to claim 15, further comprising: forming a first additional pad layer, the first additional pad layer being disposed within the second opening of the first solder resist layer and contacting the first pad layer; as well as A second additional pad layer disposed on the first additional pad layer is formed.

17. The manufacturing method according to claim 16, wherein: The cavity is formed to further include a fourth portion defined by a side surface of the second additional pad layer.

18. The manufacturing method according to claim 17, wherein: The second width of the second portion is smaller than each of the first width of the first portion and the third width of the third portion, and The width of the fourth portion is formed to be different from the first width of the first portion, the second width of the second portion, and the third width of the third portion.

19. The manufacturing method according to claim 14, wherein: A first width of the first portion, a second width of the second portion, and a third width of the third portion are different from each other.

20. The manufacturing method according to claim 19, wherein: The second width of the second portion is smaller than each of the first width of the first portion and the third width of the third portion.

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