Memory array and method for forming memory array including strings of memory cells

Abstract

The invention relates to a memory array and a method for forming a memory array including strings of memory cells. In some embodiments, a memory array is described that includes a vertical stack comprising alternating insulating and conductive levels. A string of channel material of a memory cell is in the stack. A string of channel material protrudes upward from the material of an uppermost one of the levels. A first insulator material is over the material of the uppermost level directly against a side of the channel material of the upwardly protruding channel material string. The first insulator material includes at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. A second insulator material is over the first insulator material. The first and second insulator materials include different compositions from each other. Conductive vias in the second insulator material are individually electrically coupled directly to individual ones of the strings of channel material.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of an invention patent application with an application date of November 3, 2020, application number "202011207488.7", and invention name "Memory array and method for forming a memory array including a memory cell string". Technical Field

[0003] Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays including strings of memory cells. Background Art

[0004] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0005] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time when not powered. Conventionally, non-volatile memory is designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. The retention time of volatile memory may be a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

[0006] A field effect transistor is an electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Application of an appropriate voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a charge storage region that can be reversibly programmed as part of the gate construction between the gate insulator and the conductive gate.

[0007] Flash memory is a type of memory and has a wide range of uses in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they are standardized and provides the ability to remotely upgrade devices to enhance features.

[0008] NAND may be the infrastructure for integrated flash memory. A NAND cell unit includes at least one selection device coupled in series to a series combination of memory cells (the series combination is often referred to as a NAND string). The NAND architecture may be configured as a three-dimensional arrangement that includes vertically stacked memory cells that individually include vertical transistors that can be reversibly programmed. Control or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0009] The memory array may be arranged into memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, such as shown and described in U.S. Published Patent Applications Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in an individual word line level of vertically stacked memory cells. Connections to these word lines may occur in a so-called "stair step structure" at the ends or edges of the array of vertically stacked memory cells. The stair step structure includes individual "stairs" (also referred to as "steps" or "stair steps") that define contact areas for individual word lines, on which vertically extending conductive vias contact to provide electrical access to the word lines. Summary of the invention

[0010] A method for forming a memory array is described. The method includes: forming a stack, the stack including first and second layers alternating vertically; forming strings of channel material in the stack, the strings of channel material protruding upward from material of an uppermost layer of the layers; forming a first insulator material above the material of the uppermost layer beside the upwardly protruding strings of channel material, the first insulator material including at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; and forming a second insulator material above the first insulator material and forming conductive vias therein, the conductive vias individually directly electrically coupled to individual ones of the strings of channel material.

[0011] A method for forming a memory array is described. The method includes: forming a stack, the stack including vertically alternating first and second levels; forming strings of channel material in the stack, the second level material being horizontally interposed between immediate neighbors of the strings of channel material; removing at least some of the second level material of an upper second level so that the strings of channel material protrude upward from material of an uppermost level of the levels; forming a first insulator material above the material of the uppermost level next to the upwardly protruding string of channel material, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; forming horizontally elongated trenches through the first insulator material and into the stack to form laterally spaced memory block regions and forming an intervening material in the trenches; forming a second insulator material above the first insulator material and the intervening material, the first and second insulator materials comprising different compositions relative to each other; and forming conductive vias in the second insulator material to individually directly electrically couple to individual ones of the strings of channel material.

[0012] A method for forming a memory array is described. The method includes: forming a stack, the stack including vertically alternating first and second layers; forming strings of channel material in the stack, the strings of channel material individually having memory cell material along them, the second layer material horizontally interposed between the immediate neighbors of the strings of channel material; removing at least some of the second layer material of the upper second layer so that the strings of channel material protrude upwardly from the material of the uppermost layer of the layers; removing at least some of the memory cell material so that the at least some of the memory cell material does not protrude upwardly from the material of the uppermost layer; and forming a plurality of channels of channel material in the stack adjacent to the remaining portion of the memory cell material (if any) and adjacent to the upwardly protruding strings of channel material. forming a first insulator material, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; forming horizontally elongated trenches through the first insulator material and into the stack to form laterally spaced memory block regions and forming an intervening material in the trenches; forming a second insulator material over the first insulator material and the intervening material, the first and second insulator materials comprising different compositions from each other, the second insulator material comprising the same composition of at least some of the at least some memory cell materials; and forming conductive vias in the second insulator material to directly electrically couple to individual ones of the channel material strings individually.

[0013] A method for forming a memory array is described. The method includes: forming a stack including a first layer and a second layer that alternate vertically, the second layer including silicon dioxide; forming strings of channel material in the stack, the strings of channel material individually having memory cell material including silicon dioxide along them, the silicon dioxide level of the second layer material being between the immediate neighbors of the strings of channel material; removing at least some of the silicon dioxide of the upper second layer so that the strings of channel material protrude upward from the material of the uppermost layer of the layers; removing the memory cell material, including removing the silicon dioxide of the memory cell material so that none of the memory cell materials protrude upward from the material of the uppermost layer; and removing the memory cell material next to and directly against the channel material of the upwardly protruding strings of channel material. A first insulator material is formed above the material of the uppermost layer of the channel material, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; horizontally elongated trenches are formed through the first insulator material and into the stack to form laterally spaced memory block regions and an intermediate material is formed in the trenches; a second insulator material comprising silicon dioxide is formed above the first insulator material and the intermediate material, the first and second insulator materials comprising different compositions from each other; and contact openings are etched through the silicon dioxide of the second insulator material and thereafter conductive vias are formed in the contact openings, the conductive vias being individually directly electrically coupled to individual ones of the channel material strings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate in process according to an embodiment of the present invention, and is a view taken along Figure 2 The line 1-1 is obtained.

[0015] Figure 2 It is along Figure 1 A diagrammatic cross-sectional view obtained along line 2-2 in FIG.

[0016] Figure 3 , 3A , 3B, 4, 4A, 4B, 5, 5A, 6, 6A to 8A, 9 to 10A, 11 to 14A, 15 to 16A and 17 to 18A are examples of processes according to some embodiments of the present invention. Figure 1 and 2 Diagrammatic sequential cross-sectional views and / or enlarged views of the structure or parts thereof.

[0017] Fig.19 , 20, 20A, 21 and 21A show alternative example method and / or structural embodiments of the present invention. DETAILED DESCRIPTION

[0018] Embodiments of the present invention encompass methods for forming memory arrays, such as arrays of NAND or other memory cells with peripheral control circuitry beneath the array (e.g., CMOS beneath the array). Embodiments of the present invention encompass so-called "gate last" or "replacement gate" processes, so-called "gate first" processes, and other processes now known or developed in the future that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays that are independent of the method of manufacture (e.g., NAND architecture). Reference Figures 1 to 18A A first example method embodiment is described, which may be considered a "gate last" or "replacement gate" process.

[0019] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive / conductive / conductive, semiconductive / semiconductive / semiconductive or insulating / insulator / insulating (i.e., electrically herein) materials. Various materials have been vertically formed over base substrate 11. The materials may be Figure 1 and 2 1. The depicted material may be adjacent to, vertically inside, or vertically outside. For example, other partially or fully manufactured components of the integrated circuit system may be disposed above, around, or somewhere within the base substrate 11. Control and / or other peripheral circuitry for operating components within an array (e.g., array 12) of vertically extending memory cell strings may also be manufactured and may or may not be completely or partially within the array or sub-array. In addition, multiple sub-arrays may also be manufactured and operated independently, in conjunction, or otherwise relative to each other. In this document, a "sub-array" may also be considered an array.

[0020] A conductor layer 16 including conductive material 17 has been formed over substrate 11. Conductor layer 16 may include portions of control circuitry for controlling read and write access to transistors and / or memory cells to be formed within array 12 (e.g., array under-peripheral circuitry and / or a common source line or plate). A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 has been formed over conductor layer 16. An example thickness for each of layers 20 and 22 is 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown, where it is more likely that stack 18 includes tens, a hundred, or more than a hundred layers 20 and 22. Other circuitry that may or may not be part of peripheral circuitry and / or control circuitry may be interposed between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive material and insulating material of such circuitry may be below a lowermost conductive layer 22 and / or above an uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and lowermost conductive layer 22, and one or more select gate layers may be above uppermost conductive layer 22. Regardless, conductive layer 22 (alternatively referred to as the first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as the second layer) may not include insulating material or be insulating at this point in the processing in conjunction with the example method embodiments initially described herein (which are "last gates" or "replacement gates"). Example conductive layer 22 includes first material 26 (e.g., silicon nitride), which may be a sacrificial material in whole or in part. Example insulating layer 20 includes second material 24 (e.g., silicon dioxide), which has a composition different from the composition of first material 26 and may be a sacrificial material in whole or in part. Uppermost insulating layer 20 and stack 18 may be considered to have a top 21.

[0021] A channel opening 25 has been formed (e.g., by etching) through the insulating layer 20 and the conductive layer 22 to the conductor layer 16. The channel opening 25 may taper radially inward (not shown), moving deeper into the stack 18. In some embodiments, the channel opening 25 may partially enter the conductive material 17 of the conductor layer 16 as shown, or may stop above the material (not shown). Alternatively, as an example, the channel opening 25 may stop at or within the top of the lowermost insulating layer 20. The reason for extending the channel opening 25 to at least the conductive material 17 of the conductor layer 16 is to ensure that the subsequently formed channel material (not shown) is directly electrically coupled to the conductor layer 16, without using alternative processes and structures to make such a connection when such a connection is desired. An etch stop material (not shown) may be within or on top of the conductive material 17 of the conductor layer 16 to facilitate stopping etching of the channel opening 25 relative to the conductor layer 16 when desired. This etch stop material may be a sacrificial material or a non-sacrificial material. By way of example and for simplicity, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory block regions 58 that will comprise laterally spaced memory blocks 58 in a finished circuit system configuration. In this document, a "block" generally includes a "sub-block." Memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and oriented, for example, along direction 55. Otherwise, memory block regions 58 may not be discernible at this point in processing. Any alternative existing or future developed arrangements and configurations may be used.

[0022] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thus including individual channel material strings that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally interposed between the gate region and the channel material. In one such embodiment, a memory structure is formed that includes a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge passing material. The storage material (e.g., a floating gate material (e.g., doped or undoped silicon) or a charge trapping material (e.g., silicon nitride, metal dots, etc.)) of the individual memory cells is vertically along individual ones of the charge blocking region. The insulating charge passing material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulator oxides (e.g., silicon dioxide)) is laterally interposed between the channel material and the storage material.

[0023] Figure 3 , 3A, 3B, 4, 4A and 4B show where charge blocking material 30, storage material 32 and charge passing material 34 have been formed vertically in individual channel openings 25 along insulating layer 20 and conductive layer 22. Transistor materials 30, 32 and 34 (e.g., memory cell materials) may be formed by, for example, depositing respective thin layers thereof over stack 18 and within individual channel openings 25, then planarizing this back to at least the top surface of stack 18. In one embodiment, at least some of memory cell materials 30, 32 and / or 34 include silicon dioxide, and additional example memory cell materials are described in more detail below.

[0024] Channel material 36 has also been formed vertically in channel opening 25 along insulating layer 20 and conductive layer 22, thus comprising individually operable strings of channel material 53 having, in one embodiment, memory cell material (e.g., 30, 32, and / or 34) along them and having a second level of material (e.g., 24) horizontally between immediately adjacent strings of channel material 53. Due to scale, materials 30, 32, 34, and 36 are collectively shown as Figure 3 and 4 37 in the figure and indicated only as material 37. Example channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Example thicknesses of each of materials 30, 32, 34, and 36 are 25 to 100 angstroms. A punch etch may be performed as shown to remove materials 30, 32, and 34 from the base of the channel opening 25 to expose the conductor layer 16 so that the channel material 36 is directly against the conductive material 17 of the conductor layer 16. This punch etch may occur separately with respect to each of materials 30, 32, and 34 (as shown), or may occur collectively with respect to all materials after deposition of material 34 (not shown). Alternatively, and by way of example only, a punch etch may not be performed, and the channel material 36 may be directly electrically coupled to the conductive material 17 of the conductor layer 16 by a separate conductive interconnect (not shown). The channel opening 25 is shown to include a radially central solid dielectric material 38 (e.g., a spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 25 may include void space(s) (not shown) and / or be free of solid material (not shown). Regardless, and in one embodiment, the conductive material 31 (e.g., a conductive plug, such as conductively doped polysilicon) directly abuts the lateral inner side 44 in the upper portion of the individual string of channel material 53. One or more of the materials 30, 32, 34, and 36 may not extend to the top of the conductive material 31 (not shown).

[0025] refer to Figure 5 and 5A, at least some of the second level material 24 (e.g., silicon dioxide) of the upper second level 20 (e.g., the uppermost second level 20) is removed, for example, by etching, so that the strings of channel material 53 protrude upward from the uppermost material of the levels 20, 22. In one embodiment and as shown, this removal is performed only on some of the second level material 24 of the upper second level 20, whereby the uppermost level of the stack 18 remains as a level 20 due to some of the second level 24 remaining, while the strings of channel material 53 protrude upward from its second level material 24.

[0026] The embodiment described and shown above is only one example of a manner in which strings of channel material 53 are formed to protrude upward from the material of the uppermost level of stack 18. Any other existing or future developed technology may be used.

[0027] Additionally, in one embodiment and as shown, memory cell materials 30, 32, and 34 have been removed (e.g., by etching) such that none of such materials protrude upward from the material of the uppermost level of stack 18. As an example, consider an embodiment in which material 24 is silicon dioxide and memory cell materials 30, 32, and 34 are individually one or more of silicon dioxide and silicon nitride layers. In this example embodiment, the depicted construction may be produced by sequentially etching one of silicon dioxide and silicon nitride selectively relative to the other using modified or different chemistries. As an example, a solution of 100:1 (by volume) of water to HF will selectively etch silicon dioxide relative to silicon nitride, while a solution of 1000:1 (by volume) of water to HF will selectively etch silicon nitride relative to silicon dioxide. Thus, and in this example, in the event that it is desired to achieve Figure 5 and 5A With the example configurations shown, such etching chemistries may be used interchangeably. Figure 5 and 5A With the configuration shown, a skilled artisan would be able to select other chemistries for etching other different materials. One or more of materials 30, 32, and 34 may be etched such that its top is below the top of the uppermost level of stack 18 (not shown).

[0028] refer to Figure 6 and 6A, a first insulator material 39 has been formed over the material of the uppermost level of the stack 18 and beside the upwardly protruding strings of channel material 53. In the example depicted embodiment, the first insulator material 39 has been formed over the second level of material 24, where the uppermost level is the second level 20. Regardless, and in one embodiment as shown, the first insulator material 39 is formed directly against the channel material 36 of the upwardly protruding strings of channel material 53 (e.g., directly against the sides 45 of the channel material 36). For example, the first insulator material 39 as shown may be formed first deposited to overfill the horizontal space between the upwardly protruding strings of channel material 53, which is then polished back to at least the top surfaces of the strings of channel material 53 and the conductive material 31. In one embodiment, and as shown, the first insulator material 39 has been formed after the conductive material 31 has been formed directly against the lateral inner sides 44 of the individual upwardly protruding strings of channel material 53.

[0029] The first insulator material 39 includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. In one embodiment, the first insulator material 39 includes (a). In one such embodiment, the first insulator material 39 includes one and only one of carbon, oxygen, boron, or phosphorus. In another such embodiment, the first insulator material 39 includes at least two of carbon, oxygen, boron, and phosphorus. In one embodiment, one or more of carbon, oxygen, boron, and phosphorus in the first insulator material 39 has a total concentration of at least about 2 atomic percent, and in one such embodiment, this total concentration does not exceed about 20 atomic percent. In one embodiment, this total concentration is at least about 4 atomic percent, and in one embodiment at least about 10 atomic percent. In one embodiment, this total concentration is from about 6 atomic percent to about 11 atomic percent. In one embodiment, the first insulator material 39 includes (b). In one embodiment, the first insulator material 39 includes both (a) and (b), and in another embodiment includes only one of (a) and (b). In one embodiment, the insulating layer 20 includes an insulating material (e.g., 24) having a composition different from the composition of the first insulator material 39.

[0030] refer to Figure 7 , 8 8A, horizontally elongated trenches 40 have been formed (e.g., by anisotropic etching) through the first insulator material 39 and into the stack 18 to form laterally spaced memory block regions 58. The horizontally elongated trenches 40 may have respective bottoms directly against the conductive material 17 of the conductor level 16 (e.g., on top of or within) (as shown) or may have respective bottoms above the conductive material 17 of the conductor level 16 (not shown).

[0031] The above process shows that the trench opening 25 is formed and filled before the trench 40 is formed. This order can be reversed. Alternatively, the trench 40 can be formed between the formation and filling of the trench opening 25 (a non-ideal state). In addition, the above process shows that the first insulator material 39 is formed before the trench 40 is formed, although this order can be reversed.

[0032] refer to Fig. 9 , 10 , 10A, 11 and 12, and in one embodiment, material 26 (not shown) of conductive layer 22 has been removed, such as by anisotropic etching that is ideally selective relative to other exposed materials (e.g., using liquid or vapor H3PO4 as the primary etchant, where material 26 is silicon nitride, second insulator material 41 includes (a) and / or (b) and the other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive layer 22 is a sacrificial material and has been replaced with conductive material 48, and thereafter removed from trench 40, thereby forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0033] A thin insulating liner (e.g., Al2O3 and not shown) may be formed before forming conductive material 48. The approximate location of transistor and / or memory cell 56 is Fig.12 Indicated by brackets, and some Fig. 9 , 10 10A, where in the depicted example, the transistor and / or memory cell 56 is essentially annular or ring-shaped. Alternatively, the transistor and / or memory cell 56 may not be completely enclosed relative to the individual channel openings 25, so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surrounding individual channel openings in individual conductive layers, where there may be multiple word lines for each channel opening in the individual conductive layers, and not shown). The conductive material 48 may be viewed as having terminal ends 50 ( Fig.12 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be considered as memory structures 65 laterally interposed between control gate region 52 and channel material 36. In one embodiment, and as shown with respect to an example "gate last" process, conductive material 48 of conductive layer 22 is formed after forming channel opening 25 and / or trench 40. Alternatively, such as with respect to a "gate first" process, conductive material of the conductive layer may be formed prior to forming channel opening 25 and / or trench 40 (not shown).

[0034] A charge blocking region (e.g., charge blocking material 30) is interposed between the storage material 32 and the individual control gate regions 52. Charge blocking may have the following functions in a memory cell: in a programming mode, charge blocking may prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in an erase mode, charge blocking may prevent charge carriers from flowing from the control gate into the storage material. Thus, charge blocking may be used to block charge migration between the control gate region and the storage material of an individual memory cell. The example charge blocking region as shown includes an insulator material 30. By further example, the charge blocking region may include a laterally (e.g., radially) outer portion of the storage material (e.g., material 32) where this storage material is insulating (e.g., in the absence of any material of a different composition between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, in the absence of any separate composition insulator material 30, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region. Furthermore, the interface of conductive material 48 and material 30 (when present) in combination with insulator material 30 may together act as a charge blocking region and alternatively or additionally may serve as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0035] refer to Fig.13 , 14 , 14A and 15, and in one embodiment, an interposer material 57 has been formed in the trench 40 between the laterally adjacent memory block regions 58. The interposer material 57 can provide lateral electrical isolation (insulation) between the laterally adjacent memory block regions 58 and the final memory block 58. This can include one or more of insulating, semiconducting and conductive materials, and in any case, can facilitate preventing the conductive layers 22 from shorting to each other in the finished circuit system structure. Example insulating materials are one or more of SiO2, Si3N4, Al2O3 and undoped polysilicon. In one embodiment, the interposer material 57 includes a laterally outermost insulating material (e.g., silicon dioxide and / or silicon nitride and not shown) and a laterally inner material (e.g., undoped polysilicon and not shown) having a composition different from the composition of the laterally outermost insulating material. In one such embodiment, the laterally inner material is insulating. In one embodiment, the interposer material 57 is insulated everywhere between the laterally adjacent memory blocks.

[0036] refer to Fig.16 and 16A, a second insulator material 41 has been formed over the first insulator material 39 and the interposer material 57. In some embodiments, the first and second insulator materials comprise different compositions from one another, with one example second insulator material 41 being silicon dioxide. Regardless, in one embodiment, the second insulator material 41 comprises the same composition as at least some of the memory cell materials 30, 32, and / or 34.

[0037] refer to Fig.17 , 18 18A, contact openings 61 have been formed through the second insulator material 41 (e.g., by etching), and conductive vias 43 have thereafter been formed therein, and the conductive vias 43 are individually directly electrically coupled to the individual strings of channel materials 53 (e.g., at least partially through the conductive material 31). The conductive vias 43 may also be directly against the channel material 36, as shown. In one embodiment and as shown, the conductive vias 43 have been formed to extend into the first insulator material 39. Alternatively, the trenches 40 and / or the intervening fill material 57 therein may be formed sometime after the second insulator material 41 is formed, including sometime after the contact openings 61 and / or the conductive vias 43 therein are formed.

[0038] Any other attribute(s) or aspect(s) shown and / or described herein with respect to other embodiments may be used with respect to the above-described embodiments.

[0039] The present invention is directed to solving the following processing challenges, but is not limited thereto. Consider the case where materials 24 and 41 have the same composition, such as silicon dioxide. In the absence of a first insulator material 39 that will not be etched by the etching chemistry used to etch contact opening 61, over-etching may occur undesirably through a slightly misaligned mask that may extend the contact opening to the conductive material 48 (not shown) of conductive line 29. This may result in a fatal short circuit when the conductive material of conductive via 43 is deposited. Furthermore, if some of the memory cell materials 30, 32, and / or 34 include the same material as materials 24 and 41, then etching of that material may also occur during etching of contact opening 61, which may also result in a fatal short circuit when conductive via 43 is formed. Thus, in this example, in the example shown and described above, memory cell materials 30, 32, and 34 are removed from above the top 21 of the uppermost level 20 of stack 18.

[0040] However, if some memory cell material 30, 32 and / or 34 does not have the same composition as second insulator material 41, then this material or materials may remain and not be removed, e.g., as with respect to Fig.19 , 20and 20A show an alternative construction 10a. Similar symbols from the above embodiments are used as appropriate, with some construction differences indicated by the suffix "a" or by different symbols. Fig.19 , 20 20A shows an example finished product structure 10a, wherein the Figure 5 and 5A No memory cell materials 30, 32, or 34 are removed in the example processing shown with respect to construction 10. Alternatively, only one or both of the memory cell materials 30, 32, and / or 34 may be removed (not shown), and the remaining one or two memory cell materials 30, 32, and / or 34 may remain (not shown). Regardless, and in one embodiment, first insulator material 39 does not directly abut channel material 36 of string of channel material 53. Any other attribute(s) or aspect(s) shown and / or described herein with respect to other embodiments may be used.

[0041] In addition and in any case, Figure 5 and 5A Only one example embodiment is shown in which only some of the second level material 24 of the upper second level 20 has been removed. Thereby, the uppermost level of the stack 18 is still the second level 20, as some of the second level material 24 remains and strings of channel material 53 protrude upwardly from that material. Fig.21 and 21A An alternative construction 10b is shown. Like symbols from the above embodiments are used as appropriate, with some construction differences indicated with a suffix "b" or with different symbols.

[0042] Fig.21 and 21A Showing an example finished product structure 10b, in which Figure 5 and 5A In the example process shown with respect to construction 10, all of the second level material 24 of the upper second level 20 has been removed. As a result, the uppermost level of stack 18 is now first level 22 because there is no second level material 24 of the previous uppermost level 20, and strings of channel material 53 protrude upwardly from the now uppermost first level 22. This process may be performed with respect to the above description with respect to Figures 9 to 12All other exposed materials in the described process (or in the first gate process) are highly selective to etching the sacrificial material 26 in the last gate process, so that the string of channel material 53 protrudes upward from the first level material 26 (or first level material 48) of the uppermost level, which in this example would be the first level / conductive level 22. The memory cell materials 30, 32 and / or 34 may be as shown in the first described embodiment (as shown). Alternatively, some or all of the memory cell material may extend to the top of the first insulator material 39 (not shown), as described above in the second embodiment with respect to structure 10a. Any other attribute(s) or aspect(s) shown and / or described herein with respect to other embodiments may be used.

[0043] Alternative embodiment configurations may be derived from the method embodiments or other embodiments described above. Regardless, embodiments of the present invention encompass memory arrays that are independent of manufacturing methods. However, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the above method embodiments may incorporate, form and / or have any of the properties described with respect to the device embodiments.

[0044] Embodiments of the present invention include a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56). The memory array includes a vertical stack (e.g., 18) including alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). A string (e.g., 53) of channel materials of the memory cells is in the stack and protrudes upward from the material of the uppermost layer (e.g., 24 / 48). A first insulator material (e.g., 39) is above the material of the uppermost layer directly against the side (e.g., 45) of the channel material (e.g., 36) of the upwardly protruding string of channel materials. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. A second insulator material (e.g., 41) is above the first insulator material. The first and second insulator materials include different compositions from each other. The conductive vias (eg, 43) are in the second insulator material and are individually directly electrically coupled to individual ones of the strings of channel material.Any other attribute(s) or aspect(s) shown and / or described herein with respect to other embodiments may be used.

[0045] The above-described process(es) or construction(s) may be viewed as relative to an array of components formed as or within a single stack or single layer of such components above or as part of an underlying base substrate (although a single stack / layer may have multiple levels). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be below the array (e.g., below-array CMOS). Regardless, one or more additional such stack(s) / layer(s) may be provided or fabricated above and / or below the stack(s) / layer(s) shown in the figures or described above. Furthermore, the array(s) of components may be the same or different in different stacks / layers relative to one another, and different stacks / layers may have the same or different thicknesses relative to one another. Intermediary structures may be disposed between vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Likewise, different stacks / layers may be electrically coupled relative to one another. Multiple stacks / layers may be fabricated individually and sequentially (eg, one on top of another), or two or more stacks / layers may be fabricated substantially simultaneously.

[0046] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting devices, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0047] In this document, unless otherwise indicated, "vertical", "higher", "up", "down", "top", "top", "bottom", "above", "below", "down", "below", "upward", and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the direction in which the substrate is processed during manufacturing, and vertical is a direction generally orthogonal to horizontal. Reference to "completely horizontal" is a direction along the surface of the main substrate (i.e., not angled therewith) and can be relative to the direction in which the substrate is processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally vertical directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "extending in the vertical direction" refer to a direction that deviates from completely horizontal by at least 45°. In addition, "extending vertically", "extending vertically", "extending horizontally", "extending horizontally" and the like with respect to a field effect transistor are references to the orientation of the channel length of the transistor, in operation, the current flows between the source / drain regions along the orientation. For bipolar junction transistors, "extending vertically", "extending vertically", "extending horizontally", "extending horizontally" and the like are reference to the orientation of the substrate length along which, in operation, current flows between the emitter and the collector. In some embodiments, any component, feature and / or region extending vertically extends vertically or within 10° of vertical.

[0048] In addition, "directly above", "directly below" and "directly below" require that the two areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. And, the use of "above" without a preceding "directly" only requires that some portion of the area / material / component above another area / material / component is vertically outside the other area / material / component (i.e., regardless of whether there is any lateral overlap between the two areas / materials / components). Similarly, the use of "below" and "under" without a preceding "directly" only requires that some portion of the area / material / component below / under another area / material / component is vertically inside the other area / material / component (i.e., regardless of whether there is any lateral overlap between the two areas / materials / components).

[0049] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous over any material overlying thereon. Where one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of such one or more compositions. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or yet to be developed technology, examples being atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0050] In addition, "thickness" itself (without a directional adjective before) is defined as the average straight-line distance perpendicular to a given material or region from the closest surface of the adjacent material or adjacent region of different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, the thickness refers to the average thickness, unless otherwise indicated, and this material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, "different compositions" only require that the parts of the two materials or regions that can be directly against each other are chemically and / or physically different (for example, if such materials or regions are not homogeneous). If the two materials or regions are not directly against each other, then "different compositions" only require that the parts of the two materials or regions that are closest to each other are chemically and / or physically different (if such materials or regions are not homogeneous). In this document, when materials, regions or structures are in at least a certain physical touching contact relative to each other, the materials, regions or structures are "directly against" another. In contrast, the words “over,” “on,” “adjacent,” “along,” and “against” without the word “directly” in front of them encompass “directly against” as well as configurations in which (several) intervening materials, (several) regions, or (several) structures result in the materials, regions, or structures not being in physical contact with each other.

[0051] As used herein, region-material-components are "electrically coupled" to one another if, in normal operation, electrical current is able to flow continuously from one of the region-material-components to the other and such flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and may be electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0052] In this document, "row" and "column" are used for convenience to distinguish one series or orientation of features from another series or orientation of features and along which components have been or may be formed. "Row" and "column" are used synonymously with respect to any series of regions, components and / or features regardless of function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect at 90° or one or more other angles (i.e., other than right angles) relative to each other.

[0053] The composition of any of the conductivity / conductor / conductive materials herein may be a metallic material and / or a conductive doped semiconductive / semiconductive / semiconductive material. "Metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0054] As used herein, any use of "selective" with respect to etching / etching, removing / removal, depositing, and / or forming / formation is an action where one material is so acted upon relative to another material at a rate of at least 2:1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another material or materials at a rate of at least 2:1 by volume for at least the first 75 angstroms of deposition, growth, or formation.

[0055] Unless otherwise indicated, the use of "or" herein includes either and both.

[0056] in conclusion

[0057] In some embodiments, a method for forming a memory array includes forming a stack including a first layer and a second layer that alternate vertically. A channel material string is formed in the stack. The channel material string protrudes upward from the material of the uppermost layer. A first insulator material is formed above the material of the uppermost layer beside the upwardly protruding channel material string. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. A second insulator material is formed above the first insulator material, and conductive vias therein are individually directly electrically coupled to individual ones of the channel material strings.

[0058] In some embodiments, a method for forming a memory array includes forming a stack including vertically alternating first and second levels. A channel material string is formed in the stack. The second level material is horizontally interposed between the immediate neighbors of the channel material string. At least some of the second level material of the upper second level is removed so that the channel material string protrudes upward from the material of the uppermost level. A first insulator material is formed above the material of the uppermost level next to the upwardly protruding channel material string. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. A trench extending horizontally through the first insulator material and into the stack is formed to form laterally spaced memory block regions and an intervening material is formed in the trench. A second insulator material is formed above the first insulator material and the intervening material. The first and second insulator materials include different compositions relative to each other. Conductive vias are formed in the second insulator material to directly electrically couple to the individual ones of the channel material string individually.

[0059] In some embodiments, a method for forming a memory array includes forming a stack including vertically alternating first and second levels. Channel material strings are formed in the stack. The channel material strings individually have memory cell materials along them. The second level material is horizontally between the immediate neighbors of the channel material strings. At least some of the second level material of the upper second level is removed so that the channel material strings protrude upward from the material of the uppermost level. At least some of the memory cell material is removed so that the at least some of the memory cell material does not protrude upward from the material of the uppermost level. A first insulator material is formed next to the remaining portion of the memory cell material (if any) and above the material of the uppermost level next to the upwardly protruding channel material strings. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. A trench extending horizontally through the first insulator material and into the stack is formed to form laterally spaced memory block regions and an intervening material is formed in the trench. A second insulator material is formed above the first insulator material and the intervening material. The first and second insulator materials include different compositions relative to each other. The second insulator material includes the same composition of at least some of the at least some memory cell materials. Conductive vias are formed in the second insulator material to individually and directly electrically couple to individual ones of the string of channel materials.

[0060] In some embodiments, a method for forming a memory array includes forming a stack including a first layer and a second layer that alternate vertically. The second layer includes silicon dioxide. A channel material string is formed in the stack. The channel material strings individually have memory cell materials including silicon dioxide along them. The silicon dioxide level of the second layer is between the immediate neighbors of the channel material string. At least some of the silicon dioxide of the upper second layer is removed so that the channel material string protrudes upward from the material of the uppermost layer of the layers. The memory cell material including its silicon dioxide is removed so that none of the memory cell materials protrudes upward from the material of the uppermost layer. A first insulator material is formed next to the channel material of the upwardly protruding channel material string and directly against the material of the uppermost layer of the channel material. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. Horizontally elongated trenches are formed through the first insulator material and into the stack to form laterally spaced memory block regions, and an interposer material is formed in the trenches. A second insulator material comprising silicon dioxide is formed over the first insulator material and the interposer material. The first and second insulator materials comprise different compositions relative to one another. Contact openings are etched through the silicon dioxide of the second insulator material, and thereafter conductive vias are formed in the contact openings, the conductive vias being individually directly electrically coupled to individual ones of the strings of channel material.

[0061] In some embodiments, a memory array including strings of memory cells includes a vertical stack comprising alternating insulating layers and conductive layers. The channel material of the memory cells is in a string in the stack. The string of channel material protrudes upward from the material of the uppermost layer of the layers. A first insulator material is above the material of the uppermost layer of the side of the channel material of the string of channel material protruding upward directly against. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. A second insulator material is above the first insulator material. The first and second insulator materials include different compositions relative to each other. Conductive vias in the second insulator material are individually directly electrically coupled to individuals in the string of channel material.

[0062] To comply with the statute, the subject matter disclosed herein has been described in language more or less specific to structural and methodological features. However, it is to be understood that the claims are not limited to the specific features shown and described, as the meaning disclosed herein includes example embodiments. Therefore, the claims are to be given the full scope of their literal terms and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A memory array comprising: a stack comprising alternating insulating and conductive layers, the stack comprising an uppermost level and strings of channel material of memory cells in the stack, the strings of channel material protruding upwardly from material of the uppermost level, the strings of channel material individually having memory cell material there along, at least some of the memory cell material not protruding upwardly from the material of the uppermost level; a first insulator material above said material of said uppermost level against sides of channel material of said strings of channel material protruding upwardly; a second insulator material overlying the first insulator material, the first insulator material and the second insulator material comprising different compositions from one another, the second insulator material comprising the same composition as at least some of the at least some memory cell materials; and Conductive vias are in the second insulator material, the conductive vias being individually directly electrically coupled to individual ones of the strings of channel material.

2. The memory array of claim 1 wherein the first insulator material comprises silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus.

3. The memory array of claim 2 wherein the first insulator material comprises only one of carbon, oxygen, boron, and phosphorus.

4. The memory array of claim 2 wherein the first insulator material comprises two or more of carbon, oxygen, boron, and phosphorus.

5. The memory array of claim 2 wherein the one or more of carbon, oxygen, boron, and phosphorus in the first insulator material has a total concentration of at least 2 atomic percent.

6. The memory array of claim 5 wherein the total concentration does not exceed 20 atomic percent.

7. The memory array of claim 1 wherein the first insulator material comprises silicon carbide.

8. The memory array of claim 1, wherein the memory array is a replacement gate NAND memory array.

9. The memory array of claim 1 wherein the conductive vias extend into the first insulator material to individually directly abut lateral sides of the first insulator material.

10. A method for forming a memory array, the method comprising: forming a stack comprising alternating insulating layers and conductive layers; forming strings of channel material in the stack, the strings of channel material protruding upward from material of an uppermost level of the insulating and conductive layers; forming a first insulator material over the material of the uppermost level directly against the sides of the channel material of the strings of channel material protruding upwardly; forming a second insulator material over the first insulator material, the first insulator material and the second insulator material comprising different compositions from each other; and Conductive vias are formed in the second insulator material, the conductive vias being individually directly electrically coupled to individual ones of the strings of channel material, the conductive vias extending into the first insulator material to individually directly abut against lateral sides of the first insulator material.

11. The method of claim 10, further comprising forming a conductive material directly against a laterally inner side of individual upwardly protruding strings of channel material. 12 . The method of claim 11 , further comprising forming the first insulator material after forming the conductive material.

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